US20020115236A1 - Methods of making compliant semiconductor chip packages - Google Patents
Methods of making compliant semiconductor chip packages Download PDFInfo
- Publication number
- US20020115236A1 US20020115236A1 US09/020,647 US2064798A US2002115236A1 US 20020115236 A1 US20020115236 A1 US 20020115236A1 US 2064798 A US2064798 A US 2064798A US 2002115236 A1 US2002115236 A1 US 2002115236A1
- Authority
- US
- United States
- Prior art keywords
- compliant
- layer
- semiconductor chip
- package
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02313—Subtractive methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0235—Shape of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0236—Shape of the insulating layers therebetween
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/024—Material of the insulating layers therebetween
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Definitions
- the present invention relates to semiconductor chip packaging. More particularly, the present invention relates to an improved compliant semiconductor package structure and methods for making the same.
- wire bonding the chip is positioned on a substrate with a bottom or back surface of the chip abutting the substrate and with the contact-bearing front or top surface of the chip facing upwardly, away from the substrate.
- Individual gold or aluminum wires are connected between the contacts on the chip and pads on the substrate.
- tape automated bonding a flexible dielectric tape with a prefabricated array of leads thereon is positioned over the chip and substrate and the individual leads are bonded to the contacts on the chip and to pads on the substrate.
- the pads on the substrate are arranged outside of the area covered by the chip, so that the wires or leads fan out from the chip to the surrounding pads.
- the area covered by the subassembly as a whole is considerably larger than the area covered by the chip. This makes the entire assembly substantially larger than it otherwise would be. Because the speed with which a microelectronic assembly can operate is inversely related to its size, this presents a serious drawback.
- the wire bonding and tape automated bonding approaches are generally most workable with chips having contacts disposed in rows extending along the periphery of the chip. They generally do not lend themselves to use with chips having contacts disposed in a so-called area array, i.e., a grid-like pattern covering all or a substantial portion of the chip front surface.
- the contact bearing surface of the chip faces towards the substrate.
- Each contact on the chip is joined by a solder bond to the corresponding pad on the substrate, as by positioning solder balls on the substrate or chip, juxtaposing the chip with the substrate in the front-face-down orientation and momentarily melting or reflowing the solder.
- the flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself.
- flip-chip assemblies suffer from significant problems with thermal stress.
- the solder bonds between the chip contacts and substrate are substantially rigid. Changes in the size of the chip and of the substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which in turn can lead to fatigue failure of the bonds.
- interposers flexible, sheet-like structures referred to as “interposers” or “chip carriers”.
- the preferred chip carriers have a plurality terminals disposed on a flexible, sheet-like top layer.
- the interposer is disposed on the front or contact bearing surface of the chip with the terminals facing upwardly, away from the chip.
- the terminals are then connected to the contacts of the chip. Most preferably, this connection is made by bonding prefabricated leads on the interposer to the chip contacts, using a tool engaged with the lead.
- the completed assembly is then connected to a substrate, as by bonding the terminals of the chip carrier to the substrate.
- the terminals on the chip carrier can move relative to the contacts on the chip without imposing significant stresses on the bonds between the leads and the chip, or on the bonds between the terminals and the substrate.
- the assembly can compensate for thermal effects.
- the assembly most preferably includes a compliant layer disposed between the terminals on the chip carrier and the face of the chip itself as, for example, an elastomeric layer incorporated in the chip carrier and disposed between the dielectric layer of the chip carrier and the chip. Such a compliant structure permits displacement of the individual terminals independently towards the chip.
- Components of this type can be connected to microelectronic elements such as semiconductor chips or wafers by juxtaposing the bottom surface of the support layer with the contact-bearing surface of the chip so as to bring the lower ends of the leads into engagement with the contacts on the chip, and then subjecting the assembly to elevated temperature and pressure conditions.
- All of the lower ends of the leads bond to the contacts on the chip substantially simultaneously.
- the bonded leads connect the terminals of the top sheet with the contacts on the chip.
- the support layer desirably is either formed from a relatively low-modulus, compliant material, or else is removed and replaced after the lead bonding step with such a compliant material.
- the terminals desirably are movable with respect to the chip to permit testing and to compensate for thermal effects.
- the components and methods of the '390 patent provide further advantages, including the ability to make all of the bonds to the chip or other component in a single lamination-like process step.
- the components and methods of the '390 application are especially advantageous when used with chips or other microelectronic elements having contacts disposed in an area array.
- the present invention contemplates a method of creating a compliant semiconductor chip package assembly and the semiconductor chip package assembly created therefrom.
- a first dielectric protective layer is provided on a contact bearing surface of a semiconductor chip.
- the semiconductor chip has a central region bounded by the chip contacts and a set of apertures.
- the apertures in the dielectric protective layer are provided such that the chip contacts are exposed.
- This first dielectric protective layer may actually be the silicon dioxide passivation layer of the semiconductor chip.
- a compliant layer preferably consisting of silicone, flexibilized epoxy, a thermosetting polymer or polyimide is provided atop the first dielectric protective layer is provided within the central region.
- the compliant layer is formed such that it has a substantially flat top surface and edges that gradually slope down to the top surface of the first dielectric protective layer.
- the sloping edges of the compliant layer may be manufactured to have a first transition region near the top surface of the compliant layer and a second transition region near the bottom surface of the compliant layer such that both the first transition region and the second transition region have a radius of curvature.
- bond ribbons are selectively electroplated atop both the first dielectric protective layer and the compliant layer such that each bond ribbon electrically connects each chip contact to a respective terminal position on the compliant layer.
- the terminal positions are the conductive elements that connect the finished assembly to a separate substrate, e.g. a printed circuit board.
- the method described above may further include the step of providing for a second dielectric protective layer atop the bond ribbons and the compliant layer after the bond ribbon electroplating step is performed.
- This optional second dielectric protective layer is fabricated with a set of apertures that expose the underlying terminal positions on the compliant layer.
- the method described above may further include the optional step of providing for an encapsulant layer above the bond ribbons. If this optional step is performed, it is performed after the step of selectively electroplating the bond ribbons. Like the first dielectric layer, the encapsulant layer is fabricated with a set of apertures so that the terminal positions are exposed.
- the encapsulant layer material consists preferably of either a curable liquid, such as silicone, a flexibilized epoxy or a gel. This optional step may also be performed just prior to the optional step of providing for a second dielectric protective layer.
- the method above can be applied simultaneously to a multiplicity of undiced semiconductor chips on a wafer or an array of diced semiconductor chips arranged in an array to form a corresponding multiplicity of compliant semiconductor chip packages.
- the present invention also claims the structure of a unique compliant semiconductor chip package having fan-in type leads.
- the compliant semiconductor chip package is comprised of (1) a semiconductor chip having a plurality of peripheral bonding pads on a face surface thereof and a central region bound by the peripheral bonding pads; (2) a first dielectric protective layer having a first surface, a second surface and apertures, wherein the first surface of the first dielectric layer is joined to the face surface of the semiconductor chip and the peripheral bonding pads are exposed through the apertures; (3) a compliant layer having a top surface and a bottom surface, wherein the bottom surface of the compliant layer is joined to the second surface of the first dielectric layer within the central region of the semiconductor chip package; and (4) a plurality of electrically conductive bond ribbons, each bond ribbon having a first end that electrically couples to a respective peripheral bonding pad of the semiconductor chip and a second end that joins to the top surface of the compliant layer to form a package terminal.
- the package terminals of the completed package are configured in an array that has an area smaller than the area bound by the peripheral bonding pads on the face of the semiconductor chip.
- the package has fan-in leads that permits minimization of the overall package size.
- the compliant layer has sloped peripheral edges so that the overlying bond ribbons are curved rather than kinked.
- the compliant semiconductor chip package may also have a compliant layer characterized by an array of bumped protrusions.
- the bumped protrusions support the overlying conductive terminal position ends of the bond ribbons and function as conductive balls that join to a substrate thus forming a ball grid array type interconnection.
- the compliant layer may have an array of concavities that are useful for placement of solder balls into each concavity. This arrangement is also useful for a ball grid array type interconnect.
- FIG. 1A is a cross-sectional view of a semiconductor chip assembly at the beginning of a fabrication process.
- FIG. 1B is a cross-sectional view of the semiconductor chip assembly after a first step of the fabrication process, showing a deposited or laminated dielectric passivation layer.
- FIG. 1C is a cross-sectional view of the semiconductor chip assembly after a second step of the fabrication process, showing a deposited or laminated compliant layer within the central region of the semiconductor chip contact-bearing surface.
- FIG. 1D is a cross-sectional view of the semiconductor chip assembly after a third step of the fabrication process, showing a conductive seed layer that has been sputtered over the assembly.
- FIG. 1E is a cross-sectional view of the semiconductor chip assembly after a fourth step of the fabrication process, illustrating how after a photolithographic step conductive bond ribbons can be formed over the assembly.
- FIG. 1F is a cross-sectional view of the semiconductor chip assembly after a fifth step of the fabrication process, showing how the assembly is coated with a second dielectric protective layer.
- FIG. 2 is a perspective view of the semiconductor chip assembly after the bond ribbons have been formed over the compliant layer but before the second dielectric protective layer is coated.
- FIG. 3 is a plan view of a wafer having a multiplicity of semiconductor chips, illustrating how said multiplicity of semiconductor chips can be simultaneously packaged using the semiconductor chip assembly process depicted in FIGS. 1 A- 1 F.
- FIG. 4 is a cross-sectional view of an alternate embodiment of the present invention, illustrating the use of a low modulus encapsulant material to provide further support and stress relief to the bond ribbons.
- FIG. 5A is a cross-sectional view of an alternate embodiment of the present invention, illustrating the formation of bumped protrusions in the compliant layer that raise the overlying terminals such that the terminals form an array over the top surface of the compliant layer.
- FIG. 5B is a perspective view of the embodiment shown in FIG. 5A.
- FIG. 6A is a cross-sectional view of an alternate embodiment of the present invention, illustrating the formation of concave areas in the compliant layer such that the overlying terminals have cup-like depressions useful for accurate placement of solder balls.
- FIG. 6B is a perspective view of the embodiment shown in FIG. 6A.
- FIGS. 1 A-F illustrate a side view of the process of creating the compliant chip package of the present invention on the face surface of a single die, on the face surfaces of multiple die arranged in a coplanar array or on the face surface of an undiced silicon wafer which may be subsequently diced into individual packaged chips or multi-chip modules.
- FIG. 1A shows a single semiconductor chip 100 with a contact bearing face surface 120 .
- the contacts 110 on the face surface 120 are typically aligned in a peripheral region 112 and further define a central region 115 therein.
- a dielectric passivation layer is deposited or adhered onto the face surface 120 of the chip 100 .
- the passivation layer may simply be the SiO 2 passivation layer (not shown) commonly found on the contact bearing surface of semiconductor chips, or a separate dielectric passivation layer 130 may be used, such as an epoxy resin, a polyimide resin, photo-imagable dielectric, etc.
- the passivation layer 130 may be spun onto and built up to a planar sheet-like form on the face surface 120 or a dielectric sheet may be laminated to the face surface 120 using any of a number of electronic grade adhesives commonly known and used by those skilled in the art.
- the passivation layer 130 covers the face surface 120 of the chip 100 while leaving the chip contacts 110 exposed so that a bond ribbon may be plated thereon in a later step, as described below. Typically, this will be done by depositing or adhering the passivation layer 130 in a continuous sheet on the face surface 120 of the chip 100 .
- a registering system such as an automatic vision system is used to locate the contacts 110 .
- the passivation layer 130 may be exposed and developed without exposing the area above the contacts 110 , that unexposed area may then be removed.
- Another removal process which can be used is to use a pulse of directed energy, such as an excimer laser, to selectively remove the passivation layer 130 above the contacts 110 .
- a continuous dielectric sheet already having set contact holes may be registered and laminated to the chip 100 .
- a compliant layer 140 is deposited or laminated onto the exposed surface of the passivation layer 130 .
- the compliant layer 140 may be stenciled, screened or transfer molded onto the passivation layer 130 using a curable liquid which, when cured, adheres to the passivation layer 130 .
- the compliant layer 140 may be adhered to the exposed surface of the passivation layer 130 in the form of cured compliant pads using the aforementioned electronic grade adhesives.
- the compliant layer 140 has a substantially flat top surface 147 which further typically has a gradual, sloping transition 145 between the face surface 120 of the chip 100 and the top surface 147 .
- This transition 145 may follow a line of curvature from the passivation layer 130 to a substantially flat top surface 147 or may simply be canted at an angle such that the transition 145 is not too vertically oriented in relation to the passivation layer 130 and the top surface 147 .
- the compliant layer 140 itself may be formed from a wide variety of materials; however, preferably, a low modulus of elasticity material is used as the compliant layer 140 .
- Compliant interposers typically are fabricated from polymeric and other materials such as silicones, flexibilized epoxy, polyimides and other thermosetting polymers, fluoropolymers and thermoplastic polymers. Also, the interposer may be a composite incorporating plural materials. The interposer may consist of, or incorporate, a foam or mesh layer.
- the flexibility of the interposer depends on the thickness and configuration of the interposer, as well as on the properties of the materials used therein.
- a flexible interposer capable of buckling or wrinkling to accommodate relative movement, can be fabricated from high elastic modulus materials, normally considered as “rigid” provided that these materials are present in thin layers.
- Relatively soft materials and foams can be used in greater thicknesses and still provide a highly flexible interposer.
- such soft materials and foams provide a highly compliant interposer, i.e., an interposer which is readily compressible in the directions perpendicular its surfaces and which therefore permits movement of the terminals in these directions.
- a plating seed layer 150 is then deposited atop the aforementioned assembly, as shown in FIG. 1D, typically using a sputtering operation.
- Typical plating seed layer materials include palladium (for electroless plating), titanium, tungsten, nickel, chromium; however, primarily copper seed layers are used.
- FIG. 1E shows the next step in which photoresist 160 is applied to the exposed top surfaces of the assembly and then exposed and developed such that bond ribbons 170 may be plated within defined areas to form conductive paths electrically connecting the chip contacts 110 near a first end region of the ribbons 170 to terminals 175 comprising the second end region of the ribbons 170 . This is perhaps more easily seen in the perspective view shown in FIG. 2.
- the ribbons 170 are plated directly onto the contacts 110 and extend in a “fan-in” arrangement from the peripheral region 112 to the central region 115 of the face surface 120 of the chip 100 atop the compliant layer 14
- Possible bond ribbon materials include copper, gold, nickel, and alloys, combinations and composites thereof, among others. Since the bond ribbons 170 are plated directly onto the chip contact/compliant layer themselves, there is no need to develop a process for bonding the ribbons 170 to the contacts, as is necessary with most other approaches such as TAB, beam lead or wirebonding. This provides a significant cost savings because specialized thermocompression or ultrasonic bonders and their bonding tools need not be purchased or maintained.
- the material selected for the bond ribbon 170 be compatible with the chip contact 110 material, which is typically aluminum. Otherwise, a phenomenon called Kirkendahl Voiding (voids created at the boundary of two metals having different interdiffusion coefficients) may cause voiding along the boundary of the two metals (ribbon/contact) leading to intermetallic degradation and embrittlement of the bond ribbon 170 itself making the lead/bond susceptible to failure during thermal cycling. Alternately, one or more barrier metals may be plated atop the chip contacts 110 prior to the bond ribbon plating step to thereby ensure the compatibility of materials.
- Kirkendahl Voiding voids created at the boundary of two metals having different interdiffusion coefficients
- one or more barrier metals may be plated atop the chip contacts 110 prior to the bond ribbon plating step to thereby ensure the compatibility of materials.
- a dielectric layer 180 is deposited or laminated over the top of the assembly so that only the terminals 175 are exposed.
- the dielectric layer may be comprised of a screened, exposed and developed or laminated sheet photo resist material or may be comprised of pyralene, epoxy resin, polyimide resin, fluoropolymer, etc. which is deposited or laminated on to the assembly, as described above in relation to the passivation layer 130 .
- the terminals 175 may then be electrically connected to a circuitized substrate, such as a printed wiring board.
- solder ball or a solid-core solder ball will be used to create this electrical connection.
- the dielectric layer 180 is thus used as a solder mask to ensure that the solder does not electrically short between adjacent bond ribbons 170 .
- Oxide layers and other surface contaminates typically build up on the surface of many types of metal (copper, nickel, etc.).
- the terminals 175 are typically flash plated with a thin layer of gold (approximately 0.25 to 0.5 microns) to inhibit the formation of these oxide layers.
- the gold layer is kept very thin so that it does not appreciably affect the aforementioned solder joint by dissolving into the solder to an amount which would embrittle the resulting solder joint between the terminal and a circuitized substrate.
- the configuration of the above described chip package allows the package to mechanically decouple the chip 100 from an attached circuitized substrate (not shown). Typically, solder connections between the chip and the circuitized substrate are woefully inadequate to compensate for the thermal mismatch problem during temperature cycling of the chip.
- the combination of the compliant layer 140 and the flexible bond ribbons plated thereon allow the package to compensate for much of the TCE mismatch problem by giving limited movement of the terminals in the X, Y and Z directions with respect to the chip contacts 110 thereby minimizing the stress placed on the solder connections themselves, without imposing substantial forces on the bond between the ribbons 170 and the chip contacts 110 .
- the compliant layer 140 is compressible, it also has the effect of compensating for any terminals 175 which are not perfectly planar with respect to its adjacent terminals when the terminals 175 are abutted against and coupled to the circuitized substrate.
- the top surface 147 of the compliant layer 140 should be made as flat and planar as possible so that the terminals 175 all lie in or near the same plane in order to minimize the amount of pressure needed to be placed on the bottom surface 125 of the chip 100 to ensure that all of the terminals/solder balls are electrically connected to a circuitized substrate.
- the chip package described above in relation to FIGS. 1 and 2 may also be provided in the form of a multiplicity of packages on a wafer incorporating a plurality of individual, undiced chips, all of the same design or of differing designs.
- an array of individual passivation layers 230 may be deposited or laminated onto the face surface 220 of the wafer 200 leaving the chip contacts 210 of the various individual chips exposed, as described above. This arrangement is shown to better define the individual chips within the wafer.
- a single passivation layer 230 is deposited or laminated onto the face surface 220 leaving the contacts 210 exposed.
- Individual compliant layers 240 are deposited or laminated onto the central regions of each of the individual chips within the wafer 200 .
- the steps found in FIGS. 1 A-F are then performed, as described above, to create a plurality of connected individually packaged chips on the face surface 220 of the wafer 200 .
- Each packaged chip having bond ribbons 270 which are connected at one end to contacts 210 and extending in to a central region of the respective chip in a fan-in fashion atop a respective compliant layer 240 and ending with a terminal 275 on the top surface 247 of the compliant layer 240 .
- the individual chips may be separated from the wafer 200 and from one another, as by cutting the wafer 200 using conventional wafer severing or “dicing” equipment commonly utilized to sever wafers into individual chips. This procedure yields a plurality of packaged chip subassemblies, each of which may be secured to an individual circuitized substrate. Alternately, the chips may be separated from the wafer 200 in multi-chip arrangements of multiples of the same or different operational chips.
- the wafer level embodiment shown in FIG. 3 could be simulated using a panel of individual chips spaced apart from one another in a processing boat. The face surfaces of the individual chips would be coplanar with respect to one another to simulate the face surface 220 of the wafer 200 .
- the chips above described steps would be performed and the chips would be separated if desired.
- a low modulus encapsulant material 290 may be deposited around the exposed surfaces of the bond ribbons 170 ′ leads prior to the step shown in FIG. 1F of depositing or laminating the assembly with the dielectric layer 180 ′.
- the encapsulant material 290 may have properties similar to those of rubber, gum or gel.
- Typical encapsulation materials include curable liquid or cured pads comprised of silicone, flexibilized epoxy, gels, thermoplastics, etc.
- a fixture may be made such that the liquid flows around the bond ribbons 170 ′ but does not flow on top of the terminals 175 ′ to ensure that solder balls may be subsequently electrically connected to the terminals 175 ′, as described above.
- a machine such as a Camalot 1818 manufactured by Camalot Systems, Inc. of Havermill, Mass. may be used to flow the liquid encapsulant into the desired areas. After the liquid is deposited, it may be cured by any number of ways depending on the encapsulant material 290 used, e.g. heat, infrared energy, etc.
- the encapsulant 290 gives each of the bond ribbons 170 ′ more support and further spreads some of the stress away from the ribbons 170 ′ thus allowing a larger TCE mismatch between the chip and a circuitized substrate, as described above.
- the dielectric layer 180 ′ may be deposited or laminated thereto.
- a conductive material such as beryllium copper, or a super plastic or shape memory alloy (such as Nitinol), is sputtered or otherwise deposited across the entire exposed surface of the chip/passivation layer/compliant layer ( 100 / 130 / 140 ) combination, shown in FIG. 1C.
- the conductive material may then be etched using industry standard photolithographic techniques resulting in a multiplicity of bond ribbons positioned and configured much like the bond ribbons 170 shown in FIG. 1E and FIG. 2.
- a barrier metal such as a flash plated layer of gold, may first be plated to the chip contacts to ensure compatibility of the electrical connection between the chip contact and the bond ribbon.
- a flash plated layer of gold may be plated atop the exposed surface of the terminal.
- the entire exposed surface of the bond ribbon could be plated with a thin layer of gold to increase the overall conductivity of such super plastic leads.
- a dielectric layer is next deposited or laminated as shown in FIG. 1F.
- FIG. 5A shows a side view and FIG. 5B a perspective view of another embodiment, according to the present invention.
- the compliant layer 140 ′ has protrusions 300 on its top surface 147 ′. These protrusions 300 may be integral with the compliant layer 140 ′ or may be deposited or laminated onto the top surface 147 ′ subsequent to the formation of the compliant layer 140 ′.
- the protrusions 300 may be formed of compliant, elastomeric material, such as the material comprising the compliant layer 140 ′, or may be comprised of a semi-rigid or rigid material.
- the bond ribbon terminals 175 ′ are plated on top of the protrusions 300 thereby providing raised surfaces which may be connected to a circuitized substrate. This technique allows for connection to such a substrate using less solder and without the need to accurately position solid-core solder balls.
- FIG. 6A shows a side view and FIG. 6B a perspective view of another embodiment, according to the present invention.
- concave areas 310 are created in the compliant layer 140 ′′. These concave areas 310 may be create in the formation of the compliant layer 140 ′′ or may be created subsequent to the formation of the compliant layer 140 ′′.
- the bond ribbon terminals 175 ′′ are plated within the concave areas 310 creating conductive “cup-like” areas on the top surface 147 ′′ of the compliant layer 140 ′′. Solder or solid-core solder balls are then placed within these areas 310 and reflowed to attach the package to a circuitized substrate, as described earlier. This technique allows for the accurate placement of solder or solid-core solder balls by allowing them to be deposited and retained within the cup-like areas.
Abstract
A compliant semiconductor chip package with fan-in leads and a method for manufacturing the same. The package, or “assembly”, contains a multiplicity of bond ribbons connected between the contacts of a semiconductor chip and corresponding terminals on a top surface of a compliant layer. The compliant layer provides stress relief to the bond ribbons encountered during handling or affixing the assembly to an external substrate. The chip package also contains a dielectric layer adjacent to at least one end of the bond ribbons. The dielectric layer relieves mechanical stresses associated with the thermal mismatch of assembly and substrate materials during thermal cycling. The assembly can be manufactured without the need for any bond wiring tools once the bond ribbons are patterned and formed during a standard photolithographic stage within the manufacturing process. The manufacturing process also amenable to simultaneous assembly of a multiplicity of undiced chips on a wafer or simultaneous assembly of diced chips in a processing boat.
Description
- The present application claims benefit of U.S. Provisional Application No. 60/007,128, filed Oct. 31, 1995.
- The present invention relates to semiconductor chip packaging. More particularly, the present invention relates to an improved compliant semiconductor package structure and methods for making the same.
- Complex microelectronic devices such as modern semiconductor chips require numerous connections to other electronic components. For example, a complex microprocessor chip may require many hundreds of connections to external devices.
- Semiconductor chips commonly have been connected to electrical traces on mounting substrates by one of three methods: wire bonding, tape automated bonding, and flip-chip bonding. In wire bonding, the chip is positioned on a substrate with a bottom or back surface of the chip abutting the substrate and with the contact-bearing front or top surface of the chip facing upwardly, away from the substrate. Individual gold or aluminum wires are connected between the contacts on the chip and pads on the substrate. In tape automated bonding a flexible dielectric tape with a prefabricated array of leads thereon is positioned over the chip and substrate and the individual leads are bonded to the contacts on the chip and to pads on the substrate. In both wire bonding and conventional tape automated bonding, the pads on the substrate are arranged outside of the area covered by the chip, so that the wires or leads fan out from the chip to the surrounding pads. The area covered by the subassembly as a whole is considerably larger than the area covered by the chip. This makes the entire assembly substantially larger than it otherwise would be. Because the speed with which a microelectronic assembly can operate is inversely related to its size, this presents a serious drawback. Moreover, the wire bonding and tape automated bonding approaches are generally most workable with chips having contacts disposed in rows extending along the periphery of the chip. They generally do not lend themselves to use with chips having contacts disposed in a so-called area array, i.e., a grid-like pattern covering all or a substantial portion of the chip front surface.
- In the flip-chip mounting technique, the contact bearing surface of the chip faces towards the substrate. Each contact on the chip is joined by a solder bond to the corresponding pad on the substrate, as by positioning solder balls on the substrate or chip, juxtaposing the chip with the substrate in the front-face-down orientation and momentarily melting or reflowing the solder. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. However, flip-chip assemblies suffer from significant problems with thermal stress. The solder bonds between the chip contacts and substrate are substantially rigid. Changes in the size of the chip and of the substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which in turn can lead to fatigue failure of the bonds. Moreover, it is difficult to test the chip before attaching it to the substrate, and hence difficult to maintain the required outgoing quality level in the finished assembly, particularly where the assembly includes numerous chips.
- Numerous attempts have been made to solve the foregoing problem. Useful solutions are disclosed in commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266. Preferred embodiments of the structures disclosed in these patents incorporate flexible, sheet-like structures referred to as “interposers” or “chip carriers”. The preferred chip carriers have a plurality terminals disposed on a flexible, sheet-like top layer. In use, the interposer is disposed on the front or contact bearing surface of the chip with the terminals facing upwardly, away from the chip. The terminals are then connected to the contacts of the chip. Most preferably, this connection is made by bonding prefabricated leads on the interposer to the chip contacts, using a tool engaged with the lead. The completed assembly is then connected to a substrate, as by bonding the terminals of the chip carrier to the substrate. Because the leads and the dielectric layer of the chip carrier are flexible, the terminals on the chip carrier can move relative to the contacts on the chip without imposing significant stresses on the bonds between the leads and the chip, or on the bonds between the terminals and the substrate. Thus, the assembly can compensate for thermal effects. Moreover, the assembly most preferably includes a compliant layer disposed between the terminals on the chip carrier and the face of the chip itself as, for example, an elastomeric layer incorporated in the chip carrier and disposed between the dielectric layer of the chip carrier and the chip. Such a compliant structure permits displacement of the individual terminals independently towards the chip. This permits effective engagement between the subassembly and a test fixture. Thus, a test fixture incorporating numerous electrical contacts can be engaged with all of the terminals in the subassembly despite minor variations in the height of the terminals. The subassembly can be tested before it is bonded to a substrate so as to provide a tested, known, good part to the substrate assembly operation. This in turn provides very substantial economic and quality advantages.
- Commonly owned U.S. Pat. No. 5,455,390 describes a further improvement. Components according to preferred embodiments of the '390 patent use a flexible, dielectric top sheet having top and bottom surfaces. A plurality of terminals are mounted on the top sheet. A support layer is disposed underneath the top sheet, the support layer having a bottom surface remote from the top sheet. A plurality of electrically conductive, elongated leads are connected to the terminals on the top sheet and extend generally side by side downwardly from the terminals through the support layer. Each lead has a lower end at the bottom surface of the support layer. The lower ends of the leads have conductive bonding materials as, for example, eutectic bonding metals. The support layer surrounds and supports the leads.
- Components of this type can be connected to microelectronic elements such as semiconductor chips or wafers by juxtaposing the bottom surface of the support layer with the contact-bearing surface of the chip so as to bring the lower ends of the leads into engagement with the contacts on the chip, and then subjecting the assembly to elevated temperature and pressure conditions.
- All of the lower ends of the leads bond to the contacts on the chip substantially simultaneously. The bonded leads connect the terminals of the top sheet with the contacts on the chip. The support layer desirably is either formed from a relatively low-modulus, compliant material, or else is removed and replaced after the lead bonding step with such a compliant material. In the finished assembly, the terminals desirably are movable with respect to the chip to permit testing and to compensate for thermal effects. However, the components and methods of the '390 patent provide further advantages, including the ability to make all of the bonds to the chip or other component in a single lamination-like process step. The components and methods of the '390 application are especially advantageous when used with chips or other microelectronic elements having contacts disposed in an area array.
- Despite the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable.
- The present invention contemplates a method of creating a compliant semiconductor chip package assembly and the semiconductor chip package assembly created therefrom.
- In the fabrication process first, a first dielectric protective layer is provided on a contact bearing surface of a semiconductor chip. The semiconductor chip has a central region bounded by the chip contacts and a set of apertures. The apertures in the dielectric protective layer are provided such that the chip contacts are exposed. This first dielectric protective layer may actually be the silicon dioxide passivation layer of the semiconductor chip.
- Second, a compliant layer, preferably consisting of silicone, flexibilized epoxy, a thermosetting polymer or polyimide is provided atop the first dielectric protective layer is provided within the central region. The compliant layer is formed such that it has a substantially flat top surface and edges that gradually slope down to the top surface of the first dielectric protective layer. The sloping edges of the compliant layer may be manufactured to have a first transition region near the top surface of the compliant layer and a second transition region near the bottom surface of the compliant layer such that both the first transition region and the second transition region have a radius of curvature.
- Finally, bond ribbons are selectively electroplated atop both the first dielectric protective layer and the compliant layer such that each bond ribbon electrically connects each chip contact to a respective terminal position on the compliant layer. The terminal positions are the conductive elements that connect the finished assembly to a separate substrate, e.g. a printed circuit board.
- The method described above may further include the step of providing for a second dielectric protective layer atop the bond ribbons and the compliant layer after the bond ribbon electroplating step is performed. This optional second dielectric protective layer is fabricated with a set of apertures that expose the underlying terminal positions on the compliant layer.
- Additionally, the method described above may further include the optional step of providing for an encapsulant layer above the bond ribbons. If this optional step is performed, it is performed after the step of selectively electroplating the bond ribbons. Like the first dielectric layer, the encapsulant layer is fabricated with a set of apertures so that the terminal positions are exposed. The encapsulant layer material consists preferably of either a curable liquid, such as silicone, a flexibilized epoxy or a gel. This optional step may also be performed just prior to the optional step of providing for a second dielectric protective layer.
- The method above can be applied simultaneously to a multiplicity of undiced semiconductor chips on a wafer or an array of diced semiconductor chips arranged in an array to form a corresponding multiplicity of compliant semiconductor chip packages.
- The present invention also claims the structure of a unique compliant semiconductor chip package having fan-in type leads. The compliant semiconductor chip package is comprised of (1) a semiconductor chip having a plurality of peripheral bonding pads on a face surface thereof and a central region bound by the peripheral bonding pads; (2) a first dielectric protective layer having a first surface, a second surface and apertures, wherein the first surface of the first dielectric layer is joined to the face surface of the semiconductor chip and the peripheral bonding pads are exposed through the apertures; (3) a compliant layer having a top surface and a bottom surface, wherein the bottom surface of the compliant layer is joined to the second surface of the first dielectric layer within the central region of the semiconductor chip package; and (4) a plurality of electrically conductive bond ribbons, each bond ribbon having a first end that electrically couples to a respective peripheral bonding pad of the semiconductor chip and a second end that joins to the top surface of the compliant layer to form a package terminal.
- The package terminals of the completed package are configured in an array that has an area smaller than the area bound by the peripheral bonding pads on the face of the semiconductor chip. In other words, the package has fan-in leads that permits minimization of the overall package size.
- For increased reliability, the compliant layer has sloped peripheral edges so that the overlying bond ribbons are curved rather than kinked.
- The compliant semiconductor chip package may also have a compliant layer characterized by an array of bumped protrusions. The bumped protrusions support the overlying conductive terminal position ends of the bond ribbons and function as conductive balls that join to a substrate thus forming a ball grid array type interconnection. Alternate to the bumped protrusions, the compliant layer may have an array of concavities that are useful for placement of solder balls into each concavity. This arrangement is also useful for a ball grid array type interconnect.
- The foregoing and other objects and advantages of the present invention will be better understood from the following Detailed Description of a Preferred Embodiment, taken together with the attached figures.
- FIG. 1A is a cross-sectional view of a semiconductor chip assembly at the beginning of a fabrication process.
- FIG. 1B is a cross-sectional view of the semiconductor chip assembly after a first step of the fabrication process, showing a deposited or laminated dielectric passivation layer.
- FIG. 1C is a cross-sectional view of the semiconductor chip assembly after a second step of the fabrication process, showing a deposited or laminated compliant layer within the central region of the semiconductor chip contact-bearing surface.
- FIG. 1D is a cross-sectional view of the semiconductor chip assembly after a third step of the fabrication process, showing a conductive seed layer that has been sputtered over the assembly.
- FIG. 1E is a cross-sectional view of the semiconductor chip assembly after a fourth step of the fabrication process, illustrating how after a photolithographic step conductive bond ribbons can be formed over the assembly.
- FIG. 1F is a cross-sectional view of the semiconductor chip assembly after a fifth step of the fabrication process, showing how the assembly is coated with a second dielectric protective layer.
- FIG. 2 is a perspective view of the semiconductor chip assembly after the bond ribbons have been formed over the compliant layer but before the second dielectric protective layer is coated.
- FIG. 3 is a plan view of a wafer having a multiplicity of semiconductor chips, illustrating how said multiplicity of semiconductor chips can be simultaneously packaged using the semiconductor chip assembly process depicted in FIGS.1A-1F.
- FIG. 4 is a cross-sectional view of an alternate embodiment of the present invention, illustrating the use of a low modulus encapsulant material to provide further support and stress relief to the bond ribbons.
- FIG. 5A is a cross-sectional view of an alternate embodiment of the present invention, illustrating the formation of bumped protrusions in the compliant layer that raise the overlying terminals such that the terminals form an array over the top surface of the compliant layer.
- FIG. 5B is a perspective view of the embodiment shown in FIG. 5A.
- FIG. 6A is a cross-sectional view of an alternate embodiment of the present invention, illustrating the formation of concave areas in the compliant layer such that the overlying terminals have cup-like depressions useful for accurate placement of solder balls.
- FIG. 6B is a perspective view of the embodiment shown in FIG. 6A.
- FIGS.1A-F illustrate a side view of the process of creating the compliant chip package of the present invention on the face surface of a single die, on the face surfaces of multiple die arranged in a coplanar array or on the face surface of an undiced silicon wafer which may be subsequently diced into individual packaged chips or multi-chip modules.
- FIG. 1A shows a
single semiconductor chip 100 with a contact bearing face surface 120. Thecontacts 110 on the face surface 120 are typically aligned in aperipheral region 112 and further define acentral region 115 therein. In FIG. 1B, a dielectric passivation layer is deposited or adhered onto the face surface 120 of thechip 100. The passivation layer may simply be the SiO2 passivation layer (not shown) commonly found on the contact bearing surface of semiconductor chips, or a separatedielectric passivation layer 130 may be used, such as an epoxy resin, a polyimide resin, photo-imagable dielectric, etc. If theseparate passivation layer 130 is used, thepassivation layer 130 may be spun onto and built up to a planar sheet-like form on the face surface 120 or a dielectric sheet may be laminated to the face surface 120 using any of a number of electronic grade adhesives commonly known and used by those skilled in the art. Thepassivation layer 130 covers the face surface 120 of thechip 100 while leaving thechip contacts 110 exposed so that a bond ribbon may be plated thereon in a later step, as described below. Typically, this will be done by depositing or adhering thepassivation layer 130 in a continuous sheet on the face surface 120 of thechip 100. A registering system, such as an automatic vision system is used to locate thecontacts 110. If a photo-imagable dielectric is used, thepassivation layer 130 may be exposed and developed without exposing the area above thecontacts 110, that unexposed area may then be removed. Another removal process which can be used is to use a pulse of directed energy, such as an excimer laser, to selectively remove thepassivation layer 130 above thecontacts 110. Alternately, a continuous dielectric sheet already having set contact holes may be registered and laminated to thechip 100. - In the next step, as illustrated in FIG. 1C, a
compliant layer 140 is deposited or laminated onto the exposed surface of thepassivation layer 130. Thecompliant layer 140 may be stenciled, screened or transfer molded onto thepassivation layer 130 using a curable liquid which, when cured, adheres to thepassivation layer 130. Alternately, thecompliant layer 140 may be adhered to the exposed surface of thepassivation layer 130 in the form of cured compliant pads using the aforementioned electronic grade adhesives. Thecompliant layer 140 has a substantially flattop surface 147 which further typically has a gradual,sloping transition 145 between the face surface 120 of thechip 100 and thetop surface 147. Thistransition 145 may follow a line of curvature from thepassivation layer 130 to a substantially flattop surface 147 or may simply be canted at an angle such that thetransition 145 is not too vertically oriented in relation to thepassivation layer 130 and thetop surface 147. Thecompliant layer 140 itself may be formed from a wide variety of materials; however, preferably, a low modulus of elasticity material is used as thecompliant layer 140. Compliant interposers typically are fabricated from polymeric and other materials such as silicones, flexibilized epoxy, polyimides and other thermosetting polymers, fluoropolymers and thermoplastic polymers. Also, the interposer may be a composite incorporating plural materials. The interposer may consist of, or incorporate, a foam or mesh layer. The flexibility of the interposer depends on the thickness and configuration of the interposer, as well as on the properties of the materials used therein. Thus, a flexible interposer, capable of buckling or wrinkling to accommodate relative movement, can be fabricated from high elastic modulus materials, normally considered as “rigid” provided that these materials are present in thin layers. Relatively soft materials and foams can be used in greater thicknesses and still provide a highly flexible interposer. Moreover, such soft materials and foams provide a highly compliant interposer, i.e., an interposer which is readily compressible in the directions perpendicular its surfaces and which therefore permits movement of the terminals in these directions. - A
plating seed layer 150 is then deposited atop the aforementioned assembly, as shown in FIG. 1D, typically using a sputtering operation. Typical plating seed layer materials include palladium (for electroless plating), titanium, tungsten, nickel, chromium; however, primarily copper seed layers are used. FIG. 1E shows the next step in which photoresist 160 is applied to the exposed top surfaces of the assembly and then exposed and developed such thatbond ribbons 170 may be plated within defined areas to form conductive paths electrically connecting thechip contacts 110 near a first end region of theribbons 170 toterminals 175 comprising the second end region of theribbons 170. This is perhaps more easily seen in the perspective view shown in FIG. 2. As shown, theribbons 170 are plated directly onto thecontacts 110 and extend in a “fan-in” arrangement from theperipheral region 112 to thecentral region 115 of the face surface 120 of thechip 100 atop the compliant layer 14 Possible bond ribbon materials include copper, gold, nickel, and alloys, combinations and composites thereof, among others. Since thebond ribbons 170 are plated directly onto the chip contact/compliant layer themselves, there is no need to develop a process for bonding theribbons 170 to the contacts, as is necessary with most other approaches such as TAB, beam lead or wirebonding. This provides a significant cost savings because specialized thermocompression or ultrasonic bonders and their bonding tools need not be purchased or maintained. It is important, however, that the material selected for thebond ribbon 170 be compatible with thechip contact 110 material, which is typically aluminum. Otherwise, a phenomenon called Kirkendahl Voiding (voids created at the boundary of two metals having different interdiffusion coefficients) may cause voiding along the boundary of the two metals (ribbon/contact) leading to intermetallic degradation and embrittlement of thebond ribbon 170 itself making the lead/bond susceptible to failure during thermal cycling. Alternately, one or more barrier metals may be plated atop thechip contacts 110 prior to the bond ribbon plating step to thereby ensure the compatibility of materials. - As shown in FIG. 1F, preferably, a
dielectric layer 180 is deposited or laminated over the top of the assembly so that only theterminals 175 are exposed. The dielectric layer may be comprised of a screened, exposed and developed or laminated sheet photo resist material or may be comprised of pyralene, epoxy resin, polyimide resin, fluoropolymer, etc. which is deposited or laminated on to the assembly, as described above in relation to thepassivation layer 130. Theterminals 175 may then be electrically connected to a circuitized substrate, such as a printed wiring board. - Typically, a solder ball or a solid-core solder ball will be used to create this electrical connection. The
dielectric layer 180 is thus used as a solder mask to ensure that the solder does not electrically short betweenadjacent bond ribbons 170. Oxide layers and other surface contaminates typically build up on the surface of many types of metal (copper, nickel, etc.). Although not shown in FIG. 1F, theterminals 175 are typically flash plated with a thin layer of gold (approximately 0.25 to 0.5 microns) to inhibit the formation of these oxide layers. The gold layer is kept very thin so that it does not appreciably affect the aforementioned solder joint by dissolving into the solder to an amount which would embrittle the resulting solder joint between the terminal and a circuitized substrate. - The configuration of the above described chip package allows the package to mechanically decouple the
chip 100 from an attached circuitized substrate (not shown). Typically, solder connections between the chip and the circuitized substrate are woefully inadequate to compensate for the thermal mismatch problem during temperature cycling of the chip. The combination of thecompliant layer 140 and the flexible bond ribbons plated thereon allow the package to compensate for much of the TCE mismatch problem by giving limited movement of the terminals in the X, Y and Z directions with respect to thechip contacts 110 thereby minimizing the stress placed on the solder connections themselves, without imposing substantial forces on the bond between theribbons 170 and thechip contacts 110. Further, because thecompliant layer 140 is compressible, it also has the effect of compensating for anyterminals 175 which are not perfectly planar with respect to its adjacent terminals when theterminals 175 are abutted against and coupled to the circuitized substrate. However, thetop surface 147 of thecompliant layer 140 should be made as flat and planar as possible so that theterminals 175 all lie in or near the same plane in order to minimize the amount of pressure needed to be placed on thebottom surface 125 of thechip 100 to ensure that all of the terminals/solder balls are electrically connected to a circuitized substrate. - As illustrated in FIG. 3, the chip package described above in relation to FIGS. 1 and 2 may also be provided in the form of a multiplicity of packages on a wafer incorporating a plurality of individual, undiced chips, all of the same design or of differing designs. As shown, an array of individual passivation layers230 may be deposited or laminated onto the
face surface 220 of thewafer 200 leaving the chip contacts 210 of the various individual chips exposed, as described above. This arrangement is shown to better define the individual chips within the wafer. Preferably, however, asingle passivation layer 230 is deposited or laminated onto theface surface 220 leaving the contacts 210 exposed. Individualcompliant layers 240, as described above, are deposited or laminated onto the central regions of each of the individual chips within thewafer 200. The steps found in FIGS. 1A-F are then performed, as described above, to create a plurality of connected individually packaged chips on theface surface 220 of thewafer 200. Each packaged chip havingbond ribbons 270 which are connected at one end to contacts 210 and extending in to a central region of the respective chip in a fan-in fashion atop a respectivecompliant layer 240 and ending with a terminal 275 on thetop surface 247 of thecompliant layer 240. After the individual packages are completed, the individual chips may be separated from thewafer 200 and from one another, as by cutting thewafer 200 using conventional wafer severing or “dicing” equipment commonly utilized to sever wafers into individual chips. This procedure yields a plurality of packaged chip subassemblies, each of which may be secured to an individual circuitized substrate. Alternately, the chips may be separated from thewafer 200 in multi-chip arrangements of multiples of the same or different operational chips. The wafer level embodiment shown in FIG. 3 could be simulated using a panel of individual chips spaced apart from one another in a processing boat. The face surfaces of the individual chips would be coplanar with respect to one another to simulate theface surface 220 of thewafer 200. The chips above described steps would be performed and the chips would be separated if desired. - In the alternate embodiment shown in FIG. 4, a low
modulus encapsulant material 290 may be deposited around the exposed surfaces of thebond ribbons 170′ leads prior to the step shown in FIG. 1F of depositing or laminating the assembly with thedielectric layer 180′. Theencapsulant material 290 may have properties similar to those of rubber, gum or gel. Typical encapsulation materials include curable liquid or cured pads comprised of silicone, flexibilized epoxy, gels, thermoplastics, etc. If theencapsulant 290 is applied as a curable liquid, a fixture may be made such that the liquid flows around thebond ribbons 170′ but does not flow on top of theterminals 175′ to ensure that solder balls may be subsequently electrically connected to theterminals 175′, as described above. Alternately, a machine such as a Camalot 1818 manufactured by Camalot Systems, Inc. of Havermill, Mass. may be used to flow the liquid encapsulant into the desired areas. After the liquid is deposited, it may be cured by any number of ways depending on theencapsulant material 290 used, e.g. heat, infrared energy, etc. Theencapsulant 290 gives each of thebond ribbons 170′ more support and further spreads some of the stress away from theribbons 170′ thus allowing a larger TCE mismatch between the chip and a circuitized substrate, as described above. After curing of theencapsulant 290, thedielectric layer 180′ may be deposited or laminated thereto. - In another alternate embodiment, a conductive material such as beryllium copper, or a super plastic or shape memory alloy (such as Nitinol), is sputtered or otherwise deposited across the entire exposed surface of the chip/passivation layer/compliant layer (100/130/140) combination, shown in FIG. 1C. The conductive material may then be etched using industry standard photolithographic techniques resulting in a multiplicity of bond ribbons positioned and configured much like the
bond ribbons 170 shown in FIG. 1E and FIG. 2. In this embodiment, as described above, a barrier metal, such as a flash plated layer of gold, may first be plated to the chip contacts to ensure compatibility of the electrical connection between the chip contact and the bond ribbon. Likewise, a flash plated layer of gold may be plated atop the exposed surface of the terminal. Also, the entire exposed surface of the bond ribbon could be plated with a thin layer of gold to increase the overall conductivity of such super plastic leads. A dielectric layer is next deposited or laminated as shown in FIG. 1F. - FIG. 5A shows a side view and FIG. 5B a perspective view of another embodiment, according to the present invention. In this embodiment, the
compliant layer 140′ hasprotrusions 300 on itstop surface 147′. Theseprotrusions 300 may be integral with thecompliant layer 140′ or may be deposited or laminated onto thetop surface 147′ subsequent to the formation of thecompliant layer 140′. Theprotrusions 300 may be formed of compliant, elastomeric material, such as the material comprising thecompliant layer 140′, or may be comprised of a semi-rigid or rigid material. Thebond ribbon terminals 175′ are plated on top of theprotrusions 300 thereby providing raised surfaces which may be connected to a circuitized substrate. This technique allows for connection to such a substrate using less solder and without the need to accurately position solid-core solder balls. - FIG. 6A shows a side view and FIG. 6B a perspective view of another embodiment, according to the present invention. In this embodiment,
concave areas 310 are created in thecompliant layer 140″. Theseconcave areas 310 may be create in the formation of thecompliant layer 140″ or may be created subsequent to the formation of thecompliant layer 140″. Thebond ribbon terminals 175″ are plated within theconcave areas 310 creating conductive “cup-like” areas on thetop surface 147″ of thecompliant layer 140″. Solder or solid-core solder balls are then placed within theseareas 310 and reflowed to attach the package to a circuitized substrate, as described earlier. This technique allows for the accurate placement of solder or solid-core solder balls by allowing them to be deposited and retained within the cup-like areas. - As these and other variations and combinations of the features discussed above can be utilized without departing from the present invention as defined by the claims, the foregoing description of the preferred embodiments should be taken by way of illustration rather than by way of limitation of the invention set forth in the claims.
Claims (20)
1. A method of creating a compliant semiconductor chip package assembly comprising the steps of:
providing a first dielectric protective layer on a contact bearing surface of a semiconductor chip, wherein the semiconductor chip has a central region bonded by chip contacts of the semiconductor chip and wherein the dielectric protective layer has a plurality of apertures such that the chip contacts are exposed;
providing a compliant layer atop the first dielectric protective layer within the central region, wherein said compliant layer has a substantially flat top surface, a bottom surface that is attached to the first dielectric protective layer and sloping edges between the top surface and the bottom surface; and
selectively electroplating bond ribbons atop the first dielectric protective layer and the compliant layer wherein each bond ribbon electrically connects each chip contact to a respective conductive terminal on the top surface of the compliant layer.
2. The method cording to claim 1 further including the step of providing a second dielectric protective layer atop exposed assembly elements on the terminal side of the assembly after the step of selectively electroplating the bond ribbons, wherein the second dielectric protective layer has a plurality of apertures such that the terminals are exposed.
3. The method according to claim 1 wherein the compliant layer material is selected from the group consisting of silicone, flexibilized epoxy, a thermosetting polymer, fluoropolymer, thermoplastic polymer, polyimide, foams and combinations or composites thereof.
4. The method according to claim 1 further including the step of providing for an encapsulant layer atop the exposed surface of the bond ribbons.
5. The method according to claim 4 wherein the encapsulant layer material is selected from the group consisting of silicone, flexibilized epoxy, thermoplastic and gel.
6. The method according to claim 4 further including the step of providing for a second dielectric protective layer. atop the encapsulant layer wherein the second dielectric protective layer has a plurality of apertures such that the terminal positions are exposed.
7. The method according to claim 1 wherein a silicon dioxide passivation layer on the face surface of the semiconductor chip comprises the first dielectric protective layer.
8. The method according to claim 1 further including the step of plating a barrier metal atop the semiconductor chip contacts, prior to the step of providing the compliant layer, whereby the barrier metal helps to prevent voiding at the boundary between the semiconductor chip contacts and the bond ribbons.
9. The method according to claim 1 applied simultaneously to a multiplicity of undiced semiconductor chips on a wafer to form a corresponding multiplicity of compliant semiconductor chip packages, the method further including the step of dicing the packages following the step for selectively electroplating the bond ribbons.
10. The method according to claim 1 applied simultaneously to a multiplicity of adjacent semiconductor chips arranged in an array to form a corresponding multiplicity of compliant semiconductor chip packages, the method further including the step of dicing the packages following the step for selectively electroplating the bond ribbons.
11. The method according to claim 1 wherein the sloping edges of the compliant layer have a first transition region near the top surface of the compliant layer and a second transition region near the bottom surface of the compliant layer and wherein both the first transition region and the second transition region have a radius of curvature.
12. A compliant semiconductor chip package assembly comprising:
a semiconductor chip having a plurality of peripheral chip contacts on a face surface thereof and a central region bound by the peripheral chip contacts;
a first dielectric protective layer having a first surface, a second surface and apertures, wherein the first surface of the first dielectric layer is attached to the face surface of the semiconductor chip and the apertures are aligned so that the chip contacts are exposed;
a compliant layer having a top surface, a bottom surface and sloping peripheral edges, wherein the bottom surface of the compliant layer is joined to the second surface of the first dielectric layer within the central region of the semiconductor chip package; and
a plurality of electrically conductive bond ribbons, each bond ribbon having a top surface, a bottom surface, a first end that electrically couples to a respective peripheral chip contact of the semiconductor chip, wherein each bond ribbon extends along the sloping edges to the top surface of the compliant layer and connects to a respective terminal.
13. The compliant semiconductor chip package of claim 12 further including a second dielectric protective layer having a first surface that is attached to the exposed package assembly elements, wherein the second dielectric layer has a plurality of apertures such that the bonding pads of the semiconductor chip are exposed.
14. The compliant semiconductor chip package of claim 12 further comprised of an encapsulant layer that is attached to the top surface of the bond ribbons.
15. The compliant semiconductor chip package of claim 14 wherein the encapsulant layer material is selected from the group consisting of a curable liquid, silicone, flexibilized epoxy, thermoplastic and gel.
16. The compliant semiconductor chip package of claim 12 wherein the plurality of package terminals are configured in an array having an area that is smaller than the area bound by the peripheral bonding pads on the face of the semiconductor chip.
17. The compliant semiconductor chip package of claim 12 , wherein the peripheral edge of the compliant layer has a first transition region near the top surface of the compliant layer and a second transition region near the second surface of the first dielectric protective layer and wherein the first and second transition regions have a radius of curvature.
18. The compliant semiconductor chip package of claim 12 , wherein the compliant layer material is selected from the group consisting of silicone, flexibilized epoxy, a thermosetting polymer, fluoropolymer, thermoplastic polymer and polyimide.
19. The compliant semiconductor chip package of claim 12 , wherein a plurality of bumped protrusions are provided and underly the plurality of package terminals such that an array of bumped package terminals is formed.
20. The compliant semiconductor chip package of claim 12 , wherein the top surface of the compliant layer has a plurality of concavities underlying the plurality of package terminals such that an array of concave-like package terminals is formed.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/020,647 US20020115236A1 (en) | 1995-10-31 | 1998-02-09 | Methods of making compliant semiconductor chip packages |
US12/587,714 US8558386B2 (en) | 1995-10-31 | 2009-10-13 | Methods of making compliant semiconductor chip packages |
US14/035,475 US20140042634A1 (en) | 1995-10-31 | 2013-09-24 | Methods of making compliant semiconductor chip packages |
US14/662,579 US20150194347A1 (en) | 1995-10-31 | 2015-03-19 | Methods of making compliant semiconductor chip packages |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US712895P | 1995-10-31 | 1995-10-31 | |
US08/739,303 US6211572B1 (en) | 1995-10-31 | 1996-10-29 | Semiconductor chip package with fan-in leads |
US09/020,647 US20020115236A1 (en) | 1995-10-31 | 1998-02-09 | Methods of making compliant semiconductor chip packages |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/739,303 Division US6211572B1 (en) | 1995-10-31 | 1996-10-29 | Semiconductor chip package with fan-in leads |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/587,714 Continuation US8558386B2 (en) | 1995-10-31 | 2009-10-13 | Methods of making compliant semiconductor chip packages |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020115236A1 true US20020115236A1 (en) | 2002-08-22 |
Family
ID=26676567
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/739,303 Expired - Lifetime US6211572B1 (en) | 1995-10-31 | 1996-10-29 | Semiconductor chip package with fan-in leads |
US09/020,647 Abandoned US20020115236A1 (en) | 1995-10-31 | 1998-02-09 | Methods of making compliant semiconductor chip packages |
US12/587,714 Expired - Fee Related US8558386B2 (en) | 1995-10-31 | 2009-10-13 | Methods of making compliant semiconductor chip packages |
US14/035,475 Abandoned US20140042634A1 (en) | 1995-10-31 | 2013-09-24 | Methods of making compliant semiconductor chip packages |
US14/662,579 Abandoned US20150194347A1 (en) | 1995-10-31 | 2015-03-19 | Methods of making compliant semiconductor chip packages |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/739,303 Expired - Lifetime US6211572B1 (en) | 1995-10-31 | 1996-10-29 | Semiconductor chip package with fan-in leads |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/587,714 Expired - Fee Related US8558386B2 (en) | 1995-10-31 | 2009-10-13 | Methods of making compliant semiconductor chip packages |
US14/035,475 Abandoned US20140042634A1 (en) | 1995-10-31 | 2013-09-24 | Methods of making compliant semiconductor chip packages |
US14/662,579 Abandoned US20150194347A1 (en) | 1995-10-31 | 2015-03-19 | Methods of making compliant semiconductor chip packages |
Country Status (1)
Country | Link |
---|---|
US (5) | US6211572B1 (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020150194A1 (en) * | 2000-07-27 | 2002-10-17 | Lucian Wielopolski | Method and device for non-invasive soil carbon content and distribution measurements |
US20030024735A1 (en) * | 2001-08-01 | 2003-02-06 | Volker Strutz | Protective device for subassemblies and method for producing a protective device |
US6617674B2 (en) * | 2001-02-20 | 2003-09-09 | Dow Corning Corporation | Semiconductor package and method of preparing same |
US20040217453A1 (en) * | 1998-10-28 | 2004-11-04 | Masahiko Ogino | Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device |
US20050208703A1 (en) * | 1999-06-17 | 2005-09-22 | Infineon Technologies, Ag | Method of producing an electronic component with flexible bonding pads |
DE102005018280B4 (en) * | 2004-04-14 | 2008-02-07 | Samsung Electronics Co., Ltd., Suwon | Method for producing a semiconductor device with bump structures and semiconductor device |
US20080315424A1 (en) * | 2001-03-30 | 2008-12-25 | Megica Corporation | Structure and manufactruing method of chip scale package |
US20090057901A1 (en) * | 2001-09-17 | 2009-03-05 | Megica Corporation | Structure of high performance combo chip and processing method |
US20090305494A1 (en) * | 2004-04-14 | 2009-12-10 | Yonghwan Kwon | Bump structure for a semiconductor device and method of manufacture |
US7960272B2 (en) | 2002-10-24 | 2011-06-14 | Megica Corporation | Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging |
US8148806B2 (en) | 2000-05-19 | 2012-04-03 | Megica Corporation | Multiple chips bonded to packaging structure with low noise and multiple selectable functions |
US8338925B2 (en) | 1995-10-31 | 2012-12-25 | Tessera, Inc. | Microelectronic assemblies having compliant layers |
Families Citing this family (106)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6870272B2 (en) * | 1994-09-20 | 2005-03-22 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
US6211572B1 (en) * | 1995-10-31 | 2001-04-03 | Tessera, Inc. | Semiconductor chip package with fan-in leads |
US6881611B1 (en) | 1996-07-12 | 2005-04-19 | Fujitsu Limited | Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device |
JP3335575B2 (en) * | 1997-06-06 | 2002-10-21 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
US6441473B1 (en) * | 1997-09-12 | 2002-08-27 | Agere Systems Guardian Corp. | Flip chip semiconductor device |
SG73490A1 (en) | 1998-01-23 | 2000-06-20 | Texas Instr Singapore Pte Ltd | High density internal ball grid array integrated circuit package |
US6333565B1 (en) * | 1998-03-23 | 2001-12-25 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
US6468638B2 (en) | 1999-03-16 | 2002-10-22 | Alien Technology Corporation | Web process interconnect in electronic assemblies |
US6500528B1 (en) * | 1999-04-27 | 2002-12-31 | Tessera, Inc. | Enhancements in sheet processing and lead formation |
AU5109900A (en) * | 1999-06-15 | 2001-01-02 | Fujikura Ltd. | Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package |
US6228687B1 (en) * | 1999-06-28 | 2001-05-08 | Micron Technology, Inc. | Wafer-level package and methods of fabricating |
US7019410B1 (en) * | 1999-12-21 | 2006-03-28 | Micron Technology, Inc. | Die attach material for TBGA or flexible circuitry |
DE10016132A1 (en) * | 2000-03-31 | 2001-10-18 | Infineon Technologies Ag | Electronic component for electronic devices comprises electronic switch and conducting paths on surface of the component to electrically connect the switch with metal-coated protrusions made from rubber-elastic insulating material |
JP3596864B2 (en) * | 2000-05-25 | 2004-12-02 | シャープ株式会社 | Semiconductor device |
JP3440070B2 (en) * | 2000-07-13 | 2003-08-25 | 沖電気工業株式会社 | Wafer and method of manufacturing wafer |
US6606247B2 (en) * | 2001-05-31 | 2003-08-12 | Alien Technology Corporation | Multi-feature-size electronic structures |
SG102639A1 (en) * | 2001-10-08 | 2004-03-26 | Micron Technology Inc | Apparatus and method for packing circuits |
US6747348B2 (en) * | 2001-10-16 | 2004-06-08 | Micron Technology, Inc. | Apparatus and method for leadless packaging of semiconductor devices |
US7214569B2 (en) * | 2002-01-23 | 2007-05-08 | Alien Technology Corporation | Apparatus incorporating small-feature-size and large-feature-size components and method for making same |
US7423336B2 (en) | 2002-04-08 | 2008-09-09 | Micron Technology, Inc. | Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices |
US7002225B2 (en) * | 2002-05-24 | 2006-02-21 | Northrup Grumman Corporation | Compliant component for supporting electrical interface component |
SG142115A1 (en) * | 2002-06-14 | 2008-05-28 | Micron Technology Inc | Wafer level packaging |
JP3969295B2 (en) * | 2002-12-02 | 2007-09-05 | セイコーエプソン株式会社 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, CIRCUIT BOARD, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE |
JP2004288816A (en) * | 2003-03-20 | 2004-10-14 | Seiko Epson Corp | Semiconductor wafer, semiconductor device and its manufacturing process, circuit board and electronic apparatus |
US7253735B2 (en) | 2003-03-24 | 2007-08-07 | Alien Technology Corporation | RFID tags and processes for producing RFID tags |
JP3693056B2 (en) * | 2003-04-21 | 2005-09-07 | セイコーエプソン株式会社 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, ELECTRONIC DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
SG119185A1 (en) * | 2003-05-06 | 2006-02-28 | Micron Technology Inc | Method for packaging circuits and packaged circuits |
DE10324450A1 (en) * | 2003-05-28 | 2005-01-05 | Infineon Technologies Ag | Contacting device for electronic circuit units and manufacturing method |
DE10345395B4 (en) | 2003-09-30 | 2006-09-14 | Infineon Technologies Ag | Semiconductor module and method for producing a semiconductor module |
US20050093170A1 (en) * | 2003-10-29 | 2005-05-05 | Texas Instruments Incorporated | Integrated interconnect package |
US7294929B2 (en) * | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
JP2005241275A (en) * | 2004-02-24 | 2005-09-08 | Japan Electronic Materials Corp | Probe card |
DE102004025684A1 (en) | 2004-04-29 | 2005-11-17 | Osram Opto Semiconductors Gmbh | Optoelectronic semiconductor chip and method for forming a contact structure for electrically contacting an optoelectronic semiconductor chip |
KR101313391B1 (en) | 2004-11-03 | 2013-10-01 | 테세라, 인코포레이티드 | Stacked packaging improvements |
JP3992038B2 (en) * | 2004-11-16 | 2007-10-17 | セイコーエプソン株式会社 | Electronic element mounting method, electronic device manufacturing method, circuit board, electronic device |
US7385284B2 (en) * | 2004-11-22 | 2008-06-10 | Alien Technology Corporation | Transponder incorporated into an electronic device |
US20060109130A1 (en) * | 2004-11-22 | 2006-05-25 | Hattick John B | Radio frequency identification (RFID) tag for an item having a conductive layer included or attached |
US7688206B2 (en) | 2004-11-22 | 2010-03-30 | Alien Technology Corporation | Radio frequency identification (RFID) tag for an item having a conductive layer included or attached |
US7456046B2 (en) * | 2005-02-23 | 2008-11-25 | International Business Machines Corporation | Method to create flexible connections for integrated circuits |
WO2006091793A1 (en) | 2005-02-25 | 2006-08-31 | Tessera, Inc. | Microelectronic assemblies having compliancy |
US7939934B2 (en) | 2005-03-16 | 2011-05-10 | Tessera, Inc. | Microelectronic packages and methods therefor |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7534652B2 (en) * | 2005-12-27 | 2009-05-19 | Tessera, Inc. | Microelectronic elements with compliant terminal mountings and methods for making the same |
US7674701B2 (en) | 2006-02-08 | 2010-03-09 | Amkor Technology, Inc. | Methods of forming metal layers using multi-layer lift-off patterns |
US7932615B2 (en) * | 2006-02-08 | 2011-04-26 | Amkor Technology, Inc. | Electronic devices including solder bumps on compliant dielectric layers |
US7749886B2 (en) * | 2006-12-20 | 2010-07-06 | Tessera, Inc. | Microelectronic assemblies having compliancy and methods therefor |
US7691682B2 (en) * | 2007-06-26 | 2010-04-06 | Micron Technology, Inc. | Build-up-package for integrated circuit devices, and methods of making same |
US8193092B2 (en) | 2007-07-31 | 2012-06-05 | Micron Technology, Inc. | Semiconductor devices including a through-substrate conductive member with an exposed end and methods of manufacturing such semiconductor devices |
KR101391040B1 (en) * | 2007-08-09 | 2014-04-30 | 삼성전자주식회사 | Printed circuit board and fabricating method thereof and electrical apparatus using the same |
CN102474033B (en) * | 2009-07-01 | 2015-06-17 | 皇家飞利浦电子股份有限公司 | Low cost-low profile lead set connector |
SG169241A1 (en) * | 2009-08-12 | 2011-03-30 | Sony Corp | An integrated circuit |
US8227918B2 (en) | 2009-09-16 | 2012-07-24 | International Business Machines Corporation | Robust FBEOL and UBM structure of C4 interconnects |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US8198739B2 (en) | 2010-08-13 | 2012-06-12 | Endicott Interconnect Technologies, Inc. | Semi-conductor chip with compressible contact structure and electronic package utilizing same |
KR101075241B1 (en) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | Microelectronic package with terminals on dielectric mass |
US20120146206A1 (en) | 2010-12-13 | 2012-06-14 | Tessera Research Llc | Pin attachment |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
KR101128063B1 (en) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | Package-on-package assembly with wire bonds to encapsulation surface |
US9105483B2 (en) | 2011-10-17 | 2015-08-11 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
EP2740818B1 (en) * | 2012-12-05 | 2016-03-30 | ATOTECH Deutschland GmbH | Method for manufacture of wire bondable and solderable surfaces on noble metal electrodes |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
CN104051384B (en) * | 2013-03-13 | 2017-09-29 | 台湾积体电路制造股份有限公司 | The method for packing and device of semiconductor devices |
US9082870B2 (en) | 2013-03-13 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of packaging semiconductor devices |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9627224B2 (en) | 2015-03-30 | 2017-04-18 | Stmicroelectronics, Inc. | Semiconductor device with sloped sidewall and related methods |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
TWI592955B (en) * | 2015-06-25 | 2017-07-21 | Wafer Mems Co Ltd | Embedded passive components and methods of mass production |
TWI555044B (en) * | 2015-06-25 | 2016-10-21 | Wafer Mems Co Ltd | A method for producing a passive element with a terminal electrode |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
USD887998S1 (en) | 2017-02-17 | 2020-06-23 | Stat Peel Ag | Chip |
US11652031B2 (en) * | 2018-12-13 | 2023-05-16 | Intel Corporation | Shrinkable package assembly |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4977441A (en) * | 1985-12-25 | 1990-12-11 | Hitachi, Ltd. | Semiconductor device and tape carrier |
US5187020A (en) * | 1990-07-31 | 1993-02-16 | Texas Instruments Incorporated | Compliant contact pad |
US5682061A (en) * | 1990-09-24 | 1997-10-28 | Tessera, Inc. | Component for connecting a semiconductor chip to a substrate |
US6326678B1 (en) * | 1993-09-03 | 2001-12-04 | Asat, Limited | Molded plastic package with heat sink and enhanced electrical performance |
US6870272B2 (en) * | 1994-09-20 | 2005-03-22 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
Family Cites Families (122)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3680206A (en) * | 1969-06-23 | 1972-08-01 | Ferranti Ltd | Assemblies of semiconductor devices having mounting pillars as circuit connections |
US4001870A (en) * | 1972-08-18 | 1977-01-04 | Hitachi, Ltd. | Isolating protective film for semiconductor devices and method for making the same |
GB1487945A (en) * | 1974-11-20 | 1977-10-05 | Ibm | Semiconductor integrated circuit devices |
US4074342A (en) * | 1974-12-20 | 1978-02-14 | International Business Machines Corporation | Electrical package for lsi devices and assembly process therefor |
JPS5321771A (en) * | 1976-08-11 | 1978-02-28 | Sharp Kk | Electronic parts mounting structure |
US4300153A (en) | 1977-09-22 | 1981-11-10 | Sharp Kabushiki Kaisha | Flat shaped semiconductor encapsulation |
US4284563A (en) * | 1978-02-08 | 1981-08-18 | Research Corporation | 9,10,11,12,12-Pentachloro 4,6-dioxa-5-thia-1-aza-tricyclo[7.2.1.02,8 ]d |
JPS5519850A (en) * | 1978-07-31 | 1980-02-12 | Hitachi Ltd | Semiconductor |
US4396936A (en) * | 1980-12-29 | 1983-08-02 | Honeywell Information Systems, Inc. | Integrated circuit chip package with improved cooling means |
US4381602A (en) * | 1980-12-29 | 1983-05-03 | Honeywell Information Systems Inc. | Method of mounting an I.C. chip on a substrate |
JPS601846A (en) * | 1983-06-18 | 1985-01-08 | Toshiba Corp | Multilayer interconnection structure semiconductor device and manufacture thereof |
US5310699A (en) * | 1984-08-28 | 1994-05-10 | Sharp Kabushiki Kaisha | Method of manufacturing a bump electrode |
US4642889A (en) * | 1985-04-29 | 1987-02-17 | Amp Incorporated | Compliant interconnection and method therefor |
US4671849A (en) * | 1985-05-06 | 1987-06-09 | International Business Machines Corporation | Method for control of etch profile |
JPS6218739A (en) * | 1985-07-18 | 1987-01-27 | Sumitomo Electric Ind Ltd | Hybrid integrated circuit |
US6043563A (en) * | 1997-05-06 | 2000-03-28 | Formfactor, Inc. | Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals |
US4716049A (en) | 1985-12-20 | 1987-12-29 | Hughes Aircraft Company | Compressive pedestal for microminiature connections |
US4902606A (en) | 1985-12-20 | 1990-02-20 | Hughes Aircraft Company | Compressive pedestal for microminiature connections |
US4924353A (en) * | 1985-12-20 | 1990-05-08 | Hughes Aircraft Company | Connector system for coupling to an integrated circuit chip |
US5302550A (en) * | 1985-12-24 | 1994-04-12 | Mitsubishi Denki Kabushiki Kaisha | Method of bonding a microelectronic device |
US4885126A (en) | 1986-10-17 | 1989-12-05 | Polonio John D | Interconnection mechanisms for electronic components |
US4813129A (en) | 1987-06-19 | 1989-03-21 | Hewlett-Packard Company | Interconnect structure for PC boards and integrated circuits |
JPH01129431A (en) * | 1987-11-16 | 1989-05-22 | Sharp Corp | Mounting system of semiconductor chip |
US4783594A (en) | 1987-11-20 | 1988-11-08 | Santa Barbara Research Center | Reticular detector array |
JPH0715087B2 (en) * | 1988-07-21 | 1995-02-22 | リンテック株式会社 | Adhesive tape and method of using the same |
US5001542A (en) * | 1988-12-05 | 1991-03-19 | Hitachi Chemical Company | Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips |
US4962985A (en) * | 1989-10-02 | 1990-10-16 | At&T Bell Laboratories | Protective coatings for optical devices comprising Langmuir-Blodgett films |
US5082811A (en) * | 1990-02-28 | 1992-01-21 | E. I. Du Pont De Nemours And Company | Ceramic dielectric compositions and method for enhancing dielectric properties |
US5656862A (en) * | 1990-03-14 | 1997-08-12 | International Business Machines Corporation | Solder interconnection structure |
US5070297A (en) * | 1990-06-04 | 1991-12-03 | Texas Instruments Incorporated | Full wafer integrated circuit testing device |
US5679977A (en) | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5072520A (en) | 1990-10-23 | 1991-12-17 | Rogers Corporation | Method of manufacturing an interconnect device having coplanar contact bumps |
US5140404A (en) * | 1990-10-24 | 1992-08-18 | Micron Technology, Inc. | Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
US5180311A (en) | 1991-01-22 | 1993-01-19 | Hughes Aircraft Company | Resilient interconnection bridge |
JP2593965B2 (en) * | 1991-01-29 | 1997-03-26 | 三菱電機株式会社 | Semiconductor device |
JP2958136B2 (en) * | 1991-03-08 | 1999-10-06 | 株式会社日立製作所 | Semiconductor integrated circuit device, its manufacturing method and mounting structure |
US5265329A (en) | 1991-06-12 | 1993-11-30 | Amp Incorporated | Fiber-filled elastomeric connector attachment method and product |
US5225966A (en) * | 1991-07-24 | 1993-07-06 | At&T Bell Laboratories | Conductive adhesive film techniques |
US5316788A (en) * | 1991-07-26 | 1994-05-31 | International Business Machines Corporation | Applying solder to high density substrates |
US5194930A (en) * | 1991-09-16 | 1993-03-16 | International Business Machines | Dielectric composition and solder interconnection structure for its use |
JP2927081B2 (en) * | 1991-10-30 | 1999-07-28 | 株式会社デンソー | Resin-sealed semiconductor device |
JPH05175280A (en) | 1991-12-20 | 1993-07-13 | Rohm Co Ltd | Packaging structure of semiconductor device and method of packaging |
US5203076A (en) * | 1991-12-23 | 1993-04-20 | Motorola, Inc. | Vacuum infiltration of underfill material for flip-chip devices |
US5212402A (en) * | 1992-02-14 | 1993-05-18 | Motorola, Inc. | Semiconductor device with integral decoupling capacitor |
US5401983A (en) * | 1992-04-08 | 1995-03-28 | Georgia Tech Research Corporation | Processes for lift-off of thin film materials or devices for fabricating three dimensional integrated circuits, optical detectors, and micromechanical devices |
US5249101A (en) * | 1992-07-06 | 1993-09-28 | International Business Machines Corporation | Chip carrier with protective coating for circuitized surface |
AU4782293A (en) * | 1992-07-24 | 1994-02-14 | Tessera, Inc. | Semiconductor connection components and methods with releasable lead support |
US5371404A (en) | 1993-02-04 | 1994-12-06 | Motorola, Inc. | Thermally conductive integrated circuit package with radio frequency shielding |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5414298A (en) * | 1993-03-26 | 1995-05-09 | Tessera, Inc. | Semiconductor chip assemblies and components with pressure contact |
JP3269171B2 (en) | 1993-04-08 | 2002-03-25 | セイコーエプソン株式会社 | Semiconductor device and clock having the same |
US5355283A (en) | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
JP3445641B2 (en) * | 1993-07-30 | 2003-09-08 | 株式会社デンソー | Semiconductor device |
US5483741A (en) * | 1993-09-03 | 1996-01-16 | Micron Technology, Inc. | Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice |
US5477611A (en) | 1993-09-20 | 1995-12-26 | Tessera, Inc. | Method of forming interface between die and chip carrier |
JP3214186B2 (en) * | 1993-10-07 | 2001-10-02 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
JPH07115096A (en) | 1993-10-18 | 1995-05-02 | Fujitsu Ltd | Bump electrode |
US5772451A (en) * | 1993-11-16 | 1998-06-30 | Form Factor, Inc. | Sockets for electronic components and methods of connecting to electronic components |
US5431571A (en) * | 1993-11-22 | 1995-07-11 | W. L. Gore & Associates, Inc. | Electrical conductive polymer matrix |
US5455390A (en) | 1994-02-01 | 1995-10-03 | Tessera, Inc. | Microelectronics unit mounting with multiple lead bonding |
US5508228A (en) * | 1994-02-14 | 1996-04-16 | Microelectronics And Computer Technology Corporation | Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same |
US5536855A (en) * | 1994-03-04 | 1996-07-16 | National Starch And Chemical Investment Holding Corporation | Process for preparing glycidyl esters for use in electronics adhesives |
US5393697A (en) * | 1994-05-06 | 1995-02-28 | Industrial Technology Research Institute | Composite bump structure and methods of fabrication |
US5431328A (en) * | 1994-05-06 | 1995-07-11 | Industrial Technology Research Institute | Composite bump flip chip bonding |
US5656547A (en) * | 1994-05-11 | 1997-08-12 | Chipscale, Inc. | Method for making a leadless surface mounted device with wrap-around flange interface contacts |
US6359335B1 (en) * | 1994-05-19 | 2002-03-19 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures |
US6177636B1 (en) * | 1994-12-29 | 2001-01-23 | Tessera, Inc. | Connection components with posts |
US5491302A (en) * | 1994-09-19 | 1996-02-13 | Tessera, Inc. | Microelectronic bonding with lead motion |
US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
US5929517A (en) * | 1994-12-29 | 1999-07-27 | Tessera, Inc. | Compliant integrated circuit package and method of fabricating the same |
US5734547A (en) * | 1995-02-13 | 1998-03-31 | Iversen; Arthur H. | Power switchgear |
US5707902A (en) * | 1995-02-13 | 1998-01-13 | Industrial Technology Research Institute | Composite bump structure and methods of fabrication |
US5801446A (en) * | 1995-03-28 | 1998-09-01 | Tessera, Inc. | Microelectronic connections with solid core joining units |
US5874781A (en) * | 1995-08-16 | 1999-02-23 | Micron Technology, Inc. | Angularly offset stacked die multichip device and method of manufacture |
US5777379A (en) | 1995-08-18 | 1998-07-07 | Tessera, Inc. | Semiconductor assemblies with reinforced peripheral regions |
US5874782A (en) | 1995-08-24 | 1999-02-23 | International Business Machines Corporation | Wafer with elevated contact structures |
US5766987A (en) * | 1995-09-22 | 1998-06-16 | Tessera, Inc. | Microelectronic encapsulation methods and equipment |
US6284563B1 (en) * | 1995-10-31 | 2001-09-04 | Tessera, Inc. | Method of making compliant microelectronic assemblies |
US6211572B1 (en) * | 1995-10-31 | 2001-04-03 | Tessera, Inc. | Semiconductor chip package with fan-in leads |
US5749997A (en) | 1995-12-27 | 1998-05-12 | Industrial Technology Research Institute | Composite bump tape automated bonding method and bonded structure |
US5789271A (en) * | 1996-03-18 | 1998-08-04 | Micron Technology, Inc. | Method for fabricating microbump interconnect for bare semiconductor dice |
AU3141297A (en) * | 1996-05-24 | 1997-12-09 | Tessera, Inc. | Connectors for microelectronic elements |
US6030856A (en) * | 1996-06-10 | 2000-02-29 | Tessera, Inc. | Bondable compliant pads for packaging of a semiconductor chip and method therefor |
US5790377A (en) * | 1996-09-12 | 1998-08-04 | Packard Hughes Interconnect Company | Integral copper column with solder bump flip chip |
US6255738B1 (en) * | 1996-09-30 | 2001-07-03 | Tessera, Inc. | Encapsulant for microelectronic devices |
US6054337A (en) | 1996-12-13 | 2000-04-25 | Tessera, Inc. | Method of making a compliant multichip package |
US6130116A (en) | 1996-12-13 | 2000-10-10 | Tessera, Inc. | Method of encapsulating a microelectronic assembly utilizing a barrier |
KR100563585B1 (en) | 1997-03-10 | 2006-03-22 | 세이코 엡슨 가부시키가이샤 | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
US6051489A (en) * | 1997-05-13 | 2000-04-18 | Chipscale, Inc. | Electronic component package with posts on the active side of the substrate |
US6313402B1 (en) | 1997-10-29 | 2001-11-06 | Packard Hughes Interconnect Company | Stress relief bend useful in an integrated circuit redistribution patch |
US5937758A (en) * | 1997-11-26 | 1999-08-17 | Motorola, Inc. | Micro-contact printing stamp |
US5956235A (en) | 1998-02-12 | 1999-09-21 | International Business Machines Corporation | Method and apparatus for flexibly connecting electronic devices |
US6337445B1 (en) * | 1998-03-16 | 2002-01-08 | Texas Instruments Incorporated | Composite connection structure and method of manufacturing |
US6642136B1 (en) | 2001-09-17 | 2003-11-04 | Megic Corporation | Method of making a low fabrication cost, high performance, high reliability chip scale package |
US6184576B1 (en) * | 1998-09-21 | 2001-02-06 | Advantest Corp. | Packaging and interconnection of contact structure |
US6197613B1 (en) * | 1999-03-23 | 2001-03-06 | Industrial Technology Research Institute | Wafer level packaging method and devices formed |
US6507095B1 (en) * | 1999-03-25 | 2003-01-14 | Seiko Epson Corporation | Wiring board, connected board and semiconductor device, method of manufacture thereof, circuit board, and electronic instrument |
US6537854B1 (en) * | 1999-05-24 | 2003-03-25 | Industrial Technology Research Institute | Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed |
JP2003502866A (en) * | 1999-06-17 | 2003-01-21 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Electronic component having a soft bond and method for manufacturing such a component |
US6277669B1 (en) * | 1999-09-15 | 2001-08-21 | Industrial Technology Research Institute | Wafer level packaging method and packages formed |
US6555908B1 (en) * | 2000-02-10 | 2003-04-29 | Epic Technologies, Inc. | Compliant, solderable input/output bump structures |
DE10014300A1 (en) * | 2000-03-23 | 2001-10-04 | Infineon Technologies Ag | Semiconductor component and method for its production |
US6767818B1 (en) * | 2000-08-07 | 2004-07-27 | Industrial Technology Research Institute | Method for forming electrically conductive bumps and devices formed |
US6462575B1 (en) | 2000-08-28 | 2002-10-08 | Micron Technology, Inc. | Method and system for wafer level testing and burning-in semiconductor components |
US6710456B1 (en) * | 2000-08-31 | 2004-03-23 | Micron Technology, Inc. | Composite interposer for BGA packages |
JP4174174B2 (en) * | 2000-09-19 | 2008-10-29 | 株式会社ルネサステクノロジ | Semiconductor device, manufacturing method thereof, and semiconductor device mounting structure |
US6433427B1 (en) * | 2001-01-16 | 2002-08-13 | Industrial Technology Research Institute | Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication |
US6388322B1 (en) | 2001-01-17 | 2002-05-14 | Aralight, Inc. | Article comprising a mechanically compliant bump |
US7148566B2 (en) | 2001-03-26 | 2006-12-12 | International Business Machines Corporation | Method and structure for an organic package with improved BGA life |
US20050097727A1 (en) * | 2001-03-28 | 2005-05-12 | Tomoo Iijima | Multi-layer wiring board, method for producing multi-layer wiring board, polishing machine for multi-layer wiring board, and metal sheet for producing wiring board |
US6767819B2 (en) * | 2001-09-12 | 2004-07-27 | Dow Corning Corporation | Apparatus with compliant electrical terminals, and methods for forming same |
TW517360B (en) * | 2001-12-19 | 2003-01-11 | Ind Tech Res Inst | Enhanced type wafer level package structure and its manufacture method |
TW503496B (en) * | 2001-12-31 | 2002-09-21 | Megic Corp | Chip packaging structure and manufacturing process of the same |
US6638870B2 (en) | 2002-01-10 | 2003-10-28 | Infineon Technologies Ag | Forming a structure on a wafer |
US6940177B2 (en) | 2002-05-16 | 2005-09-06 | Dow Corning Corporation | Semiconductor package and method of preparing same |
DE10223738B4 (en) | 2002-05-28 | 2007-09-27 | Qimonda Ag | Method for connecting integrated circuits |
WO2004077525A2 (en) | 2003-02-25 | 2004-09-10 | Tessera, Inc. | Ball grid array with bumps |
TWI223363B (en) | 2003-11-06 | 2004-11-01 | Ind Tech Res Inst | Bonding structure with compliant bumps |
US7294929B2 (en) * | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
US7807508B2 (en) * | 2006-10-31 | 2010-10-05 | Tessera Technologies Hungary Kft. | Wafer-level fabrication of lidded chips with electrodeposited dielectric coating |
US7935568B2 (en) * | 2006-10-31 | 2011-05-03 | Tessera Technologies Ireland Limited | Wafer-level fabrication of lidded chips with electrodeposited dielectric coating |
-
1996
- 1996-10-29 US US08/739,303 patent/US6211572B1/en not_active Expired - Lifetime
-
1998
- 1998-02-09 US US09/020,647 patent/US20020115236A1/en not_active Abandoned
-
2009
- 2009-10-13 US US12/587,714 patent/US8558386B2/en not_active Expired - Fee Related
-
2013
- 2013-09-24 US US14/035,475 patent/US20140042634A1/en not_active Abandoned
-
2015
- 2015-03-19 US US14/662,579 patent/US20150194347A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4977441A (en) * | 1985-12-25 | 1990-12-11 | Hitachi, Ltd. | Semiconductor device and tape carrier |
US5187020A (en) * | 1990-07-31 | 1993-02-16 | Texas Instruments Incorporated | Compliant contact pad |
US5682061A (en) * | 1990-09-24 | 1997-10-28 | Tessera, Inc. | Component for connecting a semiconductor chip to a substrate |
US6326678B1 (en) * | 1993-09-03 | 2001-12-04 | Asat, Limited | Molded plastic package with heat sink and enhanced electrical performance |
US6870272B2 (en) * | 1994-09-20 | 2005-03-22 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8338925B2 (en) | 1995-10-31 | 2012-12-25 | Tessera, Inc. | Microelectronic assemblies having compliant layers |
US20040217453A1 (en) * | 1998-10-28 | 2004-11-04 | Masahiko Ogino | Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device |
US7217992B2 (en) * | 1998-10-28 | 2007-05-15 | Renesas Technology Corp. | Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device |
US7820482B2 (en) * | 1999-06-17 | 2010-10-26 | Qimonda Ag | Method of producing an electronic component with flexible bonding |
US20050208703A1 (en) * | 1999-06-17 | 2005-09-22 | Infineon Technologies, Ag | Method of producing an electronic component with flexible bonding pads |
US8148806B2 (en) | 2000-05-19 | 2012-04-03 | Megica Corporation | Multiple chips bonded to packaging structure with low noise and multiple selectable functions |
US20020150194A1 (en) * | 2000-07-27 | 2002-10-17 | Lucian Wielopolski | Method and device for non-invasive soil carbon content and distribution measurements |
US6617674B2 (en) * | 2001-02-20 | 2003-09-09 | Dow Corning Corporation | Semiconductor package and method of preparing same |
US8912666B2 (en) | 2001-03-30 | 2014-12-16 | Qualcomm Incorporated | Structure and manufacturing method of chip scale package |
US20080315424A1 (en) * | 2001-03-30 | 2008-12-25 | Megica Corporation | Structure and manufactruing method of chip scale package |
US8748227B2 (en) | 2001-03-30 | 2014-06-10 | Megit Acquisition Corp. | Method of fabricating chip package |
US8426982B2 (en) | 2001-03-30 | 2013-04-23 | Megica Corporation | Structure and manufacturing method of chip scale package |
US9018774B2 (en) | 2001-03-30 | 2015-04-28 | Qualcomm Incorporated | Chip package |
US7235873B2 (en) * | 2001-08-01 | 2007-06-26 | Infineon Technologies Ag | Protective device for subassemblies and method for producing a protective device |
US20030024735A1 (en) * | 2001-08-01 | 2003-02-06 | Volker Strutz | Protective device for subassemblies and method for producing a protective device |
US7960212B2 (en) | 2001-09-17 | 2011-06-14 | Megica Corporation | Structure of high performance combo chip and processing method |
US8124446B2 (en) | 2001-09-17 | 2012-02-28 | Megica Corporation | Structure of high performance combo chip and processing method |
US7960842B2 (en) | 2001-09-17 | 2011-06-14 | Megica Corporation | Structure of high performance combo chip and processing method |
US7919873B2 (en) | 2001-09-17 | 2011-04-05 | Megica Corporation | Structure of high performance combo chip and processing method |
US20090057901A1 (en) * | 2001-09-17 | 2009-03-05 | Megica Corporation | Structure of high performance combo chip and processing method |
US7960272B2 (en) | 2002-10-24 | 2011-06-14 | Megica Corporation | Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging |
US8334588B2 (en) | 2002-10-24 | 2012-12-18 | Megica Corporation | Circuit component with conductive layer structure |
US8105934B2 (en) | 2004-04-14 | 2012-01-31 | Samsung Electronics Co., Ltd. | Bump structure for a semiconductor device and method of manufacture |
US20090305494A1 (en) * | 2004-04-14 | 2009-12-10 | Yonghwan Kwon | Bump structure for a semiconductor device and method of manufacture |
DE102005018280B4 (en) * | 2004-04-14 | 2008-02-07 | Samsung Electronics Co., Ltd., Suwon | Method for producing a semiconductor device with bump structures and semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US6211572B1 (en) | 2001-04-03 |
US20150194347A1 (en) | 2015-07-09 |
US20140042634A1 (en) | 2014-02-13 |
US8558386B2 (en) | 2013-10-15 |
US20100035382A1 (en) | 2010-02-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6211572B1 (en) | Semiconductor chip package with fan-in leads | |
US7112879B2 (en) | Microelectronic assemblies having compliant layers | |
US6309915B1 (en) | Semiconductor chip package with expander ring and method of making same | |
CA2159242C (en) | Process for manufacturing semiconductor device and semiconductor wafer | |
US5950070A (en) | Method of forming a chip scale package, and a tool used in forming the chip scale package | |
US6872589B2 (en) | High density chip level package for the packaging of integrated circuits and method to manufacture same | |
JP4343296B2 (en) | Manufacturing method of semiconductor device | |
US6573609B2 (en) | Microelectronic component with rigid interposer | |
KR100687548B1 (en) | Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device | |
US6012224A (en) | Method of forming compliant microelectronic mounting device | |
US20030197285A1 (en) | High density substrate for the packaging of integrated circuits | |
EP0958605A2 (en) | Molded flex circuit ball grid array and method of making | |
KR20010031602A (en) | Semiconductor device and method for manufacturing the same | |
US6468830B1 (en) | Compliant semiconductor package with anisotropic conductive material interconnects and methods therefor | |
JP2968051B2 (en) | Chip interconnect carrier and method for mounting a spring contact on a semiconductor device | |
CA2254329A1 (en) | Process for manufacturing semiconductor device and semiconductor wafer | |
KR20000043571A (en) | Fabrication method of chip sized package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: TESSERA, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FJELSTAD, JOSEPH;KARAVAKIS, KONSTANTINE;REEL/FRAME:023543/0389;SIGNING DATES FROM 20000726 TO 20000727 |