US20020137355A1 - Process for forming uniform multiple contact holes - Google Patents
Process for forming uniform multiple contact holes Download PDFInfo
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- US20020137355A1 US20020137355A1 US09/828,610 US82861001A US2002137355A1 US 20020137355 A1 US20020137355 A1 US 20020137355A1 US 82861001 A US82861001 A US 82861001A US 2002137355 A1 US2002137355 A1 US 2002137355A1
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- insulator layer
- opening
- procedure
- contact hole
- conductive region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to form uniform contact holes in insulator and in semiconductor materials.
- Micro-miniaturization or the ability to fabricate semiconductor devices using sub-micron features, has allowed increased device density, increased device performance, and a reduction of processing costs, to be realized.
- the smaller device features, achieved via micro-miniaturization has allowed performance degrading, parasitic capacitances to be reduced, while a greater number of smaller semiconductor chips, still possessing equal or increased device densities when compared to counterpart, larger semiconductor chips, have resulted in decreased processing costs for an individual smaller chip.
- the advent of micro-miniaturization has in part been accomplished via advances in specific semiconductor disciplines such as photolithography and dry etching.
- the ability to define sub-micron features in insulator or conductive layers via dry etching procedures, using an overlying photoresist shape as an etch mask, is dependent on the selectivity of the dry etching procedure. For example when defining an opening in an insulator layer, using an overlying photoresist shape as an etch mask, a dry etch chemistry featuring a high etch rate of insulator layer, and a lower etch rate for the masking photoresist shape, is desired.
- This combination however can result in polymer formation of the sides of the insulator layer, exposed in the contact hole, at various stages of the opening procedure, possibly interfering with the remaining portion of the opening procedure, thus resulting in a non-uniform definition for a specific opening, or non-uniformity between openings.
- This invention will describe a novel procedure for defining openings in an insulator layer via a combination dry—wet etching procedure, in which the polymer layer, formed during the dry etching component of the procedure, is removed prior to initiation of the wet etch component.
- This novel procedure allows a partially defined opening to be subjected to a wet etch cycle, after the overlying photoresist shape has been removed, which in turn allows any oxide formed on exposed regions of the opening formed during the photoresist stripping procedure, to also be removed.
- Prior art such as Kinzer, in U.S. Pat. No. 5,629,237, describe a dry—wet procedure for defining an opening in an insulator layer, however that prior performs the wet etch component of the opening prior to photoresist and polymer removal, thus not addressing polymer on the sides of the dry etched opening, which can interfere or retard the wet etch cycle.
- a method of defining a contact hole opening in a insulator layer, and in a top portion of an underlying semiconductor region, using a combination dry etch—wet etch procedure is described.
- An insulator layer is deposited on a semiconductor substrate, to a thickness greater than the desired final thickness, to allow for thinning as a result of a subsequent wet etch procedure.
- a tapered, first portion of the contact hole is defined in a top portion of the insulator layer via an isotropic dry etch procedure.
- An anisotropic dry etch procedure is then used to define the straight walled, contact hole opening in the remaining portion of insulator layer, and in a top portion of the semiconductor region, also resulting in the formation of a polymer layer on the exposed surfaces of the contact hole. Stripping of the masking photoresist shape, and of the polymer layer, results in oxide growth of the exposed semiconductor surfaces of the contact hole.
- a wet etch procedure is then employed to remove oxide from the surfaces of the semiconductor region exposed in the contact hole, as well as to controllably recess the exposed insulator surfaces, resulting in uniform contact holes located in the entire semiconductor substrate.
- FIGS. 1 - 6 which schematically, in cross-sectional style, describe the key stages of definition of a contact hole opening, employing a combination dry—wet etch procedure, featuring the wet etch component performed after stripping of the masking photoresist shape and of the polymer layer, which was formed on the exposed surfaces of the contact hole during the dry etching component.
- a semiconductor substrate 1 comprised of specific conductive regions, (not shown in the drawings), such as a source/drain region of a metal oxide semiconductor field effect transistor (MOSFET), device, is used and schematically shown in FIG. 1.
- the conductive region described in this invention can also be a metal interconnect structure.
- An insulator layer 2 a such as silicon oxide, or boro-phosphosilicate glass (BPSG), is next deposited via low pressure chemical vapour deposition (LPCVD), or via plasma enhanced chemical vapour deposition (PECVD), procedures, to a thickness between about 6000 to 9000 Angstroms.
- Insulator layer 2 a is intentionally formed 1000 Angstroms thicker than desired to allow for the removal of unprotected insulator layer experienced during a subsequent wet etch component of the contact hole definition procedure, thus resulting in the desired final insulator thickness between of about 5000 to 8000 Angstroms.
- Photoresist shape 3 is then formed on the top surface of insulator layer 2 a , with opening 4 a , featuring a diameter between about 5000 to 50000 Angstroms, exposing a portion of the top surface of insulator layer 2 a .
- the result of these procedures are schematically shown in FIG. 1.
- the depth of tapered portion of contact hole opening 4 b is between about 1000 to 3000 Angstroms, in insulator layer 2 a . This is schematically shown in FIG. 2.
- the tapered portion of the contact hole opening will allow improved coverage, or improved conformality, of a subsequent metal structure subsequently formed in contact hole.
- An anisotropic dry etch procedure such as a reactive ion etch (RIE) is next performed, using CHF 3 or CF 4 as an etchant, to define the contact opening 4 c , in insulator layer 2 a , with contact opening 4 c , comprised of the tapered opening in the top portion of insulator layer 2 a , and comprised of a straight walled opening, formed in the remaining portion of insulator layer, via the use of the anisotropic dry etch procedure.
- RIE reactive ion etch
- the selective, anisotropic dry etch procedure performed at a pressure between about 100 to 300 mtorr, resulting in the desired straight walled profile, also results in the undesirable formation of polymer layer 5 , on the exposed surfaces of contact hole opening 4 c .
- the diameter of straight walled portion of contact hole opening 4 c is between about 5000 to 50000 Angstroms, identical to the diameter of opening 4 a , in photoresist shape 3 . This is schematically shown in FIG. 3.
- the anisotropic dry etch procedure is continued to allow the contact hole opening to be defined in a top portion of semiconductor region 1 , at a depth between about 2000 to 6000 Angstroms.
- This procedure performed using Cl 2 or SF 6 as an etchant, at a pressure between about 100 to 1000 mtorr, will increase the surface area of the semiconductor region now exposed in contact hole opening 4 d , allowing decreased contact and interface resistance to be realized when a subsequent metal structure interfaces conductive region of semiconductor substrate 1 , in contact hole 4 d .
- Contact hole opening 4 d is now comprised of a tapered component located in a top portion of insulator layer 2 a , a straight walled component located in the bottom portion of insulator layer 2 a , and a straight walled component located in a top portion of semiconductor substrate 1 . This is schematically shown in FIG. 4.
- photoresist shape 3 As well as polymer layer 5 , are removed via plasma oxygen ashing procedures.
- the consequence of the plasma oxygen ashing procedure is the formation of thin, silicon oxide layer 6 , on the regions of semiconductor substrate 1 , exposed in contact hole 4 d .
- a wet etch procedure is next performed, addressing the removal of silicon oxide layer 6 , which if left remaining would adversely influence the contact resistance between a subsequent metal structure placed in the contact hole, to the conductive region of semiconductor substrate, as well has addressing the intentional recessing of the portions of insulator layer exposed in the contact hole opening, allowing uniformity of the final contact hole openings to be achieved.
- a wet etch procedure using either a buffered hydrofluoric (BHF), acid solution, or using a dilute hydrofluoric (DHF), solution is used remove silicon oxide layer 6 , from the exposed surfaces of semiconductor substrate 1 , as well as to laterally etch exposed regions of insulator 2 a , resulting in contact hole opening 4 e , now featuring a diameter between about 5500 to 52000 Angstroms.
- BHF buffered hydrofluoric
- DHF dilute hydrofluoric
- the wet etch procedure also results in the removal of between about 500 to 2000 Angstroms from the top portion of insulator layer 2 a , resulting in the thinner insulator layer 2 b , now at the desired, or designed thickness of between about 4000 to 8500 Angstroms.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to form uniform contact holes in insulator and in semiconductor materials.
- 2. Description of Prior Art
- Micro-miniaturization, or the ability to fabricate semiconductor devices using sub-micron features, has allowed increased device density, increased device performance, and a reduction of processing costs, to be realized. The smaller device features, achieved via micro-miniaturization, has allowed performance degrading, parasitic capacitances to be reduced, while a greater number of smaller semiconductor chips, still possessing equal or increased device densities when compared to counterpart, larger semiconductor chips, have resulted in decreased processing costs for an individual smaller chip. The advent of micro-miniaturization has in part been accomplished via advances in specific semiconductor disciplines such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed the sub-micron images to be routinely defined in the sensitive photoresist layers. In addition the development of advanced dry etching tools and processes have allowed the sub-micron images in overlying, masking photoresist shapes to be successfully transferred to underlying materials, such as insulator and conductive layers, used for the fabrication of the semiconductor devices.
- The ability to define sub-micron features in insulator or conductive layers via dry etching procedures, using an overlying photoresist shape as an etch mask, is dependent on the selectivity of the dry etching procedure. For example when defining an opening in an insulator layer, using an overlying photoresist shape as an etch mask, a dry etch chemistry featuring a high etch rate of insulator layer, and a lower etch rate for the masking photoresist shape, is desired. This combination however can result in polymer formation of the sides of the insulator layer, exposed in the contact hole, at various stages of the opening procedure, possibly interfering with the remaining portion of the opening procedure, thus resulting in a non-uniform definition for a specific opening, or non-uniformity between openings. This invention will describe a novel procedure for defining openings in an insulator layer via a combination dry—wet etching procedure, in which the polymer layer, formed during the dry etching component of the procedure, is removed prior to initiation of the wet etch component. This novel procedure allows a partially defined opening to be subjected to a wet etch cycle, after the overlying photoresist shape has been removed, which in turn allows any oxide formed on exposed regions of the opening formed during the photoresist stripping procedure, to also be removed. Prior art, such as Kinzer, in U.S. Pat. No. 5,629,237, describe a dry—wet procedure for defining an opening in an insulator layer, however that prior performs the wet etch component of the opening prior to photoresist and polymer removal, thus not addressing polymer on the sides of the dry etched opening, which can interfere or retard the wet etch cycle.
- It is an object of this invention to define a contact hole opening in an insulator layer, and in a top portion of an underlying semiconductor region.
- It is another object of this invention to employ a dry etch—wet etch procedure, to define the contact hole opening.
- It is still another object of this invention to remove the defining, masking photoresist shape, and polymer layer, from the sides of the dry etched contact hole, after the dry etching component of the contact hole opening procedure.
- It is still yet another object of this invention to perform the wet etch component of the contact hole opening procedure after stripping of the photoresist shape and polymer layer, to allow oxide formed on exposed semiconductor regions of the contact hole opening to be removed, and to improve the uniformity of the contact hole openings.
- In accordance with the present invention a method of defining a contact hole opening in a insulator layer, and in a top portion of an underlying semiconductor region, using a combination dry etch—wet etch procedure, is described. An insulator layer is deposited on a semiconductor substrate, to a thickness greater than the desired final thickness, to allow for thinning as a result of a subsequent wet etch procedure. After definition of a masking photoresist shape, a tapered, first portion of the contact hole is defined in a top portion of the insulator layer via an isotropic dry etch procedure. An anisotropic dry etch procedure is then used to define the straight walled, contact hole opening in the remaining portion of insulator layer, and in a top portion of the semiconductor region, also resulting in the formation of a polymer layer on the exposed surfaces of the contact hole. Stripping of the masking photoresist shape, and of the polymer layer, results in oxide growth of the exposed semiconductor surfaces of the contact hole. A wet etch procedure is then employed to remove oxide from the surfaces of the semiconductor region exposed in the contact hole, as well as to controllably recess the exposed insulator surfaces, resulting in uniform contact holes located in the entire semiconductor substrate.
- The object and other advantages of this invention are best described in the preferred embodiments with reference to the attached drawings that include:
- FIGS.1-6, which schematically, in cross-sectional style, describe the key stages of definition of a contact hole opening, employing a combination dry—wet etch procedure, featuring the wet etch component performed after stripping of the masking photoresist shape and of the polymer layer, which was formed on the exposed surfaces of the contact hole during the dry etching component.
- The method of defining a contact hole opening in an insulator layer, and in a top portion of a semiconductor region, employing a combination dry—wet etch procedure, featuring the wet etch component performed after stripping of the masking photoresist shape, and of a polymer layer which was formed on the exposed surfaces of the contact hole during the dry etching component, will now be described in detail. A
semiconductor substrate 1, comprised of specific conductive regions, (not shown in the drawings), such as a source/drain region of a metal oxide semiconductor field effect transistor (MOSFET), device, is used and schematically shown in FIG. 1. The conductive region described in this invention can also be a metal interconnect structure. Aninsulator layer 2 a, such as silicon oxide, or boro-phosphosilicate glass (BPSG), is next deposited via low pressure chemical vapour deposition (LPCVD), or via plasma enhanced chemical vapour deposition (PECVD), procedures, to a thickness between about 6000 to 9000 Angstroms.Insulator layer 2 a, is intentionally formed 1000 Angstroms thicker than desired to allow for the removal of unprotected insulator layer experienced during a subsequent wet etch component of the contact hole definition procedure, thus resulting in the desired final insulator thickness between of about 5000 to 8000 Angstroms.Photoresist shape 3, is then formed on the top surface ofinsulator layer 2 a, with opening 4 a, featuring a diameter between about 5000 to 50000 Angstroms, exposing a portion of the top surface ofinsulator layer 2 a. The result of these procedures are schematically shown in FIG. 1. - An isotropic, plasma or reactive ion etch (RIE), dry etch procedure, using NF3 as an etchant, at a pressure between about 1000 to 2000 mtorr, is next employed to define tapered contact hole opening 4 b, in a top portion of
insulator layer 2 a. The depth of tapered portion of contact hole opening 4 b, is between about 1000 to 3000 Angstroms, ininsulator layer 2 a. This is schematically shown in FIG. 2. The tapered portion of the contact hole opening will allow improved coverage, or improved conformality, of a subsequent metal structure subsequently formed in contact hole. - An anisotropic dry etch procedure, such as a reactive ion etch (RIE), is next performed, using CHF3 or CF4 as an etchant, to define the
contact opening 4 c, ininsulator layer 2 a, with contact opening 4 c, comprised of the tapered opening in the top portion ofinsulator layer 2 a, and comprised of a straight walled opening, formed in the remaining portion of insulator layer, via the use of the anisotropic dry etch procedure. The selective, anisotropic dry etch procedure, performed at a pressure between about 100 to 300 mtorr, resulting in the desired straight walled profile, also results in the undesirable formation ofpolymer layer 5, on the exposed surfaces of contact hole opening 4 c. The diameter of straight walled portion of contact hole opening 4 c, is between about 5000 to 50000 Angstroms, identical to the diameter of opening 4 a, inphotoresist shape 3. This is schematically shown in FIG. 3. - The anisotropic dry etch procedure is continued to allow the contact hole opening to be defined in a top portion of
semiconductor region 1, at a depth between about 2000 to 6000 Angstroms. This procedure, performed using Cl2 or SF6 as an etchant, at a pressure between about 100 to 1000 mtorr, will increase the surface area of the semiconductor region now exposed incontact hole opening 4 d, allowing decreased contact and interface resistance to be realized when a subsequent metal structure interfaces conductive region ofsemiconductor substrate 1, incontact hole 4 d. Contact hole opening 4 d, is now comprised of a tapered component located in a top portion ofinsulator layer 2 a, a straight walled component located in the bottom portion ofinsulator layer 2 a, and a straight walled component located in a top portion ofsemiconductor substrate 1. This is schematically shown in FIG. 4. - At this stage of the contact hole opening procedure
photoresist shape 3, as well aspolymer layer 5, are removed via plasma oxygen ashing procedures. The consequence of the plasma oxygen ashing procedure is the formation of thin, silicon oxide layer 6, on the regions ofsemiconductor substrate 1, exposed incontact hole 4 d. This is schematically shown in FIG. 5. A wet etch procedure is next performed, addressing the removal of silicon oxide layer 6, which if left remaining would adversely influence the contact resistance between a subsequent metal structure placed in the contact hole, to the conductive region of semiconductor substrate, as well has addressing the intentional recessing of the portions of insulator layer exposed in the contact hole opening, allowing uniformity of the final contact hole openings to be achieved. A wet etch procedure, using either a buffered hydrofluoric (BHF), acid solution, or using a dilute hydrofluoric (DHF), solution is used remove silicon oxide layer 6, from the exposed surfaces ofsemiconductor substrate 1, as well as to laterally etch exposed regions ofinsulator 2 a, resulting incontact hole opening 4 e, now featuring a diameter between about 5500 to 52000 Angstroms. This is schematically shown in FIG. 6. The controlled lateral recess formed in the sides of contact hole opening 4 e, removing between about 500 to 2000 Angstroms of insulator layer from each side of the contact hole opening, allows uniform width, or diameter, contact hole openings to be formed in all regions of the semiconductor substrate. The wet etch procedure also results in the removal of between about 500 to 2000 Angstroms from the top portion ofinsulator layer 2 a, resulting in thethinner insulator layer 2 b, now at the desired, or designed thickness of between about 4000 to 8500 Angstroms. - While this invention has been particularly shown and described with reference to, the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.
Claims (23)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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GB0107420.2 | 2001-03-24 | ||
GB0107420A GB2378314B (en) | 2001-03-24 | 2001-03-24 | Process for forming uniform multiple contact holes |
Publications (2)
Publication Number | Publication Date |
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US20020137355A1 true US20020137355A1 (en) | 2002-09-26 |
US6458710B1 US6458710B1 (en) | 2002-10-01 |
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US09/828,610 Expired - Lifetime US6458710B1 (en) | 2001-03-24 | 2001-04-09 | Process for forming uniform multiple contact holes |
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GB (1) | GB2378314B (en) |
Cited By (5)
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US20050179080A1 (en) * | 2003-07-11 | 2005-08-18 | Yi-Shing Chang | Method and system for forming source regions in memory devices |
US20060099811A1 (en) * | 2003-04-15 | 2006-05-11 | Karola Richter | Method for structuring of silicon substrates for microsystem technological device elements and associated silicon substrate |
US20090212295A1 (en) * | 2004-05-24 | 2009-08-27 | Samsung Mobile Display Co., Ltd. | Semiconductor device and method of fabricating the same |
CN102064088A (en) * | 2010-10-11 | 2011-05-18 | 山东华光光电子有限公司 | Method for preparing sapphire-graph substrate by dry method and wet method |
CN109243971A (en) * | 2018-09-07 | 2019-01-18 | 成都海威华芯科技有限公司 | A kind of semiconductor devices deielectric-coating low angle engraving method |
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US7371659B1 (en) * | 2001-12-12 | 2008-05-13 | Lsi Logic Corporation | Substrate laser marking |
US6774032B1 (en) * | 2003-05-30 | 2004-08-10 | Intel Corporation | Method of making a semiconductor device by forming a masking layer with a tapered etch profile |
KR100555505B1 (en) * | 2003-07-09 | 2006-03-03 | 삼성전자주식회사 | Method for fabrication interconnection contact to obtain expanded bottom opening in contact hole by deposition and removal of silicide layer |
US7875547B2 (en) * | 2005-01-12 | 2011-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact hole structures and contact structures and fabrication methods thereof |
JP2008159686A (en) * | 2006-12-21 | 2008-07-10 | Nippon Mektron Ltd | Method for manufacturing printed wiring board incorporating capacitors |
JP5168935B2 (en) * | 2007-02-21 | 2013-03-27 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
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US5180689A (en) * | 1991-09-10 | 1993-01-19 | Taiwan Semiconductor Manufacturing Company | Tapered opening sidewall with multi-step etching process |
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US5795793A (en) | 1994-09-01 | 1998-08-18 | International Rectifier Corporation | Process for manufacture of MOS gated device with reduced mask count |
US5629237A (en) | 1994-10-24 | 1997-05-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Taper etching without re-entrance profile |
KR0170270B1 (en) * | 1995-12-30 | 1999-03-30 | 김광호 | Profile-improving method of contact hole formed on the pospho-silicate glass |
US5877092A (en) * | 1997-06-18 | 1999-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for edge profile and design rules control |
US6025273A (en) | 1998-04-06 | 2000-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask |
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2001
- 2001-03-24 GB GB0107420A patent/GB2378314B/en not_active Expired - Fee Related
- 2001-04-09 US US09/828,610 patent/US6458710B1/en not_active Expired - Lifetime
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060099811A1 (en) * | 2003-04-15 | 2006-05-11 | Karola Richter | Method for structuring of silicon substrates for microsystem technological device elements and associated silicon substrate |
US7498266B2 (en) * | 2003-04-15 | 2009-03-03 | Technische Universitát Dresden | Method for structuring of silicon substrates for microsystem technological device elements and associated silicon substrate |
US20050179080A1 (en) * | 2003-07-11 | 2005-08-18 | Yi-Shing Chang | Method and system for forming source regions in memory devices |
US7227218B2 (en) * | 2003-07-11 | 2007-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and system for forming source regions in memory devices |
US20090212295A1 (en) * | 2004-05-24 | 2009-08-27 | Samsung Mobile Display Co., Ltd. | Semiconductor device and method of fabricating the same |
US20090275176A1 (en) * | 2004-05-24 | 2009-11-05 | Samsung Mobile Display Co., Ltd. | Semiconductor device and method of fabricating the same |
US7985992B2 (en) * | 2004-05-24 | 2011-07-26 | Samsung Mobile Display Co., Ltd. | Semiconductor device and method of fabricating the same |
US8168531B2 (en) * | 2004-05-24 | 2012-05-01 | Samsung Mobile Display Co., Ltd. | Semiconductor device and method of fabricating the same |
US8749069B2 (en) | 2004-05-24 | 2014-06-10 | Samsung Display Co., Ltd. | Semiconductor device and method of fabricating the same |
CN102064088A (en) * | 2010-10-11 | 2011-05-18 | 山东华光光电子有限公司 | Method for preparing sapphire-graph substrate by dry method and wet method |
CN109243971A (en) * | 2018-09-07 | 2019-01-18 | 成都海威华芯科技有限公司 | A kind of semiconductor devices deielectric-coating low angle engraving method |
Also Published As
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US6458710B1 (en) | 2002-10-01 |
GB2378314B (en) | 2003-08-20 |
GB2378314A (en) | 2003-02-05 |
GB0107420D0 (en) | 2001-05-16 |
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