US20030021155A1 - Soft program and soft program verify of the core cells in flash memory array - Google Patents
Soft program and soft program verify of the core cells in flash memory array Download PDFInfo
- Publication number
- US20030021155A1 US20030021155A1 US09/829,193 US82919301A US2003021155A1 US 20030021155 A1 US20030021155 A1 US 20030021155A1 US 82919301 A US82919301 A US 82919301A US 2003021155 A1 US2003021155 A1 US 2003021155A1
- Authority
- US
- United States
- Prior art keywords
- cell
- soft program
- voltage
- soft
- erased
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
Definitions
- the present invention relates generally to memory systems and in particular, to flash memory systems and methods wherein a new reference cell structure, and the application of unique reference voltages during soft program and soft program verify operations, eliminates previous problems of trimming a reference cell to a low threshold voltage, and tightens the erased core cell threshold voltage distribution, which also facilitates faster programming times.
- Flash memory is a type of electronic memory media which can be rewritten and hold its data without power. Flash memory devices generally have life spans from 100K to 1 MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in place, flash memory is less expensive and more dense. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
- DRAM dynamic random access memory
- SRAM static random access memory
- each cell 10 typically includes a metal oxide semiconductor (MOS) transistor structure having a source 12 , a drain 14 , and a channel 16 in a substrate or P-well 18 , as well as a stacked gate structure 20 overlying the channel 16 .
- the stacked gate 20 may further include a thin gate dielectric layer 22 (sometimes referred to as a tunnel oxide) formed on the surface of the P-well.
- the stacked gate 20 also includes a polysilicon floating gate 24 overlying the tunnel oxide 22 and an interpoly dielectric layer 26 overlying the floating gate.
- the interpoly dielectric layer 26 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer.
- a polysilicon control gate 28 overlies the interpoly dielectric layer 26 .
- the control gate 28 is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration.
- the drain regions 14 of the cells are connected together by a conductive bit line.
- the channel 16 of the cell conducts current between the source 12 and the drain 14 in accordance with an electric field developed in the channel 16 by the stacked gate structure 20 .
- each drain terminal 14 of the transistors within a single column is connected to the same bit line.
- each flash cell associated with a given bit line has its stacked gate terminal 28 coupled to a different word line, while all the flash cells in the array have their source terminals 12 coupled to a common source terminal.
- individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry (not shown) for programming (writing), reading or erasing functions.
- Such a conventional single bit stacked gate flash memory cell 10 is programmed by applying a relatively high voltage to the control gate 28 and connecting the source 12 to ground and the drain 14 to a predetermined potential above the source.
- a resulting high electric field across the tunnel oxide 22 leads to a phenomena called “Fowler-Nordheim” tunneling.
- electrons in the core cell channel region 16 tunnel through the gate or tunnel oxide 22 into the floating gate 24 and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric 26 and the tunnel oxide 22 .
- the threshold voltage of the cell 10 increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
- FIG. 1 b illustrates an exemplary prior art dual bit memory cell 50 .
- the memory cell 50 comprises a silicon dioxide layer 52 , a P-type substrate 54 has buried N+ source 56 and N+ drain 58 regions.
- the silicon dioxide 52 is sandwiched between two layers of silicon nitride 60 , and 62 .
- the layer 52 may comprise buried polysilicon islands or any other form of charge trapping layer.
- the memory cell 50 is capable of storing two data bits, a left bit represented by the dashed circle A and a right bit represented by the dashed circle B.
- the dual bit memory cell 50 is generally symmetrical, thus the drain 58 and the source 56 are interchangeable.
- the left junction 56 may serve as the source terminal and the right junction 58 as the drain terminal with respect to the right bit B.
- the right junction 58 may serve as the source terminal and the left junction 56 as the drain terminal for the left bit A.
- a system and methodology are provided which overcome or minimize the problems and shortcomings of conventional memory cell soft program verification schemes and systems.
- the invention includes methods and systems for verifying an erased cell threshold voltage of one or more dual bit cells in a memory device, such as a flash memory.
- the invention allows for efficient and thorough soft program verification, which minimizes inadvertent, undesired data retention, over-erase and cell read leakage issues associated with the dual bit cell architecture.
- the invention provides significant advantages when employed in association with dual bit memory cells wherein only one bit thereof is actively used for data storage. However, it will be recognized that the invention finds utility in association with dual bit memory cell architectures generally, and that the invention is thus not limited to any particular dual bit cell usage implementation or configuration.
- the erased cell threshold voltage verification method comprises the steps of performing a determination of whether a first, or second bit in the dual bit memory cell is properly soft programmed.
- Verification of proper soft programming in a dual bit memory cell configuration ensures that undesirable data retention or bit over-erase problems (resulting in a low threshold voltage, and consequent high leakage current) do not adversely affect the operation (e.g., proper erasure, read/write functionality) of the core cell.
- the invention provides significant performance advantages over conventional methods typically utilized in soft programming of single bit (e.g., stacked gate) memory cell types.
- the method may further comprise repeating the method for another dual bit memory cell, whereby a byte-wise soft programming verification may be accomplished, for example, in association with a chip erase or sector erase operation.
- a soft program verification of a core cell threshold voltage may be performed through the application of a voltage to the memory cell being verified along with an application of a different voltage to a reference cell with a known threshold voltage, then comparing the currents of the core cell under analysis and the reference cell, respectively. When this comparison indicates that one or more of the soft programming pulses have reduced the current in the cell being verified to less than that of the reference cell, the core cell threshold voltage is above a target minimum erased cell threshold voltage. Moreover, according to one aspect of the invention, the process may be repeated for each cell in the array until each erased cell threshold voltage is above a target minimum.
- the method may also include an accounting of the number of soft program pulses which are applied to any one core cell, or block of core cells, in the event the cell, or block of cells are not responding to soft program verify. In this case, where a predetermined maximum soft program pulse count is exceeded, the cell, or block of cells is identified as having failed soft programming, and therefore avoid an endless soft program loop.
- this method may include steps of initializing a pulse counter before each new cell address is selected, performing the soft program verification, determining whether the pulse counter has exceeded the preset maximum pulse count, then, if the count has not been exceeded, continuing to a step of incrementing the pulse counter as another soft program pulse is applied, or if the pulse count has been exceeded, a further step may be to proceed with appropriate actions for a failed soft programming.
- a method to custom tailor a subsequent soft programming pulse e.g., pulse width, pulse height
- a subsequent soft programming pulse e.g., pulse width, pulse height
- the method of the present invention may include several selected core cells, or blocks of cells for soft programming operations, as well as selected core cells, or blocks of cells for soft program verifications.
- a method for soft programming and soft program verifying a plurality of dual bit flash memory cells which includes the steps of soft programming the plurality of dual bit flash memory cells, verifying proper soft programming of a first bit in at least one of the plurality of dual bit flash memory cells, verifying proper soft programming of a second bit in the at least one of the plurality of dual bit flash memory cells, and determining that the cell is properly soft programmed if the first and second bits are properly soft programmed.
- FIG. 1 a is a fragmentary cross section view of an exemplary prior art, single bit flash memory cell
- FIG. 1 b is a fragmentary cross section view of an exemplary prior art dual bit memory cell in which various aspects of the present invention may be implemented;
- FIG. 2 is a distribution plot illustrating an erased cell threshold voltage distribution of a number of core cells of an exemplary prior art flash memory array
- FIG. 3 is a distribution plot illustrating an erased cell threshold voltage distribution and a programmed cell threshold voltage distribution of a number of core cells of an exemplary dual bit memory array, together with over-erased bits which require soft programming according to the invention
- FIG. 4 is a system level functional block diagram illustrating an exemplary soft program and soft program verification system in which various aspects of the invention may be carried out;
- FIG. 5 a is a schematic diagram illustrating an exemplary core cell, core current, and gate voltage in the system of FIG. 4;
- FIG. 5 b is a schematic diagram illustrating an exemplary reference cell, reference current, and gate voltage in the system of FIG. 4;
- FIG. 6 is a functional block diagram illustrating a soft program reference voltage and charge pump logic circuit of the system of FIG. 4;
- FIG. 7 is a schematic diagram illustrating an exemplary soft program multiplexer (hereinafter referred to as “mux”) logic circuit of the system of FIG. 4;
- FIG. 8 is a schematic diagram illustrating details of an exemplary soft program reference voltage logic circuit, and voltage divider circuit of the system of FIG. 6;
- FIG. 9 is a flow diagram illustrating an exemplary method for verifying memory cell soft programming according to the invention.
- the invention provides a method and a system for soft programming, and verifying proper soft programming of one or more dual bit memory cells, and may be used in conjunction with a chip or sector soft program and soft program verification operation in a flash memory device.
- a sector soft programming verify operation may be performed in order to apply soft programming pulses to each such cell in a flash memory device.
- the invention may be employed in order to verify which cells in the device have been properly soft programmed.
- the invention selectively attempts to re-soft program cells (e.g., via selective application of soft program voltage pulses to one or both individual bits in a dual bit memory cell) which have been over erased during the erase part of the algorithm that is performed before the soft program verify operation.
- the invention also provides for selective re-verification of proper soft programming of one or both bits in a dual bit cell.
- proper soft program verification may be accomplished through generating a soft program core cell verification voltage and generating a reference cell verification voltage having a value which is different from the core cell verification voltage.
- the method further includes applying the core cell verification voltage to a gate portion of an over erased core cell to thereby generate a core cell current, and applying the reference cell voltage verification voltage to a gate portion of a reference cell to thereby generate a reference cell current.
- the method includes determining whether a threshold voltage associated with the erased core cell is less than a predetermined threshold based on a comparison of the core cell current and the reference cell current.
- FIG. 2 illustrates a characteristic curve known as the erased core cell threshold voltage distribution.
- FIG. 2 illustrates how the core cell threshold voltages in a flash memory array can differ from one another following an erase operation as shown by curve 200 that represents the number of cells having particular values of threshold voltage V T . It has been found that the least erased cells will have relatively high threshold voltages in the region of V TMAX , whereas the most erased cells (sometimes referred to as “over-erased cells”) will have low threshold voltages in the region of V TMIN that can be zero or negative. However, the threshold voltage distribution curve segment 210 indicates that there is still a number of erased cells that have a relatively low threshold voltage. After correcting the V T of the most over erased cells thru the soft program and soft program verify operations, the erased core cell threshold voltage distribution curve 200 will narrow on the low end of the curve (shown by curve segment 210 ) to approximately 0 Volts.
- the background leakage current of a cell varies as a function of threshold voltage, the lower the threshold voltage of an erased cell, the higher the leakage current will be. Because there may be as many as 512 cells connected to a bitline, the total background leakage current may disadvantageously exceed the cell read current thereby leading to a subsequent read error. It is therefore desirable to prevent cells from not only being over-erased, but to reduce the threshold voltage distribution to as low a range as possible, with ideally all cells having the same high threshold voltage after erase.
- FIG. 3 illustrates characteristic cell threshold voltage distribution curves of an exemplary dual bit memory array illustrating a desired erased cell threshold voltage distribution 350 , and a programmed cell threshold voltage distribution 360 .
- some cells may have been over erased, producing an excessively low threshold voltage (shaded region 370 ) and corresponding high drain current leakage which may cause problems with later read, program verify, or even erase operations.
- Conventional methods of chip, sector, or cell soft programming typically used in the single bit stacked gate cell attempted to correct the over erased cells, by applying one or more program pulses to the over erased cells.
- Soft programming raises (or corrects) the low threshold voltages on these cells, to effectively narrow the distribution of cell threshold voltages across a flash memory array.
- Soft program verification was done by comparing the current produced in the selected core cell, and its' associated erased cell threshold voltage, to that of a reference cell with an acceptable threshold voltage.
- the inventors devised methods and systems to generate different voltages to be applied to the gate of the new reference cell structure and the core cell structure, respectively, to allow the reference cell to produce a current which compares to an erased core cell current associated with a V T >0.7 volts.
- FIG. 4 illustrates a system level functional block diagram of an exemplary soft program and soft program verification system 400 in which various aspects of the invention may be accomplished.
- the system of FIG. 4 prevents erased memory cells from exhibiting an erased cell threshold voltage below a predetermined level, may be comprised of the three functional blocks shown.
- a flash memory array system 402 of FIG. 4 includes an array of core cells 405 which are typically subdivided into sectors, blocks, and individual core cells.
- the cells are arranged in rows and columns, with all of the cells in a row having their control gate connected to a common word line.
- the drains of the cells located in a particular column are all connected to a common bit line while all the cells of the array have their sources coupled to a common source line 490 to enable the measurement of drain current in the core cells (I CORE ) at 490 .
- the memory system 402 also has address controls 410 which acts as a matrix of multiplexors working in conjunction with bit - column controls 415 and word- row controls 420 used to select a sector, block, or individual cells of the core 405 .
- the row control block 420 is connected to the word lines of the cells of the array and a column control block 415 is connected to the bit lines of the array.
- individual flash cells may be individually addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
- These flash core cells 405 will be the object of the soft program and soft program verify operations of the present invention, and discussed in greater detail in the following sections.
- a soft program control circuit 430 of FIG. 4 is configured with a soft program multiplexer 435 charge pumps 440 and a soft program reference voltage circuit 445 to generate a soft program voltage (V 1 ) at 450 , a soft program core cell verify voltage (V 3 ) at 455 , and a reference cell verification voltage (V 2 ) at 460 .
- the multiplexer circuit 430 In response to a logic command to enter the soft program mode (or for example, as the result of a soft program verify comparison command 487 ), the multiplexer circuit 430 generates a soft program enable signal 436 to control the reference logic circuit 445 or for example, the next core address selection 437 .
- the multiplexer circuit 435 also generates a regulated, clamped supply voltage 438 to the wordline charge pump circuit of 440 .
- the charge pumps of 440 include a Drain charge pump which generates a supply voltage for program verify operations, and a wordline charge pump circuit configured to generate a boosted wordline supply voltage for the voltage divider within the soft program reference voltage circuit 445 .
- the soft program reference voltage circuit 445 takes the soft program enable signals 436 and 486 , and charge pump voltages 442 and 444 , used in a reference logic circuit multiplexer within 445 to generate the discrete soft program and soft program verify voltages V 1 , V 2 , & V 3 via, for example, a voltage divider.
- a soft program verify control circuit 470 is configured with a reference cell 480 which uses V 2 , the reference cell verification voltage 460 to generate the reference cell current (I REF ) at 495 .
- the control circuit 470 further includes a soft program verify comparator circuit 475 which is configured to compare the over erased core cell verification current (I CORE ) at 490 to the reference cell current (I REF ) at 495 to generate an output indication on 477 of whether the selected erased core cell threshold voltage is below a predetermined level.
- the soft program verify comparator circuit is further operable to transfer the V T indication to a verify controls circuit 485 which is configured to output one or more soft program control signals 486 and 487 for use in soft programming based on the indication.
- comparator 475 of the soft program verify control circuit 470 has made the determination that the selected core cell V T is less than 0.7 volts, comparator 475 provides signal 477 to initiate a predetermined soft program pulse from verify controls circuit 485 via 487 back to the soft program control circuit 430 .
- a system and method to custom tailor a subsequent soft programming pulse (e.g., pulse width, pulse height) according to the differential current in the comparator 475 , to greatly speed up the overall soft programming process, or to minimize the effects of over soft programming.
- the differential current could be measured in a sense amplifier (e.g., differential current amplifier) at 475 which would be conveyed via 477 to the verify controls 485 configured to convert the differential current produced at 475 into some combination of proportional pulse width, or pulse height modulation of the soft program pulse.
- a system and method to custom tailor a subsequent soft programming pulse e.g., pulse width, pulse height
- a subsequent soft programming pulse e.g., pulse width, pulse height
- the differential current produced at 475 may be bracketed into two or more levels which would result in the selection of an appropriate optimized pulse width/height modulation of the soft programming pulse.
- the flash memory array as a whole is selected, and the differential current produced at 475 may be used to generate some combination of proportional pulse width, or pulse height modulation of the soft program pulse, or a whole series of pulses as a pulse string which is thereby tailored to the flash memory array as a whole for subsequent soft program operations.
- the inventors found, as shown in FIGS. 5 a, and 5 b, that if they supplied a predetermined drain-source bias of about 1.2 volts to both the core cell and reference cell drains, and approximately 2.7 volts to the core cell gate, and about 3.7 volts to the reference cell gate, the currents would be equivalent if the core cell V T was equal to 0.7 volt.
- the core cell V T is 0.7 volt. Otherwise, if the core cell current exceeds the reference cell current, the core cell V T is less than 0.7 volts (a predetermined threshold) and requires another soft programming pulse.
- FIG. 6 an exemplary method and system 600 is illustrated for generating the various voltages required in the soft program control circuit 430 of FIG. 4; for example, voltages for soft programming 610 , soft programming verify 620 , wordline (core cell) gate 630 , and the reference cell gate reference voltage 640 .
- a wordline charge pump circuit 650 generates a boosted supply voltage 670 , through a reference logic circuit 680 , for the soft program verify supply 620 , in response to a soft program mode enable signal 690 .
- the drain charge pump circuit 660 generates a boosted programming voltage 610 to the reference logic circuit 680 in response to a program mode signal (not shown). As can be seen from FIG.
- the soft program control system 600 is operable to generate multiple voltages (for example, via a resistor network) having different values (e.g., V 1 ⁇ V 2 ⁇ V 3 ) for use in a soft program verify mode. In the above manner, unique voltages are provided for the core cell and reference cell, respectively.
- FIG. 7 is a schematic diagram illustrating an exemplary soft program mux logic circuit 700 (e.g., relating to the program mux 435 of FIG. 4).
- This multiplexer circuit 700 uses a network of logic gates 702 to generate a soft program enable signal 710 to the reference logic circuit 680 of FIG. 6 in response to the soft program mode signal fed thru 702 .
- the multiplexer circuit 700 also uses the program supply voltage 705 controlled by a regulator transistor 720 which is held in state by a latch 715 to generate a supply voltage 740 which is clamped by a diode 730 and fed to the wordline charge pump circuit 650 of FIG. 6.
- FIG. 8 is a schematic diagram 800 illustrating more of the details of an exemplary soft program reference voltage logic circuit 805 , and voltage divider circuit 850 (e.g., relating to the circuit 600 of FIG. 6).
- the charge pump boosted wordline voltage 810 is held by latch 825 to supply the soft program verify supply 820 (or 620 of FIG. 6), which enters at regulator transistor 830 , and at the gate of the soft program mode transistor 840 , to set-up the voltage divider 850 ratios to produce the 3.7 volt reference cell gate reference voltage 860 , and the 2.7 volt erased core cell gate reference voltage 870 .
- voltages having different values are provided so that the core cell and the reference cell will have their necessary gate voltages applied thereto in order to evaluate whether the erased core cell V T is above a predetermined value.
- a method of preventing erased memory cells from exhibiting an erased cell threshold voltage below a predetermined level is provided.
- FIG. 9 is a flow diagram 900 illustrating an exemplary method for verifying memory cell soft programming according to the invention, and will be discussed in conjunction with the exemplary system of FIG. 4 for purposes of explanation.
- the method 900 begins at step 910 , after which the soft program, and soft program verify modes are enabled at step 920 .
- the method 900 proceeds to step 925 , whereat a cell address is initialized to a first address, and, for example, a pulse counter is initialized to zero at step 930 . Following step 930 the first cell address is selected at step 940 . The first memory cell is then soft program verified at step 950 . At decision step 950 , a determination is made as to whether a core cell has been properly erased, but not over erased. As illustrated and described in greater detail hereinafter with respect to FIG.
- the soft program verification operations performed at steps 950 and 965 of the method 900 may be carried out via the application of about a 2.7 volt reference voltage to the selected core cell gate, and the application of a different reference voltage to the reference cell gate (e.g., about 3.7 volts), and then comparing the two currents, and making a determination based on that comparison whether the associated erased core cell threshold voltage is greater than 0.7 volts.
- a different reference voltage e.g., about 3.7 volts
- step 950 If, for example, at step 950 the selected core cell current is not less than the reference cell current, a determination is made that the core cell has a threshold voltage which is less than 0.7 volt, and the method 900 proceeds to step 955 , whereat an accounting may be performed of the current number of soft program pulses which have already been applied to the core cell in an attempt to correct the erase cell threshold voltage. If a predetermined number of pulses N P has been exceeded, a determination may be made at step 955 to identify the core cell as having failed the soft program process and proceeds to step 970 .
- step 955 the method 900 proceeds to step 960 , whereat the current pulse count is incremented.
- step 960 method 900 continues to step 965 for the application of a soft program pulse to core cell, and a return to step 950 for another soft program verification.
- step 950 the method 900 proceeds to step 980 , whereat it is determined whether the last cell address has been reached (e.g., in a given cell memory block or sector, or in a given multiple cell memory block or sector).
- the method may be selectively employed to verify erasure of a certain number of the cells (e.g., eight or sixteen), which are connected in a NOR configuration, although other implementations are possible wherein any number of such cells may be serially verified according to the invention.
- step 985 the method proceeds to step 985 , whereat a soft program pulse counter may be reset prior to proceeding to step 990 .
- step 990 the current address is incremented before proceeding to step 940 again, whereat the next cell address is selected as before. Otherwise (e.g., all such cells have been verified), the method 900 ends at step 995 .
- the method 900 selectively verifies, re-verifies, soft programs, and re-soft programs each cell of a dual bit memory cell in order to ensure proper soft programming prior to proceeding to another such cell at step 985 , or ending at step 995 .
- the method 900 may include internal counters or other steps by which a cell may be determined to be unuseable (e.g., unable to be properly soft program) after a number of unsuccessful attempts at soft programming/verification, whereby the cell (e.g., or a number of related cells, such as a byte or word) may be marked as bad, or the part itself may hang as part of a failed sector erase operation.
- a cell may be determined to be unuseable (e.g., unable to be properly soft program) after a number of unsuccessful attempts at soft programming/verification, whereby the cell (e.g., or a number of related cells, such as a byte or word) may be marked as bad, or the part itself may hang as part of a failed sector erase operation.
- the method 900 may be employed in a manufacturing process (e.g., before or after packaging, but before shipment to a customer), redundancy may be employed to mark a cell or a number of cells as bad, and to provide alternate or redundant storage cells as a replacement, whereby acceptable manufacturing yield may be achieved.
- the method 900 may also be employed in association with a sector or chip soft program/verification operation initiated by an end-user, wherein a cell failure may be indicated to the user via the memory device hanging as a result.
Abstract
Description
- The present invention relates generally to memory systems and in particular, to flash memory systems and methods wherein a new reference cell structure, and the application of unique reference voltages during soft program and soft program verify operations, eliminates previous problems of trimming a reference cell to a low threshold voltage, and tightens the erased core cell threshold voltage distribution, which also facilitates faster programming times.
- Flash memory is a type of electronic memory media which can be rewritten and hold its data without power. Flash memory devices generally have life spans from 100K to 1 MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in place, flash memory is less expensive and more dense. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
- Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell, for example, as illustrated in prior art FIG. 1a, and designated at
reference numeral 10. In such single bit memory architectures, eachcell 10 typically includes a metal oxide semiconductor (MOS) transistor structure having asource 12, adrain 14, and achannel 16 in a substrate or P-well 18, as well as a stackedgate structure 20 overlying thechannel 16. The stackedgate 20 may further include a thin gate dielectric layer 22 (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stackedgate 20 also includes apolysilicon floating gate 24 overlying thetunnel oxide 22 and an interpolydielectric layer 26 overlying the floating gate. The interpolydielectric layer 26 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, apolysilicon control gate 28 overlies the interpolydielectric layer 26. - The
control gate 28 is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, thedrain regions 14 of the cells are connected together by a conductive bit line. Thechannel 16 of the cell conducts current between thesource 12 and thedrain 14 in accordance with an electric field developed in thechannel 16 by thestacked gate structure 20. In the NOR configuration, eachdrain terminal 14 of the transistors within a single column is connected to the same bit line. In addition, each flash cell associated with a given bit line has its stackedgate terminal 28 coupled to a different word line, while all the flash cells in the array have theirsource terminals 12 coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry (not shown) for programming (writing), reading or erasing functions. - Such a conventional single bit stacked gate
flash memory cell 10 is programmed by applying a relatively high voltage to thecontrol gate 28 and connecting thesource 12 to ground and thedrain 14 to a predetermined potential above the source. A resulting high electric field across thetunnel oxide 22 leads to a phenomena called “Fowler-Nordheim” tunneling. During this process, electrons in the corecell channel region 16 tunnel through the gate ortunnel oxide 22 into thefloating gate 24 and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric 26 and thetunnel oxide 22. As a result of the trapped electrons, the threshold voltage of thecell 10 increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed. - In order to erase a conventional single bit stacked gate
flash memory cell 10, a relatively high voltage is applied to thesource 12, and thecontrol gate 28 is held at a negative potential, while thedrain 14 is allowed to float. Under these conditions, a strong electric field is developed across thetunnel oxide 22 between thefloating gate 24 and thesource 12. The electrons that are trapped in thefloating gate 24 flow toward and cluster at the portion of the floating gate overlying thesource region 12 and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through thetunnel oxide 22. As the electrons are removed from thefloating gate 24, thecell 10 is erased. - In conventional single bit flash memory devices, an erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells which fail the initial verification. Thereafter, the erased status of the cell is again verified, and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
- After erasure, some cells may have been over erased, producing an excessively low threshold voltage and corresponding high drain current leakage which may cause problems with later read, program verify, or even erase operations. The process of soft programming has typically been adopted as a means to correct the over erased cells. Usually this process involves applying one or more program pulses to the over erased cells. The soft program process raises (or corrects) the low threshold voltages of the identified cells, to effectively narrow the distribution of erased cell threshold voltages across a flash memory array.
- Recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell. FIG. 1b illustrates an exemplary prior art dual
bit memory cell 50. Thememory cell 50 comprises asilicon dioxide layer 52, a P-type substrate 54 has buriedN+ source 56 andN+ drain 58 regions. Thesilicon dioxide 52 is sandwiched between two layers of silicon nitride 60, and 62. Alternatively, thelayer 52 may comprise buried polysilicon islands or any other form of charge trapping layer. - Overlying the nitride layer60 is a
polysilicon gate 64. Thisgate 64 is doped with an N-type impurity (e.g., phosphorus). Thememory cell 50 is capable of storing two data bits, a left bit represented by the dashed circle A and a right bit represented by the dashed circle B. The dualbit memory cell 50 is generally symmetrical, thus thedrain 58 and thesource 56 are interchangeable. Thus, theleft junction 56 may serve as the source terminal and theright junction 58 as the drain terminal with respect to the right bit B. Likewise, theright junction 58 may serve as the source terminal and theleft junction 56 as the drain terminal for the left bit A. - After erasure of a dual bit cell, the conventional soft programming, and soft program verification methods employed with single bit stacked gate architectures may be applied in certain circumstances to such dual bit devices, but are problematic at best because the end of the erase distribution VT's are not close to zero, but are at 0.7 volts. Therefore, there is a need for new and improved soft programming, and soft program verification methods and systems, which ensure proper control of the erased cell threshold voltage distribution of data bits in a dual bit memory architecture, and which account for the structural characteristics thereof.
- A system and methodology are provided which overcome or minimize the problems and shortcomings of conventional memory cell soft program verification schemes and systems. The invention includes methods and systems for verifying an erased cell threshold voltage of one or more dual bit cells in a memory device, such as a flash memory. The invention allows for efficient and thorough soft program verification, which minimizes inadvertent, undesired data retention, over-erase and cell read leakage issues associated with the dual bit cell architecture. The invention provides significant advantages when employed in association with dual bit memory cells wherein only one bit thereof is actively used for data storage. However, it will be recognized that the invention finds utility in association with dual bit memory cell architectures generally, and that the invention is thus not limited to any particular dual bit cell usage implementation or configuration.
- In accordance with one aspect of the invention, there is provided a method of verifying an erased cell threshold voltage of a dual bit memory cell. The erased cell threshold voltage verification method comprises the steps of performing a determination of whether a first, or second bit in the dual bit memory cell is properly soft programmed.
- Verification of proper soft programming in a dual bit memory cell configuration according to the inventive method ensures that undesirable data retention or bit over-erase problems (resulting in a low threshold voltage, and consequent high leakage current) do not adversely affect the operation (e.g., proper erasure, read/write functionality) of the core cell. In this manner, the invention provides significant performance advantages over conventional methods typically utilized in soft programming of single bit (e.g., stacked gate) memory cell types. The method may further comprise repeating the method for another dual bit memory cell, whereby a byte-wise soft programming verification may be accomplished, for example, in association with a chip erase or sector erase operation.
- A soft program verification of a core cell threshold voltage may be performed through the application of a voltage to the memory cell being verified along with an application of a different voltage to a reference cell with a known threshold voltage, then comparing the currents of the core cell under analysis and the reference cell, respectively. When this comparison indicates that one or more of the soft programming pulses have reduced the current in the cell being verified to less than that of the reference cell, the core cell threshold voltage is above a target minimum erased cell threshold voltage. Moreover, according to one aspect of the invention, the process may be repeated for each cell in the array until each erased cell threshold voltage is above a target minimum.
- In addition, the method may also include an accounting of the number of soft program pulses which are applied to any one core cell, or block of core cells, in the event the cell, or block of cells are not responding to soft program verify. In this case, where a predetermined maximum soft program pulse count is exceeded, the cell, or block of cells is identified as having failed soft programming, and therefore avoid an endless soft program loop. For example, this method may include steps of initializing a pulse counter before each new cell address is selected, performing the soft program verification, determining whether the pulse counter has exceeded the preset maximum pulse count, then, if the count has not been exceeded, continuing to a step of incrementing the pulse counter as another soft program pulse is applied, or if the pulse count has been exceeded, a further step may be to proceed with appropriate actions for a failed soft programming.
- According to another aspect of the invention, there is provided a method to custom tailor a subsequent soft programming pulse (e.g., pulse width, pulse height) according to the differential current in the comparator, to greatly speed up the overall soft programming process, or to minimize the effects of over soft programming.
- The method of the present invention may include several selected core cells, or blocks of cells for soft programming operations, as well as selected core cells, or blocks of cells for soft program verifications.
- According to another aspect of the invention, there is provided a method for soft programming and soft program verifying a plurality of dual bit flash memory cells, which includes the steps of soft programming the plurality of dual bit flash memory cells, verifying proper soft programming of a first bit in at least one of the plurality of dual bit flash memory cells, verifying proper soft programming of a second bit in the at least one of the plurality of dual bit flash memory cells, and determining that the cell is properly soft programmed if the first and second bits are properly soft programmed.
- To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
- FIG. 1a is a fragmentary cross section view of an exemplary prior art, single bit flash memory cell;
- FIG. 1b is a fragmentary cross section view of an exemplary prior art dual bit memory cell in which various aspects of the present invention may be implemented;
- FIG. 2 is a distribution plot illustrating an erased cell threshold voltage distribution of a number of core cells of an exemplary prior art flash memory array;
- FIG. 3 is a distribution plot illustrating an erased cell threshold voltage distribution and a programmed cell threshold voltage distribution of a number of core cells of an exemplary dual bit memory array, together with over-erased bits which require soft programming according to the invention;
- FIG. 4 is a system level functional block diagram illustrating an exemplary soft program and soft program verification system in which various aspects of the invention may be carried out;
- FIG. 5a is a schematic diagram illustrating an exemplary core cell, core current, and gate voltage in the system of FIG. 4;
- FIG. 5b is a schematic diagram illustrating an exemplary reference cell, reference current, and gate voltage in the system of FIG. 4;
- FIG. 6 is a functional block diagram illustrating a soft program reference voltage and charge pump logic circuit of the system of FIG. 4;
- FIG. 7 is a schematic diagram illustrating an exemplary soft program multiplexer (hereinafter referred to as “mux”) logic circuit of the system of FIG. 4;
- FIG. 8 is a schematic diagram illustrating details of an exemplary soft program reference voltage logic circuit, and voltage divider circuit of the system of FIG. 6; and
- FIG. 9 is a flow diagram illustrating an exemplary method for verifying memory cell soft programming according to the invention.
- The following is a detailed description of the present invention made in conjunction with the attached figures, wherein like reference numerals will refer to like elements throughout. The invention provides a method and a system for soft programming, and verifying proper soft programming of one or more dual bit memory cells, and may be used in conjunction with a chip or sector soft program and soft program verification operation in a flash memory device. For example, a sector soft programming verify operation may be performed in order to apply soft programming pulses to each such cell in a flash memory device. Thereafter, the invention may be employed in order to verify which cells in the device have been properly soft programmed.
- In addition, the invention selectively attempts to re-soft program cells (e.g., via selective application of soft program voltage pulses to one or both individual bits in a dual bit memory cell) which have been over erased during the erase part of the algorithm that is performed before the soft program verify operation. The invention also provides for selective re-verification of proper soft programming of one or both bits in a dual bit cell.
- According to one aspect of the invention, proper soft program verification may be accomplished through generating a soft program core cell verification voltage and generating a reference cell verification voltage having a value which is different from the core cell verification voltage. The method further includes applying the core cell verification voltage to a gate portion of an over erased core cell to thereby generate a core cell current, and applying the reference cell voltage verification voltage to a gate portion of a reference cell to thereby generate a reference cell current. Lastly, the method includes determining whether a threshold voltage associated with the erased core cell is less than a predetermined threshold based on a comparison of the core cell current and the reference cell current.
- Although the invention is hereinafter illustrated and described in association with a dual bit memory cell architecture wherein only one bit of each cell is used for data storage, it will be appreciated that the invention is applicable to other type architectures and other dual bit architecture usage schemes.
- Referring again to the drawings, FIG. 2 illustrates a characteristic curve known as the erased core cell threshold voltage distribution. FIG. 2 illustrates how the core cell threshold voltages in a flash memory array can differ from one another following an erase operation as shown by
curve 200 that represents the number of cells having particular values of threshold voltage VT. It has been found that the least erased cells will have relatively high threshold voltages in the region of VTMAX, whereas the most erased cells (sometimes referred to as “over-erased cells”) will have low threshold voltages in the region of VTMIN that can be zero or negative. However, the threshold voltagedistribution curve segment 210 indicates that there is still a number of erased cells that have a relatively low threshold voltage. After correcting the VT of the most over erased cells thru the soft program and soft program verify operations, the erased core cell thresholdvoltage distribution curve 200 will narrow on the low end of the curve (shown by curve segment 210) to approximately 0 Volts. - Since the background leakage current of a cell varies as a function of threshold voltage, the lower the threshold voltage of an erased cell, the higher the leakage current will be. Because there may be as many as 512 cells connected to a bitline, the total background leakage current may disadvantageously exceed the cell read current thereby leading to a subsequent read error. It is therefore desirable to prevent cells from not only being over-erased, but to reduce the threshold voltage distribution to as low a range as possible, with ideally all cells having the same high threshold voltage after erase.
- Similarly, FIG. 3 illustrates characteristic cell threshold voltage distribution curves of an exemplary dual bit memory array illustrating a desired erased cell
threshold voltage distribution 350, and a programmed cellthreshold voltage distribution 360. As discussed earlier, after erasure, some cells may have been over erased, producing an excessively low threshold voltage (shaded region 370) and corresponding high drain current leakage which may cause problems with later read, program verify, or even erase operations. Conventional methods of chip, sector, or cell soft programming typically used in the single bit stacked gate cell, attempted to correct the over erased cells, by applying one or more program pulses to the over erased cells. Soft programming raises (or corrects) the low threshold voltages on these cells, to effectively narrow the distribution of cell threshold voltages across a flash memory array. Soft program verification was done by comparing the current produced in the selected core cell, and its' associated erased cell threshold voltage, to that of a reference cell with an acceptable threshold voltage. - Comparing FIGS. 2 and 3, one sees that the prior art single bit cell was typically soft program corrected to a VTMIN of about 0 volts, whereas the dual bit erased cell, soft program corrected VTMIN increases to about 0.7 volt. In the stacked gate cell prior art, the reference cell was manufactured similar to the selected core cell(s) they were compared to, and both the reference and core cells were given the same gate voltages during the soft program verify. In the dual bit cell architecture, however, the reference cell structure can not readily be made the same as the core cells, yet a soft program verification must still be made to produce a desired erased core cell VT (e.g., VT>0.7 volts). The inventors have found in the trimming of the VT of the new reference cell structure, that attempts to trim the VT to less than about 1.7 volts results in unusably high cell leakage current.
- In accordance with the invention, and the solutions to these problems, the inventors devised methods and systems to generate different voltages to be applied to the gate of the new reference cell structure and the core cell structure, respectively, to allow the reference cell to produce a current which compares to an erased core cell current associated with a VT>0.7 volts.
- The present invention may be understood and its advantages appreciated in FIG. 4 which illustrates a system level functional block diagram of an exemplary soft program and soft
program verification system 400 in which various aspects of the invention may be accomplished. For example, the system of FIG. 4 prevents erased memory cells from exhibiting an erased cell threshold voltage below a predetermined level, may be comprised of the three functional blocks shown. - A flash
memory array system 402 of FIG. 4, includes an array ofcore cells 405 which are typically subdivided into sectors, blocks, and individual core cells. The cells are arranged in rows and columns, with all of the cells in a row having their control gate connected to a common word line. The drains of the cells located in a particular column are all connected to a common bit line while all the cells of the array have their sources coupled to acommon source line 490 to enable the measurement of drain current in the core cells (ICORE) at 490. Thememory system 402, also has address controls 410 which acts as a matrix of multiplexors working in conjunction with bit - column controls 415 and word- row controls 420 used to select a sector, block, or individual cells of thecore 405. Therow control block 420 is connected to the word lines of the cells of the array and acolumn control block 415 is connected to the bit lines of the array. In operation, individual flash cells may be individually addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions. Theseflash core cells 405 will be the object of the soft program and soft program verify operations of the present invention, and discussed in greater detail in the following sections. - A soft
program control circuit 430 of FIG. 4, is configured with asoft program multiplexer 435 charge pumps 440 and a soft programreference voltage circuit 445 to generate a soft program voltage (V1) at 450, a soft program core cell verify voltage (V3) at 455, and a reference cell verification voltage (V2) at 460. In response to a logic command to enter the soft program mode (or for example, as the result of a soft program verify comparison command 487), themultiplexer circuit 430 generates a soft program enablesignal 436 to control thereference logic circuit 445 or for example, the nextcore address selection 437. Themultiplexer circuit 435 also generates a regulated, clampedsupply voltage 438 to the wordline charge pump circuit of 440. The charge pumps of 440 include a Drain charge pump which generates a supply voltage for program verify operations, and a wordline charge pump circuit configured to generate a boosted wordline supply voltage for the voltage divider within the soft programreference voltage circuit 445. The soft programreference voltage circuit 445 takes the soft program enablesignals charge pump voltages - A soft program verify
control circuit 470 according to one exemplary aspect of the present invention of FIG. 4, is configured with areference cell 480 which uses V2, the referencecell verification voltage 460 to generate the reference cell current (IREF) at 495. Thecontrol circuit 470 further includes a soft program verifycomparator circuit 475 which is configured to compare the over erased core cell verification current (ICORE) at 490 to the reference cell current (IREF) at 495 to generate an output indication on 477 of whether the selected erased core cell threshold voltage is below a predetermined level. The soft program verify comparator circuit is further operable to transfer the VT indication to a verifycontrols circuit 485 which is configured to output one or more soft program control signals 486 and 487 for use in soft programming based on the indication. - During operation, when
comparator 475 of the soft program verifycontrol circuit 470, has made the determination that the selected core cell VT is less than 0.7 volts,comparator 475 providessignal 477 to initiate a predetermined soft program pulse from verifycontrols circuit 485 via 487 back to the softprogram control circuit 430. - Alternately, according to another aspect of the present invention, there is provided a system and method to custom tailor a subsequent soft programming pulse (e.g., pulse width, pulse height) according to the differential current in the
comparator 475, to greatly speed up the overall soft programming process, or to minimize the effects of over soft programming. To accomplish this, the differential current could be measured in a sense amplifier (e.g., differential current amplifier) at 475 which would be conveyed via 477 to the verifycontrols 485 configured to convert the differential current produced at 475 into some combination of proportional pulse width, or pulse height modulation of the soft program pulse. - In another variation of the present invention, there is provided a system and method to custom tailor a subsequent soft programming pulse (e.g., pulse width, pulse height) through the use of a look-up table located in a portion of the
core memory array 405, or in a separate memory, wherein the differential current produced at 475 may be bracketed into two or more levels which would result in the selection of an appropriate optimized pulse width/height modulation of the soft programming pulse. Yet another variation and aspect of the invention is provided by the method, wherein the flash memory array as a whole is selected, and the differential current produced at 475 may be used to generate some combination of proportional pulse width, or pulse height modulation of the soft program pulse, or a whole series of pulses as a pulse string which is thereby tailored to the flash memory array as a whole for subsequent soft program operations. - The inventors found, as shown in FIGS. 5a, and 5 b, that if they supplied a predetermined drain-source bias of about 1.2 volts to both the core cell and reference cell drains, and approximately 2.7 volts to the core cell gate, and about 3.7 volts to the reference cell gate, the currents would be equivalent if the core cell VT was equal to 0.7 volt.
- The development of this reference cell voltage is as follows:
Using the equation: ID = k(VGS − VT)2 for the erased core IDCORE = k(VGSCORE − VTCORE)2 cell: for the reference IDREF = k(VGSREF − VTREF)2 cell: given we want: VTCORE ≧ 0.7 V and VTREF 1.7 V now, for the ref- IDREF = IDCORE erence cell and the core cell currents to compare equally: and: k(VGSREF − VTREF)2 = k(VGSCORE − VTCORE)2 dividing thru: VGSREF − VTREF = VGSCORE − VTCORE solving for the VGSREF = VGSCORE − VTCORE + VTREF new ref.: substituting given VGSREF = VGSCORE − 0.7 + 1.7 values: plug in a core cell VGSREF = 2.7 − 0.7 + 1.7 value: we have: VGSREF = 3.7 volts - Therefore, if the currents through the core cell and reference cell are equal, then the core cell VT is 0.7 volt. Otherwise, if the core cell current exceeds the reference cell current, the core cell VT is less than 0.7 volts (a predetermined threshold) and requires another soft programming pulse.
- Referring now to the functional block diagram of FIG. 6, an exemplary method and
system 600 is illustrated for generating the various voltages required in the softprogram control circuit 430 of FIG. 4; for example, voltages forsoft programming 610, soft programming verify 620, wordline (core cell)gate 630, and the reference cellgate reference voltage 640. A wordlinecharge pump circuit 650 generates a boostedsupply voltage 670, through areference logic circuit 680, for the soft program verifysupply 620, in response to a soft program mode enablesignal 690. The draincharge pump circuit 660 generates a boostedprogramming voltage 610 to thereference logic circuit 680 in response to a program mode signal (not shown). As can be seen from FIG. 6, the softprogram control system 600 is operable to generate multiple voltages (for example, via a resistor network) having different values (e.g., V1≠V2≠V3) for use in a soft program verify mode. In the above manner, unique voltages are provided for the core cell and reference cell, respectively. - FIG. 7 is a schematic diagram illustrating an exemplary soft program mux logic circuit700 (e.g., relating to the
program mux 435 of FIG. 4). Thismultiplexer circuit 700 uses a network oflogic gates 702 to generate a soft program enablesignal 710 to thereference logic circuit 680 of FIG. 6 in response to the soft program mode signal fed thru 702. Themultiplexer circuit 700 also uses theprogram supply voltage 705 controlled by aregulator transistor 720 which is held in state by alatch 715 to generate asupply voltage 740 which is clamped by adiode 730 and fed to the wordlinecharge pump circuit 650 of FIG. 6. - FIG. 8 is a schematic diagram800 illustrating more of the details of an exemplary soft program reference
voltage logic circuit 805, and voltage divider circuit 850 (e.g., relating to thecircuit 600 of FIG. 6). The charge pump boostedwordline voltage 810 is held bylatch 825 to supply the soft program verify supply 820 (or 620 of FIG. 6), which enters atregulator transistor 830, and at the gate of the softprogram mode transistor 840, to set-up thevoltage divider 850 ratios to produce the 3.7 volt reference cellgate reference voltage 860, and the 2.7 volt erased core cellgate reference voltage 870. In the above exemplary manner, voltages having different values are provided so that the core cell and the reference cell will have their necessary gate voltages applied thereto in order to evaluate whether the erased core cell VT is above a predetermined value. - According to another aspect of the present invention, a method of preventing erased memory cells from exhibiting an erased cell threshold voltage below a predetermined level is provided.
- FIG. 9 is a flow diagram900 illustrating an exemplary method for verifying memory cell soft programming according to the invention, and will be discussed in conjunction with the exemplary system of FIG. 4 for purposes of explanation. For example, once an erase or erase verify operation has been performed to erase the data bits of a sector of memory (e.g., by writing a 1 value thereto), the
method 900 begins atstep 910, after which the soft program, and soft program verify modes are enabled atstep 920. - The
method 900 proceeds to step 925, whereat a cell address is initialized to a first address, and, for example, a pulse counter is initialized to zero atstep 930. Followingstep 930 the first cell address is selected atstep 940. The first memory cell is then soft program verified atstep 950. Atdecision step 950, a determination is made as to whether a core cell has been properly erased, but not over erased. As illustrated and described in greater detail hereinafter with respect to FIG. 4, the soft program verification operations performed atsteps method 900, may be carried out via the application of about a 2.7 volt reference voltage to the selected core cell gate, and the application of a different reference voltage to the reference cell gate (e.g., about 3.7 volts), and then comparing the two currents, and making a determination based on that comparison whether the associated erased core cell threshold voltage is greater than 0.7 volts. - If, for example, at
step 950 the selected core cell current is not less than the reference cell current, a determination is made that the core cell has a threshold voltage which is less than 0.7 volt, and themethod 900 proceeds to step 955, whereat an accounting may be performed of the current number of soft program pulses which have already been applied to the core cell in an attempt to correct the erase cell threshold voltage. If a predetermined number of pulses NP has been exceeded, a determination may be made atstep 955 to identify the core cell as having failed the soft program process and proceeds to step 970. In this manner, the core cell will not be subjected to repeated soft program pulses without being re-verified; the program will not hang in a never ending loop, should a selected cell be defective; and most importantly, the soft program pulse widths can be made shorter, resulting in a faster overall soft programming time, as soft programming time only need be spent in the areas of greatest need. If, however instep 955, a predetermined pulse count has not exceeded NP, themethod 900 proceeds to step 960, whereat the current pulse count is incremented. - After
step 960,method 900 continues to step 965 for the application of a soft program pulse to core cell, and a return to step 950 for another soft program verification. - Where it is found at
decision step 950 that the cell has been properly soft programmed, themethod 900 proceeds to step 980, whereat it is determined whether the last cell address has been reached (e.g., in a given cell memory block or sector, or in a given multiple cell memory block or sector). For example, the method may be selectively employed to verify erasure of a certain number of the cells (e.g., eight or sixteen), which are connected in a NOR configuration, although other implementations are possible wherein any number of such cells may be serially verified according to the invention. - If the last cell address has not been reached at
decision step 980, the method proceeds to step 985, whereat a soft program pulse counter may be reset prior to proceeding to step 990. Atstep 990 the current address is incremented before proceeding to step 940 again, whereat the next cell address is selected as before. Otherwise (e.g., all such cells have been verified), themethod 900 ends atstep 995. - Thus, the
method 900 selectively verifies, re-verifies, soft programs, and re-soft programs each cell of a dual bit memory cell in order to ensure proper soft programming prior to proceeding to another such cell atstep 985, or ending atstep 995. - It will be appreciated in this regard, that the
method 900 may include internal counters or other steps by which a cell may be determined to be unuseable (e.g., unable to be properly soft program) after a number of unsuccessful attempts at soft programming/verification, whereby the cell (e.g., or a number of related cells, such as a byte or word) may be marked as bad, or the part itself may hang as part of a failed sector erase operation. Further in this regard, if themethod 900 is employed in a manufacturing process (e.g., before or after packaging, but before shipment to a customer), redundancy may be employed to mark a cell or a number of cells as bad, and to provide alternate or redundant storage cells as a replacement, whereby acceptable manufacturing yield may be achieved. Themethod 900 may also be employed in association with a sector or chip soft program/verification operation initiated by an end-user, wherein a cell failure may be indicated to the user via the memory device hanging as a result. - Although the invention has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the term “includes” is used in either the detailed description and the claims, such term is intended to be inclusive in a manner similar to the term “comprising.”
Claims (15)
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/829,193 US6493266B1 (en) | 2001-04-09 | 2001-04-09 | Soft program and soft program verify of the core cells in flash memory array |
PCT/US2001/048734 WO2002082447A2 (en) | 2001-04-09 | 2001-12-12 | Soft program and soft program verify of the core cells in flash memory array |
EP01991202A EP1415302B1 (en) | 2001-04-09 | 2001-12-12 | Soft program and soft program verify of the core cells in flash memory array |
AU2002230944A AU2002230944A1 (en) | 2001-04-09 | 2001-12-12 | Soft program and soft program verify of the core cells in flash memory array |
JP2002580327A JP4068464B2 (en) | 2001-04-09 | 2001-12-12 | Soft program and soft program verification of core cells in a flash memory array |
CNB018231195A CN100365735C (en) | 2001-04-09 | 2001-12-12 | Soft program and soft program verify of core ctlls in flash memory array |
KR1020037013262A KR100828196B1 (en) | 2001-04-09 | 2001-12-12 | Soft program and soft program verify of the core cells in flash memory array |
DE60115716T DE60115716T2 (en) | 2001-04-09 | 2001-12-12 | SOFT PROGRAMMING AND SOFT PROGRAMMING VERIFICATION OF FLASH MEMORY CELLS |
TW091104663A TW584858B (en) | 2001-04-09 | 2002-03-13 | Soft program and soft program verify of the core cells in flash memory array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/829,193 US6493266B1 (en) | 2001-04-09 | 2001-04-09 | Soft program and soft program verify of the core cells in flash memory array |
Publications (2)
Publication Number | Publication Date |
---|---|
US6493266B1 US6493266B1 (en) | 2002-12-10 |
US20030021155A1 true US20030021155A1 (en) | 2003-01-30 |
Family
ID=25253800
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/829,193 Expired - Lifetime US6493266B1 (en) | 2001-04-09 | 2001-04-09 | Soft program and soft program verify of the core cells in flash memory array |
Country Status (9)
Country | Link |
---|---|
US (1) | US6493266B1 (en) |
EP (1) | EP1415302B1 (en) |
JP (1) | JP4068464B2 (en) |
KR (1) | KR100828196B1 (en) |
CN (1) | CN100365735C (en) |
AU (1) | AU2002230944A1 (en) |
DE (1) | DE60115716T2 (en) |
TW (1) | TW584858B (en) |
WO (1) | WO2002082447A2 (en) |
Cited By (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030161187A1 (en) * | 2002-01-31 | 2003-08-28 | Yu-Shen Lin | Method for erasing a flash EEPROM |
US20030227796A1 (en) * | 2002-06-11 | 2003-12-11 | Fujitsu Limited | Nonvolatile semiconductor memory device capable of correcting over-erased memory cells |
US20040153620A1 (en) * | 2003-01-30 | 2004-08-05 | Shai Eisen | Address scramble |
US20040222437A1 (en) * | 2000-12-07 | 2004-11-11 | Dror Avni | Programming and erasing methods for an NROM array |
US20050058005A1 (en) * | 2002-01-31 | 2005-03-17 | Assaf Shappir | Method for operating a memory device |
US6901010B1 (en) * | 2002-04-08 | 2005-05-31 | Advanced Micro Devices, Inc. | Erase method for a dual bit memory cell |
US20050117395A1 (en) * | 2002-01-31 | 2005-06-02 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US20050201401A1 (en) * | 2004-03-14 | 2005-09-15 | M-Systems Flash Disk Pioneers, Ltd. | States encoding in multi-bit flash cells |
US20050276118A1 (en) * | 2004-06-10 | 2005-12-15 | Eduardo Maayan | Reduced power programming of non-volatile cells |
US20060044919A1 (en) * | 2004-08-30 | 2006-03-02 | Spansion Llc | Non-volatile memory device and erasing method therefor |
US20060056240A1 (en) * | 2004-04-01 | 2006-03-16 | Saifun Semiconductors, Ltd. | Method, circuit and system for erasing one or more non-volatile memory cells |
US20060068551A1 (en) * | 2004-09-27 | 2006-03-30 | Saifun Semiconductors, Ltd. | Method for embedding NROM |
US20060152975A1 (en) * | 2002-07-10 | 2006-07-13 | Eduardo Maayan | Multiple use memory chip |
US20060158940A1 (en) * | 2005-01-19 | 2006-07-20 | Saifun Semiconductors, Ltd. | Partial erase verify |
US20060211188A1 (en) * | 2004-10-14 | 2006-09-21 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
US20060285386A1 (en) * | 2005-06-15 | 2006-12-21 | Saifun Semiconductors, Ltd. | Accessing an NROM array |
US20060285408A1 (en) * | 2005-06-17 | 2006-12-21 | Saifun Semiconductors, Ltd. | Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells |
US20070032016A1 (en) * | 2001-11-19 | 2007-02-08 | Saifun Semiconductors Ltd. | Protective layer in memory device and method therefor |
US20070036007A1 (en) * | 2005-08-09 | 2007-02-15 | Saifun Semiconductors, Ltd. | Sticky bit buffer |
US20070051982A1 (en) * | 2005-07-18 | 2007-03-08 | Saifun Semiconductors Ltd. | Dense non-volatile memory array and method of fabrication |
US20070097747A1 (en) * | 2005-10-27 | 2007-05-03 | Yan Li | Apparatus for programming of multi-state non-volatile memory using smart verify |
US20070096199A1 (en) * | 2005-09-08 | 2007-05-03 | Eli Lusky | Method of manufacturing symmetric arrays |
US20070097749A1 (en) * | 2005-10-27 | 2007-05-03 | Yan Li | Method for programming of multi-state non-volatile memory using smart verify |
US20070103980A1 (en) * | 2005-11-10 | 2007-05-10 | Gert Koebernick | Method for operating a semiconductor memory device and semiconductor memory device |
US20070120180A1 (en) * | 2005-11-25 | 2007-05-31 | Boaz Eitan | Transition areas for dense memory arrays |
US20070133276A1 (en) * | 2003-09-16 | 2007-06-14 | Eli Lusky | Operating array cells with matched reference cells |
US20070141788A1 (en) * | 2005-05-25 | 2007-06-21 | Ilan Bloom | Method for embedding non-volatile memory with logic circuitry |
US20070153575A1 (en) * | 2006-01-03 | 2007-07-05 | Saifun Semiconductors, Ltd. | Method, system, and circuit for operating a non-volatile memory array |
US20070159880A1 (en) * | 2006-01-12 | 2007-07-12 | Boaz Eitan | Secondary injection for NROM |
US20070168637A1 (en) * | 2003-01-31 | 2007-07-19 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
US20070171717A1 (en) * | 2004-08-12 | 2007-07-26 | Saifun Semiconductors Ltd. | Dynamic matching of signal path and reference path for sensing |
US20070173017A1 (en) * | 2006-01-20 | 2007-07-26 | Saifun Semiconductors, Ltd. | Advanced non-volatile memory array and method of fabrication thereof |
US20070194835A1 (en) * | 2006-02-21 | 2007-08-23 | Alexander Kushnarenko | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US20070196982A1 (en) * | 2006-02-21 | 2007-08-23 | Saifun Semiconductors Ltd. | Nrom non-volatile mode of operation |
US20070195607A1 (en) * | 2006-02-21 | 2007-08-23 | Saifun Semiconductors Ltd. | Nrom non-volatile memory and mode of operation |
US20070237003A1 (en) * | 2006-04-05 | 2007-10-11 | Ashot Melik-Martirosian | Flash memory programming and verification with reduced leakage current |
US20070253248A1 (en) * | 2006-04-27 | 2007-11-01 | Eduardo Maayan | Method for programming a reference cell |
US20070255889A1 (en) * | 2006-03-22 | 2007-11-01 | Yoav Yogev | Non-volatile memory device and method of operating the device |
US20080094127A1 (en) * | 2006-09-18 | 2008-04-24 | Yoram Betser | Measuring and controlling current consumption and output current of charge pumps |
US20080111177A1 (en) * | 1997-08-01 | 2008-05-15 | Eduardo Maayan | Non-volatile memory cell and non-volatile memory device using said cell |
US20080239599A1 (en) * | 2007-04-01 | 2008-10-02 | Yehuda Yizraeli | Clamping Voltage Events Such As ESD |
US7489560B2 (en) | 2006-04-05 | 2009-02-10 | Spansion Llc | Reduction of leakage current and program disturbs in flash memory devices |
US20090190408A1 (en) * | 2008-01-28 | 2009-07-30 | Andreas Kux | Method of Operating an Integrated Circuit, Integrated Circuit and Method to Determine an Operating Point |
US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
US7675782B2 (en) | 2002-10-29 | 2010-03-09 | Saifun Semiconductors Ltd. | Method, system and circuit for programming a non-volatile memory array |
US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
US20120134228A1 (en) * | 2010-11-30 | 2012-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Charge pump control scheme for memory word line |
US8245099B2 (en) | 2004-03-14 | 2012-08-14 | Sandisk Il Ltd. | States encoding in multi-bit flash cells for optimizing error rate |
US20120218827A1 (en) * | 2011-02-28 | 2012-08-30 | Hynix Semiconductor Inc. | Memory apparatus and method for controlling erase operation of the same |
US20140063946A1 (en) * | 2012-08-28 | 2014-03-06 | Fuchen Mu | Non-volatile memory (nvm) that uses soft programming |
US8830756B2 (en) * | 2013-01-23 | 2014-09-09 | Freescale Semiconductor, Inc. | Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory |
US8947958B2 (en) | 2012-10-09 | 2015-02-03 | Freescale Semiconductor, Inc. | Latent slow bit detection for non-volatile memory |
US8995198B1 (en) | 2013-10-10 | 2015-03-31 | Spansion Llc | Multi-pass soft programming |
US8995202B2 (en) | 2012-05-21 | 2015-03-31 | Freescale Semiconductor, Inc. | Test flow to detect a latent leaky bit of a non-volatile memory |
CN114995750A (en) * | 2022-05-25 | 2022-09-02 | 北京得瑞领新科技有限公司 | Method, device, storage medium and storage equipment for improving reliability of flash memory data |
US11594281B2 (en) | 2006-12-14 | 2023-02-28 | Mosaid Technologies Inc. | Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6584017B2 (en) * | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
US6925007B2 (en) | 2001-10-31 | 2005-08-02 | Sandisk Corporation | Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements |
US6897522B2 (en) * | 2001-10-31 | 2005-05-24 | Sandisk Corporation | Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements |
US7001807B1 (en) | 2001-12-20 | 2006-02-21 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
US6639271B1 (en) * | 2001-12-20 | 2003-10-28 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
US6661711B2 (en) * | 2002-02-06 | 2003-12-09 | Sandisk Corporation | Implementation of an inhibit during soft programming to tighten an erase voltage distribution |
US6639844B1 (en) * | 2002-03-13 | 2003-10-28 | Advanced Micro Devices, Inc. | Overerase correction method |
JP2003346484A (en) * | 2002-05-23 | 2003-12-05 | Mitsubishi Electric Corp | Nonvolatile semiconductor storage device |
EP1453059B1 (en) * | 2003-02-28 | 2005-10-12 | STMicroelectronics S.r.l. | Gate voltage regulation system for a non volatile memory cells and a programming and soft programming phase |
US6917542B2 (en) * | 2003-07-29 | 2005-07-12 | Sandisk Corporation | Detecting over programmed memory |
US6914823B2 (en) * | 2003-07-29 | 2005-07-05 | Sandisk Corporation | Detecting over programmed memory after further programming |
US6954393B2 (en) * | 2003-09-16 | 2005-10-11 | Saifun Semiconductors Ltd. | Reading array cell with matched reference cell |
KR100634169B1 (en) * | 2004-03-10 | 2006-10-16 | 삼성전자주식회사 | Sense amplifier and method for generating variable reference level |
TWI258768B (en) * | 2004-03-10 | 2006-07-21 | Samsung Electronics Co Ltd | Sense amplifier and method for generating variable reference level |
TWI247311B (en) * | 2004-03-25 | 2006-01-11 | Elite Semiconductor Esmt | Circuit and method for preventing nonvolatile memory from over erasure |
CN100353457C (en) * | 2004-04-30 | 2007-12-05 | 晶豪科技股份有限公司 | Circuit and method for preventing non-volatile memory from over-erasing |
US6834012B1 (en) * | 2004-06-08 | 2004-12-21 | Advanced Micro Devices, Inc. | Memory device and methods of using negative gate stress to correct over-erased memory cells |
US7180775B2 (en) * | 2004-08-05 | 2007-02-20 | Msystems Ltd. | Different numbers of bits per cell in non-volatile memory devices |
US7092290B2 (en) * | 2004-11-16 | 2006-08-15 | Sandisk Corporation | High speed programming system with reduced over programming |
WO2006105133A1 (en) * | 2005-03-31 | 2006-10-05 | Sandisk Corporation | Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells |
JP2006294144A (en) * | 2005-04-12 | 2006-10-26 | Toshiba Corp | Nonvolatile semiconductor memory device |
US7170796B1 (en) * | 2005-08-01 | 2007-01-30 | Spansion Llc | Methods and systems for reducing the threshold voltage distribution following a memory cell erase |
US7428172B2 (en) * | 2006-07-17 | 2008-09-23 | Freescale Semiconductor, Inc. | Concurrent programming and program verification of floating gate transistor |
KR100841980B1 (en) * | 2006-12-19 | 2008-06-27 | 삼성전자주식회사 | Erase method of flash memory device capable of improving distributions of threshold voltage of erased memory cell |
US7619934B2 (en) * | 2006-12-20 | 2009-11-17 | Spansion Llc | Method and apparatus for adaptive memory cell overerase compensation |
KR101348173B1 (en) * | 2007-05-25 | 2014-01-08 | 삼성전자주식회사 | Flash memory device, erase and program methods, and memory system including the same |
KR100960479B1 (en) * | 2007-12-24 | 2010-06-01 | 주식회사 하이닉스반도체 | Flash memory apparatus and operating method thereof |
KR101378365B1 (en) | 2008-03-12 | 2014-03-28 | 삼성전자주식회사 | Apparatus and method for hybrid detecting memory data |
KR101414494B1 (en) | 2008-03-17 | 2014-07-04 | 삼성전자주식회사 | Memory device and memory data read method |
KR101400691B1 (en) | 2008-05-14 | 2014-05-29 | 삼성전자주식회사 | Memory device and memory programming method |
KR20120030818A (en) | 2010-09-20 | 2012-03-29 | 삼성전자주식회사 | Non-volatile memory device and erase method thereof |
US8289773B2 (en) | 2010-11-09 | 2012-10-16 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) erase operation with brownout recovery technique |
JP5671335B2 (en) * | 2010-12-28 | 2015-02-18 | ラピスセミコンダクタ株式会社 | Data writing method and nonvolatile semiconductor memory device |
KR101775429B1 (en) | 2011-01-04 | 2017-09-06 | 삼성전자 주식회사 | Nonvolatile memory device and method of programming the same |
US8929139B2 (en) | 2011-04-13 | 2015-01-06 | Macronix International Co., Ltd. | Method and apparatus for leakage suppression in flash memory |
US8526240B2 (en) * | 2011-08-17 | 2013-09-03 | Ememory Technology Inc. | Flash memory and memory cell programming method thereof |
US8576633B2 (en) * | 2011-09-29 | 2013-11-05 | Cypress Semiconductor Corp. | 1T smart write |
US10825529B2 (en) | 2014-08-08 | 2020-11-03 | Macronix International Co., Ltd. | Low latency memory erase suspend operation |
JP6088602B2 (en) * | 2015-08-12 | 2017-03-01 | ウィンボンド エレクトロニクス コーポレーション | Nonvolatile semiconductor memory device |
KR102524916B1 (en) * | 2018-03-13 | 2023-04-26 | 에스케이하이닉스 주식회사 | Storage device and operating method thereof |
US10832765B2 (en) * | 2018-06-29 | 2020-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Variation tolerant read assist circuit for SRAM |
US11355185B2 (en) | 2019-11-26 | 2022-06-07 | Cypress Semiconductor Corporation | Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof |
CN112527550B (en) * | 2020-11-26 | 2023-06-30 | 中山市江波龙电子有限公司 | Method for generating rereading table of storage device, testing device and storage medium |
US20230409237A1 (en) * | 2022-06-17 | 2023-12-21 | Western Digital Technologies, Inc. | Data Storage Device With Weak Bits Handling |
CN116959544B (en) * | 2023-09-20 | 2023-12-15 | 上海芯存天下电子科技有限公司 | Verification current setting method, operation verification method and related equipment |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03106075A (en) * | 1989-09-20 | 1991-05-02 | Fujitsu Ltd | Nonvolatile semiconductor storage device and readout and write thereof |
EP0596198B1 (en) * | 1992-07-10 | 2000-03-29 | Sony Corporation | Flash eprom with erase verification and address scrambling architecture |
US5600593A (en) * | 1994-12-06 | 1997-02-04 | National Semiconductor Corporation | Apparatus and method for reducing erased threshold voltage distribution in flash memory arrays |
US5774400A (en) | 1995-12-26 | 1998-06-30 | Nvx Corporation | Structure and method to prevent over erasure of nonvolatile memory transistors |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US5963477A (en) | 1997-12-09 | 1999-10-05 | Macronix International Co., Ltd. | Flash EPROM erase algorithm with wordline level retry |
JP3344313B2 (en) * | 1998-03-25 | 2002-11-11 | 日本電気株式会社 | Nonvolatile semiconductor memory device |
JP3346274B2 (en) * | 1998-04-27 | 2002-11-18 | 日本電気株式会社 | Nonvolatile semiconductor memory device |
US6215148B1 (en) * | 1998-05-20 | 2001-04-10 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
TW439293B (en) * | 1999-03-18 | 2001-06-07 | Toshiba Corp | Nonvolatile semiconductor memory |
US6172909B1 (en) | 1999-08-09 | 2001-01-09 | Advanced Micro Devices, Inc. | Ramped gate technique for soft programming to tighten the Vt distribution |
US6344994B1 (en) * | 2001-01-31 | 2002-02-05 | Advanced Micro Devices | Data retention characteristics as a result of high temperature bake |
-
2001
- 2001-04-09 US US09/829,193 patent/US6493266B1/en not_active Expired - Lifetime
- 2001-12-12 KR KR1020037013262A patent/KR100828196B1/en not_active IP Right Cessation
- 2001-12-12 AU AU2002230944A patent/AU2002230944A1/en not_active Abandoned
- 2001-12-12 CN CNB018231195A patent/CN100365735C/en not_active Expired - Lifetime
- 2001-12-12 DE DE60115716T patent/DE60115716T2/en not_active Expired - Lifetime
- 2001-12-12 WO PCT/US2001/048734 patent/WO2002082447A2/en active IP Right Grant
- 2001-12-12 JP JP2002580327A patent/JP4068464B2/en not_active Expired - Fee Related
- 2001-12-12 EP EP01991202A patent/EP1415302B1/en not_active Expired - Lifetime
-
2002
- 2002-03-13 TW TW091104663A patent/TW584858B/en not_active IP Right Cessation
Cited By (91)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090032862A1 (en) * | 1997-08-01 | 2009-02-05 | Eduardo Maayan | Non-volatile memory cell and non-volatile memory device using said cell |
US20080111177A1 (en) * | 1997-08-01 | 2008-05-15 | Eduardo Maayan | Non-volatile memory cell and non-volatile memory device using said cell |
US20040222437A1 (en) * | 2000-12-07 | 2004-11-11 | Dror Avni | Programming and erasing methods for an NROM array |
US20070032016A1 (en) * | 2001-11-19 | 2007-02-08 | Saifun Semiconductors Ltd. | Protective layer in memory device and method therefor |
US20060126396A1 (en) * | 2002-01-31 | 2006-06-15 | Saifun Semiconductors, Ltd. | Method, system, and circuit for operating a non-volatile memory array |
US20050058005A1 (en) * | 2002-01-31 | 2005-03-17 | Assaf Shappir | Method for operating a memory device |
US20050117395A1 (en) * | 2002-01-31 | 2005-06-02 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US6930926B2 (en) * | 2002-01-31 | 2005-08-16 | Macronix International Co., Ltd. | Method for erasing a flash EEPROM |
US7079420B2 (en) | 2002-01-31 | 2006-07-18 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US20030161187A1 (en) * | 2002-01-31 | 2003-08-28 | Yu-Shen Lin | Method for erasing a flash EEPROM |
US6901010B1 (en) * | 2002-04-08 | 2005-05-31 | Advanced Micro Devices, Inc. | Erase method for a dual bit memory cell |
US6903980B2 (en) * | 2002-06-11 | 2005-06-07 | Fujitsu Limited | Nonvolatile semiconductor memory device capable of correcting over-erased memory cells |
US20030227796A1 (en) * | 2002-06-11 | 2003-12-11 | Fujitsu Limited | Nonvolatile semiconductor memory device capable of correcting over-erased memory cells |
US7738304B2 (en) | 2002-07-10 | 2010-06-15 | Saifun Semiconductors Ltd. | Multiple use memory chip |
US20060152975A1 (en) * | 2002-07-10 | 2006-07-13 | Eduardo Maayan | Multiple use memory chip |
US7675782B2 (en) | 2002-10-29 | 2010-03-09 | Saifun Semiconductors Ltd. | Method, system and circuit for programming a non-volatile memory array |
US20040153620A1 (en) * | 2003-01-30 | 2004-08-05 | Shai Eisen | Address scramble |
US20070168637A1 (en) * | 2003-01-31 | 2007-07-19 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
US7743230B2 (en) | 2003-01-31 | 2010-06-22 | Saifun Semiconductors Ltd. | Memory array programming circuit and a method for using the circuit |
US20070133276A1 (en) * | 2003-09-16 | 2007-06-14 | Eli Lusky | Operating array cells with matched reference cells |
KR100931890B1 (en) | 2004-03-14 | 2009-12-15 | 샌디스크 아이엘 엘티디 | State Encoding in Multi-bit Flash Cells |
WO2005086576A3 (en) * | 2004-03-14 | 2008-10-16 | Milsys Ltd | States encoding in multi-bit flash cells |
US7310347B2 (en) * | 2004-03-14 | 2007-12-18 | Sandisk, Il Ltd. | States encoding in multi-bit flash cells |
US8245099B2 (en) | 2004-03-14 | 2012-08-14 | Sandisk Il Ltd. | States encoding in multi-bit flash cells for optimizing error rate |
US20050201401A1 (en) * | 2004-03-14 | 2005-09-15 | M-Systems Flash Disk Pioneers, Ltd. | States encoding in multi-bit flash cells |
US7652930B2 (en) | 2004-04-01 | 2010-01-26 | Saifun Semiconductors Ltd. | Method, circuit and system for erasing one or more non-volatile memory cells |
US20060056240A1 (en) * | 2004-04-01 | 2006-03-16 | Saifun Semiconductors, Ltd. | Method, circuit and system for erasing one or more non-volatile memory cells |
US20050276118A1 (en) * | 2004-06-10 | 2005-12-15 | Eduardo Maayan | Reduced power programming of non-volatile cells |
US7366025B2 (en) | 2004-06-10 | 2008-04-29 | Saifun Semiconductors Ltd. | Reduced power programming of non-volatile cells |
US20070171717A1 (en) * | 2004-08-12 | 2007-07-26 | Saifun Semiconductors Ltd. | Dynamic matching of signal path and reference path for sensing |
TWI405210B (en) * | 2004-08-30 | 2013-08-11 | Spansion Llc | Non-volatile memory device and erasing method therefor |
US20060044919A1 (en) * | 2004-08-30 | 2006-03-02 | Spansion Llc | Non-volatile memory device and erasing method therefor |
US7266019B2 (en) * | 2004-08-30 | 2007-09-04 | Spansion Llc | Non-volatile memory device and erasing method therefor |
US20060068551A1 (en) * | 2004-09-27 | 2006-03-30 | Saifun Semiconductors, Ltd. | Method for embedding NROM |
US7964459B2 (en) | 2004-10-14 | 2011-06-21 | Spansion Israel Ltd. | Non-volatile memory structure and method of fabrication |
US20100173464A1 (en) * | 2004-10-14 | 2010-07-08 | Eli Lusky | Non-volatile memory structure and method of fabrication |
US20060211188A1 (en) * | 2004-10-14 | 2006-09-21 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
US20060158940A1 (en) * | 2005-01-19 | 2006-07-20 | Saifun Semiconductors, Ltd. | Partial erase verify |
US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
US20070141788A1 (en) * | 2005-05-25 | 2007-06-21 | Ilan Bloom | Method for embedding non-volatile memory with logic circuitry |
US20060285386A1 (en) * | 2005-06-15 | 2006-12-21 | Saifun Semiconductors, Ltd. | Accessing an NROM array |
US8400841B2 (en) | 2005-06-15 | 2013-03-19 | Spansion Israel Ltd. | Device to program adjacent storage cells of different NROM cells |
US20060285408A1 (en) * | 2005-06-17 | 2006-12-21 | Saifun Semiconductors, Ltd. | Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells |
US20070051982A1 (en) * | 2005-07-18 | 2007-03-08 | Saifun Semiconductors Ltd. | Dense non-volatile memory array and method of fabrication |
US7786512B2 (en) | 2005-07-18 | 2010-08-31 | Saifun Semiconductors Ltd. | Dense non-volatile memory array and method of fabrication |
US20070036007A1 (en) * | 2005-08-09 | 2007-02-15 | Saifun Semiconductors, Ltd. | Sticky bit buffer |
US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
US20070096199A1 (en) * | 2005-09-08 | 2007-05-03 | Eli Lusky | Method of manufacturing symmetric arrays |
US7301817B2 (en) | 2005-10-27 | 2007-11-27 | Sandisk Corporation | Method for programming of multi-state non-volatile memory using smart verify |
US20070097747A1 (en) * | 2005-10-27 | 2007-05-03 | Yan Li | Apparatus for programming of multi-state non-volatile memory using smart verify |
US20070097749A1 (en) * | 2005-10-27 | 2007-05-03 | Yan Li | Method for programming of multi-state non-volatile memory using smart verify |
US7366022B2 (en) | 2005-10-27 | 2008-04-29 | Sandisk Corporation | Apparatus for programming of multi-state non-volatile memory using smart verify |
US7492634B2 (en) | 2005-10-27 | 2009-02-17 | Sandisk Corporation | Method for programming of multi-state non-volatile memory using smart verify |
DE102006005077B3 (en) * | 2005-11-10 | 2007-06-14 | Infineon Technologies Flash Gmbh & Co. Kg | Method for operating a semiconductor memory device and semiconductor memory device |
US20070103980A1 (en) * | 2005-11-10 | 2007-05-10 | Gert Koebernick | Method for operating a semiconductor memory device and semiconductor memory device |
US20070120180A1 (en) * | 2005-11-25 | 2007-05-31 | Boaz Eitan | Transition areas for dense memory arrays |
US20070153575A1 (en) * | 2006-01-03 | 2007-07-05 | Saifun Semiconductors, Ltd. | Method, system, and circuit for operating a non-volatile memory array |
US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
US20070159880A1 (en) * | 2006-01-12 | 2007-07-12 | Boaz Eitan | Secondary injection for NROM |
US20070173017A1 (en) * | 2006-01-20 | 2007-07-26 | Saifun Semiconductors, Ltd. | Advanced non-volatile memory array and method of fabrication thereof |
US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US20070195607A1 (en) * | 2006-02-21 | 2007-08-23 | Saifun Semiconductors Ltd. | Nrom non-volatile memory and mode of operation |
US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
US20070196982A1 (en) * | 2006-02-21 | 2007-08-23 | Saifun Semiconductors Ltd. | Nrom non-volatile mode of operation |
US7760554B2 (en) | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
US20070194835A1 (en) * | 2006-02-21 | 2007-08-23 | Alexander Kushnarenko | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US20070255889A1 (en) * | 2006-03-22 | 2007-11-01 | Yoav Yogev | Non-volatile memory device and method of operating the device |
US7630253B2 (en) | 2006-04-05 | 2009-12-08 | Spansion Llc | Flash memory programming and verification with reduced leakage current |
US20100027350A1 (en) * | 2006-04-05 | 2010-02-04 | Ashot Melik-Martirosian | Flash memory programming and verification with reduced leakage current |
US7489560B2 (en) | 2006-04-05 | 2009-02-10 | Spansion Llc | Reduction of leakage current and program disturbs in flash memory devices |
US8031528B2 (en) | 2006-04-05 | 2011-10-04 | Spansion Llc | Flash memory programming and verification with reduced leakage current |
US20070237003A1 (en) * | 2006-04-05 | 2007-10-11 | Ashot Melik-Martirosian | Flash memory programming and verification with reduced leakage current |
US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
US20070253248A1 (en) * | 2006-04-27 | 2007-11-01 | Eduardo Maayan | Method for programming a reference cell |
US20080094127A1 (en) * | 2006-09-18 | 2008-04-24 | Yoram Betser | Measuring and controlling current consumption and output current of charge pumps |
US11594281B2 (en) | 2006-12-14 | 2023-02-28 | Mosaid Technologies Inc. | Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage |
US20080239599A1 (en) * | 2007-04-01 | 2008-10-02 | Yehuda Yizraeli | Clamping Voltage Events Such As ESD |
US20090190408A1 (en) * | 2008-01-28 | 2009-07-30 | Andreas Kux | Method of Operating an Integrated Circuit, Integrated Circuit and Method to Determine an Operating Point |
US7808833B2 (en) | 2008-01-28 | 2010-10-05 | Qimonda Flash Gmbh | Method of operating an integrated circuit, integrated circuit and method to determine an operating point |
US20120134228A1 (en) * | 2010-11-30 | 2012-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Charge pump control scheme for memory word line |
US8654589B2 (en) * | 2010-11-30 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Charge pump control scheme for memory word line |
US20120218827A1 (en) * | 2011-02-28 | 2012-08-30 | Hynix Semiconductor Inc. | Memory apparatus and method for controlling erase operation of the same |
US8644082B2 (en) * | 2011-02-28 | 2014-02-04 | SK Hynix Inc. | Memory apparatus and method for controlling erase operation of the same |
US8995202B2 (en) | 2012-05-21 | 2015-03-31 | Freescale Semiconductor, Inc. | Test flow to detect a latent leaky bit of a non-volatile memory |
US8760923B2 (en) * | 2012-08-28 | 2014-06-24 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) that uses soft programming |
TWI620185B (en) * | 2012-08-28 | 2018-04-01 | 恩智浦美國公司 | Non-volatile memory (nvm) that uses soft programming |
US20140063946A1 (en) * | 2012-08-28 | 2014-03-06 | Fuchen Mu | Non-volatile memory (nvm) that uses soft programming |
US8947958B2 (en) | 2012-10-09 | 2015-02-03 | Freescale Semiconductor, Inc. | Latent slow bit detection for non-volatile memory |
US8830756B2 (en) * | 2013-01-23 | 2014-09-09 | Freescale Semiconductor, Inc. | Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory |
US8995198B1 (en) | 2013-10-10 | 2015-03-31 | Spansion Llc | Multi-pass soft programming |
CN114995750A (en) * | 2022-05-25 | 2022-09-02 | 北京得瑞领新科技有限公司 | Method, device, storage medium and storage equipment for improving reliability of flash memory data |
Also Published As
Publication number | Publication date |
---|---|
JP2004524643A (en) | 2004-08-12 |
DE60115716D1 (en) | 2006-01-12 |
KR20030096307A (en) | 2003-12-24 |
CN100365735C (en) | 2008-01-30 |
TW584858B (en) | 2004-04-21 |
JP4068464B2 (en) | 2008-03-26 |
EP1415302B1 (en) | 2005-12-07 |
EP1415302A2 (en) | 2004-05-06 |
DE60115716T2 (en) | 2006-07-13 |
CN1494720A (en) | 2004-05-05 |
KR100828196B1 (en) | 2008-05-08 |
US6493266B1 (en) | 2002-12-10 |
WO2002082447A2 (en) | 2002-10-17 |
WO2002082447A3 (en) | 2003-03-06 |
AU2002230944A1 (en) | 2002-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6493266B1 (en) | Soft program and soft program verify of the core cells in flash memory array | |
US6331951B1 (en) | Method and system for embedded chip erase verification | |
US6690602B1 (en) | Algorithm dynamic reference programming | |
US6831858B2 (en) | Non-volatile semiconductor memory device and data write control method for the same | |
US5862081A (en) | Multi-state flash EEPROM system with defect management including an error correction scheme | |
US6639844B1 (en) | Overerase correction method | |
US7009887B1 (en) | Method of determining voltage compensation for flash memory devices | |
US6567303B1 (en) | Charge injection | |
US8031528B2 (en) | Flash memory programming and verification with reduced leakage current | |
KR100953208B1 (en) | System and method for generating a reference voltage based on averaging the voltages of two complementary programmmed dual bit reference cells | |
US6834012B1 (en) | Memory device and methods of using negative gate stress to correct over-erased memory cells | |
US6449190B1 (en) | Adaptive reference cells for a memory device | |
US20020159293A1 (en) | Higher program vt and faster programming rates based on improved erase methods | |
EP1518247B1 (en) | Method of erasing a flash memory using a pre-erasing step | |
US6507522B2 (en) | Method for erasing memory cells in a nonvolatile memory | |
US6172915B1 (en) | Unified erase method in flash EEPROM | |
US6532175B1 (en) | Method and apparatus for soft program verification in a memory device | |
US6493261B1 (en) | Single bit array edges | |
US6754106B1 (en) | Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory | |
US6934190B1 (en) | Ramp source hot-hole programming for trap based non-volatile memory devices | |
US6901010B1 (en) | Erase method for a dual bit memory cell | |
WO2003063167A2 (en) | System and method for programming ono dual bit memory cells | |
US6987695B2 (en) | Writing data to nonvolatile memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YACHARENI, SANTOSH K.;HAMILTON, DARLENE G.;LE, BINH Q.;AND OTHERS;REEL/FRAME:011704/0027;SIGNING DATES FROM 20010330 TO 20010406 Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YACHARENI, SANTOSH K.;HAMILTON, DARLENE G.;LE, BINH Q.;AND OTHERS;REEL/FRAME:012246/0675;SIGNING DATES FROM 20010330 TO 20010406 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: FASL, LLC, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AMD INVESTMENTS, INC.;FUJITSU LIMITED;REEL/FRAME:015487/0501;SIGNING DATES FROM 20040330 TO 20040514 |
|
AS | Assignment |
Owner name: AMD (U.S.) HOLDINGS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:015487/0603 Effective date: 20040330 Owner name: AMD INVESTMENTS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMD (U.S.) HOLDINGS, INC.;REEL/FRAME:015487/0599 Effective date: 20040330 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: SPANSION LLC,CALIFORNIA Free format text: CHANGE OF NAME;ASSIGNOR:FASL LLC;REEL/FRAME:024170/0300 Effective date: 20100401 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: BARCLAYS BANK PLC,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:SPANSION LLC;SPANSION INC.;SPANSION TECHNOLOGY INC.;AND OTHERS;REEL/FRAME:024522/0338 Effective date: 20100510 Owner name: BARCLAYS BANK PLC, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:SPANSION LLC;SPANSION INC.;SPANSION TECHNOLOGY INC.;AND OTHERS;REEL/FRAME:024522/0338 Effective date: 20100510 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: SPANSION INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BARCLAYS BANK PLC;REEL/FRAME:035201/0159 Effective date: 20150312 Owner name: SPANSION TECHNOLOGY LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BARCLAYS BANK PLC;REEL/FRAME:035201/0159 Effective date: 20150312 Owner name: SPANSION LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BARCLAYS BANK PLC;REEL/FRAME:035201/0159 Effective date: 20150312 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK Free format text: SECURITY INTEREST;ASSIGNORS:CYPRESS SEMICONDUCTOR CORPORATION;SPANSION LLC;REEL/FRAME:035240/0429 Effective date: 20150312 |
|
AS | Assignment |
Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SPANSION, LLC;REEL/FRAME:036034/0058 Effective date: 20150601 |
|
AS | Assignment |
Owner name: MUFG UNION BANK, N.A., CALIFORNIA Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050896/0366 Effective date: 20190731 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST;ASSIGNORS:CYPRESS SEMICONDUCTOR CORPORATION;SPANSION LLC;REEL/FRAME:058002/0470 Effective date: 20150312 |
|
AS | Assignment |
Owner name: SPANSION LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MUFG UNION BANK, N.A.;REEL/FRAME:059410/0438 Effective date: 20200416 Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MUFG UNION BANK, N.A.;REEL/FRAME:059410/0438 Effective date: 20200416 |