US20030032216A1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- US20030032216A1 US20030032216A1 US10/062,535 US6253502A US2003032216A1 US 20030032216 A1 US20030032216 A1 US 20030032216A1 US 6253502 A US6253502 A US 6253502A US 2003032216 A1 US2003032216 A1 US 2003032216A1
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- United States
- Prior art keywords
- semiconductor chip
- semiconductor
- main surface
- chip
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
Definitions
- the present invention relates to semiconductor devices having multiple semiconductor chips layered on one another and manufacturing methods thereof.
- the invention more particularly relates to a semiconductor device including two semiconductor chips having their circuit forming surfaces opposed to one another, and electrodes formed on the circuit forming surfaces being electrically connected with one another, and a manufacturing method thereof.
- FIG. 18 is a sectional view of the conventional semiconductor device.
- the conventional semiconductor device includes a first semiconductor chip 1 and a second semiconductor chip 4 .
- the first semiconductor chip 1 has first electrodes 2 and bonding pads 3 on a first main surface.
- the second semiconductor chip 4 is provided with second electrodes 5 on a second main surface and has a smaller area than the first semiconductor chip 1 .
- the first and second semiconductor chips 1 and 4 are integrated so that their main surfaces (i.e., the circuit forming surfaces) are opposed to one another and the first and second electrodes 2 and 5 are electrically connected with one another. Stated differently, while the first and second electrodes 2 and 5 are registered, the second semiconductor chip 4 is placed facedown on the first semiconductor chip 1 .
- first and second electrodes 2 and 5 are connected through a metal bump 7 , while the part of the second electrode 5 in contact with the metal bump 7 is provided with a barrier metal layer 6 .
- the bonding pads 3 are provided outside the region of the first main surface of the first semiconductor chip 1 opposed to the second main surface of the second semiconductor chip 4 .
- the surface of the first semiconductor chip 1 opposite to the first main surface is secured to a die pad portion 9 a by conductive paste 10 containing palladium (Pd), silver (Ag) or the like.
- the bonding pad 3 , and a lead portion 9 b provided adjacent to the die pad portion 9 a are electrically connected with one another through a thin metal bonding wire 11 .
- the die pad portion 9 a and the lead portion 9 b are cut from a single lead frame 9 .
- the first and second semiconductor chips 1 and 4 , the die pad portion 9 a , the lead portions 9 b and the bonding wires 11 are encapsulated in a resin package 12 .
- FIGS. 19A, 19B, 20 A and 20 B are sectional views showing steps in the method of manufacturing the conventional semiconductor device.
- the first and second semiconductor chips 1 and 4 are registered. More specifically, a plurality of first electrodes 2 and a plurality of bonding pads 3 are provided on a first main surface of the first semiconductor chip 1 .
- the chip 1 is then placed on a packaging jig (not shown) and a resin 8 A is applied on the first main surface of the semiconductor chip 1 .
- the second semiconductor chip 4 having a plurality of second electrodes 5 on a second main surface is prepared over the first semiconductor chip 1 so that their main surfaces, i.e., their circuit forming surfaces are opposed to one another.
- a plurality of metal bumps 7 are formed on the second electrodes 5
- the first and second electrodes 2 and 5 are registered. Note that there is a barrier metal layer 6 provided on the part of the second electrodes 5 in contact with the metal bumps 7 .
- the first and second semiconductor chips 1 and 4 are joined with one another. More specifically, the second semiconductor chip 4 is heated and pressed using a metal tool 13 from the surface opposite to the second main surface. As a result, the first electrodes 2 on the first semiconductor chip 1 and the second electrodes 5 on the second semiconductor chip 4 are joined with one another through the metal bumps 7 formed on the second electrodes 5 (more precisely on the barrier metal layers 6 ) on the second semiconductor chip 4 . Then, the resin 8 A filled between the joined first and second semiconductor chips 1 and 4 is irradiated with ultraviolet rays or heated for curing and a resin layer 8 results.
- the joined first and second semiconductor chips 1 and 4 in an integrated form (hereinafter referred to as a “chip-layered body”) is subjected to wire-bonding. More specifically, a lead frame 9 having a die pad portion 9 a and lead portions 9 b is prepared. Then, the surface opposite to the first main surface of the first semiconductor chip 1 is secured onto the die pad portion 9 a using conductive paste 10 containing Pd, Ag or the like. The bonding pads 3 on the first semiconductor chip 1 and the lead portions 9 b are then electrically connected through thin metal bonding wires 11 . Thus, the electrical connection for the semiconductor device is completed.
- the chip-layered body after the wire-bonding step is encapsulated in a resin. More specifically, the first and second semiconductor chips 1 and 4 , the die pad portion 9 a , the lead portions 9 b and the bonding wires 11 are encapsulated in a resin package 12 . Note however that the bottom surface of the die pad portion 9 a and the bottom and outer side surfaces of the lead portions 9 b (the side surfaces opposite to the side facing the die pad portion 9 a ) are exposed out of the resin package 12 . Thus, the bottom and outer side surfaces of the lead portions 9 b serve as external terminals.
- the conventional semiconductor device and the manufacturing method thereof described above suffer from the following disadvantages.
- the thickness of the semiconductor device having multiple layers of semiconductor chips increases in proportion to the number of the semiconductor chips used.
- the thickness of the first and second semiconductor chips 1 and 4 is each about in the range from 200 to 300 ⁇ m even after the back surface (the surface opposite to the circuit forming surface (main surface)) is polished.
- the metal bumps 7 used to join the first and second semiconductor chips 1 and 4 are about as thick as several tens ⁇ m after the joining.
- the completed semiconductor device has a thickness about as large as 1 mm.
- a thickness is about the same as the thickness of the thin type packages widely used in recent years, which suggests how hard it could be to reduce the size of semiconductor devices having such a chip-layered body.
- semiconductor chips with large thickness in a semiconductor device could impede thermal radiation from the semiconductor chips, and therefore the heat radiation property of the semiconductor device as a whole could be lowered.
- the semiconductor device includes a first semiconductor chip provided with a first electrode on a first main surface, and a second semiconductor chip provided with a second electrode on a second main surface.
- the first and second semiconductor chips are integrated with one another so that the first and second main surfaces are opposed to one another and the first and second electrodes are electrically connected.
- the second semiconductor chip has a thickness smaller than a thickness of the first semiconductor chip.
- a chip-layered body including the first and second semiconductor chips may have a reduced thickness.
- the package structure including the chip-layered body encapsulated in a resin can thus be thinner, which allows the semiconductor device to have a reduced size and improved heat radiation property.
- the second semiconductor chip preferably has the thickness equal to or smaller than 1 ⁇ 2 of the thickness of the first semiconductor chip.
- the package structure for the chip-layered body can be made thinner, so that the semiconductor device can have a more reduced size and higher heat radiation property.
- a resin layer is preferably provided between the first and second main surfaces.
- a resin package to encapsulate the first and second semiconductor chips is preferably provided.
- the chip-layered body including the first and second semiconductor chips can have improved reliability.
- an area of the first main surface is larger than an area of the second main surface, and a third electrode is provided outside a region of the first main surface opposed to the second main surface.
- a surface opposite to the first main surface of the first semiconductor chip is adhered to a die pad, a lead is provided adjacent to the die pad, and the lead and the third electrode are connected through a bonding wire.
- the first semiconductor chip, the second semiconductor chip and the bonding wire may be encapsulated in a resin package.
- a distance from the first main surface to a surface opposite to the second main surface of the second semiconductor chip is preferably smaller than a distance from the first main surface to the highest position of the bonding wire on the first main surface.
- a semiconductor device manufactured by a first manufacturing method includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface.
- the method includes a first step of integrating the first and second semiconductor chips by arranging the first and second main surfaces to be opposed to one another and electrically connecting the first and second electrodes, and a second step of polishing the second semiconductor chip integrated with the first semiconductor chip from the opposite side of the second main surface, so that the thickness of the second semiconductor chip is made smaller than the thickness of the first semiconductor chip.
- the second semiconductor chip is polished from the opposite side of the main surface (circuit forming surface), so that the second semiconductor chip has a thickness smaller than the thickness of the first semiconductor chip. Therefore, the thickness of the chip-layered body including the first and second semiconductor chips can be reduced, so that the package structure including the chip-layered body encapsulated in a resin can have a reduced thickness, which permits the semiconductor device to have a reduced size and improved heat radiation property.
- the first step preferably includes the step of forming a resin layer between the first and second main surfaces.
- the chip-layered body including the first and second semiconductor chips may have improved reliability.
- the second step preferably includes the step of reducing the thickness of the second semiconductor chip to at most 1 ⁇ 2 of the thickness of the first semiconductor chip.
- the package structure including the chip-layered body can have a more reduced thickness, so that the semiconductor device can have a more reduced size and higher heat radiation property.
- an area of the first main surface is larger than an area of the second main surface, a third electrode is provided outside a region of the first main surface opposed to the second main surface.
- the second step may precede the steps of adhering a surface of the first semiconductor chip opposite to the first main surface to a die pad, arranging a lead adjacent to the die pad and electrically connecting the lead and the third electrode through a bonding wire, and forming a resin package to encapsulate the first semiconductor chip, the second semiconductor chip and the bonding wire.
- the second step preferably includes the step of allowing a distance from the first main surface to a surface of the second semiconductor chip opposite to the second main surface to be smaller than a distance from the first main surface to the highest position of the bonding wire on the first main surface.
- a semiconductor device manufactured by a second manufacturing method includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface.
- the method includes a first step of integrating a semiconductor wafer to be a plurality of the first semiconductor chips and a plurality of discrete second semiconductor chips by arranging the first main surface of each first semiconductor chip in the semiconductor wafer to be opposed to the second main surface of each second semiconductor chip and electrically connecting the first electrode on each first semiconductor chip in the semiconductor wafer and the second electrode on each second semiconductor chip, a second step of polishing the second semiconductor chip integrated with the semiconductor wafer from an opposite side of the second main surface so that a thickness of each second semiconductor chip is smaller than a thickness of the semiconductor wafer, and a third step of separating the semiconductor wafer integrated with the second semiconductor chips into a plurality of discrete first semiconductor chips, thereby forming a plurality of chip-layered bodies each including a discrete first semiconductor chips and a discrete
- a plurality of chip-layered bodies in other words a plurality of semiconductor devices having a reduced size and improved heat radiation property can readily be manufactured simply by separating a semiconductor wafer into a plurality of discrete first semiconductor chips.
- the first step preferably includes the step of forming a resin layer between the first main surface of each first semiconductor chip in the semiconductor wafer and the second main surface of each second semiconductor chip.
- the chip-layered body including the first and second semiconductor chips can have improved reliability.
- the second step preferably includes the step of reducing the thickness of each second semiconductor chip to at most 1 ⁇ 2 of the semiconductor wafer.
- the package structure including the chip-layered body can have a more reduced thickness, so that the semiconductor device can have a more reduced size and improved heat radiation property.
- an area of the first main surface is larger than an area of the second main surface.
- a third electrode is provided outside a region of the first main surface opposed to the second main surface.
- the chip-layered bodies may each be subjected to the steps of adhering a surface of the first semiconductor chip opposite to the first main surface to a die pad, providing a lead adjacent to the die pad and electrically connecting the lead and the third electrode through a bonding wire, and forming a resin package to encapsulate the first semiconductor chip, the second semiconductor chip and the bonding wire.
- the second step preferably includes the step of arranging a distance from the first main surface of each first semiconductor chip in the semiconductor wafer to a surface of each second semiconductor chip opposite to the second main surface to be smaller than a distance from the first main surface of each first semiconductor chip in the semiconductor wafer to the highest position of the bonding wire on the first main surface.
- FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention
- FIG. 2 is a sectional view of a semiconductor device according to a modification of the first embodiment
- FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
- FIGS. 4A and 4B are sectional views showing steps in a method of manufacturing a semiconductor device according to a third embodiment of the present invention.
- FIGS. 5A and 5B are sectional views showing steps in the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- FIGS. 6A and 6B are sectional views showing steps in the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- FIG. 7 is a sectional view showing one step in the method of manufacturing a semiconductor device according to the third embodiment.
- FIGS. 8A and 8B are sectional views showing steps in a method of manufacturing a semiconductor device according to a modification of the third embodiment of the present invention.
- FIGS. 9 A, and 9 B are sectional views showing steps in the method of manufacturing a semiconductor device according to the modification of the third embodiment of the present invention.
- FIG. 10 is a sectional view showing one step in the method of manufacturing a semiconductor device according to the modification of the third embodiment
- FIGS. 11A and 11B are sectional views showing steps in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.
- FIGS. 12A and 12B are sectional views showing steps in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention.
- FIGS. 13 A, and 13 B are sectional views showing steps in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention.
- FIG. 14 is a sectional view showing one step in the method of manufacturing a semiconductor device according to the fourth embodiment.
- FIGS. 15A and 15B are sectional views showing steps in a method of manufacturing a semiconductor device according to a modification of the fourth embodiment of the present invention.
- FIGS. 16 A, and 16 B are sectional views showing steps in the method of manufacturing a semiconductor device according to the modification of the fourth embodiment of the present invention.
- FIG. 17 is a sectional view showing one step in the method of manufacturing a semiconductor device according to the modification of the fourth embodiment
- FIG. 18 is a sectional view of a conventional semiconductor device
- FIGS. 19A and 19B are sectional views showing steps in a method of manufacturing the conventional semiconductor device.
- FIGS. 20 A, and 20 B are sectional views showing steps in the method of manufacturing the conventional semiconductor device.
- FIG. 1 is a sectional view of the semiconductor device according to the first embodiment.
- the semiconductor device includes first and second semiconductor chips 101 and 104 .
- the first semiconductor chip 101 is provided with first electrodes 102 and bonding pads 103 on a first main surface.
- the second semiconductor chip 104 is provided with second electrodes 105 on a second main surface and has a smaller area than the first semiconductor chip 101 .
- the first and second semiconductor chips 101 and 104 are integrated so that their main surfaces (i.e., their circuit forming surfaces) are opposed to one another and the first and second electrodes 102 and 105 are electrically connected with one another. Stated differently, the first and second electrodes 102 and 105 are registered as the second semiconductor chip 104 is joined facedown on the first semiconductor chip 101 .
- the first and second electrodes 102 and 105 are connected with one another through metal bumps 107 .
- the part of the second electrode 105 in contact with the metal bump 107 is provided with a barrier metal layer 106 .
- the bonding pad 103 (which corresponds to the third electrode in the section of “What is claimed is:”) is provided outside the region of the first main surface of the first semiconductor chip 101 opposed to the second main surface of the second semiconductor chip 104 .
- the surface of the first semiconductor chip 101 opposite to the first main surface is adhered to a die pad portion 109 a by conductive paste 110 containing Pd, Ag or the like.
- Lead portions 109 b provided adjacent to the die pad portion 109 a are used to exchange electrical signals between elements such as transistors in the semiconductor chips and external devices.
- the lead portions 109 b and the bonding pads 103 on the first semiconductor chip 101 are electrically connected through thin metal bonding wires 111 .
- the die pad portion 109 a and the lead portion 109 b are cut from a single lead frame 109 .
- the first semiconductor chip 101 , the second semiconductor chip 104 , the die pad 109 a , the lead portions 109 b , and the bonding wires 111 are encapsulated in a resin package 112 .
- the second semiconductor chip 104 has a thickness T 2 smaller than the thickness of T 1 of the first semiconductor chip 101 (T 2 ⁇ T 1 ).
- the second semiconductor chip 104 integrated facedown with the first semiconductor chip 101 is thinner than the first semiconductor chip 101 . Therefore, the chip-layered body including the first and second semiconductor chips 101 and 104 may have a reduced thickness. This allows the package structure including the chip-layered body encapsulated in the resin package 112 to be thinner, so that the semiconductor device can have a reduced size and improved heat radiation property.
- the resin layer 108 is provided between the first main surface of the first semiconductor chip 101 and the second main surface of the second semiconductor chip 104 , and these semiconductor chips 101 and 104 are encapsulated in the resin package 112 . Therefore, the chip-layered body including the first and second semiconductor chips 101 and 104 can have improved reliability.
- FIG. 2 is a sectional view of the semiconductor device according to the modification of the first embodiment. Note that in the following description of the modification, the same elements as those in the first embodiment shown in FIG. 1 will be denoted by the same reference characters and will not be detailed.
- the second semiconductor chip 104 has a thickness T 2 equal to or smaller than 1 ⁇ 2 of the thickness T 1 of the first semiconductor chip 101 (T 2 ⁇ 2 T 1 ).
- the package structure including the layered body of the first and second semiconductor chips 101 and 104 encapsulated in the resin package 112 can be made thinner than the first embodiment, and therefore the semiconductor device can have a more reduced size and more improved heat radiation property.
- the semiconductor chip 101 has, for example, a thickness T 1 about in the range from 200 to 300 ⁇ m, while the second semiconductor chip 104 has, for example, a thickness T 2 about in the range from 50 to 100 ⁇ m.
- FIG. 3 is a sectional view of the semiconductor device according to the second embodiment.
- the same elements as those in the first embodiment shown in FIG. 1 will be denoted by the same reference characters and will not be detailed.
- the distance T chip from the first main surface of the first semiconductor chip 101 to the surface of the second semiconductor chip 104 opposite to the second main surface is smaller than the distance T wb from the first main surface of the first semiconductor chip 101 to the highest position of the bonding wire 111 on the first main surface (i.e., the peak of the loop of the bonding wire 111 ) (T chip ⁇ T wb ).
- the semiconductor device including the layered body of the first semiconductor chip 101 and the second semiconductor chip 104 placed on the lead frame 109 can surely have a reduced size and improved heat radiation property.
- FIGS. 4A, 4B, 5 A, 5 B, 6 A, 6 B, and 7 are sectional views showing steps in the method of manufacturing the semiconductor device according to the third embodiment.
- a semiconductor wafer 201 having a plurality of chip regions to be first semiconductor chips 201 a (see FIG. 6A) and a second semiconductor chip 204 are registered.
- the second semiconductor chip 204 has a smaller area than that of a chip region in the semiconductor wafer 201 (i.e., the first semiconductor chip 201 a ).
- FIGS. 4A, 4B, 5 A, 5 B, and 6 A the boundaries between the chip regions are denoted by broken lines.
- an element such as a transistor or interconnection is formed in each chip region in the semiconductor wafer 201 .
- On the surface of each chip region in the semiconductor wafer 201 i.e., on the first main surface of the semiconductor chip 201 a ), there are a plurality of first electrodes 202 (for connection with bumps) and a plurality of bonding pads 203 (for connection with thin metal wires).
- the first electrodes 202 and bonding pads 203 are formed, for example, of aluminum (Al).
- the bonding pad 203 corresponds to the “third electrode” in the section of “What is claimed is.”
- a plurality of second electrodes 205 of Al are formed on the second main surface of the semiconductor chip 204 .
- the metal bump 207 has a diameter about in the range from 3 to 100 ⁇ m and a height about in the range from 3 to 50 ⁇ m.
- the semiconductor wafer 201 is placed on the packaging jig (not shown) and a resin 208 A such as an epoxy resin is applied on the surface of one chip region in the semiconductor wafer 201 .
- the second semiconductor chip 204 is held by a tool 209 over the chip region in the semiconductor wafer 201 , so that the surface of the chip region and the second main surface of the semiconductor chip 204 are opposed to each other. Then, as shown in FIG. 4B, the chip region in the semiconductor wafer 201 and the second semiconductor chip 204 are joined with each other. More specifically, the second semiconductor chip 204 is lowered as it is held by the tool 209 , and the metal bumps 207 formed on the second electrodes 205 on the second semiconductor chip 204 and the first electrodes 202 placed in the chip region in the semiconductor wafer 201 are registered.
- the bonding pads 203 in the chip region in the semiconductor wafer 201 are provided outside the region of the surface of the chip region opposed to the second main surface of the second semiconductor chip 204 .
- the second semiconductor chip 204 is heated and pressed from the surface opposite to the second main surface using the tool 209 .
- the registered first electrodes 202 and metal bumps 207 on the second semiconductor chip 204 are joined by physical or metallurgical effect (such as interdiffusion of atoms).
- the resin 208 A applied on the surface of the chip region in the semiconductor wafer 201 enhances the adhesion between the semiconductor wafer 201 and the second semiconductor chip 204 .
- the pressing force (load) by the tool 209 should be about in the range from 0.98 to 196 mN for each metal bump 207 , and the size of the load is set on the condition that the first electrodes 202 are not damaged.
- the load may be set on the condition that the characteristics of elements such as transistors or interconnections formed under the first electrodes 202 in the semiconductor wafer 201 are unaffected.
- the resin 208 A is cured to form a resin layer 208 , so that the second semiconductor chip 204 and the semiconductor wafer 201 are integrated.
- the resin 208 A can be cured by irradiation of ultraviolet rays if it is a photosetting resin.
- the resin 208 A can be cured by heating if it is a thermosetting resin. If the resin 208 A is to be cured by heating (i.e., if the resin is a thermosetting resin), the resin 208 A is heated using heating instrument such as an oven after it is released from the pressing by the tool 209 . Alternatively, a heater installed in the tool 209 is used to directly heat the resin during the pressing step by the tool 209 . Although the temperature varies depending on the kind of the resin, the resin 208 A should be cured at a temperature about in the range from 70 to 300° C.
- FIGS. 4A and 4B are repeated as many times as the number of chip regions provided in the semiconductor wafer 201 . Then, as shown in FIG. 5A, a joined body 210 including a plurality of second semiconductor chips 204 each provided in a chip region in the semiconductor wafer 201 can be formed.
- each of the semiconductor chips 204 (the surface opposite to the second main surface) in the joined body 210 is polished. More specifically, the resin 208 A is sufficiently cured to form the resin layer 208 , and then the joined body 210 is placed on a polishing machine 211 so that the back surfaces of the second semiconductor chips 204 placed in the chip regions in the semiconductor wafer 201 are opposed to the upper surface (polishing surface) of the polishing machine 211 .
- a protection resin 212 is provided between the second semiconductor chips 204 placed in the chip regions in the semiconductor wafer 201 .
- the polishing machine 211 After the polishing surface of the polishing machine 211 is supplied with abrasive grains 213 , the polishing machine 211 is rotated as the joined body 210 is loaded with weight. In this manner, the back surfaces of the second semiconductor chips 204 are polished. At the time, in the joined body 210 removed from the polishing machine 211 , the thickness of the second semiconductor chip 204 on the semiconductor wafer 201 decreases in inverse proportion to the duration of the polishing time. Note that for the abrasive grains 213 , diamond grains having a grain size in the range from #1200 to #2000 are preferably used, and the polishing machine 211 is preferably rotated at about 5 to 50 rpm.
- the back surfaces of the second semiconductor chips 204 can be polished so that the thickness of the second semiconductor chips 204 is at least smaller than the thickness of the semiconductor wafer 201 (i.e., the thickness of the first semiconductor chips 201 a ). More specifically, the polished second semiconductor chip 204 preferably has a thickness about in the range from 50 to 100 ⁇ m. Note that the semiconductor wafer 201 has a thickness about in the range from 200 to 300 ⁇ m, and the semiconductor chip 204 before polishing is about as thick as the semiconductor wafer 201 .
- the semiconductor wafer 201 is subjected to dicing. More specifically, the chip regions in the semiconductor wafer 201 in the joined body 210 are separated as a plurality of discrete first semiconductor chips 201 a by dicing.
- a plurality of chip-layered bodies 214 each including one first semiconductor chip 201 a and one second semiconductor chip 204 joined with one another result. For the ease of illustration, only a single chip-layered body 214 will be described.
- the chip-layered body 214 is subjected to die-bonding and wire-bonding. More specifically, a lead frame 215 having a die pad portion 215 a and lead portions 215 b is prepared. The back surface of the first semiconductor chip 201 a forming the chip-layered body 214 (the surface opposite to the first main surface) is secured on the die pad portion 215 a using conductive paste 216 containing Pd, Ag or the like. Then, the bonding pad 203 on the first semiconductor chip 201 a and the lead portion 215 b are electrically connected through a thin metal bonding wire 217 .
- the thin metal wire has a diameter of about 25 ⁇ m. Gold (Au), Al or the like can be used for the thin metal wire.
- the chip-layered body 214 is encapsulated in a resin. More specifically, the first semiconductor chip 201 a , the second semiconductor chip 204 , the die pad portion 215 a and lead portions 215 b of the lead frame 215 , and the bonding wires 217 are encapsulated in a resin package 218 of an epoxy-based resin, a polyimide-based resin or the like. Note, however, that the bottom surface of the die pad portion 215 a and the bottom and outer side surfaces of the lead portions 215 b are exposed out of the resin package 218 . Thus, the bottom and outer side surfaces of the lead portions 215 b serve as external terminals.
- the plurality of first semiconductor chips 201 a in the semiconductor wafer 201 and the plurality of discrete second semiconductor chips 204 are integrated to face to one another.
- the second semiconductor chips 204 are polished from the side opposite to their main surfaces (circuit forming surfaces), so that the second semiconductor chips 204 have a thickness smaller than the thickness of the semiconductor wafer 201 or the first semiconductor chip 201 a .
- the semiconductor wafer 201 is separated into a plurality of discrete first semiconductor chips 201 a , so that a plurality of chip-layered bodies 214 each including a discrete first semiconductor chip 201 a and a discrete second semiconductor chip 204 joined with one another are formed.
- the chip-layered body 214 may have a reduced thickness, and the package structure including the chip-layered body 214 encapsulated in the resin package 218 can be made thinner. This permits the semiconductor device to have a reduced size and improved heat radiation property.
- a plurality of chip-layered bodies 214 in other words a plurality of semiconductor devices having a reduced size and improved heat radiation property can easily be produced simply by separating the semiconductor wafer 201 into a plurality of discrete semiconductor chips 201 a.
- the semiconductor wafer 201 to be separated into the plurality of semiconductor chips 201 a is not polished for the purpose of reducing the thickness of the chip-layered body 214 .
- the area of the semiconductor wafer 201 is larger than the area of the second semiconductor chip 204 , and if therefore the semiconductor wafer 201 is polished, mechanical defects such as cracking or chipping are likely to result.
- the second semiconductor chips 204 are prepared as they are separated as discrete chips and have a smaller area, and therefore such mechanical defects are much less likely if the second semiconductor chips 204 are polished.
- the second semiconductor chip 204 after the step of polishing the second semiconductor chip 204 from the back surface (see FIG. 5B), the second semiconductor chip 204 preferably has a thickness about 1 ⁇ 2 or less of the thickness of the semiconductor wafer 201 (i.e., the thickness of the first semiconductor chip 201 a ).
- the package structure including the chip-layered body 214 encapsulated in the resin package 218 can be made thinner, so that the semiconductor device can have a more reduced size and more improved heat radiation property.
- the Sn—Pb alloy is used as the material of the metal bumps 207 , while one selected from Au, In, Cu, Ni, an In—Sn alloy, a Sn—Ag alloy, a Sn—Cu alloy and a Sn—Zn alloy may be used.
- a resin having a metallic filler dispersed therein may be used instead of the metal bumps 207 .
- the metal bumps 207 are formed on the second electrodes 205 on the second semiconductor chip 204 , while the metal bumps 207 may be formed on the first electrodes 202 provided in each chip region in the semiconductor wafer 201 .
- the resin 208 A is the epoxy resin, while an acrylic resin, a polyimide resin, a urethane resin or the like can be used.
- the resin 208 A may be any of thermosetting resin, autopolymer resin, and photosetting resin.
- the resin 208 A may be preferably applied according to any suitable method among dispensing, printing and stamping methods and the like in consideration of the chip size and other conditions.
- the resin 208 A is applied on the surface of each chip region in the semiconductor wafer 201 (the first main surface of each first semiconductor chip 201 a ), while the resin 208 A may be applied on the second main surface of the second semiconductor chip 204 .
- the resin 208 A is applied before joining the first electrodes 202 and the second electrodes 205 through the metal bumps 207 .
- the resin 208 A may be applied in a different timing such as after joining these electrodes through the metal bumps 207 .
- the resin 208 A or resin layer 208 is interposed between the surfaces of the chip regions in the semiconductor wafer 201 (i.e., the first main surfaces of the first semiconductor chips 201 a ) and the second main surfaces of the second semiconductor chips 204 .
- an anisotropic conductive sheet, an anisotropic conductive resin or the like may be interposed therebetween.
- FIGS. 8A, 8B, 9 A, 9 B and 10 are sectional views showing steps in the method of manufacturing a semiconductor device according to the modification of the third embodiment. Note that according to the modification, the same elements as those in the third embodiment shown in FIGS. 4A, 4B, 5 A, 5 B, 6 A, 6 B and 7 will be denoted by the same reference characters and will not be described in some cases.
- discrete first semiconductor chips 201 a formed by dicing the semiconductor wafer are prepared and then the first and second semiconductor chips 201 a and 204 are integrated.
- the first semiconductor chip 201 a and the second semiconductor chip 204 having a smaller area than the first semiconductor chip 201 a are registered.
- first electrodes 202 for connection with bumps
- bonding pads 203 for connection with thin metal wires
- second electrodes 205 of Al, for example, on the second main surface of the second semiconductor chip 204 .
- the second electrodes 205 each have a barrier metal layer 206 thereon.
- the layer is of a metal thin film such as titanium, copper and nickel films.
- metal bumps 207 of a Sn—Pb alloy are formed on the second electrodes 205 on the second semiconductor chip 204 through the barrier metal layers 206 .
- the metal bump 207 has, for example, a diameter about in the range from 3 to 100 ⁇ m, and a height about in the range from 3 to 50 ⁇ m.
- the first semiconductor chip 201 a is placed on the packaging jig (not shown) and a resin 208 A such as an epoxy resin is applied on the first main surface of the first semiconductor chip 201 a .
- the second semiconductor chip 204 is held over the first semiconductor chip 201 a using the tool 209 so that the main surfaces of the semiconductor chips, i.e., the circuit forming surfaces are opposed to each other.
- the first semiconductor chip 201 a and the second semiconductor chip 204 are joined with each other. More specifically, the second semiconductor chip 204 is lowered as it is held by the tool 209 , and the metal bumps 207 formed on the second electrodes 205 on the second semiconductor chip 204 and the first electrodes 202 on the first semiconductor chip 201 a are registered.
- the bonding pads 203 on the first semiconductor chip 201 a are provided outside the region of the first main surface of the first semiconductor chip 201 a opposed to the second main surface of the second semiconductor chip 204 .
- the second semiconductor chip 204 is heated and pressed using the tool 209 from the surface opposite to the second main surface.
- the resin 208 A applied on the first main surface of the first semiconductor chip 201 a enhances the adhesion between the first and second semiconductor chips 201 a and 204 .
- the pressing force (load) applied by the tool 209 is suitably about in the range from 0.98 to 196 mN for each metal bump 207 , and the load is set on the condition that the first electrodes 202 are not damaged. Alternatively, the load could be set on the condition that the characteristics of elements such as transistors, interconnections or the like formed under the first electrodes 202 on the first semiconductor chip 201 a are unaffected.
- the resin 208 A is cured to form the resin layer 208 , so that the second and first semiconductor chips 204 and 201 a are integrated.
- the back surface of the second semiconductor chip 204 (the surface opposite to the second main surface) is polished. More specifically, the resin 208 A is sufficiently cured to form the resin layer 208 and then the joined body 210 is placed on the polishing machine 211 so that the back surface of the second semiconductor chip 204 is opposed to the upper surface (polishing surface) of the polishing machine 211 . Abrasive grains 213 are supplied to the polishing surface of the polishing machine 211 , and then the joined body 210 is loaded with weight as the polishing machine 211 is rotated to polish the back surface of the second semiconductor chip 204 .
- the thickness of the second semiconductor chip 204 decreases in inverse proportion to the duration of the polishing time period.
- the abrasive grains 213 diamond grains having a grain size in the range from #1200 to #2000 are preferably used, and the polishing machine 211 is preferably rotated at about 5 to 50 rpm.
- the back surface of the second semiconductor chip 204 is polished so that the thickness of the second semiconductor chip 204 is at least smaller than that of the first semiconductor chip 201 a . More specifically, the thickness of the polished semiconductor chip 204 preferably has a thickness about in the range from 50 to 100 ⁇ m. Note that the second semiconductor chip 204 before the polishing has a thickness about in the range from 200 to 300 ⁇ m which is about as large as the thickness of the first semiconductor chip 201 a.
- the chip-layered body 214 including the first semiconductor chip 201 a and the second semiconductor chip 204 having a polished back surface joined with one another is subjected to die-bonding and wire-bonding, and resin encapsulation. More specifically, a lead frame 215 having a die pad portion 215 a and lead portions 215 b is prepared. The back surface of the first semiconductor chip 201 a of the chip-layered body 214 (the surface opposite to the first main surface) is secured on the die pad portion 215 a with conductive paste 216 containing Pd, Ag or the like.
- the bonding pads 203 on the first semiconductor chip 201 a and the lead portions 215 b are electrically connected with one another through the thin metal bonding wires 217 .
- the thin metal wires have a diameter of about 25 ⁇ m.
- the material of the thin metal wires can be for example Au or Al.
- the first semiconductor chip 201 a , the second semiconductor chip 204 , the die pad portion 215 a and lead portions 215 b of the lead frame 215 and the bonding wires 217 are encapsulated in a resin package 218 of an epoxy-based resin or a polyimide-based resin.
- the bottom surface of the die pad portion 215 a and the bottom and outer side surfaces of the lead portions 215 b are exposed out of the resin package 218 , so that the bottom and outer side surfaces of the lead portions 215 b can serve as external terminals.
- the first and second semiconductor chips 201 a and 204 are integrated to face to one another, and then the second semiconductor chip 204 is polished from the opposite side to the main surface (i.e., the circuit forming surface) so that the second semiconductor chip 204 is made thinner than the first semiconductor chip 201 a . Therefore, the layered-body (chip-layered body 214 ) including the first and second semiconductor chips 201 a and 204 can have a reduced thickness. As a result, the package structure including the chip-layered body 214 encapsulated in the resin package 218 can be made thinner, which allows the semiconductor device to have a reduced size and improved heat radiation property.
- the thickness of the second semiconductor chip 204 is preferably reduced to 1 ⁇ 2 or less of the thickness of the first semiconductor chip 201 a .
- the package structure including the chip-layered body 214 encapsulated in the resin package 218 can be made thinner, and therefore the semiconductor device can have a more reduced size and higher heat radiation property.
- the Sn—Pb alloy is used for the material of the metal bumps 207 , while any one of Au, In, Cu, Ni, an In—Sn alloy, a Sn—Ag alloy, a Sn—Cu alloy, and a Sn—Zn alloy may be used.
- conductive paste, an anisotropic conductive resin or a resin having a metallic filler dispersed therein may be used instead of the metal bumps 207 .
- the metal bumps 207 are formed on the second electrodes 205 on the second semiconductor chip 204 , while the metal bumps 207 may be formed on the first electrodes 202 on the first semiconductor chip 201 a.
- the resin 208 A is the epoxy resin, while an acrylic resin, a polyimide resin, a urethane resin or like may be used.
- the resin 208 A may be any of thermosetting resin, autopolymer resin and photosetting resin.
- the resin 208 A is preferably applied by any suitable method among dispensing, printing and stamping methods and the like in consideration of the chip size and other conditions.
- the resin 208 A is applied on the first main surface of the first semiconductor chip 201 a , while the resin 208 A may be applied on the second main surface of the second semiconductor chip 204 .
- the resin 208 A is applied before joining the first and second electrodes 202 and 205 through the metal bumps 207 , while the resin 208 A may be applied in a different timing such as after joining these electrodes through the metal bumps 207 .
- the resin 208 A or resin layer 208 is interposed between the first main surface of the first semiconductor chip 201 a and the second main surface of the second semiconductor chip 204 , while an anisotropic conductive sheet or an anisotropic conductive resin may be interposed.
- FIGS. 11A, 11B, 12 A, 12 B, 13 A, 13 B and 14 are sectional views showing steps in the method of manufacturing a semiconductor device according to the fourth embodiment.
- FIG. 11A similarly to the step shown in FIG. 4A according to the third embodiment, a semiconductor wafer 201 and a second semiconductor chip 204 are registered.
- the wafer 201 has a plurality of chip regions to be a plurality of semiconductor chips 201 a (see FIG. 13A).
- the second semiconductor chip 204 has a smaller area than a chip region (i.e., the first semiconductor chip 201 a ).
- FIGS. 11A, 11B, 12 A, 12 B, and 13 A show the boundaries between the chip regions by the dotted lines.
- elements such as transistors or interconnections are formed in the chip regions in the semiconductor wafer 201 .
- the bonding pad 203 corresponds to the “third electrode” in the section of “What is claimed is.”
- a plurality of second electrodes 205 of Al are provided on the second main surface of the second semiconductor chip 204 .
- Barrier metal layers 206 of a thin metal film of titanium, copper, nickel or the like is provided on the second electrodes 205 .
- metal bumps 207 of a Sn—Pb alloy are formed on the second electrodes 205 on the second semiconductor chip 204 through the barrier metal layers 206 .
- the metal bump 207 has a diameter of about 3 to 100 ⁇ m and a height of about 3 to 50 ⁇ m.
- the semiconductor wafer 201 is placed on a packaging jig (not shown) and a resin 208 A such as an epoxy resin is applied on the surface of one chip region in the semiconductor wafer 201 .
- the second semiconductor chip 204 is held using the tool 209 over the chip region in the semiconductor wafer 201 so that the surface of the chip region and the second main surface of the second semiconductor chip 204 are opposed to each other.
- the chip region in the semiconductor wafer 201 and the second semiconductor chip 204 are joined with one another. More specifically, the second semiconductor chip 204 is lowered as it is held by the tool 209 . Thus, the metal bumps 207 formed on the second electrodes 205 on the second semiconductor chip 204 and the first electrodes 202 provided in the chip region in the semiconductor wafer 201 are registered.
- the bonding pads 203 in the chip region in the semiconductor wafer 201 are formed outside the region of the surface of the chip region opposed to the second main surface of the second semiconductor chip 204 .
- the second semiconductor chip 204 is heated and pressed using the tool 209 from the surface opposite to the second main surface.
- the registered first electrodes 202 and the metal bumps 207 on the second semiconductor chip 204 are joined by physical or metallurgical effect.
- the resin 208 A previously applied on the surface of the chip region in the semiconductor wafer 201 enhances the adhesion between the semiconductor wafer 201 and the second semiconductor chip 204 .
- the pressing force (load) by the tool 209 is suitably about in the range from 0.98 to 196 mN for each metal bump 207 , and the load is set on the condition that the first electrodes 202 are not damaged. Alternatively, the load may be set on the condition that the characteristics of elements such as transistors or interconnections formed under the first electrodes 202 in the semiconductor wafer 201 are unaffected.
- the resin 208 A is cured to form the resin layer 208 , so that the second semiconductor chip 204 and the semiconductor wafer 201 are integrated.
- the resin 208 A which is a photosetting resin, it is cured by irradiation of ultraviolet rays.
- the resin 208 A is a thermosetting resin, it is cured by heating.
- the resin 208 A is heated using heating instrument such as an oven after it is released from the pressing by the tool 209 or directly heated during the pressing step by the tool 209 using a heater installed in the tool 209 .
- the resin is appropriately heated for curing at a temperature of about 70 to 300° C. though the temperature depends on the material of the resin 208 A.
- FIGS. 11A and 11B are repeated as many times as the number of chip regions provided in the semiconductor wafer 201 , so that the joined body 210 as shown in FIG. 12( a ) results.
- a plurality of second semiconductor chips 204 are provided in the chip regions in the semiconductor wafer 201 .
- the back surface of the second semiconductor chip 204 (the surface opposite to the second main surface) in the joined body 210 is polished. More specifically, the resin 208 A is sufficiently cured to form the resin layer 208 .
- the joined body 210 is then placed on the polishing machine 211 so that the back surfaces of the second semiconductor chips 204 in the chip regions in the semiconductor wafer 201 are opposed to the upper surface (polishing surface) of the polishing machine 211 .
- the protection resin 212 is a thermosetting liquid resin, and supplied between the second semiconductor chips 204 on the surface of the semiconductor wafer 201 by spraying, centrifugal spin coating, attaching resin taping or the like.
- Abrasive grains 213 are supplied to the polishing surface of the polishing machine 211 , and then the polishing machine 211 is rotated as the joined body 210 is loaded with weight, so that the back surfaces of the second semiconductor chips 204 are polished.
- the thickness of the second semiconductor chip 204 on the semiconductor wafer 201 decreases in inverse proportion to the duration of the polishing time. More specifically, the polished second semiconductor chip 204 may have a thickness about in the range from 50 to 100 ⁇ m.
- the semiconductor wafer 201 has a thickness about in the range from 200 to 300 ⁇ m (which is substantially equal to the thickness of the second semiconductor chip 204 before polishing).
- the thickness of the second semiconductor chip 204 is at least smaller than that of the semiconductor wafer 201 (i.e., the thickness of the first semiconductor chip 201 a ).
- the abrasive grains 213 are preferably diamond grains having a grain size in the range from #1200 to #2000, and the polishing machine 211 is preferably rotated at about 5 to 50 rpm.
- the semiconductor wafer 201 is separated by dicing. More specifically, the chip regions in the semiconductor wafer 201 in the joined body 210 are separated as a plurality of discrete first semiconductor chips 201 a by dicing.
- a plurality of chip-layered bodies 214 each including one first semiconductor chip 201 a and one second semiconductor chip 204 joined with each other result. For the ease of illustration, only a single chip-layered body 214 will be described.
- the chip-layered body 214 is subjected to die-bonding and wire-bonding. More specifically, a lead frame 215 having a die pad portion 215 a and lead portions 215 b is prepared, and the back surface of the first semiconductor chip 201 a (the surface opposite to the first main surface) of the chip-layered body 214 is secured on the die pad portion 215 a with conductive paste 216 containing Pd, Ag or the like. Then, the bonding pads 203 on the first semiconductor chip 201 a and the lead portions 215 b are electrically connected through thin metal bonding wires 217 .
- the thin metal wire has a diameter of about 25 ⁇ m.
- the material of the thin metal wire can be Au, Al or the like.
- the back surface of the second semiconductor chip 204 is polished so that the distance T chip from the first main surface of the first semiconductor chip 201 a to the back surface of the second semiconductor chip 204 (the surface opposite to the second main surface) is smaller than the distance T wb from the first main surface of the first semiconductor chip 201 a to the highest position of the bonding wire 217 on the first main surface (the peak of the loop of the bonding wire 217 ). More specifically, the distance T chip is about 100 to 150 ⁇ m and T wb is about 150 to 400 ⁇ m though they vary depending on the kind of the semiconductor device.
- the chip-layered body 214 after the wire-bonding step is encapsulated in a resin. More specifically, the first semiconductor chip 201 a , the second semiconductor chip 204 , the die pad portion 215 a and the lead portions 215 b of the lead frame 215 , and the bonding wires 217 are encapsulated in a resin package 218 of an epoxy-based resin, a polyimide-based resin or the like. Note however that the bottom surface of the die pad portion 215 a and the bottom and outer side surfaces of the lead portions 215 b are exposed out of the resin package 218 . Thus, the bottom and outer side surfaces of the lead portions 215 b can serve as external terminals.
- the plurality of first semiconductor chips 201 a in the semiconductor wafer 201 and a plurality of discrete second semiconductor chips 204 are integrated to face to one another. Then, the semiconductor chips 204 are polished from the opposite side of their main surfaces (circuit forming surfaces). Therefore, the second semiconductor chips 204 have a thickness smaller than that of the semiconductor wafer 201 , i.e., the thickness of the first semiconductor chips 201 a .
- the semiconductor wafer 201 is then separated into a plurality of discrete semiconductor chips 201 a , so that a plurality of chip-layered bodies 214 each including a discrete first semiconductor chip 201 a and a discrete second semiconductor chip 204 joined with one another result.
- the chip-layered body 214 may have a reduced thickness so that the package structure including the chip-layered body 214 encapsulated in the resin package 218 can be thinner.
- the semiconductor device may have a reduced size and improved heat radiation property.
- the plurality of chip-layered bodies 214 in other words the plurality of semiconductor devices having a reduced size and improved heat radiation property can readily be manufactured simply by separating the semiconductor wafer 201 into the plurality of discrete first semiconductor chips 201 a.
- the back surface of the second semiconductor chip 204 is polished so that the distance from the first main surface of the first semiconductor chip 201 a to the back surface of the second semiconductor chip 204 is smaller than the distance from the first main surface of the first semiconductor chip 201 a to the peak of the loop of the bonding wire 217 .
- the second semiconductor chips 204 after the step of polishing the second semiconductor chip 204 from the back surface (see FIG. 12B), the second semiconductor chips 204 preferably have a thickness equal to or less than 1 ⁇ 2 of the thickness of the semiconductor wafer 201 (i.e., the first semiconductor chips 201 a ). In this way, the package structure including the chip-layered body 214 encapsulated in the resin package 218 can be made thinner. Therefore, the semiconductor device can have a more reduced size and more improved heat radiation property.
- the Sn—Pb alloy is used for the material of the metal bumps 207 , while any one of Au, In, Cu, Ni, an In—Sn alloy, a Sn—Ag alloy, a Sn—Cu alloy, a Sn—Zn alloy and the like can be used.
- a resin having a metallic filler dispersed therein may be used instead of the metal bumps 207 .
- the metal bumps 207 are formed on the second electrodes 205 on the second semiconductor chip 204 , while the metal bumps 207 may be formed on the first electrodes 202 provided in the chip regions in the semiconductor wafer 201 .
- the resin 208 A is the epoxy resin, while an acrylic resin, a polyimide resin, a urethane resin or the like may be used.
- the resin 208 A may be any of thermosetting resin, autopolymer resin, photosetting resin and the like.
- the resin 208 A may preferably be applied by any suitable method among dispensing, printing, and stamping methods and the like in consideration of the chip size and other conditions.
- the resin 208 A is applied on the surface of the chip region in the semiconductor wafer 201 (i.e., the first main surface of the first semiconductor chip 201 a ), while the resin 208 A may be applied on the second main surface of the second semiconductor chip 204 .
- the resin 208 A is applied before joining the first and second electrodes 202 and 205 through the metal bumps 207 , while the resin 208 A may be applied in a different timing such as after joining the first and second electrodes 202 and 205 through the metal bumps 207 .
- the resin 208 A or resin layer 208 is interposed between the surface of each chip region in the semiconductor wafer 201 (i.e., the first main surface of each of the first semiconductor chips 201 a ) and the second main surface of each of the second semiconductor chips 204 . Meanwhile, an anisotropic conductive sheet, an anisotropic conductive resin or the like may be interposed therebetween.
- FIGS. 15A, 15B, 16 A, 16 B and 17 are sectional views showing steps in the method of manufacturing a semiconductor device according to the modification of the fourth embodiment.
- the same elements as those in the fourth embodiment shown in FIGS. 11A, 11B, 12 A, 12 B, 13 A, 13 B and 14 will be denoted by the same reference characters and will not be detailed in some cases.
- discrete first semiconductor chips 201 a formed by dicing a semiconductor wafer are prepared, and then the first and second semiconductor chips 201 a and 204 are integrated.
- the first semiconductor chip 201 a and the second semiconductor chip 204 having a smaller area than the first semiconductor chip 201 a are registered.
- first electrodes 202 of Al for example, (for connection with bumps)
- second electrodes 205 of Al for example, on the second main surface of the second semiconductor chip 204 .
- barrier metal layer 206 of a thin metal film such as titanium, copper and nickel films is formed on each of the second electrodes 205 .
- metal bumps 207 of a Sn—Pb alloy are formed on the second electrodes 205 on the second semiconductor chip 204 through the barrier metal layers 206 .
- the metal bumps 207 have, for example, a diameter about in the range from 3 to 100 ⁇ m and a height about in the range from 3 to 50 ⁇ m.
- the first semiconductor chip 201 a is placed on a packaging jig (not shown) and a resin 208 A such as an epoxy resin is applied on the first main surface of the first semiconductor chip 201 a .
- the second semiconductor chip 204 is held over the first semiconductor chip 201 a using a tool 209 so that their main surfaces i.e., the circuit forming surfaces are opposed to one another.
- the first and second semiconductor chips 201 a and 204 are joined with one another. More specifically, the second semiconductor chip 204 is lowered as it is held by the tool 209 . Then, the metal bumps 207 formed on the second electrodes 205 on the second semiconductor chip 204 and the first electrodes 202 on the first semiconductor chip 201 a are registered.
- the bonding pads 203 on the first semiconductor chip 201 a are provided outside the region of the first main surface of the first semiconductor chip 201 a opposed to the second main surface of the second semiconductor chip 204 .
- the second semiconductor chip 204 is heated and pressed using the tool 209 from the surface opposite to the second main surface.
- the resin 208 A applied on the first main surface of the first semiconductor chip 201 a enhances the adhesion between the first and second semiconductor chips 201 a and 204 .
- the pressing force (load) by the tool 209 is suitably about 0.98 to 196 mN for each metal bump 207 , while the load is set on the condition that the first electrodes 202 are not damaged. Alternatively, the load may be set on the condition that the characteristics of elements such as transistors and interconnections and the like formed under the first electrodes 202 are unaffected.
- the resin 208 A is cured to form a resin layer 208 , so that the second semiconductor chip 204 and the first semiconductor chip 201 a are integrated.
- the back surface of the second semiconductor chip 204 (the surface opposite to the second main surface) in the joined body 210 having the second semiconductor chips 204 placed on the first semiconductor chip 201 a is polished. More specifically, the resin 208 A is sufficiently cured to form the resin layer 208 , and then the joined body 210 is placed on a polishing machine 211 so that the back surface of the second semiconductor chip 204 is opposed to the upper surface (polishing surface) of the polishing machine 211 .
- the polishing surface of the polishing machine 211 is supplied with abrasive grains 213 , and then the polishing machine 211 is rotated as the joined body 210 is pressed, so that the back surface of the second semiconductor chip 204 is polished.
- the thickness of the second semiconductor chip 204 decreases in inverse proportion to the duration of the polishing time. More specifically, the polished second semiconductor chip 204 can have a thickness about in the range from 50 to 100 ⁇ m.
- the first semiconductor chip 201 a has a thickness of about 200 to 300 ⁇ m (which is substantially equal to the thickness of the second semiconductor chip 204 before the polishing step).
- the second semiconductor chip 204 has a thickness at least smaller than the thickness of the first semiconductor chip 201 a .
- the abrasive grains 213 may preferably be diamond grains having a grain size in the range from #1200 to #2000, and the polishing machine 211 is preferably rotated at about 5 to 50 rpm.
- the chip-layered body 214 including the first semiconductor chip 201 a and the second semiconductor chip 204 having a polished back surface joined with one another is subjected to die-bonding and wire-bonding and resin encapsulation. More specifically, a lead frame 215 having a die pad portion 215 a and lead portions 215 b is prepared. The back surface of the first semiconductor chip 201 a of the chip-layered body 214 (the surface opposite to the first main surface) is secured on the die pad portion 215 a , for example, with conductive paste 216 containing Pd, Ag or the like.
- the bonding pads 203 on the first semiconductor chip 201 a and the lead portions 215 b are electrically connected through thin metal bonding wires 217 .
- the thin metal wire has a diameter of about 25 ⁇ m.
- the material of the thin metal wire may be Au, Al or the like.
- the back surface of the second semiconductor chip 204 is polished so that the distance T chip from the first main surface of the first semiconductor chip 201 a to the back surface of the second semiconductor chip 204 (the surface opposite to the second main surface) is smaller than the distance T wb from the first main surface of the first semiconductor chip 201 a to the highest position of the bonding wire 217 (i.e., the peak of the loop of the bonding wire 217 ) on the first main surface. More specifically, the distance T chip is about in the range from 100 to 150 ⁇ m, and T wb is about in the range from 150 to 400 ⁇ m.
- the first semiconductor chip 201 a , the second semiconductor chip 204 , the die pad portion 215 a and lead portions 215 b of the lead frame 215 , and the bonding wires 217 are encapsulated in a resin package 218 of, for example, an epoxy-based resin or a polyimide-based resin.
- a resin package 218 of, for example, an epoxy-based resin or a polyimide-based resin.
- the bottom surface of the die pad portion 215 a , and the bottom and outer side surfaces of the lead portions 215 b are exposed out of the resin package 218 , so that the bottom and outer side surfaces of the lead portions 215 b serve as external terminals.
- the first and second semiconductor chips 201 a and 204 are integrated to face to one another, and then the second semiconductor chip 204 is polished from the side opposite to the main surface (i.e., circuit forming surface), so that the second semiconductor chip 204 has a thickness smaller than the thickness of the first semiconductor chip 201 a .
- the layered body (chip-layered body 214 ) of the first and second semiconductor chips 201 a and 204 can have a reduced thickness. Therefore, the package structure including the chip-layered body 214 encapsulated in the resin package 218 can be made thinner, and the semiconductor device can have a reduced size and improved heat radiation property.
- the back surface of the second semiconductor chip 204 is polished so that the distance from the first main surface of the first semiconductor chip 201 a to the back surface of the second semiconductor chip 204 is smaller than the distance from the first main surface of the first semiconductor chip 201 a to the peak of the loop of the bonding wire 217 . Therefore, if the chip-layered body 214 is placed on the lead frame 215 in the semiconductor device, the device may surely have a reduced size and improved heat radiation property.
- the second semiconductor chip 204 after the step of polishing the second semiconductor chip 204 from the back surface (see FIG. 16A), the second semiconductor chip 204 preferably has a thickness about 1 ⁇ 2 or less of the thickness of the first semiconductor chip 201 a . In this way, the package structure including the chip-layered body 214 encapsulated in the resin package 218 can be made thinner, so that the semiconductor device can have a more reduced size and higher heat radiation property.
- the Sn—Pb alloy is used for the material of the metal bumps 207 , while any one of Au, In, Cu, Ni, an In—Sn alloy, a Sn—Ag alloy, a Sn—Cu alloy and a Sn—Zn alloy may be used.
- the material used for electrical connection between the first and second electrodes 202 and 205 may be conductive paste, an anisotropic conductive resin or a resin having a metallic filler dispersed therein instead of the metal bumps 207 .
- the metal bumps 207 are formed on the second electrodes 205 on the second semiconductor chip 204 , while the metal bumps 207 may be formed on the first electrodes 202 on the first semiconductor chip 201 a.
- the resin 208 A is the epoxy resin, while an acrylic resin, a polyimide resin, a urethane resin or the like can be used.
- the resin 208 A may be any of thermosetting, autopolymer, photosetting resin and the like.
- the resin 208 A may preferably be applied by any of dispensing, printing and stamping methods and the like in consideration of the chip size and other conditions.
- the resin 208 A is applied on the first main surface of the first semiconductor chip 201 a , while the resin 208 A may be applied on the second main surface of the semiconductor chip 204 .
- the resin 208 A is applied before joining the first and second electrodes 202 and 205 through the metal bumps 207 , while the resin 208 A may be applied in a different timing such as after joining these electrodes through the metal bumps 207 .
- the resin 208 A or resin layer 208 is interposed between the first main surface of the first semiconductor chip 201 a and the second main surface of the second semiconductor chip 204 , while an anisotropic conductive sheet, anisotropic conductive resin or the like may be interposed.
Abstract
Description
- The present invention relates to semiconductor devices having multiple semiconductor chips layered on one another and manufacturing methods thereof. The invention more particularly relates to a semiconductor device including two semiconductor chips having their circuit forming surfaces opposed to one another, and electrodes formed on the circuit forming surfaces being electrically connected with one another, and a manufacturing method thereof.
- In recent years, with the advent of smaller size electronic devices capable of high speed processing, a three-dimensional structure including two or more kinds of semiconductor chips layered on one another has come to be widely researched and developed.
- Such a conventional three-dimensional semiconductor device will be now described.
- FIG. 18 is a sectional view of the conventional semiconductor device.
- As shown in FIG. 18, the conventional semiconductor device includes a
first semiconductor chip 1 and asecond semiconductor chip 4. Thefirst semiconductor chip 1 hasfirst electrodes 2 and bondingpads 3 on a first main surface. Thesecond semiconductor chip 4 is provided withsecond electrodes 5 on a second main surface and has a smaller area than thefirst semiconductor chip 1. Herein, the first andsecond semiconductor chips second electrodes second electrodes second semiconductor chip 4 is placed facedown on thefirst semiconductor chip 1. More specifically, the first andsecond electrodes metal bump 7, while the part of thesecond electrode 5 in contact with themetal bump 7 is provided with abarrier metal layer 6. Thebonding pads 3 are provided outside the region of the first main surface of thefirst semiconductor chip 1 opposed to the second main surface of thesecond semiconductor chip 4. There is aresin layer 8 filled between the first main surface of thefirst semiconductor chip 1 and the second main surface of thesecond semiconductor chip 4. More specifically, the first andsecond semiconductor chips resin layer 8 into an integrated form. - The surface of the
first semiconductor chip 1 opposite to the first main surface is secured to adie pad portion 9 a byconductive paste 10 containing palladium (Pd), silver (Ag) or the like. Thebonding pad 3, and alead portion 9 b provided adjacent to thedie pad portion 9 a are electrically connected with one another through a thinmetal bonding wire 11. Note that thedie pad portion 9 a and thelead portion 9 b are cut from asingle lead frame 9. The first andsecond semiconductor chips die pad portion 9 a, thelead portions 9 b and thebonding wires 11 are encapsulated in aresin package 12. - A method of manufacturing the conventional semiconductor device will be now described.
- FIGS. 19A, 19B,20A and 20B are sectional views showing steps in the method of manufacturing the conventional semiconductor device.
- As shown in FIG. 19A, the first and
second semiconductor chips first electrodes 2 and a plurality ofbonding pads 3 are provided on a first main surface of thefirst semiconductor chip 1. Thechip 1 is then placed on a packaging jig (not shown) and aresin 8A is applied on the first main surface of thesemiconductor chip 1. Thesecond semiconductor chip 4 having a plurality ofsecond electrodes 5 on a second main surface is prepared over thefirst semiconductor chip 1 so that their main surfaces, i.e., their circuit forming surfaces are opposed to one another. Then, after a plurality ofmetal bumps 7 are formed on thesecond electrodes 5, the first andsecond electrodes barrier metal layer 6 provided on the part of thesecond electrodes 5 in contact with themetal bumps 7. - Then, as shown in FIG. 19B, the first and
second semiconductor chips second semiconductor chip 4 is heated and pressed using ametal tool 13 from the surface opposite to the second main surface. As a result, thefirst electrodes 2 on thefirst semiconductor chip 1 and thesecond electrodes 5 on thesecond semiconductor chip 4 are joined with one another through themetal bumps 7 formed on the second electrodes 5 (more precisely on the barrier metal layers 6) on thesecond semiconductor chip 4. Then, theresin 8A filled between the joined first andsecond semiconductor chips resin layer 8 results. - Then, as shown in FIG. 20A, the joined first and
second semiconductor chips lead frame 9 having adie pad portion 9 a andlead portions 9 b is prepared. Then, the surface opposite to the first main surface of thefirst semiconductor chip 1 is secured onto thedie pad portion 9 a usingconductive paste 10 containing Pd, Ag or the like. Thebonding pads 3 on thefirst semiconductor chip 1 and thelead portions 9 b are then electrically connected through thinmetal bonding wires 11. Thus, the electrical connection for the semiconductor device is completed. - As shown in FIG. 20B, the chip-layered body after the wire-bonding step is encapsulated in a resin. More specifically, the first and
second semiconductor chips die pad portion 9 a, thelead portions 9 b and thebonding wires 11 are encapsulated in aresin package 12. Note however that the bottom surface of thedie pad portion 9 a and the bottom and outer side surfaces of thelead portions 9 b (the side surfaces opposite to the side facing thedie pad portion 9 a) are exposed out of theresin package 12. Thus, the bottom and outer side surfaces of thelead portions 9 b serve as external terminals. - However, the conventional semiconductor device and the manufacturing method thereof described above suffer from the following disadvantages. The thickness of the semiconductor device having multiple layers of semiconductor chips increases in proportion to the number of the semiconductor chips used. For example, in the conventional semiconductor device shown in FIG. 18, the thickness of the first and
second semiconductor chips metal bumps 7 used to join the first andsecond semiconductor chips second semiconductor chips die pad portion 9 a as thick as several hundreds μm and the die-bonded chip-layered body as a whole is encapsulated in theresin package 12, the completed semiconductor device has a thickness about as large as 1 mm. Such a thickness is about the same as the thickness of the thin type packages widely used in recent years, which suggests how hard it could be to reduce the size of semiconductor devices having such a chip-layered body. - Meanwhile, semiconductor chips with large thickness in a semiconductor device could impede thermal radiation from the semiconductor chips, and therefore the heat radiation property of the semiconductor device as a whole could be lowered.
- In view of the foregoing, it is an object of the present invention to reduce the thickness of a chip-layered body forming a semiconductor device, and allow the semiconductor device to have a reduced size and improved heat radiation property.
- In order to achieve the object, the semiconductor device according to the present invention includes a first semiconductor chip provided with a first electrode on a first main surface, and a second semiconductor chip provided with a second electrode on a second main surface. The first and second semiconductor chips are integrated with one another so that the first and second main surfaces are opposed to one another and the first and second electrodes are electrically connected. The second semiconductor chip has a thickness smaller than a thickness of the first semiconductor chip.
- In the semiconductor device according to the present invention, since the second semiconductor chip integrated facedown with the first semiconductor chip has a thickness smaller than that of the first semiconductor chip, a chip-layered body including the first and second semiconductor chips may have a reduced thickness. The package structure including the chip-layered body encapsulated in a resin can thus be thinner, which allows the semiconductor device to have a reduced size and improved heat radiation property.
- In the semiconductor device according to the present invention, the second semiconductor chip preferably has the thickness equal to or smaller than ½ of the thickness of the first semiconductor chip.
- In this way, the package structure for the chip-layered body can be made thinner, so that the semiconductor device can have a more reduced size and higher heat radiation property.
- In the semiconductor device according to the present invention, a resin layer is preferably provided between the first and second main surfaces. Alternatively, a resin package to encapsulate the first and second semiconductor chips is preferably provided.
- In this way, the chip-layered body including the first and second semiconductor chips can have improved reliability.
- In the semiconductor device according to the present invention, an area of the first main surface is larger than an area of the second main surface, and a third electrode is provided outside a region of the first main surface opposed to the second main surface. A surface opposite to the first main surface of the first semiconductor chip is adhered to a die pad, a lead is provided adjacent to the die pad, and the lead and the third electrode are connected through a bonding wire. The first semiconductor chip, the second semiconductor chip and the bonding wire may be encapsulated in a resin package. In this case, a distance from the first main surface to a surface opposite to the second main surface of the second semiconductor chip is preferably smaller than a distance from the first main surface to the highest position of the bonding wire on the first main surface. In this way, a semiconductor device including a chip-layered body of the first and second semiconductor chips placed on a lead frame can surely have a reduced size and improved heat radiation property.
- A semiconductor device manufactured by a first manufacturing method according to the present invention includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The method includes a first step of integrating the first and second semiconductor chips by arranging the first and second main surfaces to be opposed to one another and electrically connecting the first and second electrodes, and a second step of polishing the second semiconductor chip integrated with the first semiconductor chip from the opposite side of the second main surface, so that the thickness of the second semiconductor chip is made smaller than the thickness of the first semiconductor chip.
- According to the first method, after the first and second semiconductor chips are integrated to be opposed to one another, the second semiconductor chip is polished from the opposite side of the main surface (circuit forming surface), so that the second semiconductor chip has a thickness smaller than the thickness of the first semiconductor chip. Therefore, the thickness of the chip-layered body including the first and second semiconductor chips can be reduced, so that the package structure including the chip-layered body encapsulated in a resin can have a reduced thickness, which permits the semiconductor device to have a reduced size and improved heat radiation property.
- By the first method, the first step preferably includes the step of forming a resin layer between the first and second main surfaces.
- In this way, the chip-layered body including the first and second semiconductor chips may have improved reliability.
- By the first method, the second step preferably includes the step of reducing the thickness of the second semiconductor chip to at most ½ of the thickness of the first semiconductor chip.
- In this way, the package structure including the chip-layered body can have a more reduced thickness, so that the semiconductor device can have a more reduced size and higher heat radiation property.
- By the first method, an area of the first main surface is larger than an area of the second main surface, a third electrode is provided outside a region of the first main surface opposed to the second main surface. The second step may precede the steps of adhering a surface of the first semiconductor chip opposite to the first main surface to a die pad, arranging a lead adjacent to the die pad and electrically connecting the lead and the third electrode through a bonding wire, and forming a resin package to encapsulate the first semiconductor chip, the second semiconductor chip and the bonding wire. In this case, the second step preferably includes the step of allowing a distance from the first main surface to a surface of the second semiconductor chip opposite to the second main surface to be smaller than a distance from the first main surface to the highest position of the bonding wire on the first main surface. In this way, the semiconductor device provided with the chip-layered body including the first and second semiconductor chips placed on a lead frame can surely have a reduced size and improved heat radiation property.
- A semiconductor device manufactured by a second manufacturing method according to the present invention includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The method includes a first step of integrating a semiconductor wafer to be a plurality of the first semiconductor chips and a plurality of discrete second semiconductor chips by arranging the first main surface of each first semiconductor chip in the semiconductor wafer to be opposed to the second main surface of each second semiconductor chip and electrically connecting the first electrode on each first semiconductor chip in the semiconductor wafer and the second electrode on each second semiconductor chip, a second step of polishing the second semiconductor chip integrated with the semiconductor wafer from an opposite side of the second main surface so that a thickness of each second semiconductor chip is smaller than a thickness of the semiconductor wafer, and a third step of separating the semiconductor wafer integrated with the second semiconductor chips into a plurality of discrete first semiconductor chips, thereby forming a plurality of chip-layered bodies each including a discrete first semiconductor chips and a discrete the second semiconductor chips integrated with one another.
- By the second method, in addition to the effects brought about by the first method, the following effect results. More specifically, a plurality of chip-layered bodies, in other words a plurality of semiconductor devices having a reduced size and improved heat radiation property can readily be manufactured simply by separating a semiconductor wafer into a plurality of discrete first semiconductor chips.
- By the second method, the first step preferably includes the step of forming a resin layer between the first main surface of each first semiconductor chip in the semiconductor wafer and the second main surface of each second semiconductor chip.
- In this way, the chip-layered body including the first and second semiconductor chips can have improved reliability.
- By the second method, the second step preferably includes the step of reducing the thickness of each second semiconductor chip to at most ½ of the semiconductor wafer.
- In this way, the package structure including the chip-layered body can have a more reduced thickness, so that the semiconductor device can have a more reduced size and improved heat radiation property.
- By the second method, an area of the first main surface is larger than an area of the second main surface. A third electrode is provided outside a region of the first main surface opposed to the second main surface. After the third step, the chip-layered bodies may each be subjected to the steps of adhering a surface of the first semiconductor chip opposite to the first main surface to a die pad, providing a lead adjacent to the die pad and electrically connecting the lead and the third electrode through a bonding wire, and forming a resin package to encapsulate the first semiconductor chip, the second semiconductor chip and the bonding wire. In this case, the second step preferably includes the step of arranging a distance from the first main surface of each first semiconductor chip in the semiconductor wafer to a surface of each second semiconductor chip opposite to the second main surface to be smaller than a distance from the first main surface of each first semiconductor chip in the semiconductor wafer to the highest position of the bonding wire on the first main surface. In this way, the semiconductor device including the chip-layered body of the first and second semiconductor chips placed on a lead frame can surely have a reduced size and improved heat radiation property.
- FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
- FIG. 2 is a sectional view of a semiconductor device according to a modification of the first embodiment;
- FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention;
- FIGS. 4A and 4B are sectional views showing steps in a method of manufacturing a semiconductor device according to a third embodiment of the present invention;
- FIGS. 5A and 5B are sectional views showing steps in the method of manufacturing a semiconductor device according to the third embodiment of the present invention;
- FIGS. 6A and 6B are sectional views showing steps in the method of manufacturing a semiconductor device according to the third embodiment of the present invention;
- FIG. 7 is a sectional view showing one step in the method of manufacturing a semiconductor device according to the third embodiment;
- FIGS. 8A and 8B are sectional views showing steps in a method of manufacturing a semiconductor device according to a modification of the third embodiment of the present invention;
- FIGS.9A, and 9B are sectional views showing steps in the method of manufacturing a semiconductor device according to the modification of the third embodiment of the present invention;
- FIG. 10 is a sectional view showing one step in the method of manufacturing a semiconductor device according to the modification of the third embodiment;
- FIGS. 11A and 11B are sectional views showing steps in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention;
- FIGS. 12A and 12B are sectional views showing steps in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention;
- FIGS.13A, and 13B are sectional views showing steps in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention;
- FIG. 14 is a sectional view showing one step in the method of manufacturing a semiconductor device according to the fourth embodiment;
- FIGS. 15A and 15B are sectional views showing steps in a method of manufacturing a semiconductor device according to a modification of the fourth embodiment of the present invention;
- FIGS.16A, and 16B are sectional views showing steps in the method of manufacturing a semiconductor device according to the modification of the fourth embodiment of the present invention;
- FIG. 17 is a sectional view showing one step in the method of manufacturing a semiconductor device according to the modification of the fourth embodiment;
- FIG. 18 is a sectional view of a conventional semiconductor device;
- FIGS. 19A and 19B are sectional views showing steps in a method of manufacturing the conventional semiconductor device; and
- FIGS.20A, and 20B are sectional views showing steps in the method of manufacturing the conventional semiconductor device.
- [First Embodiment]
- A semiconductor device according to a first embodiment of the present invention will be now described in conjunction with the accompanying drawings.
- FIG. 1 is a sectional view of the semiconductor device according to the first embodiment.
- As shown in FIG. 1, the semiconductor device according to the first embodiment includes first and
second semiconductor chips first semiconductor chip 101 is provided withfirst electrodes 102 andbonding pads 103 on a first main surface. Thesecond semiconductor chip 104 is provided withsecond electrodes 105 on a second main surface and has a smaller area than thefirst semiconductor chip 101. Herein, the first andsecond semiconductor chips second electrodes second electrodes second semiconductor chip 104 is joined facedown on thefirst semiconductor chip 101. More specifically, the first andsecond electrodes second electrode 105 in contact with themetal bump 107 is provided with abarrier metal layer 106. Note that the bonding pad 103 (which corresponds to the third electrode in the section of “What is claimed is:”) is provided outside the region of the first main surface of thefirst semiconductor chip 101 opposed to the second main surface of thesecond semiconductor chip 104. There is aresin layer 108 filled between the first main surface of thefirst semiconductor chip 101 and the second main surface of thesecond semiconductor chip 104. More specifically, thefirst semiconductor chip 101 and thesecond semiconductor chip 104 are adhered by theresin layer 108 into an integrated form. - The surface of the
first semiconductor chip 101 opposite to the first main surface is adhered to adie pad portion 109 a byconductive paste 110 containing Pd, Ag or the like. Leadportions 109 b provided adjacent to thedie pad portion 109 a are used to exchange electrical signals between elements such as transistors in the semiconductor chips and external devices. Thelead portions 109 b and thebonding pads 103 on thefirst semiconductor chip 101 are electrically connected through thinmetal bonding wires 111. Note that thedie pad portion 109 a and thelead portion 109 b are cut from asingle lead frame 109. Thefirst semiconductor chip 101, thesecond semiconductor chip 104, thedie pad 109 a, thelead portions 109 b, and thebonding wires 111 are encapsulated in aresin package 112. - Herein, according to the first embodiment, as shown in FIG. 1, the
second semiconductor chip 104 has a thickness T2 smaller than the thickness of T1 of the first semiconductor chip 101 (T2<T1). - According to the first embodiment, the
second semiconductor chip 104 integrated facedown with thefirst semiconductor chip 101 is thinner than thefirst semiconductor chip 101. Therefore, the chip-layered body including the first andsecond semiconductor chips resin package 112 to be thinner, so that the semiconductor device can have a reduced size and improved heat radiation property. - Also according to the first embodiment, the
resin layer 108 is provided between the first main surface of thefirst semiconductor chip 101 and the second main surface of thesecond semiconductor chip 104, and thesesemiconductor chips resin package 112. Therefore, the chip-layered body including the first andsecond semiconductor chips - [Modification of First Embodiment]
- A semiconductor device according to a modification of the first embodiment of the present invention will be now described in conjunction with the accompanying drawings.
- FIG. 2 is a sectional view of the semiconductor device according to the modification of the first embodiment. Note that in the following description of the modification, the same elements as those in the first embodiment shown in FIG. 1 will be denoted by the same reference characters and will not be detailed.
- As shown in FIG. 2, according to the modification of the first embodiment, the
second semiconductor chip 104 has a thickness T2 equal to or smaller than ½ of the thickness T1 of the first semiconductor chip 101 (T2×2 T1). - According to the modification of the first embodiment, the package structure including the layered body of the first and
second semiconductor chips resin package 112 can be made thinner than the first embodiment, and therefore the semiconductor device can have a more reduced size and more improved heat radiation property. - According to the modification of the first embodiment, the
semiconductor chip 101 has, for example, a thickness T1 about in the range from 200 to 300 μm, while thesecond semiconductor chip 104 has, for example, a thickness T2 about in the range from 50 to 100 μm. - [Second Embodiment]
- A semiconductor device according to a second embodiment of the present invention will be now described in conjunction with the accompanying drawings.
- FIG. 3 is a sectional view of the semiconductor device according to the second embodiment. In the following description of the second embodiment, the same elements as those in the first embodiment shown in FIG. 1 will be denoted by the same reference characters and will not be detailed.
- As shown in FIG. 3, according to the second embodiment, the distance Tchip from the first main surface of the
first semiconductor chip 101 to the surface of thesecond semiconductor chip 104 opposite to the second main surface is smaller than the distance Twb from the first main surface of thefirst semiconductor chip 101 to the highest position of thebonding wire 111 on the first main surface (i.e., the peak of the loop of the bonding wire 111) (Tchip<Twb). - According to the second embodiment, in addition to the effects brought about by the first embodiment, the following effect results. The semiconductor device including the layered body of the
first semiconductor chip 101 and thesecond semiconductor chip 104 placed on thelead frame 109 can surely have a reduced size and improved heat radiation property. - [Third Embodiment]
- A method of manufacturing a semiconductor device according to a third embodiment of the present invention will be now described in conjunction with the accompanying drawings.
- FIGS. 4A, 4B,5A, 5B, 6A, 6B, and 7 are sectional views showing steps in the method of manufacturing the semiconductor device according to the third embodiment.
- As shown in FIG. 4A, a
semiconductor wafer 201 having a plurality of chip regions to befirst semiconductor chips 201 a (see FIG. 6A) and asecond semiconductor chip 204 are registered. Thesecond semiconductor chip 204 has a smaller area than that of a chip region in the semiconductor wafer 201 (i.e., thefirst semiconductor chip 201 a). Note that in FIGS. 4A, 4B, 5A, 5B, and 6A, the boundaries between the chip regions are denoted by broken lines. - Here, an element such as a transistor or interconnection is formed in each chip region in the
semiconductor wafer 201. On the surface of each chip region in the semiconductor wafer 201 (i.e., on the first main surface of thesemiconductor chip 201 a), there are a plurality of first electrodes 202 (for connection with bumps) and a plurality of bonding pads 203 (for connection with thin metal wires). Thefirst electrodes 202 andbonding pads 203 are formed, for example, of aluminum (Al). Thebonding pad 203 corresponds to the “third electrode” in the section of “What is claimed is.” Meanwhile, a plurality ofsecond electrodes 205 of Al, for example, are formed on the second main surface of thesemiconductor chip 204. Abarrier metal layer 206 of a titanium, copper or nickel metal thin film, for example, is formed on each of thesecond electrodes 205. - More specifically, as shown in FIG. 4A, a
metal bump 207 of an alloy of tin (Sn) and lead (Pb) (Sn—Pb alloy), for example, is formed on each of thesecond electrodes 205 on thesecond semiconductor chip 204 through thebarrier metal layer 206. Themetal bump 207 has a diameter about in the range from 3 to 100 μm and a height about in the range from 3 to 50 μm. Thesemiconductor wafer 201 is placed on the packaging jig (not shown) and aresin 208A such as an epoxy resin is applied on the surface of one chip region in thesemiconductor wafer 201. Then, thesecond semiconductor chip 204 is held by atool 209 over the chip region in thesemiconductor wafer 201, so that the surface of the chip region and the second main surface of thesemiconductor chip 204 are opposed to each other. Then, as shown in FIG. 4B, the chip region in thesemiconductor wafer 201 and thesecond semiconductor chip 204 are joined with each other. More specifically, thesecond semiconductor chip 204 is lowered as it is held by thetool 209, and the metal bumps 207 formed on thesecond electrodes 205 on thesecond semiconductor chip 204 and thefirst electrodes 202 placed in the chip region in thesemiconductor wafer 201 are registered. Here, thebonding pads 203 in the chip region in thesemiconductor wafer 201 are provided outside the region of the surface of the chip region opposed to the second main surface of thesecond semiconductor chip 204. - Then, the
second semiconductor chip 204 is heated and pressed from the surface opposite to the second main surface using thetool 209. Thus, the registeredfirst electrodes 202 andmetal bumps 207 on thesecond semiconductor chip 204 are joined by physical or metallurgical effect (such as interdiffusion of atoms). At the time, theresin 208A applied on the surface of the chip region in thesemiconductor wafer 201 enhances the adhesion between thesemiconductor wafer 201 and thesecond semiconductor chip 204. Note that the pressing force (load) by thetool 209 should be about in the range from 0.98 to 196 mN for eachmetal bump 207, and the size of the load is set on the condition that thefirst electrodes 202 are not damaged. Alternatively, the load may be set on the condition that the characteristics of elements such as transistors or interconnections formed under thefirst electrodes 202 in thesemiconductor wafer 201 are unaffected. - Then, the
resin 208A is cured to form aresin layer 208, so that thesecond semiconductor chip 204 and thesemiconductor wafer 201 are integrated. At the time, theresin 208A can be cured by irradiation of ultraviolet rays if it is a photosetting resin. Theresin 208A can be cured by heating if it is a thermosetting resin. If theresin 208A is to be cured by heating (i.e., if the resin is a thermosetting resin), theresin 208A is heated using heating instrument such as an oven after it is released from the pressing by thetool 209. Alternatively, a heater installed in thetool 209 is used to directly heat the resin during the pressing step by thetool 209. Although the temperature varies depending on the kind of the resin, theresin 208A should be cured at a temperature about in the range from 70 to 300° C. - The steps shown in FIGS. 4A and 4B are repeated as many times as the number of chip regions provided in the
semiconductor wafer 201. Then, as shown in FIG. 5A, a joinedbody 210 including a plurality ofsecond semiconductor chips 204 each provided in a chip region in thesemiconductor wafer 201 can be formed. - Then, as shown in FIG. 5B, the back surface of each of the semiconductor chips204 (the surface opposite to the second main surface) in the joined
body 210 is polished. More specifically, theresin 208A is sufficiently cured to form theresin layer 208, and then the joinedbody 210 is placed on a polishingmachine 211 so that the back surfaces of thesecond semiconductor chips 204 placed in the chip regions in thesemiconductor wafer 201 are opposed to the upper surface (polishing surface) of the polishingmachine 211. Aprotection resin 212 is provided between thesecond semiconductor chips 204 placed in the chip regions in thesemiconductor wafer 201. After the polishing surface of the polishingmachine 211 is supplied withabrasive grains 213, the polishingmachine 211 is rotated as the joinedbody 210 is loaded with weight. In this manner, the back surfaces of thesecond semiconductor chips 204 are polished. At the time, in the joinedbody 210 removed from the polishingmachine 211, the thickness of thesecond semiconductor chip 204 on thesemiconductor wafer 201 decreases in inverse proportion to the duration of the polishing time. Note that for theabrasive grains 213, diamond grains having a grain size in the range from #1200 to #2000 are preferably used, and the polishingmachine 211 is preferably rotated at about 5 to 50 rpm. - According to the third embodiment, the back surfaces of the
second semiconductor chips 204 can be polished so that the thickness of thesecond semiconductor chips 204 is at least smaller than the thickness of the semiconductor wafer 201 (i.e., the thickness of thefirst semiconductor chips 201 a). More specifically, the polishedsecond semiconductor chip 204 preferably has a thickness about in the range from 50 to 100 μm. Note that thesemiconductor wafer 201 has a thickness about in the range from 200 to 300 μm, and thesemiconductor chip 204 before polishing is about as thick as thesemiconductor wafer 201. - Then, as shown in FIG. 6A, the
semiconductor wafer 201 is subjected to dicing. More specifically, the chip regions in thesemiconductor wafer 201 in the joinedbody 210 are separated as a plurality of discretefirst semiconductor chips 201 a by dicing. Thus, a plurality of chip-layeredbodies 214 each including onefirst semiconductor chip 201 a and onesecond semiconductor chip 204 joined with one another result. For the ease of illustration, only a single chip-layeredbody 214 will be described. - As shown in FIG. 6B, the chip-layered
body 214 is subjected to die-bonding and wire-bonding. More specifically, alead frame 215 having adie pad portion 215 a andlead portions 215 b is prepared. The back surface of thefirst semiconductor chip 201 a forming the chip-layered body 214 (the surface opposite to the first main surface) is secured on thedie pad portion 215 a usingconductive paste 216 containing Pd, Ag or the like. Then, thebonding pad 203 on thefirst semiconductor chip 201 a and thelead portion 215 b are electrically connected through a thinmetal bonding wire 217. Here, the thin metal wire has a diameter of about 25 μm. Gold (Au), Al or the like can be used for the thin metal wire. - As shown in FIG. 7, after the wire-bonding step, the chip-layered
body 214 is encapsulated in a resin. More specifically, thefirst semiconductor chip 201 a, thesecond semiconductor chip 204, thedie pad portion 215 a andlead portions 215 b of thelead frame 215, and thebonding wires 217 are encapsulated in aresin package 218 of an epoxy-based resin, a polyimide-based resin or the like. Note, however, that the bottom surface of thedie pad portion 215 a and the bottom and outer side surfaces of thelead portions 215 b are exposed out of theresin package 218. Thus, the bottom and outer side surfaces of thelead portions 215 b serve as external terminals. - As in the foregoing, according to the third embodiment, the plurality of
first semiconductor chips 201 a in thesemiconductor wafer 201 and the plurality of discretesecond semiconductor chips 204 are integrated to face to one another. Then, thesecond semiconductor chips 204 are polished from the side opposite to their main surfaces (circuit forming surfaces), so that thesecond semiconductor chips 204 have a thickness smaller than the thickness of thesemiconductor wafer 201 or thefirst semiconductor chip 201 a. Then, thesemiconductor wafer 201 is separated into a plurality of discretefirst semiconductor chips 201 a, so that a plurality of chip-layeredbodies 214 each including a discretefirst semiconductor chip 201 a and a discretesecond semiconductor chip 204 joined with one another are formed. Therefore, the chip-layeredbody 214 may have a reduced thickness, and the package structure including the chip-layeredbody 214 encapsulated in theresin package 218 can be made thinner. This permits the semiconductor device to have a reduced size and improved heat radiation property. A plurality of chip-layeredbodies 214, in other words a plurality of semiconductor devices having a reduced size and improved heat radiation property can easily be produced simply by separating thesemiconductor wafer 201 into a plurality ofdiscrete semiconductor chips 201 a. - Meanwhile, according to the third embodiment, the
semiconductor wafer 201 to be separated into the plurality ofsemiconductor chips 201 a is not polished for the purpose of reducing the thickness of the chip-layeredbody 214. This is because the area of thesemiconductor wafer 201 is larger than the area of thesecond semiconductor chip 204, and if therefore thesemiconductor wafer 201 is polished, mechanical defects such as cracking or chipping are likely to result. In contrast, thesecond semiconductor chips 204 are prepared as they are separated as discrete chips and have a smaller area, and therefore such mechanical defects are much less likely if thesecond semiconductor chips 204 are polished. - Note that according to the third embodiment, after the step of polishing the
second semiconductor chip 204 from the back surface (see FIG. 5B), thesecond semiconductor chip 204 preferably has a thickness about ½ or less of the thickness of the semiconductor wafer 201 (i.e., the thickness of thefirst semiconductor chip 201 a). Thus, the package structure including the chip-layeredbody 214 encapsulated in theresin package 218 can be made thinner, so that the semiconductor device can have a more reduced size and more improved heat radiation property. - According to the third embodiment, the Sn—Pb alloy is used as the material of the metal bumps207, while one selected from Au, In, Cu, Ni, an In—Sn alloy, a Sn—Ag alloy, a Sn—Cu alloy and a Sn—Zn alloy may be used. For electrical connection between the first and
second electrodes - According to the third embodiment, the metal bumps207 are formed on the
second electrodes 205 on thesecond semiconductor chip 204, while the metal bumps 207 may be formed on thefirst electrodes 202 provided in each chip region in thesemiconductor wafer 201. - According to the third embodiment, the
resin 208A is the epoxy resin, while an acrylic resin, a polyimide resin, a urethane resin or the like can be used. Theresin 208A may be any of thermosetting resin, autopolymer resin, and photosetting resin. Theresin 208A may be preferably applied according to any suitable method among dispensing, printing and stamping methods and the like in consideration of the chip size and other conditions. - According to the third embodiment, the
resin 208A is applied on the surface of each chip region in the semiconductor wafer 201 (the first main surface of eachfirst semiconductor chip 201 a), while theresin 208A may be applied on the second main surface of thesecond semiconductor chip 204. - According to the third embodiment, the
resin 208A is applied before joining thefirst electrodes 202 and thesecond electrodes 205 through the metal bumps 207. Theresin 208A may be applied in a different timing such as after joining these electrodes through the metal bumps 207. - According to the third embodiment, the
resin 208A orresin layer 208 is interposed between the surfaces of the chip regions in the semiconductor wafer 201 (i.e., the first main surfaces of thefirst semiconductor chips 201 a) and the second main surfaces of the second semiconductor chips 204. Meanwhile, an anisotropic conductive sheet, an anisotropic conductive resin or the like may be interposed therebetween. - [Modification of Third Embodiment]
- A method of manufacturing a semiconductor device according to a modification of the third embodiment of the invention will be now descried in conjunction with the accompanying drawings.
- FIGS. 8A, 8B,9A, 9B and 10 are sectional views showing steps in the method of manufacturing a semiconductor device according to the modification of the third embodiment. Note that according to the modification, the same elements as those in the third embodiment shown in FIGS. 4A, 4B, 5A, 5B, 6A, 6B and 7 will be denoted by the same reference characters and will not be described in some cases.
- Unlike the third embodiment, according to the modification of the third embodiment, discrete
first semiconductor chips 201 a formed by dicing the semiconductor wafer are prepared and then the first andsecond semiconductor chips - As shown in FIG. 8A, the
first semiconductor chip 201 a and thesecond semiconductor chip 204 having a smaller area than thefirst semiconductor chip 201 a are registered. Note that there are a plurality of first electrodes 202 (for connection with bumps) of Al, for example, and a plurality of bonding pads 203 (for connection with thin metal wires) of Al, for example, on the first main surface of thefirst semiconductor chip 201 a. Meanwhile, there are a plurality ofsecond electrodes 205 of Al, for example, on the second main surface of thesecond semiconductor chip 204. Thesecond electrodes 205 each have abarrier metal layer 206 thereon. The layer is of a metal thin film such as titanium, copper and nickel films. - More specifically, as shown in FIG. 8A, metal bumps207 of a Sn—Pb alloy, for example, are formed on the
second electrodes 205 on thesecond semiconductor chip 204 through the barrier metal layers 206. Themetal bump 207 has, for example, a diameter about in the range from 3 to 100 μm, and a height about in the range from 3 to 50 μm. Thefirst semiconductor chip 201 a is placed on the packaging jig (not shown) and aresin 208A such as an epoxy resin is applied on the first main surface of thefirst semiconductor chip 201 a. Then, thesecond semiconductor chip 204 is held over thefirst semiconductor chip 201 a using thetool 209 so that the main surfaces of the semiconductor chips, i.e., the circuit forming surfaces are opposed to each other. - Then, as shown in FIG. 8B, the
first semiconductor chip 201 a and thesecond semiconductor chip 204 are joined with each other. More specifically, thesecond semiconductor chip 204 is lowered as it is held by thetool 209, and the metal bumps 207 formed on thesecond electrodes 205 on thesecond semiconductor chip 204 and thefirst electrodes 202 on thefirst semiconductor chip 201 a are registered. Here, thebonding pads 203 on thefirst semiconductor chip 201 a are provided outside the region of the first main surface of thefirst semiconductor chip 201 a opposed to the second main surface of thesecond semiconductor chip 204. Then, thesecond semiconductor chip 204 is heated and pressed using thetool 209 from the surface opposite to the second main surface. Thus, the registeredfirst electrodes 202 andmetal bumps 207 on thesecond semiconductor chip 204 are joined. At the time, theresin 208A applied on the first main surface of thefirst semiconductor chip 201 a enhances the adhesion between the first andsecond semiconductor chips tool 209 is suitably about in the range from 0.98 to 196 mN for eachmetal bump 207, and the load is set on the condition that thefirst electrodes 202 are not damaged. Alternatively, the load could be set on the condition that the characteristics of elements such as transistors, interconnections or the like formed under thefirst electrodes 202 on thefirst semiconductor chip 201 a are unaffected. Then, theresin 208A is cured to form theresin layer 208, so that the second andfirst semiconductor chips - Then, as shown in FIG. 9A, in the joined
body 210 having thefirst semiconductor chip 201 a and thesecond semiconductor chip 204 placed thereon, the back surface of the second semiconductor chip 204 (the surface opposite to the second main surface) is polished. More specifically, theresin 208A is sufficiently cured to form theresin layer 208 and then the joinedbody 210 is placed on the polishingmachine 211 so that the back surface of thesecond semiconductor chip 204 is opposed to the upper surface (polishing surface) of the polishingmachine 211.Abrasive grains 213 are supplied to the polishing surface of the polishingmachine 211, and then the joinedbody 210 is loaded with weight as the polishingmachine 211 is rotated to polish the back surface of thesecond semiconductor chip 204. At the time, in the joinedbody 210 removed from the polishingmachine 211, the thickness of thesecond semiconductor chip 204 decreases in inverse proportion to the duration of the polishing time period. Note that for theabrasive grains 213, diamond grains having a grain size in the range from #1200 to #2000 are preferably used, and the polishingmachine 211 is preferably rotated at about 5 to 50 rpm. - According to the modification of the third embodiment, the back surface of the
second semiconductor chip 204 is polished so that the thickness of thesecond semiconductor chip 204 is at least smaller than that of thefirst semiconductor chip 201 a. More specifically, the thickness of thepolished semiconductor chip 204 preferably has a thickness about in the range from 50 to 100 μm. Note that thesecond semiconductor chip 204 before the polishing has a thickness about in the range from 200 to 300 μm which is about as large as the thickness of thefirst semiconductor chip 201 a. - As shown in FIGS. 9B and 10, the chip-layered
body 214 including thefirst semiconductor chip 201 a and thesecond semiconductor chip 204 having a polished back surface joined with one another is subjected to die-bonding and wire-bonding, and resin encapsulation. More specifically, alead frame 215 having adie pad portion 215 a andlead portions 215 b is prepared. The back surface of thefirst semiconductor chip 201 a of the chip-layered body 214 (the surface opposite to the first main surface) is secured on thedie pad portion 215 a withconductive paste 216 containing Pd, Ag or the like. Then, thebonding pads 203 on thefirst semiconductor chip 201 a and thelead portions 215 b are electrically connected with one another through the thinmetal bonding wires 217. The thin metal wires have a diameter of about 25 μm. The material of the thin metal wires can be for example Au or Al. Finally, thefirst semiconductor chip 201 a, thesecond semiconductor chip 204, thedie pad portion 215 a andlead portions 215 b of thelead frame 215 and thebonding wires 217 are encapsulated in aresin package 218 of an epoxy-based resin or a polyimide-based resin. Note, however, that the bottom surface of thedie pad portion 215 a and the bottom and outer side surfaces of thelead portions 215 b are exposed out of theresin package 218, so that the bottom and outer side surfaces of thelead portions 215 b can serve as external terminals. - As in the foregoing, according to the modification of the third embodiment, the first and
second semiconductor chips second semiconductor chip 204 is polished from the opposite side to the main surface (i.e., the circuit forming surface) so that thesecond semiconductor chip 204 is made thinner than thefirst semiconductor chip 201 a. Therefore, the layered-body (chip-layered body 214) including the first andsecond semiconductor chips body 214 encapsulated in theresin package 218 can be made thinner, which allows the semiconductor device to have a reduced size and improved heat radiation property. - According to the modification of the third embodiment, after the step of polishing the
second semiconductor chip 204 from the back surface (see FIG. 9A), the thickness of thesecond semiconductor chip 204 is preferably reduced to ½ or less of the thickness of thefirst semiconductor chip 201 a. Thus, the package structure including the chip-layeredbody 214 encapsulated in theresin package 218 can be made thinner, and therefore the semiconductor device can have a more reduced size and higher heat radiation property. - According to the modification of the third embodiment, the Sn—Pb alloy is used for the material of the metal bumps207, while any one of Au, In, Cu, Ni, an In—Sn alloy, a Sn—Ag alloy, a Sn—Cu alloy, and a Sn—Zn alloy may be used. As the material for electrical connection between the first and
second electrodes - According to the modification of the third embodiment, the metal bumps207 are formed on the
second electrodes 205 on thesecond semiconductor chip 204, while the metal bumps 207 may be formed on thefirst electrodes 202 on thefirst semiconductor chip 201 a. - According to the modification of the third embodiment, the
resin 208A is the epoxy resin, while an acrylic resin, a polyimide resin, a urethane resin or like may be used. Theresin 208A may be any of thermosetting resin, autopolymer resin and photosetting resin. Theresin 208A is preferably applied by any suitable method among dispensing, printing and stamping methods and the like in consideration of the chip size and other conditions. - According to the modification of the third embodiment, the
resin 208A is applied on the first main surface of thefirst semiconductor chip 201 a, while theresin 208A may be applied on the second main surface of thesecond semiconductor chip 204. - According to the modification of the third embodiment, the
resin 208A is applied before joining the first andsecond electrodes resin 208A may be applied in a different timing such as after joining these electrodes through the metal bumps 207. - According to the modification of the third embodiment, the
resin 208A orresin layer 208 is interposed between the first main surface of thefirst semiconductor chip 201 a and the second main surface of thesecond semiconductor chip 204, while an anisotropic conductive sheet or an anisotropic conductive resin may be interposed. - [Fourth Embodiment]
- A method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be now described.
- FIGS. 11A, 11B,12A, 12B, 13A, 13B and 14 are sectional views showing steps in the method of manufacturing a semiconductor device according to the fourth embodiment.
- As shown in FIG. 11A, similarly to the step shown in FIG. 4A according to the third embodiment, a
semiconductor wafer 201 and asecond semiconductor chip 204 are registered. Thewafer 201 has a plurality of chip regions to be a plurality ofsemiconductor chips 201 a (see FIG. 13A). Thesecond semiconductor chip 204 has a smaller area than a chip region (i.e., thefirst semiconductor chip 201 a). Note that FIGS. 11A, 11B, 12A, 12B, and 13A show the boundaries between the chip regions by the dotted lines. - Here, elements such as transistors or interconnections are formed in the chip regions in the
semiconductor wafer 201. A plurality of first electrodes 202 (for connection with bumps) of Al, for example, and a plurality of bonding pads 203 (for connection with thin metal wires) of Al, for example, are formed on the surface of each of the chip regions (i.e., the first main surface of thesemiconductor chips 201 a) in thesemiconductor wafer 201. Thebonding pad 203 corresponds to the “third electrode” in the section of “What is claimed is.” Meanwhile, a plurality ofsecond electrodes 205 of Al, for example, are provided on the second main surface of thesecond semiconductor chip 204. Barrier metal layers 206 of a thin metal film of titanium, copper, nickel or the like is provided on thesecond electrodes 205. - More specifically, as shown in FIG. 11A, metal bumps207 of a Sn—Pb alloy, for example, are formed on the
second electrodes 205 on thesecond semiconductor chip 204 through the barrier metal layers 206. Themetal bump 207 has a diameter of about 3 to 100 μm and a height of about 3 to 50 μm. Thesemiconductor wafer 201 is placed on a packaging jig (not shown) and aresin 208A such as an epoxy resin is applied on the surface of one chip region in thesemiconductor wafer 201. Thesecond semiconductor chip 204 is held using thetool 209 over the chip region in thesemiconductor wafer 201 so that the surface of the chip region and the second main surface of thesecond semiconductor chip 204 are opposed to each other. - As shown in FIG. 11B, similarly to the step shown in FIG. 4B according to the third embodiment, the chip region in the
semiconductor wafer 201 and thesecond semiconductor chip 204 are joined with one another. More specifically, thesecond semiconductor chip 204 is lowered as it is held by thetool 209. Thus, the metal bumps 207 formed on thesecond electrodes 205 on thesecond semiconductor chip 204 and thefirst electrodes 202 provided in the chip region in thesemiconductor wafer 201 are registered. Here, thebonding pads 203 in the chip region in thesemiconductor wafer 201 are formed outside the region of the surface of the chip region opposed to the second main surface of thesecond semiconductor chip 204. - Then, the
second semiconductor chip 204 is heated and pressed using thetool 209 from the surface opposite to the second main surface. As a result, the registeredfirst electrodes 202 and the metal bumps 207 on thesecond semiconductor chip 204 are joined by physical or metallurgical effect. At the time, theresin 208A previously applied on the surface of the chip region in thesemiconductor wafer 201 enhances the adhesion between thesemiconductor wafer 201 and thesecond semiconductor chip 204. Note that the pressing force (load) by thetool 209 is suitably about in the range from 0.98 to 196 mN for eachmetal bump 207, and the load is set on the condition that thefirst electrodes 202 are not damaged. Alternatively, the load may be set on the condition that the characteristics of elements such as transistors or interconnections formed under thefirst electrodes 202 in thesemiconductor wafer 201 are unaffected. - Then, the
resin 208A is cured to form theresin layer 208, so that thesecond semiconductor chip 204 and thesemiconductor wafer 201 are integrated. At the time, if theresin 208A which is a photosetting resin, it is cured by irradiation of ultraviolet rays. If theresin 208A is a thermosetting resin, it is cured by heating. In this case, theresin 208A is heated using heating instrument such as an oven after it is released from the pressing by thetool 209 or directly heated during the pressing step by thetool 209 using a heater installed in thetool 209. The resin is appropriately heated for curing at a temperature of about 70 to 300° C. though the temperature depends on the material of theresin 208A. - The steps shown in FIGS. 11A and 11B are repeated as many times as the number of chip regions provided in the
semiconductor wafer 201, so that the joinedbody 210 as shown in FIG. 12(a) results. As shown, a plurality ofsecond semiconductor chips 204 are provided in the chip regions in thesemiconductor wafer 201. - As shown in FIG. 12B, similarly to the step shown in FIG. 5B according to the third embodiment, the back surface of the second semiconductor chip204 (the surface opposite to the second main surface) in the joined
body 210 is polished. More specifically, theresin 208A is sufficiently cured to form theresin layer 208. The joinedbody 210 is then placed on the polishingmachine 211 so that the back surfaces of thesecond semiconductor chips 204 in the chip regions in thesemiconductor wafer 201 are opposed to the upper surface (polishing surface) of the polishingmachine 211. There is aprotection resin 212 between thesecond semiconductor chips 204 placed in the chip regions in thesemiconductor wafer 201. - According to the fourth embodiment, the
protection resin 212 is a thermosetting liquid resin, and supplied between thesecond semiconductor chips 204 on the surface of thesemiconductor wafer 201 by spraying, centrifugal spin coating, attaching resin taping or the like. -
Abrasive grains 213 are supplied to the polishing surface of the polishingmachine 211, and then the polishingmachine 211 is rotated as the joinedbody 210 is loaded with weight, so that the back surfaces of thesecond semiconductor chips 204 are polished. At the time, in the joinedbody 210 removed from the polishingmachine 211, the thickness of thesecond semiconductor chip 204 on thesemiconductor wafer 201 decreases in inverse proportion to the duration of the polishing time. More specifically, the polishedsecond semiconductor chip 204 may have a thickness about in the range from 50 to 100 μm. Thesemiconductor wafer 201 has a thickness about in the range from 200 to 300 μm (which is substantially equal to the thickness of thesecond semiconductor chip 204 before polishing). The thickness of thesecond semiconductor chip 204 is at least smaller than that of the semiconductor wafer 201 (i.e., the thickness of thefirst semiconductor chip 201 a). Note that theabrasive grains 213 are preferably diamond grains having a grain size in the range from #1200 to #2000, and the polishingmachine 211 is preferably rotated at about 5 to 50 rpm. - As shown in FIG. 13A, similarly to the step shown in FIG. 6A according to the third embodiment, the
semiconductor wafer 201 is separated by dicing. More specifically, the chip regions in thesemiconductor wafer 201 in the joinedbody 210 are separated as a plurality of discretefirst semiconductor chips 201 a by dicing. Thus, a plurality of chip-layeredbodies 214 each including onefirst semiconductor chip 201 a and onesecond semiconductor chip 204 joined with each other result. For the ease of illustration, only a single chip-layeredbody 214 will be described. - As shown in FIG. 13B, the chip-layered
body 214 is subjected to die-bonding and wire-bonding. More specifically, alead frame 215 having adie pad portion 215 a andlead portions 215 b is prepared, and the back surface of thefirst semiconductor chip 201 a (the surface opposite to the first main surface) of the chip-layeredbody 214 is secured on thedie pad portion 215 a withconductive paste 216 containing Pd, Ag or the like. Then, thebonding pads 203 on thefirst semiconductor chip 201 a and thelead portions 215 b are electrically connected through thinmetal bonding wires 217. Here, the thin metal wire has a diameter of about 25 μm. The material of the thin metal wire can be Au, Al or the like. - According to the fourth embodiment, as shown in FIG. 13B, the back surface of the
second semiconductor chip 204 is polished so that the distance Tchip from the first main surface of thefirst semiconductor chip 201 a to the back surface of the second semiconductor chip 204 (the surface opposite to the second main surface) is smaller than the distance Twb from the first main surface of thefirst semiconductor chip 201 a to the highest position of thebonding wire 217 on the first main surface (the peak of the loop of the bonding wire 217). More specifically, the distance Tchip is about 100 to 150 μm and Twb is about 150 to 400 μm though they vary depending on the kind of the semiconductor device. - Then, as shown in FIG. 14, similarly to the step shown in FIG. 7 according to the third embodiment, the chip-layered
body 214 after the wire-bonding step is encapsulated in a resin. More specifically, thefirst semiconductor chip 201 a, thesecond semiconductor chip 204, thedie pad portion 215 a and thelead portions 215 b of thelead frame 215, and thebonding wires 217 are encapsulated in aresin package 218 of an epoxy-based resin, a polyimide-based resin or the like. Note however that the bottom surface of thedie pad portion 215 a and the bottom and outer side surfaces of thelead portions 215 b are exposed out of theresin package 218. Thus, the bottom and outer side surfaces of thelead portions 215 b can serve as external terminals. - As in the foregoing, according to the fourth embodiment, the plurality of
first semiconductor chips 201 a in thesemiconductor wafer 201 and a plurality of discretesecond semiconductor chips 204 are integrated to face to one another. Then, thesemiconductor chips 204 are polished from the opposite side of their main surfaces (circuit forming surfaces). Therefore, thesecond semiconductor chips 204 have a thickness smaller than that of thesemiconductor wafer 201, i.e., the thickness of thefirst semiconductor chips 201 a. Thesemiconductor wafer 201 is then separated into a plurality ofdiscrete semiconductor chips 201 a, so that a plurality of chip-layeredbodies 214 each including a discretefirst semiconductor chip 201 a and a discretesecond semiconductor chip 204 joined with one another result. As a result, the chip-layeredbody 214 may have a reduced thickness so that the package structure including the chip-layeredbody 214 encapsulated in theresin package 218 can be thinner. As a result, the semiconductor device may have a reduced size and improved heat radiation property. Thus, the plurality of chip-layeredbodies 214, in other words the plurality of semiconductor devices having a reduced size and improved heat radiation property can readily be manufactured simply by separating thesemiconductor wafer 201 into the plurality of discretefirst semiconductor chips 201 a. - According to the fourth embodiment, the back surface of the
second semiconductor chip 204 is polished so that the distance from the first main surface of thefirst semiconductor chip 201 a to the back surface of thesecond semiconductor chip 204 is smaller than the distance from the first main surface of thefirst semiconductor chip 201 a to the peak of the loop of thebonding wire 217. As a result, if the chip-layeredbody 214 is placed on thelead frame 215 in the semiconductor device, the device can surely have a reduced size and improved heat radiation property. - Note that according to the fourth embodiment, after the step of polishing the
second semiconductor chip 204 from the back surface (see FIG. 12B), thesecond semiconductor chips 204 preferably have a thickness equal to or less than ½ of the thickness of the semiconductor wafer 201 (i.e., thefirst semiconductor chips 201 a). In this way, the package structure including the chip-layeredbody 214 encapsulated in theresin package 218 can be made thinner. Therefore, the semiconductor device can have a more reduced size and more improved heat radiation property. - Also according to the fourth embodiment, the Sn—Pb alloy is used for the material of the metal bumps207, while any one of Au, In, Cu, Ni, an In—Sn alloy, a Sn—Ag alloy, a Sn—Cu alloy, a Sn—Zn alloy and the like can be used. For the material used for electrical connection between the
first electrodes 202 and thesecond electrodes 205, a resin having a metallic filler dispersed therein may be used instead of the metal bumps 207. - According to the fourth embodiment, the metal bumps207 are formed on the
second electrodes 205 on thesecond semiconductor chip 204, while the metal bumps 207 may be formed on thefirst electrodes 202 provided in the chip regions in thesemiconductor wafer 201. - According to the fourth embodiment, the
resin 208A is the epoxy resin, while an acrylic resin, a polyimide resin, a urethane resin or the like may be used. Theresin 208A may be any of thermosetting resin, autopolymer resin, photosetting resin and the like. Theresin 208A may preferably be applied by any suitable method among dispensing, printing, and stamping methods and the like in consideration of the chip size and other conditions. - According to the fourth embodiment, the
resin 208A is applied on the surface of the chip region in the semiconductor wafer 201 (i.e., the first main surface of thefirst semiconductor chip 201 a), while theresin 208A may be applied on the second main surface of thesecond semiconductor chip 204. - According to the fourth embodiment, the
resin 208A is applied before joining the first andsecond electrodes resin 208A may be applied in a different timing such as after joining the first andsecond electrodes - According to the fourth embodiment, the
resin 208A orresin layer 208 is interposed between the surface of each chip region in the semiconductor wafer 201 (i.e., the first main surface of each of thefirst semiconductor chips 201 a) and the second main surface of each of the second semiconductor chips 204. Meanwhile, an anisotropic conductive sheet, an anisotropic conductive resin or the like may be interposed therebetween. - [Modification of Fourth Embodiment]
- A method of manufacturing a semiconductor device according to a modification of the fourth embodiment of the present invention will be now described.
- FIGS. 15A, 15B,16A, 16B and 17 are sectional views showing steps in the method of manufacturing a semiconductor device according to the modification of the fourth embodiment. The same elements as those in the fourth embodiment shown in FIGS. 11A, 11B, 12A, 12B, 13A, 13B and 14 will be denoted by the same reference characters and will not be detailed in some cases.
- Unlike the fourth embodiment, according to the modification of the fourth embodiment, discrete
first semiconductor chips 201 a formed by dicing a semiconductor wafer are prepared, and then the first andsecond semiconductor chips - As shown in FIG. 15A, similarly to the step shown in FIG. 8A according to the modification of the third embodiment, the
first semiconductor chip 201 a and thesecond semiconductor chip 204 having a smaller area than thefirst semiconductor chip 201 a are registered. Note that on the first main surface of thefirst semiconductor chip 201 a, there are a plurality offirst electrodes 202 of Al, for example, (for connection with bumps) and a plurality ofbonding pads 203 of Al, for example (for connection with thin metal wires). Meanwhile, there are a plurality ofsecond electrodes 205 of Al, for example, on the second main surface of thesecond semiconductor chip 204. There is abarrier metal layer 206 of a thin metal film such as titanium, copper and nickel films is formed on each of thesecond electrodes 205. - More specifically, as shown in FIG. 15A, metal bumps207 of a Sn—Pb alloy, for example, are formed on the
second electrodes 205 on thesecond semiconductor chip 204 through the barrier metal layers 206. The metal bumps 207 have, for example, a diameter about in the range from 3 to 100 μm and a height about in the range from 3 to 50 μm. Thefirst semiconductor chip 201 a is placed on a packaging jig (not shown) and aresin 208A such as an epoxy resin is applied on the first main surface of thefirst semiconductor chip 201 a. Then, thesecond semiconductor chip 204 is held over thefirst semiconductor chip 201 a using atool 209 so that their main surfaces i.e., the circuit forming surfaces are opposed to one another. - As shown in FIG. 15B, similarly to the step shown in FIG. 8B according to the modification of the third embodiment, the first and
second semiconductor chips second semiconductor chip 204 is lowered as it is held by thetool 209. Then, the metal bumps 207 formed on thesecond electrodes 205 on thesecond semiconductor chip 204 and thefirst electrodes 202 on thefirst semiconductor chip 201 a are registered. Here, thebonding pads 203 on thefirst semiconductor chip 201 a are provided outside the region of the first main surface of thefirst semiconductor chip 201 a opposed to the second main surface of thesecond semiconductor chip 204. Then, thesecond semiconductor chip 204 is heated and pressed using thetool 209 from the surface opposite to the second main surface. Thus, the registeredfirst electrodes 202 andmetal bumps 207 on thesecond semiconductor chip 204 are joined with one another. Theresin 208A applied on the first main surface of thefirst semiconductor chip 201 a enhances the adhesion between the first andsecond semiconductor chips tool 209 is suitably about 0.98 to 196 mN for eachmetal bump 207, while the load is set on the condition that thefirst electrodes 202 are not damaged. Alternatively, the load may be set on the condition that the characteristics of elements such as transistors and interconnections and the like formed under thefirst electrodes 202 are unaffected. Then, theresin 208A is cured to form aresin layer 208, so that thesecond semiconductor chip 204 and thefirst semiconductor chip 201 a are integrated. - As shown in FIG. 16A, similarly to the step shown in FIG. 9A according to the modification of the third embodiment, the back surface of the second semiconductor chip204 (the surface opposite to the second main surface) in the joined
body 210 having thesecond semiconductor chips 204 placed on thefirst semiconductor chip 201 a is polished. More specifically, theresin 208A is sufficiently cured to form theresin layer 208, and then the joinedbody 210 is placed on a polishingmachine 211 so that the back surface of thesecond semiconductor chip 204 is opposed to the upper surface (polishing surface) of the polishingmachine 211. The polishing surface of the polishingmachine 211 is supplied withabrasive grains 213, and then the polishingmachine 211 is rotated as the joinedbody 210 is pressed, so that the back surface of thesecond semiconductor chip 204 is polished. At the time, in the joinedbody 210 removed from the polishingmachine 211, the thickness of thesecond semiconductor chip 204 decreases in inverse proportion to the duration of the polishing time. More specifically, the polishedsecond semiconductor chip 204 can have a thickness about in the range from 50 to 100 μm. Thefirst semiconductor chip 201 a has a thickness of about 200 to 300 μm (which is substantially equal to the thickness of thesecond semiconductor chip 204 before the polishing step). Therefore, thesecond semiconductor chip 204 has a thickness at least smaller than the thickness of thefirst semiconductor chip 201 a. Note that theabrasive grains 213 may preferably be diamond grains having a grain size in the range from #1200 to #2000, and the polishingmachine 211 is preferably rotated at about 5 to 50 rpm. - As shown in FIGS. 16B and 17, the chip-layered
body 214 including thefirst semiconductor chip 201 a and thesecond semiconductor chip 204 having a polished back surface joined with one another is subjected to die-bonding and wire-bonding and resin encapsulation. More specifically, alead frame 215 having adie pad portion 215 a andlead portions 215 b is prepared. The back surface of thefirst semiconductor chip 201 a of the chip-layered body 214 (the surface opposite to the first main surface) is secured on thedie pad portion 215 a, for example, withconductive paste 216 containing Pd, Ag or the like. Then, thebonding pads 203 on thefirst semiconductor chip 201 a and thelead portions 215 b are electrically connected through thinmetal bonding wires 217. Here, the thin metal wire has a diameter of about 25 μm. The material of the thin metal wire may be Au, Al or the like. - According to the modification of the fourth embodiment, as shown in FIG. 17, the back surface of the
second semiconductor chip 204 is polished so that the distance Tchip from the first main surface of thefirst semiconductor chip 201 a to the back surface of the second semiconductor chip 204 (the surface opposite to the second main surface) is smaller than the distance Twb from the first main surface of thefirst semiconductor chip 201 a to the highest position of the bonding wire 217 (i.e., the peak of the loop of the bonding wire 217) on the first main surface. More specifically, the distance Tchip is about in the range from 100 to 150 μm, and Twb is about in the range from 150 to 400 μm. - Finally, the
first semiconductor chip 201 a, thesecond semiconductor chip 204, thedie pad portion 215 a andlead portions 215 b of thelead frame 215, and thebonding wires 217 are encapsulated in aresin package 218 of, for example, an epoxy-based resin or a polyimide-based resin. However, the bottom surface of thedie pad portion 215 a, and the bottom and outer side surfaces of thelead portions 215 b are exposed out of theresin package 218, so that the bottom and outer side surfaces of thelead portions 215 b serve as external terminals. - As in the foregoing, according to the modification of the fourth embodiment, the first and
second semiconductor chips second semiconductor chip 204 is polished from the side opposite to the main surface (i.e., circuit forming surface), so that thesecond semiconductor chip 204 has a thickness smaller than the thickness of thefirst semiconductor chip 201 a. As a result, the layered body (chip-layered body 214) of the first andsecond semiconductor chips body 214 encapsulated in theresin package 218 can be made thinner, and the semiconductor device can have a reduced size and improved heat radiation property. - According to the modification of the fourth embodiment, the back surface of the
second semiconductor chip 204 is polished so that the distance from the first main surface of thefirst semiconductor chip 201 a to the back surface of thesecond semiconductor chip 204 is smaller than the distance from the first main surface of thefirst semiconductor chip 201 a to the peak of the loop of thebonding wire 217. Therefore, if the chip-layeredbody 214 is placed on thelead frame 215 in the semiconductor device, the device may surely have a reduced size and improved heat radiation property. - According to the modification of the fourth embodiment, after the step of polishing the
second semiconductor chip 204 from the back surface (see FIG. 16A), thesecond semiconductor chip 204 preferably has a thickness about ½ or less of the thickness of thefirst semiconductor chip 201 a. In this way, the package structure including the chip-layeredbody 214 encapsulated in theresin package 218 can be made thinner, so that the semiconductor device can have a more reduced size and higher heat radiation property. - According to the modification of the fourth embodiment, the Sn—Pb alloy is used for the material of the metal bumps207, while any one of Au, In, Cu, Ni, an In—Sn alloy, a Sn—Ag alloy, a Sn—Cu alloy and a Sn—Zn alloy may be used. The material used for electrical connection between the first and
second electrodes - According to the modification of the fourth embodiment, the metal bumps207 are formed on the
second electrodes 205 on thesecond semiconductor chip 204, while the metal bumps 207 may be formed on thefirst electrodes 202 on thefirst semiconductor chip 201 a. - According to the modification of the fourth embodiment, the
resin 208A is the epoxy resin, while an acrylic resin, a polyimide resin, a urethane resin or the like can be used. Theresin 208A may be any of thermosetting, autopolymer, photosetting resin and the like. Theresin 208A may preferably be applied by any of dispensing, printing and stamping methods and the like in consideration of the chip size and other conditions. - According to the modification of the fourth embodiment, the
resin 208A is applied on the first main surface of thefirst semiconductor chip 201 a, while theresin 208A may be applied on the second main surface of thesemiconductor chip 204. - According to the modification of the fourth embodiment, the
resin 208A is applied before joining the first andsecond electrodes resin 208A may be applied in a different timing such as after joining these electrodes through the metal bumps 207. - According to the modification of the fourth embodiment, the
resin 208A orresin layer 208 is interposed between the first main surface of thefirst semiconductor chip 201 a and the second main surface of thesecond semiconductor chip 204, while an anisotropic conductive sheet, anisotropic conductive resin or the like may be interposed.
Claims (16)
Priority Applications (1)
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US10/621,305 US6815255B2 (en) | 2001-08-08 | 2003-07-18 | Semiconductor device and manufacturing method thereof |
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-
2002
- 2002-02-05 US US10/062,535 patent/US20030032216A1/en not_active Abandoned
- 2002-02-22 TW TW091103181A patent/TW541680B/en not_active IP Right Cessation
- 2002-06-07 KR KR1020020031799A patent/KR100559652B1/en not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
TW541680B (en) | 2003-07-11 |
KR100559652B1 (en) | 2006-03-10 |
KR20030014342A (en) | 2003-02-17 |
US6815255B2 (en) | 2004-11-09 |
JP3649169B2 (en) | 2005-05-18 |
JP2003060154A (en) | 2003-02-28 |
US20040029314A1 (en) | 2004-02-12 |
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