US20040004270A1 - Germanium implanted HBT bipolar - Google Patents
Germanium implanted HBT bipolar Download PDFInfo
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- US20040004270A1 US20040004270A1 US10/615,084 US61508403A US2004004270A1 US 20040004270 A1 US20040004270 A1 US 20040004270A1 US 61508403 A US61508403 A US 61508403A US 2004004270 A1 US2004004270 A1 US 2004004270A1
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 17
- 229910052732 germanium Inorganic materials 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229910000927 Ge alloy Inorganic materials 0.000 claims abstract description 3
- 229910000676 Si alloy Inorganic materials 0.000 claims abstract description 3
- 229910045601 alloy Inorganic materials 0.000 claims abstract 24
- 239000000956 alloy Substances 0.000 claims abstract 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 94
- 238000000034 method Methods 0.000 claims description 54
- 239000000377 silicon dioxide Substances 0.000 claims description 47
- 235000012239 silicon dioxide Nutrition 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 19
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000007669 thermal treatment Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 27
- 239000011241 protective layer Substances 0.000 claims 6
- 229910005926 GexSi1-x Inorganic materials 0.000 description 42
- 238000004519 manufacturing process Methods 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000004630 atomic force microscopy Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 238000004151 rapid thermal annealing Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 4
- 230000003746 surface roughness Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000001000 micrograph Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
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- 238000005215 recombination Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
Definitions
- This invention relates generally to a process for fabricating a vertical structure high carrier mobility transistor on a crystalline silicon substrate, having a collector region located at a lower portion of the substrate.
- the invention relates, particularly but not exclusively, to a process for fabricating a heterostructure bipolar transistor (HBT) for very high frequency applications, and the description to follow is given with reference to this applicational field for convenience of illustration.
- HBT heterostructure bipolar transistor
- this technology has been applied to bipolar transistor devices, to thereby improve both the injection efficiency of the charge carriers and the passage frequency (f t ) value, the latter being closely related to the cut-off frequency (f T ) of the device.
- Heterostructures can be prepared by different methods, of which the MBE (Molecular Beam Epitaxy) method is the best known and provides a structure free of lattice imperfections; other, more expensive methods are sophisticated versions of CVD which, however, have a disadvantage in that their throughput adds to the cost of the silicon die.
- MBE Molecular Beam Epitaxy
- a bipolar transistor implemented with a vertical structure including a Ge x Si 1-x heterostructure between the base and collector regions will now be described in relation to such a field of application.
- the HBT bipolar transistor under consideration is illustrated schematically by the enlarged cross-sectional view of FIG. 1.
- This HBT transistor has a vertical structure of the NPN type and is formed on a crystalline semiconductor substrate 1 wherein, by successive implantations, a collector region 2 of the N type, a base region 3 of the P type, and an emitter region 4 of the N type have been defined, from the substrate bottom up.
- the collector region 2 includes a heavily N-doped layer 5 effective to provide a good ohmic contact with a collector metal (not shown because conventional) provided in a lower portion of the substrate 1 .
- An added feature of the HBT transistor shown in FIG. 1 is an opening provided above the substrate 1 to isolate the base region 3 and later allow formation of a contact region 9 above the emitter region 4 .
- This contact region 9 comprises a heavily N-doped layer 7 overlaid by a metal layer 8 .
- This Ge x Si 1-x heterostructure is characterized by the x and 1 -x concentrations, respectively associated with the germanium and silicon atoms, varying with the spatial implant depth in the substrate 1 .
- the energy band curve of the bipolar transistor HBT is plotted as a full line for comparison with the band curve of a standard bipolar transistor (BJT), plotted as a broken line.
- a comparison of the two band curves of the transistors HBT and BJT shows that the bipolar transistor HBT has an energy level in the conduction band which is always below that of the standard transistor BJT, through the base region to the interface with the collector region.
- An active zone bias of the bipolar transistor HBT conforming with the above band curve allows of faster injection of the carriers from the emitter region, thereby greatly reducing their passage time.
- the Ge x Si 1-x heterostructure provided between the base and collector regions enables the P-doping of the base region to be increased, thereby lowering the value of the intrinsic resistance R bb in the base region that restricts the applications of bipolar transistors at high frequencies.
- FIGS. 3 a - 3 f A previously mentioned method of conventionally forming the HBT transistor with a Ge x Si 1-x heterostructure will now be described with reference, in particular, to FIGS. 3 a - 3 f .
- the same reference numerals used for similar elements in FIG. 1 have been retained for convenience.
- FIG. 3 a shows a crystalline silicon substrate 1 which has been doped with impurities of the N type and formed with a window 10 by selective deposition of a protective material 11 .
- This protective material comprises a material layer, including impurities of the P type, which is deposited over the substrate and insulated by a dielectric capping.
- a first implantation of germanium (Ge) is carried out through this window 10 , and is followed by a second implantation of acceptor impurities, such as boron (B) atoms or BF 2 + ions.
- acceptor impurities such as boron (B) atoms or BF 2 + ions.
- a step of re-construction of the crystal lattice of the substrate 1 is carried out by an RTA (Rapid Thermal Annealing) process, or a conventional thermal process in an oven, which is also applied to aid in driving the implanted ions into sites freed in the crystal lattice.
- RTA Rapid Thermal Annealing
- FIG. 3 b The outcome of this re-construction step is shown in FIG. 3 b , where a planar base region 3 , extending at the window 10 to a sufficient depth to allow of the subsequent creation of an emitter region, is highlighted for the first time.
- a collector region 2 is defined which is incorporated to the remaining portion, not implanted with P-type impurities, of the substrate 1 .
- the base region extending as far as the interface to the collector region 2 , will presently feature a Ge x Si 1-x heterostructure formed during the first implanting step and characterized by an energy band curve of the kind shown in FIG. 2.
- a second dielectric layer 14 typically of silicon nitride (Si 3 N 4 ), onto the first thin dielectric layer 12 ;
- the process for fabricating the HBT transistor comprises a first chemio-physical etching (RIE) step and a second etching step, respectively of the polysilicon layer 15 and the second dielectric layer 14 , to partially form isolation spacers at the edges of the window 10 , as shown in FIG. 3 d.
- RIE chemio-physical etching
- the HBT transistor with Ge x Si 1-x heterostructure can now be completed by conventional processes for the formation of an emitter region 4 accommodated within the base region 3 and overlaid by a corresponding emitter contact 9 .
- FIG. 3 f is a general view of the HBT transistor with Ge x Si 1-x heterostructure being provided with an emitter contact 9 which comprises a first polysilicon layer 7 heavily doped with impurities of the N type and metallized on top by a layer 8 .
- the HBT transistors (T 1 , T 2 ) in question have values (At1, At2) of their emitter surface areas of 2 ⁇ 7.4 ⁇ m 2 and 0.4 ⁇ 7.4 ⁇ m 2 , respectively, resulting in a ratio (At1/At2) of five between their emitter areas and a ratio (pt1/pt2) of 1.2 between the outer perimeters of their emitter regions.
- An embodiment of this invention is directed to a transistor with Ge x Si 1-x heterostructure, which can overcome the limitations described hereinabove so as to further improve its frequency performance.
- the inventors of this invention recognized that the cause for HBT transistors deviating from the ideal is because of surface re-combination phenomena, rather than recombination phenomena reputedly occurring within the Ge x Si 1-x heterostructure.
- Such surface re-combination phenomena have been found to occur in the neighborhood of the interface between the crystalline semiconductor substrate, incorporating a HBT transistor, and a thin layer of silicon dioxide (SiO 2 ) grown to aid in the formation of the spacers near an emitter region.
- SiO 2 silicon dioxide
- the transistor is formed by a process that includes the steps of: defining a window in the semiconductor substrate; providing a first implantation of germanium atoms through said window; providing a second implantation of acceptor dopants through said window to define a base region; applying an RTA (Rapid Thermal Annealing) treatment to re-construct the crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy; forming a dielectric layer by chemical vapor deposition; forming spacers at window edges; forming an emitter region in the substrate through the window; and forming an emitter contact region.
- RTA Rapid Thermal Annealing
- FIG. 1 is an enlarged cross-sectional view of a semiconductor substrate which integrates a high-mobility NPN transistor with a vertical structure including a Ge x Si 1-x heterostructure, according to the prior art.
- FIG. 2 is an energy band plot typical of a high-mobility NPN transistor
- FIGS. 3 a - 3 f illustrate conventional process steps yielding the high-mobility NPN transistor shown schematically in FIG. 1.
- FIG. 4 is a voltage vs. current plot illustrating the behavior of the base and collector currents for two high-mobility NPN transistors T 1 and T 2 with a Ge x Si 1-x heterostructure having a ratio At1/At2 of 5 of their respective emitter areas.
- FIG. 5 is an enlarged cross-sectional view of a semiconductor body of crystalline silicon as implanted to provide a Ge x Si 1-x heterostructure, which has been subjected to an oxidation step for growing a silicon dioxide layer thereon.
- FIG. 6 is a photograph taken by Atomic Force Microscopy (AFM), which shows an SiO 2 /Ge x Si 1-x interface of a conventionally made transistor.
- AFM Atomic Force Microscopy
- FIG. 7 is a plot illustrating the dependence of surface roughness at an SiO 2 /Ge x Si 1-x interface on the amount of germanium segregated in the interface itself.
- FIG. 8 illustrates a similar situation to that of FIG. 7, but relating to a practical instance of a high carrier mobility transistor also having an SiO 2 /Ge x Si 1-x interface.
- FIGS. 9 a - 9 f illustrate the process steps according to this invention that yield a high-mobility NPN transistor similar to that shown schematically in FIG. 1.
- FIG. 10 shows an atomic force microphotograph of the SiO 2 /Ge x Si 1-x interface of an HBT transistor of the present invention.
- FIG. 11 is a plot showing the behavior of the collector and base currents versus the base-emitter bias voltage, for profiles of acceptor impurities in substrates integrating two different types of HBT transistors.
- FIG. 12 is a plot of the collector current versus the collector-emitter bias voltage, for two different types of HBT transistors.
- FIG. 13 is a plot of the concentration
- FIG. 10 is a photograph taken by Atomic Force Microscopy (AFM), which shows an SiO 2 /Ge x Si 1-x interface obtained with the fabrication process of this invention.
- AFM Atomic Force Microscopy
- FIG. 14 is a plot of the cut-off frequency versus the collector bias current for two different types of HBT transistors.
- the inventors of the present invention have spotted the main cause of performance deviations from an ideal device which limit, for example, the performance of a high-mobility HBT transistor, in the surface re-combination phenomena that appear at the silicon dioxide-to-germanium/silicon heterostructure, SiO 2 /Ge x Si 1-x .
- This layer 33 is trapped from beneath by the Ge x Si 1-x heterostructure, and from above, by the silicon dioxide layer 32 .
- the silicon dioxide layer 32 develops a surface roughness, due to the underlying germanium layer 33 , which is responsible for the surface re-combination phenomena occurring at the SiO 2 /Ge x Si 1-x interface.
- This surface roughness is brought out by the atomic force microphotograph of FIG. 6, showing the surface of the silicon dioxide layer 32 after the thermal growth process.
- FIG. 7 is a plot showing the linearly increasing dependence of the amount of segregated germanium in the layer 33 on the surface roughness (Rms) of the layer 32 .
- HBT high carrier mobility bipolar transistor
- FIG. 8 is a cross-section through the high-mobility transistor of FIG. 1, with enlarged detail views of the emitter 4 and base 3 regions.
- FIG. 9 a shows a substrate 1 of crystalline silicon (Si), lightly doped with impurities of the N type and having a bottom region 5 which is heavily doped with impurities of the N type. This bottom region 5 corresponds to the ohmic region of a collector contact (not shown here).
- a window 10 is formed above the substrate 1 by selective deposition of a protective material 11 over the substrate 1 .
- This protective material 11 comprises a first layer in direct contact with the substrate 1 wherein acceptor impurities are embedded and which is capped by a dielectric material.
- a first step of implanting germanium (Ge) is carried out through this window 10 , followed by a second step of implanting acceptor impurities, such as boron (B) atoms or BF2+ ions.
- acceptor impurities such as boron (B) atoms or BF2+ ions.
- the crystal lattice of the substrate 1 is re-constructed by an RTA (Rapid Thermal Annealing) process or a conventional treatment in an oven, also is intended to aid in the insertion of the implanted atoms into sites left free in the crystal lattice.
- RTA Rapid Thermal Annealing
- FIG. 9 b The outcome of the last-mentioned step is shown in FIG. 9 b , where a planar base region 3 , extending at the window 10 to a sufficient depth in the substrate 1 to allow of the subsequent creation of an emitter region, is highlighted for the first time.
- a collector region 2 is defined which is included in the remaining portion, not implanted with acceptor impurities, of the substrate 1 and, accordingly, also contains the collector ohmic contact region 5 .
- the base region extending as far as the interface to the collector region 2 , will presently exhibit an energy band curve of the kind shown in FIG. 2 as a result of a Ge x Si 1-x heterostructure having been formed during the first implanting step.
- a first thin dielectric layer 12 ′ of silicon dioxide (SiO 2 ) will be formed over the substrate 1 by chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- this thin dielectric layer 12 ′ of silicon dioxide is formed by a CVD process, not by a thermal growth process.
- the process for fabricating a HBT transistor according to the an embodiment of the invention is carried on through conventional steps including the deposition of a second dielectric layer 14 on top of said first thin dielectric layer 12 ′, followed by the deposition of a polysilicon layer 15 .
- the second dielectric layer comprises silicon nitride (Si 3 N 4 ) to ensure proper adhesion on the underlying dielectric layer 12 ′.
- a first chemio-physical etching (RIE) step will be carried out on the polysilicon layer 15 , and a second etching step on the second dielectric layer 14 , to obtain the partial formation of isolation spacers at the edges of the window 10 , as shown schematically in FIG. 9 d.
- RIE chemio-physical etching
- a third, wet etching step carried out on the remaining portions of the polysilicon layer 15 and a fourth etching step carried out on just the first thin dielectric layer 12 ′ will complete the formation of the spacers 50 , thereby exposing the base region 3 again, as shown in FIG. 9 e.
- the HBT transistor formed according to the teachings of this invention can then be completed with conventional processes to form an emitter region 4 within the base region 2 .
- the emitter region 4 will be overlaid with a corresponding top emitter contact 9 , optimized to enhance the injection efficiency of the HBT transistor.
- FIG. 9 f is a comprehensive view showing the HBT transistor with a Ge x Si 1-x heterojunction and the emitter contact 9 comprising a first polysilicon layer 7 , heavily doped with impurities of the N type and capped by a metal layer 8 .
- a second alternative embodiment of the inventive process for fabricating HBT transistors will now be described and comprises processing steps which are identical with those described above up to the moment of forming the first thin dielectric layer 12 ′ of silicon dioxide.
- the first thin dielectric layer of silicon dioxide is replaced by a thick dielectric layer of silicon dioxide (SiO 2 ) also deposited by chemical vapor deposition (CVD).
- the thick dielectric layer of silicon dioxide could also be deposited by an APCVD process, followed by an optional thermal process.
- the steps of the second alternative embodiment of the fabrication process include: depositing a layer 15 of polysilicon; etching inside the window region; and forming an emitter region overlaid by an electric contact, similar to the first embodiment described.
- the first thin dielectric layer 12 ′ is formed by depositing a sacrificial silicon (Si) layer and then subjecting it to thermal oxidation. This sacrificial layer is deposited inside the window region 10 in direct contact with the Ge x Si 1-x heterostructure included in the substrate 1 .
- the process steps described for forming the first thin dielectric layer 12 ′ by a sacrificial layer will yield the same results, in terms of quality of the SiO 2 /Ge x Si 1-x interface, as were obtained previously by forming the layer 12 ′ with a chemical vapor deposition (CVD) process.
- CVD chemical vapor deposition
- the sacrificial layer deposited inhibits the formation of the occluded germanium layer between the heterostructure and the first thin dielectric layer 12 ′ because it prevents the oxidation process from reaching the Ge x Si 1-x heterostructure.
- the third alternative embodiment of the process may also have the step of forming the thin dielectric layer 12 ′ followed by a suitable thermal treatment.
- the steps of the third alternative embodiment of the HBT transistor fabrication process will then include: depositing a second dielectric layer 14 ; depositing a layer 15 of polysilicon; etching inside the window region; and forming an emitter region overlaid by an electric contact, similar to the first embodiment described.
- the second dielectric layer may comprise silicon nitride (Si 3 N 4 ).
- a fourth alternative embodiment of the HBT transistor fabrication process includes processing steps identical with those previously described in relation to the third alternative embodiment up to the moment when the first thin dielectric layer 12 ′ is formed.
- the first dielectric layer of silicon dioxide is further grown thermally to provide a dielectric layer of increased thickness embedding, or replacing, the second dielectric layer 14 .
- the fourth alternative embodiment of the HBT transistor fabrication process may also have the oxidation step followed by a suitable thermal treatment.
- next steps of the fourth alternative embodiment of the fabrication process will include: depositing a layer 15 of polysilicon; etching inside the window region; and forming an emitter region overlaid by an electric contact, similar to the second embodiment described.
- collector bias currents in the milliampere range allow HBT transistors fabricated with the invention process to attain cut-off frequencies in the 20 GHz range, that is hitherto unattainable values.
- the fabrication process of this invention allows the frequency field of application of HBT transistors to be further extended, while eliminating deviations of the base current from the ideal.
Abstract
A vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate. The transistor includes a heterostructure alloy region positioned in the substrate and comprised of a heterostructure alloy of silicon and germanium. A base region is positioned in the substrate above the first conducting region and doped with P-type impurities. A first dielectric layer is positioned on, and directly contacts, the heterostructure alloy region, and defines a first window directly above the heterostructure alloy region. The transistor also includes an emitter positioned in the heterostructure alloy region and between the first window and the base region. The emitter is comprised of the heterostructure alloy doped with impurities of the first type and directly contacts the first dielectric layer.
Description
- This application is a divisional of U.S. patent application Ser. No. 09/724,563, filed Nov. 27, 2000, now pending, which is a continuation of U.S. patent application Ser. No. 09/087,398, filed on Mar. 29, 1998, which applications are incorporated herein by reference in their entireties.
- 1. Field of the Invention
- This invention relates generally to a process for fabricating a vertical structure high carrier mobility transistor on a crystalline silicon substrate, having a collector region located at a lower portion of the substrate.
- The invention relates, particularly but not exclusively, to a process for fabricating a heterostructure bipolar transistor (HBT) for very high frequency applications, and the description to follow is given with reference to this applicational field for convenience of illustration.
- 2. Description of the Related Art
- As skilled persons in the art know well, the application of heterostructures to solid state electronic devices has prompted a vast increase of their working range at very high frequencies.
- In particular, this technology has been applied to bipolar transistor devices, to thereby improve both the injection efficiency of the charge carriers and the passage frequency (ft) value, the latter being closely related to the cut-off frequency (fT) of the device.
- Heterostructures can be prepared by different methods, of which the MBE (Molecular Beam Epitaxy) method is the best known and provides a structure free of lattice imperfections; other, more expensive methods are sophisticated versions of CVD which, however, have a disadvantage in that their throughput adds to the cost of the silicon die.
- Yet this MBE method has only sparsely been applied to large volume industrial processes, on account of it involving lengthy processing steps that command strict control of their physical parameters.
- Thus, it has often been more convenient to adopt other methods, such as ion implantation, which could yield similar heterostructures of a fair quality within acceptable times for large volume production lines.
- A bipolar transistor implemented with a vertical structure including a GexSi1-x heterostructure between the base and collector regions will now be described in relation to such a field of application.
- The HBT bipolar transistor under consideration is illustrated schematically by the enlarged cross-sectional view of FIG. 1.
- This HBT transistor has a vertical structure of the NPN type and is formed on a
crystalline semiconductor substrate 1 wherein, by successive implantations, acollector region 2 of the N type, abase region 3 of the P type, and an emitter region 4 of the N type have been defined, from the substrate bottom up. - Specifically, it can be seen that the
collector region 2 includes a heavily N-dopedlayer 5 effective to provide a good ohmic contact with a collector metal (not shown because conventional) provided in a lower portion of thesubstrate 1. - An added feature of the HBT transistor shown in FIG. 1 is an opening provided above the
substrate 1 to isolate thebase region 3 and later allow formation of acontact region 9 above the emitter region 4. - This
contact region 9 comprises a heavily N-dopedlayer 7 overlaid by ametal layer 8. - Having briefly described the HBT transistor, the GexSi1-x heterostructure formed within the
crystalline silicon substrate 1 will now be examined to see what changes are introduced in the energy band curve of the HBT transistor. - This GexSi1-x heterostructure is characterized by the x and 1-x concentrations, respectively associated with the germanium and silicon atoms, varying with the spatial implant depth in the
substrate 1. - In FIG. 2, the energy band curve of the bipolar transistor HBT is plotted as a full line for comparison with the band curve of a standard bipolar transistor (BJT), plotted as a broken line.
- A comparison of the two band curves of the transistors HBT and BJT shows that the bipolar transistor HBT has an energy level in the conduction band which is always below that of the standard transistor BJT, through the base region to the interface with the collector region.
- In particular, it can be seen that for the transistor HBT, when moving from its base region toward its collector region, there occurs a gradual slow decrease of its energy gap (Eg) which can be regarded as an effect of spatial modulation of the energy gap. This modulation is obtained by suitable implantation profiles of the germanium (Ge) atomic species whose concentration is maximal at the collector-base interface and minimal or almost nil at the emitter-base interface.
- An active zone bias of the bipolar transistor HBT conforming with the above band curve allows of faster injection of the carriers from the emitter region, thereby greatly reducing their passage time.
- The net result is a markedly increased cut-off frequency (fT) of the HBT transistor and a decreased proportion of carriers trapped within the base.
- Thus, for HBT transistors biased with collector currents in the milliampere range, high cut-off frequency values can be obtained which would not be achievable by conventional bipolar technology.
- The GexSi1-x heterostructure provided between the base and collector regions enables the P-doping of the base region to be increased, thereby lowering the value of the intrinsic resistance Rbb in the base region that restricts the applications of bipolar transistors at high frequencies.
- A previously mentioned method of conventionally forming the HBT transistor with a GexSi1-x heterostructure will now be described with reference, in particular, to FIGS. 3a-3 f. The same reference numerals used for similar elements in FIG. 1 have been retained for convenience.
- FIG. 3a shows a
crystalline silicon substrate 1 which has been doped with impurities of the N type and formed with awindow 10 by selective deposition of aprotective material 11. This protective material comprises a material layer, including impurities of the P type, which is deposited over the substrate and insulated by a dielectric capping. - A first implantation of germanium (Ge) is carried out through this
window 10, and is followed by a second implantation of acceptor impurities, such as boron (B) atoms or BF2 + ions. - Thereafter, a step of re-construction of the crystal lattice of the
substrate 1 is carried out by an RTA (Rapid Thermal Annealing) process, or a conventional thermal process in an oven, which is also applied to aid in driving the implanted ions into sites freed in the crystal lattice. - The outcome of this re-construction step is shown in FIG. 3b, where a
planar base region 3, extending at thewindow 10 to a sufficient depth to allow of the subsequent creation of an emitter region, is highlighted for the first time. - Simultaneously with the formation of the
base region 3 in thesubstrate 1, acollector region 2 is defined which is incorporated to the remaining portion, not implanted with P-type impurities, of thesubstrate 1. - The base region, extending as far as the interface to the
collector region 2, will presently feature a GexSi1-x heterostructure formed during the first implanting step and characterized by an energy band curve of the kind shown in FIG. 2. - From now on, as shown in FIG. 3c, the processing over the
substrate 1, at the location of thewindow 10 and theprotective material 11, will see the following successive operations: - thermal growth of a first thin
dielectric layer 12 of silicon dioxide (SiO2); - deposition of a second
dielectric layer 14, typically of silicon nitride (Si3N4), onto the first thindielectric layer 12; - deposition of a
polysilicon layer 15. - To provide an emitter region at the location of the
window 10 in thesubstrate 1, the process for fabricating the HBT transistor comprises a first chemio-physical etching (RIE) step and a second etching step, respectively of thepolysilicon layer 15 and the seconddielectric layer 14, to partially form isolation spacers at the edges of thewindow 10, as shown in FIG. 3d. - A third wet etching step of the remaining portions of the
polysilicon layer 15, and a fourth etching step of the first thindielectric layer 12 only, bring to completion the formation of thespacers 50, thereby exposing thebase region 3 again, as shown in FIG. 3e. - The HBT transistor with GexSi1-x heterostructure can now be completed by conventional processes for the formation of an emitter region 4 accommodated within the
base region 3 and overlaid by acorresponding emitter contact 9. - FIG. 3f is a general view of the HBT transistor with GexSi1-x heterostructure being provided with an
emitter contact 9 which comprises afirst polysilicon layer 7 heavily doped with impurities of the N type and metallized on top by alayer 8. - The HBT transistors with GexSi1-x heterojunction fabricated with the above process have revealed upon testing a behavior of the base current which is less than ideal.
- This deviation from the ideal is brought out by the graph of FIG. 4, where the collector and base currents are plotted versus the voltage Vbe between the base and the emitter, for two different HBT transistors formed on a common substrate.
- The HBT transistors (T1, T2) in question have values (At1, At2) of their emitter surface areas of 2×7.4 μm2 and 0.4×7.4 μm2, respectively, resulting in a ratio (At1/At2) of five between their emitter areas and a ratio (pt1/pt2) of 1.2 between the outer perimeters of their emitter regions.
- On the graph, the curves relating to the transistor T1 are full lines, and those relating to the transistor T2 are broken lines.
- It can be seen from the graph that the base currents (those having flatter curves) of T1 and T2 differ little from each other, although the ratio (At1/At2) of their emitter areas is of five.
- This brings out the existence of a non-ideal component for the base current which is unaffected by changes in the emitter surface area. This deviation from the ideal, well recognized in the art, has been attributed heretofore to attempts of the GexSi1-x heterostructure, regarded as being responsible for re-combination phenomena within the semiconductor substrate, to relax.
- An embodiment of this invention is directed to a transistor with GexSi1-x heterostructure, which can overcome the limitations described hereinabove so as to further improve its frequency performance.
- The inventors of this invention recognized that the cause for HBT transistors deviating from the ideal is because of surface re-combination phenomena, rather than recombination phenomena reputedly occurring within the GexSi1-x heterostructure.
- Such surface re-combination phenomena have been found to occur in the neighborhood of the interface between the crystalline semiconductor substrate, incorporating a HBT transistor, and a thin layer of silicon dioxide (SiO2) grown to aid in the formation of the spacers near an emitter region.
- In one embodiment, the transistor is formed by a process that includes the steps of: defining a window in the semiconductor substrate; providing a first implantation of germanium atoms through said window; providing a second implantation of acceptor dopants through said window to define a base region; applying an RTA (Rapid Thermal Annealing) treatment to re-construct the crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy; forming a dielectric layer by chemical vapor deposition; forming spacers at window edges; forming an emitter region in the substrate through the window; and forming an emitter contact region.
- The features and advantages of the transistor according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
- FIG. 1 is an enlarged cross-sectional view of a semiconductor substrate which integrates a high-mobility NPN transistor with a vertical structure including a GexSi1-x heterostructure, according to the prior art.
- FIG. 2 is an energy band plot typical of a high-mobility NPN transistor;
- FIGS. 3a-3 f illustrate conventional process steps yielding the high-mobility NPN transistor shown schematically in FIG. 1.
- FIG. 4 is a voltage vs. current plot illustrating the behavior of the base and collector currents for two high-mobility NPN transistors T1 and T2 with a GexSi1-x heterostructure having a ratio At1/At2 of 5 of their respective emitter areas.
- FIG. 5 is an enlarged cross-sectional view of a semiconductor body of crystalline silicon as implanted to provide a GexSi1-x heterostructure, which has been subjected to an oxidation step for growing a silicon dioxide layer thereon.
- FIG. 6 is a photograph taken by Atomic Force Microscopy (AFM), which shows an SiO2/GexSi1-x interface of a conventionally made transistor.
- FIG. 7 is a plot illustrating the dependence of surface roughness at an SiO2/GexSi1-x interface on the amount of germanium segregated in the interface itself.
- FIG. 8 illustrates a similar situation to that of FIG. 7, but relating to a practical instance of a high carrier mobility transistor also having an SiO2/GexSi1-x interface.
- FIGS. 9a-9 f illustrate the process steps according to this invention that yield a high-mobility NPN transistor similar to that shown schematically in FIG. 1.
- FIG. 10 shows an atomic force microphotograph of the SiO2/GexSi1-x interface of an HBT transistor of the present invention.
- FIG. 11 is a plot showing the behavior of the collector and base currents versus the base-emitter bias voltage, for profiles of acceptor impurities in substrates integrating two different types of HBT transistors.
- FIG. 12 is a plot of the collector current versus the collector-emitter bias voltage, for two different types of HBT transistors.
- FIG. 13 is a plot of the concentration FIG. 10 is a photograph taken by Atomic Force Microscopy (AFM), which shows an SiO2/GexSi1-x interface obtained with the fabrication process of this invention.
- FIG. 14 is a plot of the cut-off frequency versus the collector bias current for two different types of HBT transistors.
- The inventors of the present invention have spotted the main cause of performance deviations from an ideal device which limit, for example, the performance of a high-mobility HBT transistor, in the surface re-combination phenomena that appear at the silicon dioxide-to-germanium/silicon heterostructure, SiO2/GexSi1-x.
- In order to provide experimental evidence of the above conclusion, the inventors have conducted a series of atomic force microscopy (AFM) analyses to photograph the situation at the SiO2/GexSi1-x interface and has gathered useful elements for evaluation.
- These analyses have shown a situation of the kind schematically illustrated in FIG. 5, wherein, on a
body 30 of crystalline silicon implanted to produce a GexSi1-x heterostructure, alayer 33 of pure germanium develops subsequently to a step of growing alayer 32 of silicon dioxide on thecrystalline body 30. - This
layer 33 is trapped from beneath by the GexSi1-x heterostructure, and from above, by thesilicon dioxide layer 32. This can be explained in theory by that the step of growing the silicon dioxide (SiO2) thermally, as carried out in direct contact with the GexSi1-x heterostructure, causes the silicon (Si) atoms present at its top surface to be depleted upward, thereby promoting the formation of thelayer 33 of pure germanium. - In so doing, the
silicon dioxide layer 32 develops a surface roughness, due to theunderlying germanium layer 33, which is responsible for the surface re-combination phenomena occurring at the SiO2/GexSi1-x interface. - This surface roughness is brought out by the atomic force microphotograph of FIG. 6, showing the surface of the
silicon dioxide layer 32 after the thermal growth process. - FIG. 7 is a plot showing the linearly increasing dependence of the amount of segregated germanium in the
layer 33 on the surface roughness (Rms) of thelayer 32. - A similar situation to the above, for an SiO2/GexSi1-xinterface, is encountered where a high carrier mobility bipolar transistor (HBT) having a vertical structure with a GexSi1-x heterostructure is fabricated by the process steps described under the Background of the Invention heading.
- FIG. 8 is a cross-section through the high-mobility transistor of FIG. 1, with enlarged detail views of the emitter4 and
base 3 regions. - This figure highlights that the base and emitter regions are in direct contact with the
isolation spacers 50 comprised of a firstthin dielectric layer 12 of silicon dioxide and asecond dielectric layer 14. - It is to be emphasized, therefore, that a GexSi1-x heterostructure is present within the
base region 3 whereover the firstthin dielectric layer 12 of silicon dioxide comprising bothisolation spacers 50 has been grown. - Accordingly, a narrow region of the SiO2/GexSi1-x interface has been marked with a heavy circle where the presence is displayed of a
layer 90 of segregated germanium resulting from the thermal oxidation process employed for growing the firstthin dielectric layer 12. - To overcome the drawbacks connected with the SiO2/GexSi1-x interface which limit the performance of conventional high-mobility transistors (HBT), a process for fabricating the transistor according to this invention is proposed herein below with reference to FIGS. 9a-9 f.
- For convenient comparison of the present inventive process with the process described under the Background of the Invention heading, the same reference numerals have been used to denote similar items with those shown in FIGS. 1 and 3a-3 f.
- FIG. 9a shows a
substrate 1 of crystalline silicon (Si), lightly doped with impurities of the N type and having abottom region 5 which is heavily doped with impurities of the N type. Thisbottom region 5 corresponds to the ohmic region of a collector contact (not shown here). - A
window 10 is formed above thesubstrate 1 by selective deposition of aprotective material 11 over thesubstrate 1. Thisprotective material 11 comprises a first layer in direct contact with thesubstrate 1 wherein acceptor impurities are embedded and which is capped by a dielectric material. - A first step of implanting germanium (Ge) is carried out through this
window 10, followed by a second step of implanting acceptor impurities, such as boron (B) atoms or BF2+ ions. - Thereafter, the crystal lattice of the
substrate 1 is re-constructed by an RTA (Rapid Thermal Annealing) process or a conventional treatment in an oven, also is intended to aid in the insertion of the implanted atoms into sites left free in the crystal lattice. - The outcome of the last-mentioned step is shown in FIG. 9b, where a
planar base region 3, extending at thewindow 10 to a sufficient depth in thesubstrate 1 to allow of the subsequent creation of an emitter region, is highlighted for the first time. - Simultaneously with the definition of the
base region 3 in thesubstrate 1, acollector region 2 is defined which is included in the remaining portion, not implanted with acceptor impurities, of thesubstrate 1 and, accordingly, also contains the collectorohmic contact region 5. - The base region, extending as far as the interface to the
collector region 2, will presently exhibit an energy band curve of the kind shown in FIG. 2 as a result of a GexSi1-x heterostructure having been formed during the first implanting step. - At this stage, as shown in FIG. 9c, at the location of the
window 10 and theprotective material 11, a firstthin dielectric layer 12′ of silicon dioxide (SiO2) will be formed over thesubstrate 1 by chemical vapor deposition (CVD). Other types of CVD, such as PECVD, APCVD, LPCVD, UV-assisted CVD, could also be used. - Unlike the prior art, this
thin dielectric layer 12′ of silicon dioxide is formed by a CVD process, not by a thermal growth process. - This provides an improved SiO2/GexSi1-x interface, as can be seen in FIG. 10 which shows an atomic force microphotograph of the SiO2/GexSi1-x interface thus obtained.
- It can be seen that the roughness of the SiO2/GexSi1-x interface shown in FIG. 10 is significantly less than that in FIG. 6 where the silicon dioxide was grown by thermal oxidation.
- Excellent results, as regards to the formation of the SiO2/GexSi1-x interface, were also obtained by depositing the first
thin dielectric layer 12′ of silicon dioxide by an atmospheric pressure chemical vapor deposition (APCVD) process. - To further enhance the quality of the interface, and thus reduce the faults originating local surface re-combination phenomena, it is contemplated that a thermal process should follow the deposition of the first
thin dielectric layer 12′. - The process for fabricating a HBT transistor according to the an embodiment of the invention is carried on through conventional steps including the deposition of a
second dielectric layer 14 on top of said firstthin dielectric layer 12′, followed by the deposition of apolysilicon layer 15. - In a first alternative embodiment, the second dielectric layer comprises silicon nitride (Si3N4) to ensure proper adhesion on the
underlying dielectric layer 12′. - Finally, to form an emitter region in the
substrate 1, at the location of thewindow 10, a first chemio-physical etching (RIE) step will be carried out on thepolysilicon layer 15, and a second etching step on thesecond dielectric layer 14, to obtain the partial formation of isolation spacers at the edges of thewindow 10, as shown schematically in FIG. 9d. - A third, wet etching step carried out on the remaining portions of the
polysilicon layer 15 and a fourth etching step carried out on just the firstthin dielectric layer 12′ will complete the formation of thespacers 50, thereby exposing thebase region 3 again, as shown in FIG. 9e. - The HBT transistor formed according to the teachings of this invention can then be completed with conventional processes to form an emitter region4 within the
base region 2. - Finally, the emitter region4 will be overlaid with a corresponding
top emitter contact 9, optimized to enhance the injection efficiency of the HBT transistor. - FIG. 9f is a comprehensive view showing the HBT transistor with a GexSi1-x heterojunction and the
emitter contact 9 comprising afirst polysilicon layer 7, heavily doped with impurities of the N type and capped by ametal layer 8. - A second alternative embodiment of the inventive process for fabricating HBT transistors will now be described and comprises processing steps which are identical with those described above up to the moment of forming the first
thin dielectric layer 12′ of silicon dioxide. - In this second alternative embodiment, the first thin dielectric layer of silicon dioxide is replaced by a thick dielectric layer of silicon dioxide (SiO2) also deposited by chemical vapor deposition (CVD).
- In this embodiment, the thick dielectric layer of silicon dioxide could also be deposited by an APCVD process, followed by an optional thermal process.
- The steps of the second alternative embodiment of the fabrication process include: depositing a
layer 15 of polysilicon; etching inside the window region; and forming an emitter region overlaid by an electric contact, similar to the first embodiment described. - Also within the principle of this invention, a third alternative embodiment of the HBT transistor fabrication process will now be disclosed which includes the same process steps as those previously described up to the moment of forming the first
thin dielectric layer 12′. - In this third alternative embodiment, the first
thin dielectric layer 12′ is formed by depositing a sacrificial silicon (Si) layer and then subjecting it to thermal oxidation. This sacrificial layer is deposited inside thewindow region 10 in direct contact with the GexSi1-x heterostructure included in thesubstrate 1. - Advantageously, the process steps described for forming the first
thin dielectric layer 12′ by a sacrificial layer will yield the same results, in terms of quality of the SiO2/GexSi1-x interface, as were obtained previously by forming thelayer 12′ with a chemical vapor deposition (CVD) process. - It has been found that the sacrificial layer deposited inhibits the formation of the occluded germanium layer between the heterostructure and the first
thin dielectric layer 12′ because it prevents the oxidation process from reaching the GexSi1-x heterostructure. - In order to further minimize the surface re-combination phenomena that occur at the SiO2/GexSi1-x interface, the third alternative embodiment of the process may also have the step of forming the
thin dielectric layer 12′ followed by a suitable thermal treatment. - The steps of the third alternative embodiment of the HBT transistor fabrication process will then include: depositing a
second dielectric layer 14; depositing alayer 15 of polysilicon; etching inside the window region; and forming an emitter region overlaid by an electric contact, similar to the first embodiment described. - To improve the adhesion of the
second dielectric layer 14 on the firstthin dielectric layer 12′, the second dielectric layer may comprise silicon nitride (Si3N4). - Again within the principle of this invention, a fourth alternative embodiment of the HBT transistor fabrication process is provided which includes processing steps identical with those previously described in relation to the third alternative embodiment up to the moment when the first
thin dielectric layer 12′ is formed. - In this embodiment, the first dielectric layer of silicon dioxide is further grown thermally to provide a dielectric layer of increased thickness embedding, or replacing, the
second dielectric layer 14. - In order to minimize the surface re-combination phenomena that occur at the SiO2/GexSi1-x interface, the fourth alternative embodiment of the HBT transistor fabrication process may also have the oxidation step followed by a suitable thermal treatment.
- The next steps of the fourth alternative embodiment of the fabrication process will include: depositing a
layer 15 of polysilicon; etching inside the window region; and forming an emitter region overlaid by an electric contact, similar to the second embodiment described. - Advantageously, by adopting the fabrication processes of this invention, the technical problem of the base current deviating from the ideal in HBT transistors can be solved.
- The truth of this statement is brought out by the graph in FIG. 11 which illustrates the behavior of the collector (Ic) and base (IB) currents versus bias voltage (Vbe), as applied between the base and the emitter, for two HBT transistors having the same emitter surface area but formed with different fabrication methods. In fact, two patterns can be distinguished on this graph: the one (broken line) associated with the HBT transistor which has the
dielectric layer 12 grown by thermal oxidation, and the other (full line) associated with the HBT transistor formed by the process of this invention with thedielectric layer 12′ deposited by CVD. These two patterns nearly match each other, and this match reveals a marked reduction in the deviation of the base current from the ideal. - FIG. 12 shows, for the same types of HBT transistors as above, the behavior of their respective collector currents (Ic) versus the bias voltage (Vce) across the collector and emitter.
- It is evinced from this graph that, for HBT transistors fabricated by the process of the invention (full line curve), a significant increase occurs in the variation percent of the current gain versus the collector current. It should be also emphasized that these transistors have lower saturation voltage values, thereby affording lower power consumption.
- Another advantage of the fabrication process of this invention or its first embodiment (CVD deposition of the
layer 12′) is that it involves relatively low deposition temperatures. This prevents back diffusion of the implanted acceptor impurities, thereby avoiding an oxidation-enhanced diffusion of boron and further raising the cut-off frequency of the HBT transistor fabricated by the process of this invention. - A confirmation of the above statements can be found in the graphs of FIG. 13 and FIG. 14 which show, for the two types of HBT transistors described above, the concentration profile of the acceptor impurities versus depth into the substrate and the behavior of the cut-off frequency versus the collector bias current.
- Finally, notice that collector bias currents in the milliampere range allow HBT transistors fabricated with the invention process to attain cut-off frequencies in the 20 GHz range, that is hitherto unattainable values.
- In conclusion, the fabrication process of this invention allows the frequency field of application of HBT transistors to be further extended, while eliminating deviations of the base current from the ideal.
- From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
- All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheetare incorporated herein by reference, in their entirety.
Claims (18)
1. A heterostructure bipolar transistor, comprising:
a substrate comprised of a first semiconductor material doped with impurities of a first type, the substrate including a first conducting region;
a heterostructure alloy region positioned in the substrate and comprised of a heterostructure alloy of atoms of the first semiconductor material and atoms of a second semiconductor material;
a base region positioned in the substrate above the first conducting region and doped with impurities of a second type;
a first dielectric layer positioned on the substrate, the first dielectric layer defining a first window directly above the heterostructure alloy region;
a second conducting region positioned in the heterostructure alloy region and between the first window and the base region, the second conducting region being comprised of the heterostructure alloy doped with impurities of the first type; and
a contact region positioned in the first window and comprised of the first semiconductor material, the contact region directly contacting the heterostructure alloy of the second conducting region in the heterostructure alloy region.
2. The transistor of claim 1 wherein the first dielectric layer directly contacts the heterostructure alloy of the of the heterostructure alloy region.
3. The transistor of claim 1 , further comprising:
a protective layer positioned over the semiconductor substrate and defining a second window above the heterostructure alloy region, the first dielectric layer being positioned in the second window between the protective layer and the first window.
4. The transistor of claim 3 , further comprising a second dielectric layer positioned on the first dielectric layer and in the second window between the protective layer and the first window.
5. The transistor of claim 4 wherein the first dielectric layer is silicon dioxide and the second dielectric layer is silicon nitride.
6. The transistor of claim 1 wherein the first semiconductor material is silicon, the second semiconductor material is germanium.
7. The transistor of claim 1 , further comprising a metal contact formed directly on the contact region.
8. A heterostructure bipolar transistor, comprising:
a substrate comprised of a first semiconductor material doped with impurities of a first type, the substrate including a first conducting region;
a heterostructure alloy region positioned in the substrate and comprised of a heterostructure alloy of atoms of the first semiconductor material and atoms of a second semiconductor material;
a base region positioned in the substrate above the first conducting region and doped with impurities of a second type;
a first dielectric layer positioned on, and directly contacting, the heterostructure alloy region, the first dielectric layer defining a first window directly above the heterostructure alloy region; and
a second conducting region positioned in the heterostructure alloy region and between the first window and the base region, the second conducting region being comprised of the heterostructure alloy doped with impurities of the first type and directly contacting the first dielectric layer.
9. The transistor of claim 8 , further comprising:
a protective layer positioned over the semiconductor substrate and defining a second window above the heterostructure alloy region, the first dielectric layer being positioned in the second window between the protective layer and the first window.
10. The transistor of claim 9 , further comprising a second dielectric layer positioned on the first dielectric layer and in the second window between the protective layer and the first window.
11. The transistor of claim 10 wherein the first dielectric layer is silicon dioxide and the second dielectric layer is silicon nitride.
12. The transistor of claim 8 wherein the first semiconductor material is silicon, the second semiconductor material is germanium.
13. The transistor of claim 8 , further comprising:
a contact region positioned in the first window and comprised of the first semiconductor material, the contact region directly contacting the heterostructure alloy of the second conducting region in the heterostructure alloy region; and
a metal contact formed directly on the contact region.
14. A vertical structure high carrier mobility bipolar transistor, comprising substrate of crystalline silicon doped with impurities of the N type, having a collector region located at a lower portion of the substrate, the transistor being obtained by a process that includes:
defining a window above the substrate;
providing a first implantation of germanium atoms through said window into the substrate;
providing a second implantation of acceptor dopants through said window to define a base region in the substrate;
applying an RTA treatment, or treatment in an oven, to re-construct a crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy;
forming by chemical vapor deposition a first thin dielectric layer of silicon dioxide on the substrate;
depositing a second dielectric layer onto said first dielectric layer;
depositing a polysilicon layer onto said second dielectric layer;
etching away, within the window region, said first and second dielectric layers, and the polysilicon layer, to expose the base region and form isolation spacers at edges of the window; and
forming an N-doped emitter in the base and window regions.
15. The transistor of claim 14 wherein the deposition of the first thin dielectric layer of silicon dioxide is carried out by an atmospheric pressure chemical vapor deposition process.
16. The transistor of claim 14 wherein the deposition of the first thin dielectric layer of silicon dioxide is followed by thermal treatment.
17. The transistor of claim 14 wherein the second dielectric layer is silicon nitride.
18. The transistor of claim 14 wherein the emitter directly contacts the first dielectric layer.
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US10/615,084 US20040004270A1 (en) | 1997-05-30 | 2003-07-07 | Germanium implanted HBT bipolar |
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EP97830259.4 | 1997-05-30 | ||
EP97830259A EP0881669B1 (en) | 1997-05-30 | 1997-05-30 | Manufacturing process of a germanium implanted heterojunction bipolar transistor |
US8739898A | 1998-05-29 | 1998-05-29 | |
US09/724,563 US6624017B1 (en) | 1997-05-30 | 2000-11-27 | Manufacturing process of a germanium implanted HBT bipolar transistor |
US10/615,084 US20040004270A1 (en) | 1997-05-30 | 2003-07-07 | Germanium implanted HBT bipolar |
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CN102142457A (en) * | 2011-03-15 | 2011-08-03 | 上海宏力半导体制造有限公司 | Heterojunction bipolar transistor and manufacturing method thereof |
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Also Published As
Publication number | Publication date |
---|---|
EP0881669B1 (en) | 2005-12-14 |
DE69734871D1 (en) | 2006-01-19 |
EP0881669A1 (en) | 1998-12-02 |
JPH1187364A (en) | 1999-03-30 |
US6624017B1 (en) | 2003-09-23 |
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