US20040030864A1

US20040030864A1 - Expanded functionality of processor operations within a fixed width instruction encoding

Info

Publication number: US20040030864A1
Application number: US10/311,264
Authority: US
Inventors: Andrew Webber
Original assignee: Imagination Technologies Ltd
Current assignee: Imagination Technologies Ltd
Priority date: 2001-04-23
Filing date: 2002-04-23
Publication date: 2004-02-12
Also published as: DE60211505T2; EP1384145A1; GB0109939D0; JP2011044163A; GB2374950A; WO2002086701A1; JP4667717B2; US8209520B2; JP2004520650A; EP1384145B1; DE60211505D1; GB2374950B; US20070288723A1

Abstract

An apparatus for executing fixed width instructions in a multiple execution unit system has a means for fetching instructions from memory, and a decoder for decoding each fetched instruction in turn. A determination is made as to whether each decoded instruction includes a portion to fetch a locally stored instruction from a local store. If it does, the locally stored instruction is fetched and locally stored portion are executed.

Description

This invention relates-to instruction encoding of the fixed width type and is of particular benefit in processing systems which include multiple execution units or pipelines.

In almost all forms of processing unit, e.g. central processing units or digital signal processors, instructions that control the operations of the system have a fixed size limit, often known as the instructions width. This limit imposes a restriction on how much each instruction can describe. In particular, processing systems which have multiple execution units or pipelines may be unable to usefully specify activity within all of those execution units or pipelines within the fixed width constraint of the instruction. This means that the full processing power of the system cannot always be fully utilised. One option would be to increase the width of the instructions size, for example by using very long instruction words. This, however, would slow down the instructions fetch and decoding process and would require wider parallel buses to transport the instructions.

Preferred embodiments of the invention can be used with systems such as that described in our international patent application number WO97/38372, the contents of which are herein incorporated by reference. This document discloses a processing system which manages the processing of a number of different processing instructions threads by one or more data processors.

Preferred embodiments of the present invention seek to overcome the problems associated with these existing systems by use of a locally stored or template instruction. These are usually the functional parts of an instruction which are stored separately and can then be invoked for particular processing units with a single regular instruction. This allows multiple compatible instructions to be invoked with a single instruction issued within the fixed width size limit of the system. The single instruction which is used to invoke the template instruction can be issued with variable parameters, thereby retaining much of the variability of purpose that the many individual instructions which would otherwise have been required would have had. For example the template instruction may be to read data from memory and to enter it into the memory register of a processing unit. The memory read operation would be stored in a template instruction along with the function instructing it to write the read data to the register of a processing unit. The single instruction which invokes the template, would specify the template to be accessed and the registers to be used by that template function. Thus, the relevant data from memory will be read and written into the registers specified in, the invocation instruction. Thus, the invocation instruction only needs to include the template invocation function and the registers required rather than having to specify the memory read instruction for each register. Thus, the reading of data from memory into a number of registers associated with individual processing units can be accomplished using fewer fixed width instructions than would otherwise have been the case.

A preferred embodiment of the invention will now be described in detail by way of example with reference to the accompanying figures in which: [0005]
FIG. 1 is a block diagram of the base architecture of a multithreaded multiprocessor system of the type in which an embodiment of the invention may be used; [0006]
FIG. 2 shows schematically the instruction scheduler and memory read/write controller of the media control core of FIG. 1; [0007]
FIG. 3 shows a standard fixed width instruction of the type which could be scheduled by the apparatus of FIG. 2; [0008]
FIG. 4 shows the flow of control in template instruction scheduling; [0009]
FIG. 5 shows a regular instruction of the type shown in FIG. 1 with a template selection bit and also a template defining instruction which also includes a template defining bit; [0010]
FIG. 6 shows a flow diagram of the flow of control in an embodiment of the invention; and [0011]
FIG. 7 is a block hardware diagram of the instruction scheduler of FIG. 2.[0012]
In the block diagram of FIG. 1, the central part of the system is the media control core (MCC) [0013] 2 which comprises a fine grained multithreaded multiprocessor. It has a plurality of inputs and outputs which can be coupled to real time data input and output devices 4 which may be for example, video sources, audio sources, video outputs, audio outputs, data sources, storage devices, etc. In the most simple example only a single input and a single output are provided. Also coupled to the MCC 2 are a plurality of data processing unit 6. Each of these comprises a data processing core 8 which controls the processing of data by a data pipeline 10. The core 8 decodes the sequences of micro instructions for the pipeline 10 after these have been provided to the instructions scheduler in the MCC 2.
Also coupled to the [0014] MCC 2 is a multibank cache memory 12 from which data may be retrieved by the MCC 2 and data processing unit 6 and into which data may be written by the MCC 2 and the data processing unit 6. It includes temporary storage for data and instructions to be performed by the data processing cores on the input data and other internally generated data. These various sets of instructions will, when activated, comprise processing threads.
A portion of the internal architecture of the [0015] media control core 2 is shown in FIG. 2. This comprises an instruction scheduler 16 and a memory read write unit 18. Instructions are provided to the scheduler by the memory read/write unit. These instructions have a fixed width of Nbits as will be discussed below with reference to FIG. 3. The instruction scheduler sends instructions to data processing unit 6. In this example, the data processing units illustrated are two general data processing units and two digital signal processing units. Because of the multithreaded nature of the processor, the instruction set incorporates instructions that may usefully utilise several execution units at once, for example, both DSP units may be used at the same time. Instructions for the processing units 6 are carried via an instruction bus 20.
In FIG. 3 it can be seen that in this example, each instruction supplied to the instruction scheduler has the same fixed width with the bits of the instruction being subdivided into operational code (opcode) fields in a number of ways. These opcode fields typically select the functionality of the instruction, or the registers housed within [0016] data processing cores 8, to which that function is to be applied. Thus, in FIG. 3, the instruction specifies three registers, which will typically reside in each of three separate processing units 6, and a single function which is to be applied to all of those registers. In the example given, some of the bits of the instructions bits are marked as spare. This will not always be the case but it is in many cases preferable to have spare bits allocated so that other functions may be selected.
It will be appreciated that if additional processing units are used, it may not be possible to provide instructions for all of these simultaneously, thereby leading to less than the maximum processing power being used. [0017]
Accordingly, we have appreciated that the instruction bandwidth can be increased using the same fixed width instruction bus and clock frequency by use of what are known as template instructions. These are locally stored instructions which specify the nature of all the elements of an operation to be performed, e.g. a memory operation, without specifying the memory locations to be addressed or the registers to be accessed in that memory operation. Instructions are stored in a template table and the basic block diagram of how this is arranged within the instruction scheduler is shown in FIG. 4. This flow diagram illustrates at [0018] 24, an instruction fetch from memory. At 26, the instruction is decoded and if the decoder detects that it is an instruction which invokes a template instruction, a template instruction is read from a template table 28. Instructions are then executed at 30 and program flow returns to the instruction fetch block 24.
The template instructions are now described in more detail with reference to FIGS. 5A and B. [0019] 5A shows a regular instruction which comprises 3 register selections and a function selector. One of the bits of the spare bits is set as a 0 and this particular bit is recognised by the instruction decoder as defining this as a regular instruction.
In FIG. 5B, a template defining instruction is shown. This is an instruction which is sent to store a template instruction in the template table [0020] 28. The bit that was set as 0 in the regular instruction is now set as a 1 and the instruction decoder recognises this as a template defining instruction and sends data to the template table 28. The template defining instruction in this example comprises a memory operation function selector. This defines whether the operation is a memory read or write and, the size of transfer, and address generation information. The address generation will usually be of the form base register and offset register, or base register and immediate number (a small number defined with the instruction as opposed to one coming from a register). The memory operation may also specify which processing unit is to be used. The memory address generation will then be performed by that execution unit. The template selector defines the location in the template table 28 to which the template instruction will be written. The function selector selects the function to be used in the execution unit(s) when the template instruction is invoked by a template invocation instruction. This could be “add”, “multiply”, “shift” etc. Thus, all the elements of the memory operation are specified in the template definition in place of bits which would be used in a regular instruction.
A template invocation instruction is shown in FIG. 6. This has essentially the same form as the regular instruction shown in FIG. 5. However, in this case the instruction's function is to invoke the function specified by a given template in relation to e.g. the registers specified in the template invocation instruction. Thus, at the [0021] instruction decode step 26 in FIG. 4, the template select function from the instruction of FIG. 6 will be recognised. This will specify the particular template to the invoked. In the case of the example of FIG. 5B, if this template is invoked, this causes the memory operation specified to be performed and the function specified to be performed with the relevant data on the registers specified in the invocation instruction. If this was a memory read operation it accesses memory as defined by the function selector of FIG. 5B and writes data of the appropriate size to the registers specified in the instruction of FIG. 6.
A more detailed design of the circuits to be included in the instructions scheduler to implement all of this is shown in FIG. 7. This comprises an interface with the memory read/[0022] write unit 18 of FIG. 2. In response to instruction data memory request unit 30, this provides instructions to an instruction data buffer 32. These are then passed in turn to an instruction predecode unit 34. This provides at an output the resource requirements for that instruction which are then supplied to an AND gate 36 whose other input unit is resource availability. If availability matches requirements then the output of the AND gate enables an instruction schedule unit 38 which passes the instructions to an instruction postdecode unit 40 where they are arranged for passing to instruction execution unit 42 and thus to execution units 6.
A template table [0023] 28 communicates with the instruction predecode unit 34 and the instruction postdecode unit 40. When a template invocation instruction of the type shown in FIG. 6 is detected at the instruction predecode unit, this will pass to instruction schedule unit 38 and instruction postdecode unit 40. This will recognise the instruction at a template invocation instruction and using the template select function from the instruction of FIG. 6 will send a read signal to the template table 28, to select the appropriate template instruction. This is then sent to instruction predecode unit 34, and passes through as previously described with resource requirements being matched to availability and the instruction from the template being passed through to instruction execution at 42 via the instruction postdecode unit 40 which has retained the register selectors specified in the template invocation instruction. Preferably the template instruction is provided to both predecode and postdecode units with the predecode then checking resource availability and enabling the scheduler to send data to the postdecode unit to start execution of the function from the template with the registers specified in the invocation instruction
When the instruction received is a template defining instruction, and the appropriate one of the spare bits is set to 1, this is recognised by the instruction predecode and postdecode unit and the template instruction is read into a portion of the template table defined by the template selector of FIG. 5B from the instruction [0024] post decode unit 40. Any further execution takes place at that stage.
After the [0025] instruction execution unit 42 has sent data to the execution unit 6 the flow of program control returns to the instruction data memory request unit 30 and execution continues.
Because of the use of template defining instructions it will be appreciated that the template table can change during execution of any particular program. Thus, a trade off can be achieved between the size of the template table and the speed of processing. A large template table is able to store all the possible types of operation which might be required and would not need to be updated. However, if a smaller template table is used, each program that runs on it might start by first defining a set of template instructions which it will use and writing these into a template table. The program can then execute with appropriate access to the template instructions being made as required. In such a situation, the contents of the template table can be dynamically altered during execution of the program by sending further template defining instructions as these are required when the program passes to a different stage of execution. [0026]
The use of the template instructions thus enables instructions which could not be invoked using a fixed width instruction bus to be invoked, simultaneously, thereby improving the processing speed of the unit and making better use of processing resources, and without using very long instruction words. [0027]

Claims

1. Apparatus for executing fixed width instructions in a multiple execution unit system comprising:

means for fetching instructions from memory;

means for decoding each fetched instruction in turn;

means for determining whether each decoded instruction includes a portion to fetch a locally stored instruction portion from a local store means;

means for fetching the locally stored instruction portion in dependence on the determination; and

means for causing the decoded instruction and locally stored instruction portion to execute on at least one of the execution units.

2. Apparatus according to claim 1 including means for storing additional local instructions in the local storage means in response to data included in a fetched instruction.

3. Apparatus according to claim 2 in which the data included in the fetched instruction includes data defining the location in the local storage means into which the additional local instruction to be written.

4. Apparatus according to claim 1, 2 or 3 in which locally stored instructions comprises at least a functional portion defining the type of operation to be performed.

5. A method for executing fixed width instructions in a multiple execution unit system comprising the steps of:

fetching instruction from memory;

decoding each fetched instruction in turn;

determining whether each decoded instruction includes a portion to fetch locally stored instruction portion;

fetching the locally stored instruction portion in dependence in the determination; and

causing the decoded instruction and locally stored instruction portions to execute on at least one of the execution units.

6. A method according to claim 5 including the step of storing additional local instruction in response to data included in a fetched instruction.

7. Apparatus according to claim 6 in which the data included in the fetched instruction includes data defining the location in a local storage means into which the additional local instruction is to be stored.

8. A method according to claims 5, 6 or 7 in which the locally stored instruction comprises at least a functional part defining the type of operation to be performed.

9. Apparatus for executing fixed width instructions in a multiple execution unit system substantially as herein described with reference to the drawings.

10. A method for executing fixed width instructions in a multiple execution unit system substantially as herein described with reference to the drawings.