US20040036643A1 - Digital pixel sensor with a dynamic comparator having reduced threshold voltage sensitivity - Google Patents
Digital pixel sensor with a dynamic comparator having reduced threshold voltage sensitivity Download PDFInfo
- Publication number
- US20040036643A1 US20040036643A1 US10/226,079 US22607902A US2004036643A1 US 20040036643 A1 US20040036643 A1 US 20040036643A1 US 22607902 A US22607902 A US 22607902A US 2004036643 A1 US2004036643 A1 US 2004036643A1
- Authority
- US
- United States
- Prior art keywords
- transistor
- coupled
- source
- voltage
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
- H03K3/356191—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes with synchronous operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
- H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
- H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
- H04N3/155—Control of the image-sensor operation, e.g. image processing within the image-sensor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/063—Current sense amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/56—Input signal compared with linear ramp
Definitions
- the present invention relates to a digital pixel sensor architecture. More specifically, a digital pixel architecture which incorporates a dynamic comparator having reduced sensitivity to threshold voltage mismatches in its input transistors.
- a conventional digital pixel sensor 100 architecture is illustrated in FIG. 1.
- the conventional digital pixel sensor 100 includes a photoconversion element, such as a photodiode, for converting optical energy into an analog electrical signal.
- the electrical signal is supplied to an analog-to-digital converter (ADC), which converts the analog electrical signal into a digital signal.
- ADC analog-to-digital converter
- the conventional digital pixel sensor 100 therefore differs from several other pixel sensor architectures, such as CMOS active pixel sensors (APS), because the conventional digital pixel sensor performs local analog-to-digital conversion (i.e., digitization at each pixel) instead of global analog-to-digital conversion (i.e., digitization at a common location outside the pixel).
- the conventional digital pixel sensor 100 architecture has several advantages over pixel architectures which perform global analog-to-digital conversion.
- the analog signal generated by the photodiode 101 is susceptible to substrate noise and column fixed pattern noise.
- a local digitization architecture minimizes these susceptibilities.
- the conventional digital pixel sensor 100 architecture is capable of operating at a higher speed, since an entire array of pixels may be digitized at once. In contrast, each pixel of an active pixel sensor array must be sequentially digitized.
- the gap in speed between sensor architectures such as the digital pixel sensor 100 and an active pixel sensor increases with resolution.
- the conventional digital pixel sensor 100 architecture is problematic because the increased circuitry, i.e., the local analog-to-digital converter and the local memory increase circuit complexity which reduces fill factor, i.e., less of the pixel circuitry is devoted to converting light into electrical signals. Additionally, the location of a memory within the pixel makes it difficult to access the information stored in the memory. Accordingly, there is a need and desire for a pixel architecture which is fast, has good fill factor, and minimizes substrate and fixed pattern noise.
- the present invention is directed to a digital pixel sensor (DPS) architecture which incorporates a new comparator and divides the analog-to-digital conversion circuitry between each pixel and a column processing circuit of the pixel array.
- the digital conversions are performed one row at a time, instead of for the entire array at once.
- the row-by-row digitization does not degrade the speed of the DPS architecture since the speed of an imaging system is typically limited by a chip's off-chip data output rate.
- the row-by-row digitization is also advantageous because the limited number of simultaneous conversions provides superior noise immunity.
- the digitized values are stored in a separate frame memory independent of the pixel circuitry.
- the DPS architecture of the present invention has a better fill factor because each pixel no longer includes its own frame memory and analog-to-digital converter. At the same time, the DPS architecture of the present invention preserves the superior noise and speed characteristics associated with digital pixel systems.
- the comparator is preferably of a new design which shares the low power characteristics of dynamic comparators, but which is less sensitive to mismatching of the threshold voltages of its input transistors.
- FIG. 1 is an illustration of a prior art digital pixel
- FIG. 2 is an illustration the digital pixel sensor architecture of the present invention
- FIG. 3 a more detailed illustration of the digital pixel and column digital processing circuit of in accordance with the present invention
- FIG. 4A is an illustration of one embodiment of a digitizing circuit to be used with the comparator of the digital pixel for performing analog-to-digital conversion
- FIG. 4B is an illustration of another embodiment of the digitizing circuit to be used with the comparator of the digital pixel for performing analog-to-digital conversion
- FIG. 5 is an illustration of a processing subcircuit portion of the column digital processing circuit
- FIG. 6 is a timing diagram showing the operation of the digital pixel architecture illustrated in FIG. 3;
- FIG. 7A is an illustration of the dynamic comparator which may be used in the pixel architecture of the present invention.
- FIG. 7B is a timing diagram showing the operation of the dynamic comparator
- FIG. 2 a digital pixel sensor architecture 200 in accordance with the principles of the present invention.
- the architecture 200 includes a pixel array 201 having a plurality of digital pixels 202 .
- the pixel array 201 is also associated with a column digital processing circuit 203 .
- the structure of and the interconnection between a digital pixel 202 and the column digital processing circuit 203 are shown in greater detail in FIG. 3.
- Also associated with the pixel array 201 is a first row decoder 203 for decoding a row of pixels 202 in the pixel array 201 .
- the architecture 200 further includes an independent frame memory 210 .
- a second row decoder 211 is associated with the frame memory 210 and used to decode a row of memory cells in the frame memory 210 .
- a column decoder 212 is associated with the frame memory 210 for decoding a column of memory cells in the frame memory 210 .
- sense amplifiers 213 and output circuitry 220 are used to output data stored in the frame memory 210 .
- the digital pixel 202 includes a photoconversion element, such as a photodiode 101 coupled to a source/drain terminal of a transfer transistor 304 and a source/drain terminal of a reset transistor 301 .
- the digital pixel 202 also includes a memory in the form of a capacitor 305 , which is coupled via node-A to the other source/drain terminal of the transfer transistor and to a source/drain terminal of a memory reset transistor 302 .
- the reset and memory reset transistors 301 , 302 each have one source/drain terminal coupled to node 303 , which is kept at a potential of Vdd.
- the gates of the reset transistor 301 , memory reset transistor 302 , and transfer transistor 304 are respectively coupled to control signals RST, MRST, and TX, which may be sequenced by a control circuit, such as the control circuit 230 illustrated in FIG. 2.
- Control signals RST, MRST, TX, and ROW begin low, thereby ensuring that reset transistor 301 , memory reset transistor 302 , transfer transistor 304 , and row transistor 307 - 308 are non-conducting. Then the RST signal goes high and causes the reset transistor 301 to conduct, thereby coupling the Vdd voltage to the photodiode 101 . As a result, the photodiode 101 is set to a known state.
- the photodiode 101 continues to accumulate charge until the signal TX is brought high, causing the transfer transistor 304 to conduct, and thereby permitting some of the charge built up in the photodiode 101 to charge memory capacitor 305 .
- the TX signal subsequently goes low and the transfer transistor 304 stops conducting.
- the voltage at node-A is the photosignal of the pixel and is based on the charge stored in the capacitor 305 .
- the ROW signal then goes high, causing row transistors 307 , 308 to conduct, thereby permitting the result of the comparator 309 to be input to the digitizing subcircuit 350 .
- the processing of the digitizing subcircuit 350 and the processing subcircuit 351 will be explained later, but for now it is sufficient to note that the comparator 309 of the present invention operates only when the STROBE signal is high.
- the STROBE signal is therefore related to the digitization process of the signal at node-A; however, the number of pulses and the pulse width will be dependent upon how the digitizing subcircuit 350 is implemented.
- Each row of pixels in the imaging array has its own STROBE signal, thereby providing a means for power savings.
- the next event is the MRST signal going high, thereby causing memory transistor 302 to become conductive and Vdd potential to be coupled to the memory capacitor 305 .
- the MRST signal then goes low and memory rest transistor 302 becomes non-conductive.
- the voltage at node-A now represents the reset signal of the pixel.
- a second pulse train then follows, to permit the reset signal to be digitized.
- ROW signal transitions to a low state.
- the pixel 202 does not include an analog-to-digital converter, the pixel 202 incorporates a comparator 309 , which is used with the column digital processing circuit 203 to digitize the analog signal at node-A. More specifically, node-A is coupled to the minus terminal of the comparator 309 .
- the comparator 309 has its plus terminal coupled to node-B on reference signal line 306 , which extends to additional pixels sharing the same column address as the pixel 202 .
- the output and plus input of the comparator 309 are coupled to source/drain terminals of row transistors 307 , 308 .
- the transistor 308 serves for reducing parasitic capacitance of line 306 .
- the transistor 307 connects a given row to the read-out line 309 , which is common for all pixels in a given column and connect to node-C of the digital processing circuit 203 .
- the plus input of the comparator 309 is further coupled to a digitizing subcircuit 350 of the column digital processing circuit 203 at node C. Additionally, at node D, the digitizing subcircuit 350 is coupled to the plus input of the comparator 309 via node-B and row transistor 308 .
- the comparator 309 may be used with a suitable digitizing subcircuit 350 located in the column digital processing circuit 203 to perform analog-to-digital conversion.
- a suitable digitizing subcircuit 350 is shown in FIG. 4A. This embodiment utilizes the “ramp” method for analog-to-digital conversion.
- This digitizing subcircuit 350 includes a counter 401 which accepts control signals CRESET and CINC to respectively reset the counter 401 value to zero and to increment the counter 401 value.
- the counter 401 outputs a digital numeric value at output COUT, which is supplied to an analog ramp generator 402 and a multi-bit latch 403 .
- the analog ramp generator 402 produces an analog signal at output RRAMP_OUT proportional to the digital signal received at input RDIG_IN, which is coupled to the output of the counter 401 .
- the latch 403 receives from node-C the result of the comparison made by comparator 309 (FIG. 3) and couples the result to input LENB, which causes the latch 403 to latch the value at its input terminal LINPUT, which is coupled to the output of the counter 401 .
- a read signal can be applied to the LREAD control terminal of the latch 403 to cause the latched value to be output at terminal LOUTPUT, which outputs the digitized value to the processing subcircuit 351 via node-E.
- the analog ramp generator 402 and counter 401 generate global signals and can therefore be relocated, for example, inside control circuit 203 (FIG. 2).
- FIG. 4B is an alternate embodiment of the digitizing subcircuit 350 .
- This embodiment utilizes a “successive approximation” method for performing the analog-to-digital conversion and produces the result in a iterative manner, at a rate of one bit per iteration, beginning with the most significant bit and ending with the least significant bit.
- the embodiment requires the use of a shift register 410 , a digital-to-analog control circuit 411 and digital-to-analog converter 412 (which may be implemented using switched capacitor banks, or any other suitable method), and a digital-to-analog converter 412 .
- the digital-to-analog control circuit 411 and the shift register 410 are respectively reset by applying control signals to the DACC_RESET and SR_REST terminals, respectively.
- the control circuit 411 outputs a digital signal corresponding to a midpoint value taken about a lower and upper point. Since the control circuit 411 was just reset, the lower point defaults to zero and the upper point defaults to the maximum value.
- the midpoint value is output from terminal DACC_OUT and then read by the digital-to-analog converter 412 at input DAC_IN.
- the converter 412 produces an analog signal corresponding to the digital input at terminal DAC_IN on output terminal DAC_OUT, which is supplied to the comparator 309 (FIG. 3) via node-D, node-B, and transistor 308 .
- the result of the comparison becomes the answer for the current iteration, which in this first round, corresponds to the most significant bit.
- the result is stored into the shift register 410 and also provided to the digital-to-analog control circuit 411 , which calculates a new midpoint value taken around a different upper and lower range, based upon result of the prior round comparison.
- the processing proceeds as described above, until the iteration completes for the least significant bit.
- the value stored in the shift register may be read and provided to the processing subcircuit 351 via node-E.
- both embodiments can optionally utilize the strobe signal as a clocking mechanism for the digitizing subcircuit 350 , since each step of the digitization is dependent upon the operation of the comparator 309 .
- the digitizing subcircuit 350 can be clocked and controlled by any other suitable control circuit, such as control circuit 230 (FIG. 2).
- the processing subcircuit 351 is illustrated in FIG. 5, and includes at least two registers 501 , 502 , a processor 503 , and a processing controller 504 .
- Each of the registers 501 , 502 are capable of receiving and storing a value provided from the digitizing subcircuit 350 at node-E.
- Register 502 is also capable of storing a value received from the frame memory (via node F).
- the processor 503 is a circuit which must be able perform at least addition and subtraction on the contents of the two registers 501 , 502 , which can be provided to the processor 503 at terminals PIN 1 , PIN 2 .
- the result computed by the processor 503 is made available at node-F via terminal POUT.
- a processing control circuit 504 is coupled to the registers 501 , 502 and the processor 503 via a control bus 505 .
- the processing control circuit 504 may also be coupled to the control circuit 230 (FIG. 2).
- the processing circuit 351 is used to add or subtract two digital signals. For example, to implement double sampling or correlated double sampling, a photo signal is subtracted from a previous reset signal or from the current reset signal, respectively.
- the processing control circuit 504 may output an offset on signal line 506 to one of the registers 502 so that an offset may be added to a photo or reset signal.
- the design of the processing subcircuit 351 may be altered to take advantage of any properties associated with the type of analog-to-digital conversion used in the digitizing circuit 350 .
- the registers 501 , 502 and processor 503 may be adapted to operate in a pipelined manner by performing bitwise addition.
- registers 501 , 502 may be shift registers and the processor 503 may be a bitwise adder.
- the comparator 309 (FIG. 3) in the pixel 202 is a key element in the analog-to-digital conversion of the pixel signal.
- a comparator suitable for use as comparator 309 should feature high resolution and low power consumption.
- Dynamic comparators feature low power consumption.
- conventional dynamic comparators are problematic because minor mismatches in the threshold voltages of their two input transistors may cause the comparator to output a false result.
- the use of traditional high precision comparators should be avoided in the pixel due to their high power consumption and the sheer number of pixels present in a high resolution sensor.
- comparator 309 includes two PMOS transistors 401 , 402 , each having a first source/drain terminal coupled to a Vdd potential source and a second source/drain terminal coupled to output nodes I and I′.
- the gates of each PMOS transistor 401 , 402 are also cross coupled to nodes I′ and I, respectively.
- the output nodes I, I′ (I is the comparator decision, I′ is the complement of I) are also coupled a first source/drain terminal of NMOS precharge transistors 403 , 404 , respectively.
- the second source/drain terminals of the NMOS precharge transistors 403 , 404 are coupled to a Vdd potential source.
- Transistor 405 is the NMOS input transistor for the minus signal. Transistor 405 has one source/drain terminal coupled to node I and another source/drain terminal coupled to a first source/drain terminal of the transistor 409 and capacitor 407 .
- the gate of input transistor 405 is coupled in parallel to a source/drain terminal of a transistor 411 and to a first source/drain terminal of transistor 413 .
- the second source/drain terminal of transistor 411 is coupled to a Vbias voltage source, while the second source/drain terminal of transistor 413 is coupled to the minus terminal of the comparator 309 .
- Transistor 406 is the NMOS input transistor for the plus signal. Transistor 406 has one source/drain terminal coupled to node I′ and another source/drain terminal coupled to a first source/drain terminal of transistor 410 and capacitor 408 . The gate of input transistor 406 is coupled in parallel to a first source/drain terminal of transistor 412 and to a first source/drain terminal of transistor 414 . The second source/drain terminal of transistor 412 is coupled to a Vbias voltage source, while the second source/drain terminal of transistor 414 is coupled to the plus terminal of the comparator 309 .
- the comparator 309 operates as follows.
- the STROBE signal is brought high and causes capacitors 407 and 408 to respectively discharge through transistors 409 , 410 .
- the STROBE signal then goes low.
- the PRECHARGE signal which was low, is brought high, while the PRECHARGE# signal, which was high, is brought low.
- This permits the Vbias voltage which is set to be slightly more than the threshold voltage of the input transistors 405 , 406 , to cause the input transistors 405 , 406 to conduct.
- PRECHARGE# being low, this permits transistors 403 , 404 to conduct.
- the Vdd potential source begins to respectively charge capacitors 407 , 408 .
- the Vdd potential source will continue to charge the capacitors 407 , 408 until the voltage at the source is of each respective input transistor 405 , 406 is at Vbias minus the threshold voltage of the respective input transistor 405 , 406 , i.e., the voltage at the source of transistor 405 is charged until it is at Vbias minus the threshold voltage of transistor 405 , while the voltage at the source of transistor 406 is charged until it is at Vbias minus the threshold voltage of transistor 406 .
- the PRECHARGE signal then goes low and PRECHARGE# goes high.
- transistors 413 , 414 conduct to couple the signals at node G and H (which should have a voltage greater than the Vbias) to the gates of input transistors 405 , 406 respectively.
- the input transistor 405 , 406 with the greater voltage will have a lower gate barrier and will sink, more current.
- the comparator 309 utilizes the charge stored in capacitors 407 , 408 in making the comparison and there is no through current. Thus, the comparator 309 achieves lower power consumption while maintaining isolation from a mismatch of input transistor threshold voltages.
- the present invention is therefore directed to a digital pixel sensor architecture in which each digital pixel in a pixel array includes a comparator which can be used with a suitable digitizing subcircuit located in a column digital processing circuit associated with the pixel array.
- the column digital processing circuit also includes an processing subcircuit which supports at least subtracting photo and reset signals.
- the comparator of the digital pixel is preferably one which is designed to minimize power consumption and susceptibility to mismatches in threshold voltages in the input transistors.
Abstract
Description
- The present invention relates to a digital pixel sensor architecture. More specifically, a digital pixel architecture which incorporates a dynamic comparator having reduced sensitivity to threshold voltage mismatches in its input transistors.
- A conventional
digital pixel sensor 100 architecture is illustrated in FIG. 1. The conventionaldigital pixel sensor 100 includes a photoconversion element, such as a photodiode, for converting optical energy into an analog electrical signal. The electrical signal is supplied to an analog-to-digital converter (ADC), which converts the analog electrical signal into a digital signal. The conventionaldigital pixel sensor 100 therefore differs from several other pixel sensor architectures, such as CMOS active pixel sensors (APS), because the conventional digital pixel sensor performs local analog-to-digital conversion (i.e., digitization at each pixel) instead of global analog-to-digital conversion (i.e., digitization at a common location outside the pixel). - The conventional
digital pixel sensor 100 architecture has several advantages over pixel architectures which perform global analog-to-digital conversion. For example, the analog signal generated by thephotodiode 101 is susceptible to substrate noise and column fixed pattern noise. A local digitization architecture minimizes these susceptibilities. Additionally, the conventionaldigital pixel sensor 100 architecture is capable of operating at a higher speed, since an entire array of pixels may be digitized at once. In contrast, each pixel of an active pixel sensor array must be sequentially digitized. Thus, the gap in speed between sensor architectures such as thedigital pixel sensor 100 and an active pixel sensor increases with resolution. - The conventional
digital pixel sensor 100 architecture, however, is problematic because the increased circuitry, i.e., the local analog-to-digital converter and the local memory increase circuit complexity which reduces fill factor, i.e., less of the pixel circuitry is devoted to converting light into electrical signals. Additionally, the location of a memory within the pixel makes it difficult to access the information stored in the memory. Accordingly, there is a need and desire for a pixel architecture which is fast, has good fill factor, and minimizes substrate and fixed pattern noise. - The present invention is directed to a digital pixel sensor (DPS) architecture which incorporates a new comparator and divides the analog-to-digital conversion circuitry between each pixel and a column processing circuit of the pixel array. The digital conversions are performed one row at a time, instead of for the entire array at once. The row-by-row digitization does not degrade the speed of the DPS architecture since the speed of an imaging system is typically limited by a chip's off-chip data output rate. The row-by-row digitization is also advantageous because the limited number of simultaneous conversions provides superior noise immunity. The digitized values are stored in a separate frame memory independent of the pixel circuitry. The DPS architecture of the present invention has a better fill factor because each pixel no longer includes its own frame memory and analog-to-digital converter. At the same time, the DPS architecture of the present invention preserves the superior noise and speed characteristics associated with digital pixel systems. The comparator is preferably of a new design which shares the low power characteristics of dynamic comparators, but which is less sensitive to mismatching of the threshold voltages of its input transistors.
- The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments of the invention given below with reference to the accompanying drawings.
- FIG. 1 is an illustration of a prior art digital pixel;
- FIG. 2 is an illustration the digital pixel sensor architecture of the present invention;
- FIG. 3 a more detailed illustration of the digital pixel and column digital processing circuit of in accordance with the present invention;
- FIG. 4A is an illustration of one embodiment of a digitizing circuit to be used with the comparator of the digital pixel for performing analog-to-digital conversion;
- FIG. 4B is an illustration of another embodiment of the digitizing circuit to be used with the comparator of the digital pixel for performing analog-to-digital conversion;
- FIG. 5 is an illustration of a processing subcircuit portion of the column digital processing circuit;
- FIG. 6 is a timing diagram showing the operation of the digital pixel architecture illustrated in FIG. 3;
- FIG. 7A is an illustration of the dynamic comparator which may be used in the pixel architecture of the present invention;
- FIG. 7B is a timing diagram showing the operation of the dynamic comparator;
- Now referring to the drawings, where like reference numerals designate like elements, there is shown in FIG. 2 a digital
pixel sensor architecture 200 in accordance with the principles of the present invention. Thearchitecture 200 includes apixel array 201 having a plurality ofdigital pixels 202. Thepixel array 201 is also associated with a columndigital processing circuit 203. The structure of and the interconnection between adigital pixel 202 and the columndigital processing circuit 203 are shown in greater detail in FIG. 3. Also associated with thepixel array 201 is afirst row decoder 203 for decoding a row ofpixels 202 in thepixel array 201. - As seen in FIG. 2, the
architecture 200 further includes anindependent frame memory 210. Asecond row decoder 211 is associated with theframe memory 210 and used to decode a row of memory cells in theframe memory 210. Also associated with theframe memory 210 is acolumn decoder 212 for decoding a column of memory cells in theframe memory 210. Additionally,sense amplifiers 213 andoutput circuitry 220 are used to output data stored in theframe memory 210. - In FIG. 3, the structure of a
digital pixel 202 is illustrated in the top portion of the figure (above the dashed fine). Thedigital pixel 202, includes a photoconversion element, such as aphotodiode 101 coupled to a source/drain terminal of atransfer transistor 304 and a source/drain terminal of areset transistor 301. Thedigital pixel 202 also includes a memory in the form of acapacitor 305, which is coupled via node-A to the other source/drain terminal of the transfer transistor and to a source/drain terminal of amemory reset transistor 302. The reset andmemory reset transistors node 303, which is kept at a potential of Vdd. The gates of thereset transistor 301,memory reset transistor 302, andtransfer transistor 304 are respectively coupled to control signals RST, MRST, and TX, which may be sequenced by a control circuit, such as thecontrol circuit 230 illustrated in FIG. 2. - Now referring also to the timing diagram of FIG. 6, the operation of the
pixel 202 can be explained. Control signals RST, MRST, TX, and ROW begin low, thereby ensuring that resettransistor 301,memory reset transistor 302,transfer transistor 304, and row transistor 307-308 are non-conducting. Then the RST signal goes high and causes thereset transistor 301 to conduct, thereby coupling the Vdd voltage to thephotodiode 101. As a result, thephotodiode 101 is set to a known state. After the RST signal goes low again, thephotodiode 101 continues to accumulate charge until the signal TX is brought high, causing thetransfer transistor 304 to conduct, and thereby permitting some of the charge built up in thephotodiode 101 to chargememory capacitor 305. The TX signal subsequently goes low and thetransfer transistor 304 stops conducting. The voltage at node-A is the photosignal of the pixel and is based on the charge stored in thecapacitor 305. - The ROW signal then goes high, causing
row transistors comparator 309 to be input to the digitizingsubcircuit 350. The processing of thedigitizing subcircuit 350 and theprocessing subcircuit 351 will be explained later, but for now it is sufficient to note that thecomparator 309 of the present invention operates only when the STROBE signal is high. The STROBE signal is therefore related to the digitization process of the signal at node-A; however, the number of pulses and the pulse width will be dependent upon how the digitizingsubcircuit 350 is implemented. Each row of pixels in the imaging array has its own STROBE signal, thereby providing a means for power savings. The next event is the MRST signal going high, thereby causingmemory transistor 302 to become conductive and Vdd potential to be coupled to thememory capacitor 305. The MRST signal then goes low andmemory rest transistor 302 becomes non-conductive. The voltage at node-A now represents the reset signal of the pixel. A second pulse train then follows, to permit the reset signal to be digitized. Finally, ROW signal transitions to a low state. - Although the
pixel 202 does not include an analog-to-digital converter, thepixel 202 incorporates acomparator 309, which is used with the columndigital processing circuit 203 to digitize the analog signal at node-A. More specifically, node-A is coupled to the minus terminal of thecomparator 309. Thecomparator 309 has its plus terminal coupled to node-B onreference signal line 306, which extends to additional pixels sharing the same column address as thepixel 202. The output and plus input of thecomparator 309 are coupled to source/drain terminals ofrow transistors transistor 308 serves for reducing parasitic capacitance ofline 306. Thetransistor 307 connects a given row to the read-outline 309, which is common for all pixels in a given column and connect to node-C of thedigital processing circuit 203. The plus input of thecomparator 309 is further coupled to a digitizingsubcircuit 350 of the columndigital processing circuit 203 at node C. Additionally, at node D, the digitizingsubcircuit 350 is coupled to the plus input of thecomparator 309 via node-B androw transistor 308. - The
comparator 309 may be used with asuitable digitizing subcircuit 350 located in the columndigital processing circuit 203 to perform analog-to-digital conversion. For example, one embodiment of asuitable digitizing subcircuit 350 is shown in FIG. 4A. This embodiment utilizes the “ramp” method for analog-to-digital conversion. This digitizingsubcircuit 350 includes acounter 401 which accepts control signals CRESET and CINC to respectively reset thecounter 401 value to zero and to increment thecounter 401 value. Thecounter 401 outputs a digital numeric value at output COUT, which is supplied to ananalog ramp generator 402 and amulti-bit latch 403. Theanalog ramp generator 402 produces an analog signal at output RRAMP_OUT proportional to the digital signal received at input RDIG_IN, which is coupled to the output of thecounter 401. Thelatch 403 receives from node-C the result of the comparison made by comparator 309 (FIG. 3) and couples the result to input LENB, which causes thelatch 403 to latch the value at its input terminal LINPUT, which is coupled to the output of thecounter 401. A read signal can be applied to the LREAD control terminal of thelatch 403 to cause the latched value to be output at terminal LOUTPUT, which outputs the digitized value to theprocessing subcircuit 351 via node-E. It should be noted that while theanalog ramp generator 402 and counter 401 generate global signals and can therefore be relocated, for example, inside control circuit 203 (FIG. 2). - FIG. 4B is an alternate embodiment of the digitizing
subcircuit 350. This embodiment utilizes a “successive approximation” method for performing the analog-to-digital conversion and produces the result in a iterative manner, at a rate of one bit per iteration, beginning with the most significant bit and ending with the least significant bit. As can be seen in FIG. 4B, the embodiment requires the use of ashift register 410, a digital-to-analog control circuit 411 and digital-to-analog converter 412 (which may be implemented using switched capacitor banks, or any other suitable method), and a digital-to-analog converter 412. In the beginning, the digital-to-analog control circuit 411 and theshift register 410 are respectively reset by applying control signals to the DACC_RESET and SR_REST terminals, respectively. In response thecontrol circuit 411 outputs a digital signal corresponding to a midpoint value taken about a lower and upper point. Since thecontrol circuit 411 was just reset, the lower point defaults to zero and the upper point defaults to the maximum value. The midpoint value is output from terminal DACC_OUT and then read by the digital-to-analog converter 412 at input DAC_IN. Theconverter 412 produces an analog signal corresponding to the digital input at terminal DAC_IN on output terminal DAC_OUT, which is supplied to the comparator 309 (FIG. 3) via node-D, node-B, andtransistor 308. - The result of the comparison becomes the answer for the current iteration, which in this first round, corresponds to the most significant bit. The result is stored into the
shift register 410 and also provided to the digital-to-analog control circuit 411, which calculates a new midpoint value taken around a different upper and lower range, based upon result of the prior round comparison. The processing proceeds as described above, until the iteration completes for the least significant bit. At this time, the value stored in the shift register may be read and provided to theprocessing subcircuit 351 via node-E. - It should be noted that although the STROBE signal was not illustrated in either FIGS. 4A or4B, both embodiments can optionally utilize the strobe signal as a clocking mechanism for the digitizing
subcircuit 350, since each step of the digitization is dependent upon the operation of thecomparator 309. Alternatively, the digitizingsubcircuit 350 can be clocked and controlled by any other suitable control circuit, such as control circuit 230 (FIG. 2). - The
processing subcircuit 351 is illustrated in FIG. 5, and includes at least tworegisters processor 503, and aprocessing controller 504. Each of theregisters subcircuit 350 at node-E. Register 502 is also capable of storing a value received from the frame memory (via node F). Theprocessor 503 is a circuit which must be able perform at least addition and subtraction on the contents of the tworegisters processor 503 at terminals PIN1, PIN2. The result computed by theprocessor 503 is made available at node-F via terminal POUT. Aprocessing control circuit 504 is coupled to theregisters processor 503 via acontrol bus 505. Theprocessing control circuit 504 may also be coupled to the control circuit 230 (FIG. 2). - The
processing circuit 351 is used to add or subtract two digital signals. For example, to implement double sampling or correlated double sampling, a photo signal is subtracted from a previous reset signal or from the current reset signal, respectively. Alternatively, theprocessing control circuit 504 may output an offset onsignal line 506 to one of theregisters 502 so that an offset may be added to a photo or reset signal. - The design of the
processing subcircuit 351 may be altered to take advantage of any properties associated with the type of analog-to-digital conversion used in the digitizingcircuit 350. For example, if as in FIG. 4B the digital signal at node-E is provided at a rate of one bit per iteration, theregisters processor 503 may be adapted to operate in a pipelined manner by performing bitwise addition. For example, registers 501, 502 may be shift registers and theprocessor 503 may be a bitwise adder. - The comparator309 (FIG. 3) in the
pixel 202 is a key element in the analog-to-digital conversion of the pixel signal. Ideally, a comparator suitable for use ascomparator 309 should feature high resolution and low power consumption. Dynamic comparators feature low power consumption. However, conventional dynamic comparators are problematic because minor mismatches in the threshold voltages of their two input transistors may cause the comparator to output a false result. On the other hand, the use of traditional high precision comparators should be avoided in the pixel due to their high power consumption and the sheer number of pixels present in a high resolution sensor. - The present invention therefore contemplates using a new comparator design for
comparator 309. As illustrated in FIG. 7A,comparator 309 includes twoPMOS transistors PMOS transistor - The output nodes I, I′ (I is the comparator decision, I′ is the complement of I) are also coupled a first source/drain terminal of
NMOS precharge transistors precharge transistors -
Transistor 405 is the NMOS input transistor for the minus signal.Transistor 405 has one source/drain terminal coupled to node I and another source/drain terminal coupled to a first source/drain terminal of thetransistor 409 andcapacitor 407. The gate ofinput transistor 405 is coupled in parallel to a source/drain terminal of atransistor 411 and to a first source/drain terminal oftransistor 413. The second source/drain terminal oftransistor 411 is coupled to a Vbias voltage source, while the second source/drain terminal oftransistor 413 is coupled to the minus terminal of thecomparator 309. -
Transistor 406 is the NMOS input transistor for the plus signal.Transistor 406 has one source/drain terminal coupled to node I′ and another source/drain terminal coupled to a first source/drain terminal oftransistor 410 andcapacitor 408. The gate ofinput transistor 406 is coupled in parallel to a first source/drain terminal oftransistor 412 and to a first source/drain terminal oftransistor 414. The second source/drain terminal oftransistor 412 is coupled to a Vbias voltage source, while the second source/drain terminal oftransistor 414 is coupled to the plus terminal of thecomparator 309. - Referring now also to the timing diagram of FIG. 7B, the
comparator 309 operates as follows. The STROBE signal is brought high and causescapacitors transistors input transistors input transistors transistors capacitors capacitors respective input transistor respective input transistor transistor 405 is charged until it is at Vbias minus the threshold voltage oftransistor 405, while the voltage at the source oftransistor 406 is charged until it is at Vbias minus the threshold voltage oftransistor 406. This isolates the effect of having different threshold voltages on the twoinput transistors - The PRECHARGE signal then goes low and PRECHARGE# goes high. When the SAMPLE signal goes high,
transistors input transistors input transistor PMOS transistors comparator 309 utilizes the charge stored incapacitors comparator 309 achieves lower power consumption while maintaining isolation from a mismatch of input transistor threshold voltages. - The present invention is therefore directed to a digital pixel sensor architecture in which each digital pixel in a pixel array includes a comparator which can be used with a suitable digitizing subcircuit located in a column digital processing circuit associated with the pixel array. The column digital processing circuit also includes an processing subcircuit which supports at least subtracting photo and reset signals. The comparator of the digital pixel is preferably one which is designed to minimize power consumption and susceptibility to mismatches in threshold voltages in the input transistors.
- While the invention has been described in detail in connection with the exemplary embodiment, it should be understood that the invention is not limited to the above disclosed embodiment. Rather, the invention can be modified to incorporate any number of variations, alternations, substitutions, or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not limited by the foregoing description or drawings, but is only limited by the scope of the appended claims.
Claims (40)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/226,079 US6707410B1 (en) | 2002-08-23 | 2002-08-23 | Digital pixel sensor with a dynamic comparator having reduced threshold voltage sensitivity |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/226,079 US6707410B1 (en) | 2002-08-23 | 2002-08-23 | Digital pixel sensor with a dynamic comparator having reduced threshold voltage sensitivity |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040036643A1 true US20040036643A1 (en) | 2004-02-26 |
US6707410B1 US6707410B1 (en) | 2004-03-16 |
Family
ID=31887158
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/226,079 Expired - Lifetime US6707410B1 (en) | 2002-08-23 | 2002-08-23 | Digital pixel sensor with a dynamic comparator having reduced threshold voltage sensitivity |
Country Status (1)
Country | Link |
---|---|
US (1) | US6707410B1 (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040099790A1 (en) * | 2002-11-27 | 2004-05-27 | Microsoft Corporation | Photo-sensor array for motion detection |
US20040178324A1 (en) * | 2003-03-13 | 2004-09-16 | John Scott-Thomas | Imaging Device |
US20080106622A1 (en) * | 2004-06-02 | 2008-05-08 | The Science And Technology Facilities Council | Imaging Device |
US20100264296A1 (en) * | 2006-06-29 | 2010-10-21 | Noble Peak Vision Corp. | Mixed analog and digital pixel for high dynamic range readout |
US20120104238A1 (en) * | 2010-10-29 | 2012-05-03 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and method for operating the same |
KR101155754B1 (en) * | 2004-07-16 | 2012-06-12 | 소니 주식회사 | Data processing method, semiconductor device for detecting physical quantity distribution, and electronic apparatus |
WO2013158965A1 (en) * | 2012-04-19 | 2013-10-24 | Raytheon Company | Repartitioned digital pixel |
US20180020176A1 (en) * | 2016-07-13 | 2018-01-18 | SK Hynix Inc. | Pixel signal readout device, method thereof, and cmos image sensor including the same |
US20190267423A1 (en) * | 2018-02-28 | 2019-08-29 | Samsung Electronics Co., Ltd. | Image Sensor Chips Having Sub-Chips |
CN110474638A (en) * | 2019-07-30 | 2019-11-19 | 成都铭科思微电子技术有限责任公司 | The Background calibration circuit and method of latch-type comparator imbalance error |
CN111629161A (en) * | 2019-02-28 | 2020-09-04 | 爱思开海力士有限公司 | Comparator and image sensing device including the same |
US11006062B2 (en) * | 2018-11-20 | 2021-05-11 | Beijing Boe Technology Development Co., Ltd. | Pixel sensing circuit and driving method thereof, image sensor and electronic device |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6891143B2 (en) * | 2002-10-30 | 2005-05-10 | Microsoft Corporation | Photo-sensor array with pixel-level signal comparison |
KR100581296B1 (en) * | 2002-12-05 | 2006-05-17 | 주식회사 애트랩 | Image sensor for motion detection and image signal processing system using it |
US7738014B2 (en) * | 2002-12-05 | 2010-06-15 | Atlab Inc. | Image sensor and optical pointing system |
US20100225579A1 (en) * | 2002-12-05 | 2010-09-09 | Atlab Inc. | Image sensor and optical pointing system |
US7148831B2 (en) * | 2003-10-27 | 2006-12-12 | Micron Technology, Inc. | Variable quantization ADC for image sensors |
US7126512B2 (en) * | 2004-03-19 | 2006-10-24 | Charles Douglas Murphy | Comparing circuits for time-to-threshold A/D conversion in digital imaging arrays |
US7515188B2 (en) * | 2004-07-16 | 2009-04-07 | Micron Technology, Inc. | Method and system for reducing mismatch between reference and intensity paths in analog to digital converters in CMOS active pixel sensors |
US7468501B2 (en) * | 2005-05-12 | 2008-12-23 | California Institute Of Technology | Linear dynamic range enhancement in a CMOS imager |
US7488926B2 (en) * | 2006-01-06 | 2009-02-10 | Microsoft Corporation | Pixel array with shared pixel output lines |
US7242332B1 (en) * | 2006-05-04 | 2007-07-10 | Micron Technology, Inc. | Column-parallel sigma-delta analog-to-digital conversion with gain and offset control |
US20090002535A1 (en) * | 2007-06-27 | 2009-01-01 | Arizona Board Of Regents On Behalf Of Arizona State University | Offset-compensated self-reset cmos image sensors |
US8982260B2 (en) * | 2010-02-11 | 2015-03-17 | Idatamap Pty. Ltd. | Image matching, data compression and tracking architectures |
US9029753B2 (en) | 2012-09-27 | 2015-05-12 | National Tsing Hua University | Optical recognition system and method thereof |
KR102197480B1 (en) * | 2014-09-29 | 2020-12-31 | 에스케이하이닉스 주식회사 | Image sensor and method of operating the same |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4611130A (en) * | 1984-02-13 | 1986-09-09 | At&T Bell Laboratories | Floating input comparator with precharging of input parasitic capacitors |
US5461425A (en) * | 1994-02-15 | 1995-10-24 | Stanford University | CMOS image sensor with pixel level A/D conversion |
US6218892B1 (en) * | 1997-06-20 | 2001-04-17 | Intel Corporation | Differential circuits employing forward body bias |
US6377303B2 (en) * | 1997-11-26 | 2002-04-23 | Intel Corporation | Strobe compatible digital image sensor with low device count per pixel analog-to-digital conversion |
US6271785B1 (en) * | 1998-04-29 | 2001-08-07 | Texas Instruments Incorporated | CMOS imager with an A/D per pixel convertor |
-
2002
- 2002-08-23 US US10/226,079 patent/US6707410B1/en not_active Expired - Lifetime
Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040099790A1 (en) * | 2002-11-27 | 2004-05-27 | Microsoft Corporation | Photo-sensor array for motion detection |
US20040178324A1 (en) * | 2003-03-13 | 2004-09-16 | John Scott-Thomas | Imaging Device |
US7019277B2 (en) * | 2003-03-13 | 2006-03-28 | Psion Teklogix Systems Inc. | Imaging device |
USRE44523E1 (en) * | 2003-03-13 | 2013-10-08 | Harusaki Technologies, Llc | Imaging device with pre-charged signal line |
US20080106622A1 (en) * | 2004-06-02 | 2008-05-08 | The Science And Technology Facilities Council | Imaging Device |
US7719589B2 (en) * | 2004-06-02 | 2010-05-18 | The Science And Technology Facilities Council | Imaging array with enhanced event detection |
KR101155754B1 (en) * | 2004-07-16 | 2012-06-12 | 소니 주식회사 | Data processing method, semiconductor device for detecting physical quantity distribution, and electronic apparatus |
US20100264296A1 (en) * | 2006-06-29 | 2010-10-21 | Noble Peak Vision Corp. | Mixed analog and digital pixel for high dynamic range readout |
US8022350B2 (en) * | 2006-06-29 | 2011-09-20 | Infrared Newco, Inc. | Imaging pixel comprising a comparator to compare integrated photocurrent to a reference value and digital output circuitry |
US8586907B2 (en) | 2006-06-29 | 2013-11-19 | Infrared Newco, Inc. | Methods of operating an imaging pixel to accumulate charge from a photocurrent |
US9209209B2 (en) * | 2010-10-29 | 2015-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and method for operating the same |
US20120104238A1 (en) * | 2010-10-29 | 2012-05-03 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and method for operating the same |
WO2013158965A1 (en) * | 2012-04-19 | 2013-10-24 | Raytheon Company | Repartitioned digital pixel |
US9154713B2 (en) | 2012-04-19 | 2015-10-06 | Raytheon Company | Repartitioned digital pixel |
EP4192026A1 (en) * | 2012-04-19 | 2023-06-07 | Raytheon Company | Repartitioned digital pixel |
US20180020176A1 (en) * | 2016-07-13 | 2018-01-18 | SK Hynix Inc. | Pixel signal readout device, method thereof, and cmos image sensor including the same |
US10187599B2 (en) * | 2016-07-13 | 2019-01-22 | SK Hynix Inc. | Pixel signal readout device, method thereof, and CMOS image sensor including the same |
US20190267423A1 (en) * | 2018-02-28 | 2019-08-29 | Samsung Electronics Co., Ltd. | Image Sensor Chips Having Sub-Chips |
US10763294B2 (en) * | 2018-02-28 | 2020-09-01 | Samsung Electronics Co., Ltd. | Image sensor chips having sub-chips |
US11006062B2 (en) * | 2018-11-20 | 2021-05-11 | Beijing Boe Technology Development Co., Ltd. | Pixel sensing circuit and driving method thereof, image sensor and electronic device |
CN111629161A (en) * | 2019-02-28 | 2020-09-04 | 爱思开海力士有限公司 | Comparator and image sensing device including the same |
US11330214B2 (en) | 2019-02-28 | 2022-05-10 | SK Hynix Inc. | Comparator and image sensing device including the same |
CN110474638A (en) * | 2019-07-30 | 2019-11-19 | 成都铭科思微电子技术有限责任公司 | The Background calibration circuit and method of latch-type comparator imbalance error |
Also Published As
Publication number | Publication date |
---|---|
US6707410B1 (en) | 2004-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6707410B1 (en) | Digital pixel sensor with a dynamic comparator having reduced threshold voltage sensitivity | |
US6670904B1 (en) | Double-ramp ADC for CMOS sensors | |
KR102469080B1 (en) | Comparator, and cmos image sensor thereof | |
US5461425A (en) | CMOS image sensor with pixel level A/D conversion | |
US5929800A (en) | Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier | |
US7385547B2 (en) | Minimized differential SAR-type column-wide ADC for CMOS image sensors | |
US7265706B2 (en) | Minimized SAR-type column-wide ADC for image sensors | |
US10998914B2 (en) | Multi-stage conversion analog-to-digital converter | |
US7280140B2 (en) | Image sensor reading during reset and reading on release from reset | |
US7471228B2 (en) | Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry | |
US9264644B2 (en) | Analog-to-digital conversion for image sensor with non-destructive read pixel | |
US6525304B1 (en) | Circuitry for converting analog signals from pixel sensor to a digital and for storing the digital signal | |
US7479916B1 (en) | High resolution column-based analog-to-digital converter with wide input voltage range for dental X-ray CMOS image sensor | |
US9548755B2 (en) | Analog-to-digital converter with redundancy for image sensor readout | |
US20040233312A1 (en) | CMOS image sensor with noise cancellation | |
WO1997018633A1 (en) | Capacitively coupled successive approximation ultra low power analog-to-digital converter | |
US20100060503A1 (en) | Successive approximation type a/d converter, method of controlling successive approximation type a/d converter, solid-state imaging device, and imaging apparatus | |
US6583817B1 (en) | Autocalibration of the A/D converter within the CMOS type image sensor | |
US8450673B2 (en) | Pixel circuit, imaging integrated circuit, and method for image information acquisition | |
US20090213258A1 (en) | Imaging Array with Improved Dynamic Range | |
US9900538B2 (en) | Phase delay counting analog-to-digital converter circuitry | |
US6747695B1 (en) | Integrated CMOS imager | |
US7649488B1 (en) | Low-power column parallel cyclic analog-to-digital converter | |
US7012557B2 (en) | Ramp modulation ADC for imagers | |
EP3496275B1 (en) | Multi-stage conversion analog-to-digital converter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BOCK, NIKOLAI E.;REEL/FRAME:013236/0606 Effective date: 20020822 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: APTINA IMAGING CORPORATION, CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:028579/0291 Effective date: 20080926 |
|
FPAY | Fee payment |
Year of fee payment: 12 |