US20040046243A1 - Methods of split cavity wall plating for an integrated circuit package - Google Patents

Methods of split cavity wall plating for an integrated circuit package Download PDF

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Publication number
US20040046243A1
US20040046243A1 US10/657,415 US65741503A US2004046243A1 US 20040046243 A1 US20040046243 A1 US 20040046243A1 US 65741503 A US65741503 A US 65741503A US 2004046243 A1 US2004046243 A1 US 2004046243A1
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bond shelf
bond
new
shelf
recited
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US10/657,415
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Elissa Carapella
Mark Palmer
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Priority claimed from US09/153,630 external-priority patent/US6153829A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49131—Assembling to base an electrical component, e.g., capacitor, etc. by utilizing optical sighting device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Definitions

  • the present invention relates to an integrated circuit package.
  • Integrated circuits are typically housed within a package which has a plurality of external contacts that are soldered to a printed circuit board.
  • the package may also have a number of internal bond pads that are connected to corresponding pads of the integrated circuit by bond wires or a tape automated bonding (TAB) tape.
  • TAB tape automated bonding
  • the internal bond pads may be connected to the external contacts by routing layers and busses within the package.
  • the busses and routing layers have conductive planes and traces that are dedicated to the power/ground busses and digital signal lines of the integrated circuit, respectively.
  • a conventional package may have a first bus layer dedicated to power, one or more routing layers dedicated to digital signals and a second bus layer dedicated to ground.
  • the various conductive layers are spatially located within different planes in the package.
  • the layers are typically interconnected by conductive vias formed within the package.
  • the bond pads may also be connected to the internal conductive layers by vias.
  • Vias are typically formed by creating a hole in the dielectric package material and then plating the hole with a conductive material such as copper. The plating process is a relatively time consuming and expensive step. For this reason it is desirable to create an integrated circuit package with a minimal number of vias.
  • Some integrated circuits require power at different voltage levels. For example, an integrated circuit may require both 3.3 V and 2.0 V power.
  • the additional voltage level requires an additional conductive power plane within the package.
  • the second power plane can be created by forming an additional conductive layer within the package.
  • the additional conductive layer requires more vias to connect the second power plane to the bond pads. It would be desirable to provide a dual voltage integrated circuit package which minimized the number of vias required to interconnect the pads and conductive layers of the package.
  • U.S. Pat. No. 5,557,502 issued to Banerjee et al., discloses an integrated circuit package which has a conductive strip that wraps around an edge of a bond shelf to interconnect a power bus to one or more bond pads on the shelf.
  • the conductive strip is typically formed by initially masking all surfaces of the integrated circuit package except for the edge, and then dipping the package into a plating bath of copper. The plating bath plates copper onto the edge on the bond shelf.
  • the conductive copper strip extends continuously along the entire edge of the bond shelf. Because of this only one voltage level can be supplied to the contact pads located on the bond shelf with the plated edge. To provide more design flexibility it would be desirable to connect multiple power/ground planes to the bond pads on the bond shelf with the conductive strip.
  • the present invention is an electronic package that may include a first bond pad and a second bond pad located on a bond shelf.
  • the bond shelf may have an edge.
  • the package may have a first conductive bus that may be connected to the first bond pad by a first conductive strip that extends along the edge of the bond shelf.
  • the package may also have a second conductive bus that may be connected to the second bond pad by a second conductive strip that extends along the edge of the bond shelf.
  • FIG. 1 is a cross-sectional view of an integrated circuit package of the present invention
  • FIG. 2 is a top sectional view of the package
  • FIG. 3 is a top cross-sectional view of the integrated circuit package showing a pair of power busses within the same plane of the package;
  • FIG. 4 is an enlarged perspective view of a bond shelf of the package showing a pair of conductive strips that wrap around the edge of a bond shelf to connect a pair of conductive busses to bond pads located on the shelf;
  • FIG. 5 is a perspective view showing the package masked by a plating resist material
  • FIG. 6 is a side view showing the package within a plating bath
  • FIG. 7 is an enlarged view of a conductive strip that extends along an edge of a bond shelf.
  • FIGS. 1 - 3 show an integrated circuit package 10 of the present invention.
  • the integrated circuit 12 has a plurality of bond pads 14 that are connected to corresponding bond pads 16 of a package housing 11 .
  • the bond pads 14 and 16 may be connected by bond wires 17 or a tape automated bonding (TAB) tape (not shown).
  • TAB tape automated bonding
  • the bond pads 16 may be located on a first bond shelf 18 , a second bond shelf 20 and a third bond shelf 22 . Although three bond shelves are shown and described, it is to be understood that the package 10 may have any number of bond shelves.
  • the bond pads 16 of the first bond shelf 18 are connected to a pair of power busses 24 and 26 within the package.
  • the busses 24 and 26 are separated and located within the same horizontal plane of the package. By locating both power busses 24 and 26 within the same plane the present invention provides a package that may require less layers than a package that has two power busses located within different layers of the package.
  • the package 10 may also have one or more layers of routing traces 28 and a ground bus 30 dedicated to the digital signal lines and ground of the integrated circuit 12 , respectively.
  • the busses 24 , 26 and 30 , and traces 28 are connected to a plurality of contacts 32 that are attached to surface pads 33 located on a bottom surface of the package 10 .
  • the contacts 32 may be solder balls that are reflowed onto a printed circuit board 34 .
  • the printed circuit board 34 may be a motherboard of a computer that contains a power supply(ies) 36 that provides two different voltage levels of power.
  • the power bus 24 is connected to one voltage level, such as 3.3 V, and the other power bus 26 can be connected to a second voltage level, such as 2.0 V.
  • the package provides two different voltage levels to the integrated circuit 12 .
  • the busses 24 and 26 are described as being both dedicated to power, it is to be understood that one bus may be connected to power and the other bus may be connected to ground. Such a configuration may reduce the capacitance of the package 10 .
  • solder balls 32 are shown and described, it is to be understood that the package 10 may have other types of contacts such as pins (not shown) that are soldered to the printed circuit board 34 .
  • the bond pads 16 and layers of busses 24 and 26 , routing traces 28 , bus 30 , and contacts 32 may all be interconnected by vias 38 .
  • the busses 24 and 26 may include clearance spaces 42 that electrically isolate the busses 24 and 26 from the vias 38 . Additionally, the busses 24 and 26 are also separated by spaces 43 .
  • FIG. 4 shows a first conductive strip 44 and a second conductive strip 46 that wrap around an edge of the first bond shelf 18 to connect the bond pads 16 to the power busses 24 and 26 .
  • the conductive strips 44 and 46 can be separated by a pair of notches 48 formed in the first bond shelf 18 .
  • Some of the bond pads 16 are connected to bus 24 by conductive strip 44 while other bond pads 16 are connected to bus 26 by strip 46 .
  • the separate strips allow the bond pads 16 on the first bond shelf 18 to be connected to two different voltage levels.
  • the other bond pads 16 on the first bond shelf 18 may be interconnected to other layers and/or contacts 32 by vias 38 .
  • the package 10 is constructed with a laminated printed circuit board process.
  • the ground layer 30 can be formed on a dielectric substrate with conventional photolithographic techniques.
  • a second substrate may be placed on the ground layer 30 .
  • the layer may have a plurality of holes used for the formation of the vias 38 .
  • the second substrate may contain copper layers that are etched to form the routing traces 28 and bond pads 16 . Additional substrates may be added to create the busses 24 and 26 , and bond pads 16 .
  • the vias 38 can then be formed with a plating process. The substrates are then “auto-claved” to form the package housing 11 .
  • the conductive strips 44 and 46 can be formed by initially masking off all surfaces of the package housing, except the edge 49 of the first bond shelf 18 with a plating resist maskant 50 , as shown in FIG. 5.
  • the masked housing can then be dipped into a plating bath 52 as shown in FIG. 6.
  • the plating bath 52 plates a conductive material such as copper onto the edge 49 of the first bond shelf 18 .
  • the maskant 50 is then removed and the notches 48 can be drilled into the edges of the first bond shelf 18 to separate the plated material into the first and second conductive strips 44 and 46 . All exposed copper surfaces may then be plated with gold.
  • portions 54 of the conductive strips 44 and 46 may extend onto the first bond shelf 18 to connect to a bonding pad 16 .
  • the extra portions 54 may further anchor the conductive strips 44 and 46 to the housing and reduce the likelihood of delamination during the drilling process.
  • the additional portions 54 can be formed by not masking the end of the first bond shelf 18 so that conductive material plates onto the shelf.
  • the integrated circuit 12 may be mounted onto the package and connected to the bond pads 16 .
  • the integrated circuit 12 may then be enclosed with an encapsulant 56 .
  • the contacts 32 are attached to the surface pads 33 to complete the package 10 .

Abstract

An electronic package that may include a first bond pad and a second bond pad located on a bond shelf. The bond shelf may have an edge. The package may have a first conductive bus that may be connected to the first bond pad by a first conductive strip that extends along the edge of the bond shelf. The package may also have a second conductive bus that may be connected to the second bond pad by a second conductive strip that extends along the edge of the bond shelf.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit and is a divisional of application Ser. No. 09/665,034, filed Sep. 9, 2000, now pending which is a continuation of application Ser. No. 09/153,630, filed Sep. 15, 1998, now issued as U.S. Pat. No. 6,153,829.[0001]
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention relates to an integrated circuit package. [0003]
  • 2. Description of Related Art [0004]
  • Integrated circuits are typically housed within a package which has a plurality of external contacts that are soldered to a printed circuit board. The package may also have a number of internal bond pads that are connected to corresponding pads of the integrated circuit by bond wires or a tape automated bonding (TAB) tape. The internal bond pads may be connected to the external contacts by routing layers and busses within the package. The busses and routing layers have conductive planes and traces that are dedicated to the power/ground busses and digital signal lines of the integrated circuit, respectively. By way of example, a conventional package may have a first bus layer dedicated to power, one or more routing layers dedicated to digital signals and a second bus layer dedicated to ground. [0005]
  • The various conductive layers are spatially located within different planes in the package. The layers are typically interconnected by conductive vias formed within the package. The bond pads may also be connected to the internal conductive layers by vias. Vias are typically formed by creating a hole in the dielectric package material and then plating the hole with a conductive material such as copper. The plating process is a relatively time consuming and expensive step. For this reason it is desirable to create an integrated circuit package with a minimal number of vias. [0006]
  • Some integrated circuits require power at different voltage levels. For example, an integrated circuit may require both 3.3 V and 2.0 V power. The additional voltage level requires an additional conductive power plane within the package. The second power plane can be created by forming an additional conductive layer within the package. The additional conductive layer requires more vias to connect the second power plane to the bond pads. It would be desirable to provide a dual voltage integrated circuit package which minimized the number of vias required to interconnect the pads and conductive layers of the package. [0007]
  • U.S. Pat. No. 5,557,502, issued to Banerjee et al., discloses an integrated circuit package which has a conductive strip that wraps around an edge of a bond shelf to interconnect a power bus to one or more bond pads on the shelf. The conductive strip is typically formed by initially masking all surfaces of the integrated circuit package except for the edge, and then dipping the package into a plating bath of copper. The plating bath plates copper onto the edge on the bond shelf. [0008]
  • The conductive copper strip extends continuously along the entire edge of the bond shelf. Because of this only one voltage level can be supplied to the contact pads located on the bond shelf with the plated edge. To provide more design flexibility it would be desirable to connect multiple power/ground planes to the bond pads on the bond shelf with the conductive strip. [0009]
    • SUMMARY OF THE INVENTION
  • The present invention is an electronic package that may include a first bond pad and a second bond pad located on a bond shelf. The bond shelf may have an edge. The package may have a first conductive bus that may be connected to the first bond pad by a first conductive strip that extends along the edge of the bond shelf. The package may also have a second conductive bus that may be connected to the second bond pad by a second conductive strip that extends along the edge of the bond shelf. [0010]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of an integrated circuit package of the present invention; [0011]
  • FIG. 2 is a top sectional view of the package; [0012]
  • FIG. 3 is a top cross-sectional view of the integrated circuit package showing a pair of power busses within the same plane of the package; [0013]
  • FIG. 4 is an enlarged perspective view of a bond shelf of the package showing a pair of conductive strips that wrap around the edge of a bond shelf to connect a pair of conductive busses to bond pads located on the shelf; [0014]
  • FIG. 5 is a perspective view showing the package masked by a plating resist material; [0015]
  • FIG. 6 is a side view showing the package within a plating bath; [0016]
  • FIG. 7 is an enlarged view of a conductive strip that extends along an edge of a bond shelf. [0017]
    • DETAILED DESCRIPTION OF THE INVENTION
  • Referring to the drawings more particularly by reference numbers, FIGS. [0018] 1-3 show an integrated circuit package 10 of the present invention. Mounted to the package 10 is an integrated circuit 12. Although an integrated circuit 12 is shown and described, it is to be understood that the package 10 may house any passive or active electrical device. The integrated circuit 12 has a plurality of bond pads 14 that are connected to corresponding bond pads 16 of a package housing 11. The bond pads 14 and 16 may be connected by bond wires 17 or a tape automated bonding (TAB) tape (not shown). The bond pads 16 may be located on a first bond shelf 18, a second bond shelf 20 and a third bond shelf 22. Although three bond shelves are shown and described, it is to be understood that the package 10 may have any number of bond shelves.
  • The [0019] bond pads 16 of the first bond shelf 18 are connected to a pair of power busses 24 and 26 within the package. The busses 24 and 26 are separated and located within the same horizontal plane of the package. By locating both power busses 24 and 26 within the same plane the present invention provides a package that may require less layers than a package that has two power busses located within different layers of the package.
  • The [0020] package 10 may also have one or more layers of routing traces 28 and a ground bus 30 dedicated to the digital signal lines and ground of the integrated circuit 12, respectively. The busses 24, 26 and 30, and traces 28 are connected to a plurality of contacts 32 that are attached to surface pads 33 located on a bottom surface of the package 10. The contacts 32 may be solder balls that are reflowed onto a printed circuit board 34. By way of example, the printed circuit board 34 may be a motherboard of a computer that contains a power supply(ies) 36 that provides two different voltage levels of power.
  • In one embodiment, the [0021] power bus 24 is connected to one voltage level, such as 3.3 V, and the other power bus 26 can be connected to a second voltage level, such as 2.0 V. In this manner the package provides two different voltage levels to the integrated circuit 12. Although the busses 24 and 26 are described as being both dedicated to power, it is to be understood that one bus may be connected to power and the other bus may be connected to ground. Such a configuration may reduce the capacitance of the package 10. Additionally, although solder balls 32 are shown and described, it is to be understood that the package 10 may have other types of contacts such as pins (not shown) that are soldered to the printed circuit board 34.
  • The [0022] bond pads 16 and layers of busses 24 and 26, routing traces 28, bus 30, and contacts 32 may all be interconnected by vias 38. The busses 24 and 26 may include clearance spaces 42 that electrically isolate the busses 24 and 26 from the vias 38. Additionally, the busses 24 and 26 are also separated by spaces 43.
  • FIG. 4 shows a first [0023] conductive strip 44 and a second conductive strip 46 that wrap around an edge of the first bond shelf 18 to connect the bond pads 16 to the power busses 24 and 26. The conductive strips 44 and 46 can be separated by a pair of notches 48 formed in the first bond shelf 18. Some of the bond pads 16 are connected to bus 24 by conductive strip 44 while other bond pads 16 are connected to bus 26 by strip 46. The separate strips allow the bond pads 16 on the first bond shelf 18 to be connected to two different voltage levels. The other bond pads 16 on the first bond shelf 18 may be interconnected to other layers and/or contacts 32 by vias 38.
  • In the preferred embodiment, the [0024] package 10 is constructed with a laminated printed circuit board process. The ground layer 30 can be formed on a dielectric substrate with conventional photolithographic techniques. A second substrate may be placed on the ground layer 30. The layer may have a plurality of holes used for the formation of the vias 38. The second substrate may contain copper layers that are etched to form the routing traces 28 and bond pads 16. Additional substrates may be added to create the busses 24 and 26, and bond pads 16. The vias 38 can then be formed with a plating process. The substrates are then “auto-claved” to form the package housing 11.
  • The [0025] conductive strips 44 and 46 can be formed by initially masking off all surfaces of the package housing, except the edge 49 of the first bond shelf 18 with a plating resist maskant 50, as shown in FIG. 5. The masked housing can then be dipped into a plating bath 52 as shown in FIG. 6. The plating bath 52 plates a conductive material such as copper onto the edge 49 of the first bond shelf 18. The maskant 50 is then removed and the notches 48 can be drilled into the edges of the first bond shelf 18 to separate the plated material into the first and second conductive strips 44 and 46. All exposed copper surfaces may then be plated with gold.
  • As shown in FIG. 7, [0026] portions 54 of the conductive strips 44 and 46 may extend onto the first bond shelf 18 to connect to a bonding pad 16. The extra portions 54 may further anchor the conductive strips 44 and 46 to the housing and reduce the likelihood of delamination during the drilling process. The additional portions 54 can be formed by not masking the end of the first bond shelf 18 so that conductive material plates onto the shelf.
  • Referring to FIGS. 1 and 2, after the [0027] strips 44 and 46 are formed, the integrated circuit 12 may be mounted onto the package and connected to the bond pads 16. The integrated circuit 12 may then be enclosed with an encapsulant 56. The contacts 32 are attached to the surface pads 33 to complete the package 10.
  • While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art. [0028]

Claims (25)

What is claimed is:
1-16. (Cancelled)
17. (New) A method of forming an integrated circuit package, comprising:
providing a package housing having a first plurality of bonding pads located on a first bond shelf, the first bond shelf having a first edge;
forming a first conductive strip along the first edge of the first bond shelf, the first conductive strip wrapping around the edge of the first bond shelf from at least one of the first plurality of bonding pads on the first bond shelf to a first conductor under the first bond shelf; and,
removing a portion of the first conductive strip.
18. (New) The method as recited in claim 17, wherein
the first conductive strip is formed by plating a conductive material onto the first edge.
19. (New) The method as recited in claim 17, wherein
the first conductor under the first bond shelf is a power bus.
20. (New) The method as recited in claim 17, wherein
the first conductor under the first bond shelf is a routing trace.
21. (New) The method as recited in claim 17, wherein
the portion of the first conductive strip is removed by
drilling a portion of the first bond shelf.
22. (New) The method as recited in claim 21, wherein
the portion drilled in the first bond shelf is a notch.
23. (New) The method as recited in claim 17, wherein
the portion of the first conductive strip is removed by
etching away a portion of the first conductive strip of the first bond shelf.
24. (New) The method as recited in claim 17, wherein
the package housing is provided by
forming a first conductive layer on a first dielectric substrate,
placing a second dielectric substrate on the first conductive layer of the first dielectric substrate, the second dielectric substrate having a second conductive layer, and
etching the second conductive layer to form the first plurality of bonding pads.
25. (New) The method as recited in claim 24, wherein
the first conductive layer forms the first conductor under the first bond shelf.
26. (New) The method as recited in claim 24, wherein
the etching of the second conductive layer to further form a second conductor, and
the package housing has a second plurality of bonding pads located on a second bond shelf, the second bond shelf having a second edge, the package housing is further provided by
placing a third dielectric substrate on the second conductive layer of the second dielectric substrate, the third dielectric substrate having a third conductive layer, and
etching the third conductive layer to form a second plurality of bonding pads, and
the method further includes
forming a second conductive strip along the second edge of the second bond shelf, the second conductive strip wrapping around the second edge of the second bond shelf from at least one of the second plurality of bonding pads on the second bond shelf to the second conductor under the second bond shelf.
27. (New) The method as recited in claim 26, wherein
the second conductive layer forms the second conductor under the second bond shelf.
28. (New) The method as recited in claim 26, wherein
the second conductive strip is formed by plating a conductive material onto the second edge.
29. (New) The method as recited in claim 26, wherein
the second conductor under the second bond shelf is a power bus.
30. (New) The method as recited in claim 26, wherein
the second conductor under the second bond shelf is a routing trace.
31. (New) A method of forming an integrated circuit package, comprising:
providing a package housing having a first bond shelf with a top surface and an inside surface;
forming a conductive material along the inside surface of the first bond shelf, a first portion of the conductive material wrapping around from the inside surface onto the top surface of the first bond shelf to form at least one of a first plurality of bonding pads on the top surface of the first bond shelf; and,
removing a second portion of the conductive material along the inside surface of the bond shelf to form a pair of separate conductive strips along the inside surface of the bond shelf.
32. (New) The method as recited in claim 31, wherein
the conductive material is formed along the inside surface by plating a conductive material onto the inside surface.
33. (New) The method as recited in claim 31, wherein
the second portion of the conductive material is removed by
drilling a portion of the first bond shelf.
34. (New) The method as recited in claim 33, wherein
the portion drilled in the first bond shelf is a notch.
35. (New) The method as recited in claim 31, wherein
the second portion of the conductive material is removed by etching away a portion of the conductive material from the inside surface of the first bond shelf.
36. (New) A method of forming an integrated circuit package, comprising:
providing a package housing having a rectangular bond shelf with a rectangular top surface and an inside surface perpendicular with the top surface, the bond shelf having a first plurality of bonding pads located on the top surface;
forming a conductive material along the side surface of the bond shelf, a first portion of the conductive material wrapping around from the inside surface onto the top surface of the bond shelf to couple to at least one of the first plurality of bonding pads on the top surface of the bond shelf; and,
removing a second portion of the conductive material along the inside surface of the bond shelf to form a pair of separate conductive strips along the inside surface of the bond shelf.
37. (New) The method as recited in claim 36, wherein
the conductive material is formed along the inside surface by plating a conductive material onto the inside surface of the bond shelf.
38. (New) The method as recited in claim 36, wherein
the second portion of the conductive material is removed by
drilling a portion of the bond shelf.
39. (New) The method as recited in claim 38, wherein
the portion drilled in the bond shelf is a notch.
40. (New) The method as recited in claim 36, wherein
the second portion of the conductive material is removed by etching away a portion of the conductive material from the inside of the first bond shelf.
US10/657,415 1998-09-15 2003-09-08 Methods of split cavity wall plating for an integrated circuit package Abandoned US20040046243A1 (en)

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US09/153,630 US6153829A (en) 1998-09-15 1998-09-15 Split cavity wall plating for an integrated circuit package
US09/665,034 US7020958B1 (en) 1998-09-15 2000-09-19 Methods forming an integrated circuit package with a split cavity wall
US10/657,415 US20040046243A1 (en) 1998-09-15 2003-09-08 Methods of split cavity wall plating for an integrated circuit package

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