US20040084400A1

US20040084400A1 - Patterning metal stack layers of magnetic switching device, utilizing a bilayer metal hardmask

Info

Publication number: US20040084400A1
Application number: US10/283,348
Authority: US
Inventors: Gregory Costrini; John Hummel; George Stojakovic; Kia-Seng Low
Original assignee: Infineon Technologies AG; International Business Machines Corp
Current assignee: Infineon Technologies AG; International Business Machines Corp
Priority date: 2002-10-30
Filing date: 2002-10-30
Publication date: 2004-05-06
Also published as: TW200422204A; WO2004040602A3; WO2004040602A2; TWI230662B; US20050207064A1; US7097777B2; EP1556864A2

Abstract

Patterning metal stack layers of a magnetic switching device to enable a critical lithography level to be made on planar substrate without any topography and enable a second lithography step without topography from a top patterned hardmask, comprising:

a) depositing a magnetic tunnel junction stack over oxide layer containing metal transistors surrounded by Cu lines, in which a via connects pinned magnet to at least one metal transistor, forming a bilayer hardmask by depositing layer of TiN on magnetic tunnel junction stack and a layer of W on TiN;

b) patterning a junction of the device by opening a portion of W hardmask over metal transistor with an etch stop on TiN hardmask, depositing a tunnel junction resist and developing a resist feature on top of hardmask;

c) opening the remaining W hardmask and stripping remaining resist and etch residue;

d) performing a metal etch to isolate one device from an adjacent device and depositing anti-reflective coating;

e) transferring resist pattern into the TiN hardmask by opening the TiN hardmask and stripping any remaining resist and etch residue;

f) patterning to isolate one device from an adjacent device to form a memory array by etching a portion of the top layer of the magnetic tunnel junction stack and opening the remaining portion of the TiN hardmask selective to the W hardmask that holds pattern for the device junction; and

g) affecting junction pattern transfer using the W hardmask by performing a tunnel junction etch and capping the magnetic switching device by depositing Al and oxidizing the deposited aluminum to form a layer of Al₂O₃to getter corrosive residuals and passivate metal surface of device from oxidation and/or corrosion.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to magnetic switching devices, and more particularly to a method for patterning metal stack layers of a magnetic switching device utilizing a bilayer metal hardmask patterned in two lithography steps with concommitant hardmask open etch and resist strip steps. The hardmask materials are chosen so that the mask open etch chemistry is designed with good selectivity, thereby enabling patterning of the hardmask layers prior to etching of the metal stack layers.

2. Description of the Related Art

Magnetic random access memory (MRAM or “MagRam”) is a solid state device using magnetic thin film elements as a storage mechanism. The storage mechanism is dependent upon the relative orientation of the magnetization of two electrodes, and on the ability to detect this orientation by electrical means.

MRAM arrays include an array of magnetic memory cells positioned at the intersections of wordlines and bitlines. Generally, each cell includes a magnetically changeable or “free” region, and a nearby magnetic reference region, arranged into a magnetic tunnel junction (“MTJ”) device.

The principle underling storage of data in these memory cells is the ability to change the relative orientation of the magnetization of the free and reference regions by changing the direction of magnetization along the easy axis (“EA”) of the free region, and the ability to read this relative orientation difference thereafter.

An MRAM cell is written by reversing the free region magnetization using applied bi-directional electrical and resultant magnetic stimuli via its receive bitline and wordline.

The MRAM cell is read by measuring the resultant tunneling resistance between the bitline and wordline, which assumes one of two values depending on the relative orientation of the magnetization of the free region with respect to the reference region. If the free region is modeled as a simple elemental magnet having a direction of magnetization which is free to rotate but with a strong preference for aligning in either direction along its easy axis (+EA or −EA), and if the reference region is a similar elemental magnet but having a direction of magnetization fixed in the +EA direction, two states (and the two possible tunneling resistance values) are defined for the cell: aligned (+EA/+EA and an-aligned (−EM +EA).

In operation, the MRAM device can be read by measuring the tunneling resistance, to infer the magnetization state of the storage layer with respect to the fixed layer. The MRAM can be written by reversing free layer magnetization using external magnetic fields. If the free layer is imagined as a simple elemental magnet which is free to rotate but with a strong energetic preference for aligning parallel to the X axis, and if the pinned layer is a similar elemental magnet but frozen in the +X direction, there is then at least two states possible for the device (e.g., aligned and anti-aligned)(i.e., in +X or −X directions).

A wet chemical etch process for patterning MRAM magnetic layers is disclosed in U.S. Pat. No. 6,426,012 B1. The process comprises:

providing a magnetic structure which includes at least one bottom magnetic film layer and at least one top magnetic film layer, wherein the top and bottom magnetic film layers are separated by a tunnel barrier layer, and the at least one top magnetic film layer having a passivating layer formed thereon, the passivating layer including a surface oxide region formed therein;

forming a patterned resist on the passivating layer wherein a portion of the passivating layer is exposed;

removing the surface oxide layer from the exposed portion of the passivating layer by reactive-ion etching;

selectively etching the exposed portion of the passivating layer by a wet etch process which includes an etchant solution comprising an organic acid, a fluoride salt and an inhibitor which prevents pitting and dissolution of the at least one top magnetic film layer whereby a portion of the at least one top magnetic film layer is exposed; and

selectively etching the exposed portion of the at least one top magnetic film layer by a wet etch process which includes a dicarboxylic acid aqueous etchant solution stopping on the tunnel barrier layer.

U.S. Pat. No. 6,256,223 B1 disclose a current-induced magnetic switching device and memory including the same. The memory array comprises:

a plurality of first metal lines;

a plurality of second metal lines perpendicular to the plurality of first metal lines;

a plurality of two-terminal devices respectively provided at intersections of the first and second metal lines, each of the two-terminal devices including:

a pair of back-to-back diodes placed in series with a magnetic junction to allow selective read-addressing; and

a supply cell with a bias current exceeding a positive or negative current threshold (+I _cor −I_c) of the switch, the supply cell forming a same addressing circuit for selective write and read operations;

wherein, with a predetermined I _cand V_cthe I_cof only one junction situated at an intersection of the first and second metal line is selectively exceeded while keeping all other junctions unchanged.

A magnetic tunnel junction with controlled magnetic response is disclosed in U.S. Pat. No. 5,650,958. The device comprises:

a first electrode comprising a planar pinned ferromagnetic layer having first and second parallel surfaces and an antiferromagnetic layer formed on and in contact with the first surface of the pinned ferromagnetic layer, the antiferromagnetic layer pinning the magnetization of the pinned ferromagnetic layer in a preferred direction and preventing its rotation in the presence of an applied magnetic field;

a second electrode having a planar free ferromagnetic layer whose magnetization is free to rotate in the presence of an applied magnetic field;

insulating tunneling layer located between and in contract with the second surface of the pinned ferromagnetic layer of the first electrode and the free ferromagnetic layer of the second electrode for permitting tunneling current in a direction generally perpendicular to the planar pinned and free ferromagnetic layers, the pinned or free ferromagnetic layer having a lateral perimeter that does not extend beyond the lateral perimeter of the insulating tunneling layer, whereby the pinned and free ferromagnetic layers are maintained in separate spaced-apart planes without overlapping the insulating tunneling layer; and

a substrate, the first and second electrodes and tunneling layer being formed on the substrate.

There is a need when making metal stack layers of a magnetic switching device to have the critical lithography level made on a planar surface.

A further need when making metal stack layers of a magnetic switching device is to have the process rely on etch selectivity between metal hardmask layers chosen so as to enable practical process margins.

A further need in the art of providing metal stack layers for magnetic switching devices is to be able to affect reactive ion etching of the metal stack without breaking the vacuum, thereby mitigating the oxidation and/or corrosion from the ambient.

There is a still further need when performing metal stack etching in a process of making magnetic switching devices to do so without polymers present in the etch chamber, so as to mitigate corrosive residuals. Finally, there is a need when preparing metal stack layers for magnetic switching devices to enable formation of Al ₂O₃layers around the magnetic device to getter corrosive residuals and passivate the metal surface from subsequent oxidation and/or corrosion.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a method for patterning metal stack layers of a magnetic switching device to enable the critical lithography level to be made on a planar surface.

Another object of the present invention is to provide a method for patterning metal stack layers of a magnetic switching device, wherein the method relies on etch selectivity between the metal hardmask layers chosen so as to enable practical process margins.

A further object of the present invention is to provide a method for patterning metal stack layers of a magnetic switching device so as to affect reactive ion etching (RIE) of the metal stack without breaking the vacuum, thereby mitigating the oxidation and/or corrosion from the ambient.

A yet further object of the present invention is to provide a method for patterning metal stack layers of a magnetic switching device without the use of polymers present in the etch chamber, so as to mitigate corrosive residuals.

A further object yet still of the present invention is to provide a method for patterning metal stack layers of a magnetic switching device so as to enable formation of Al ₂O₃layers around the magnetic device to getter corrosive residuals and passivate the metal surface from subsequent oxidation and/or corrosion.

In general, the invention method for patterning metal stack layers of a magnetic switching device comprises:

a) depositing a magnetic tunnel junction stack over an oxide layer containing metal transistors surrounded by Cu lines, in which a via connects a pinned magnet to one of the metal transistors, forming a bilayer hardmask by depositing a layer of TiN on the metal tunnel junction stack and a layer of W on the TiN layer;

b) opening a portion of the W hardmask layer over one of said metal transistors with an etch stop on the TiN hardmask layer, depositing an anti-reflective coating (ARC), and depositing a tunnel junction resist;

c) opening the remaining W hardmask layer and stripping the resist;

d) performing a metal etch and depositing an anti-reflective coating to define a pinned magnet of the tunnel junction W hardmask;

e) performing a TiN hardmask open, etching a portion of the TiN hardmask and etching a portion of the top layer of said magnetic tunnel junction stack; and

f) capping the patterned magnetic switching device by depositing Al and oxidizing said deposited Al to form a layer of Al ₂O₃to getter corrosive residuals and passivate the metal surface of said device from oxidation and/or corrosion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a magnetic switching device at a stage following deposition of a magnetic tunnel junction stack over an oxide layer containing metal transistors surrounded by Cu lines, in which a via connects a pinned magnet to one of the metal transistors, after which a bilayer hardmask is formed by depositing a layer of TiN on the metal tunnel junction stack and depositing a layer of W on the TiN layer. [0044]
FIG. 2 depicts a cross-sectional view of the device of FIG. 1 after opening a portion of the W hardmask layer with an etch stop on TiN hardmask and depositing a resist alone or after first depositing an anti-reflection coating (ARC). [0045]
FIG. 3 is a cross-sectional view of the stage in preparing a magnetic switching device in which the W hardmask layer is opened and the resist is stripped. [0046]
FIG. 4 is a cross-sectional view depicting the step in preparing a magnetic switching device by affecting a metal etch and depositing an anti-reflective coating to define a pinned magnet of the tunnel junction W hardmask. [0047]
FIG. 5 is a cross-sectional view showing the step of performing a TiN hardmask open and opening a portion of the W hardmask, after which the resist is stripped. [0048]
FIG. 6 is a cross-sectional view showing a step of preparing the magnetic switching device in which a portion of the TiN hardmask and a portion of the top layer of the magnetic tunnel junction stack are etched. [0049]
FIG. 7 depicts a cross-sectional view showing capping of the patterned magnetic switching device by depositing Al and oxidizing the Al to form a layer of Al[0050] ₂O₃to getter corrosive residuals and passivate the metal surface of the device from oxidation and/or corrosion.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT OF THE INVENTION

Reference is now made to the drawings, in which FIG. 1 depicts a cross-sectional view of a wafer following the blanket deposition of the magnetic metal stack. The magnetic metal stack comprises a buffer layer of TaN/Ta and a pinning layer of PtMn of a thickness of from about 175 to about 375 A, and a pinned magnet of NiFe of a thickness of from about 40 to about 60 A. A tunnel barrier of alumina of a thickness of from about 10 to about 18 A is then formed on the pinned magnetic layer. The final layers are the free magnetic layer which is composed of NiFe (about 40 A) capped with a Ta/TaN layer. [0051]
The method utilizes a bi-layer metal hardmask material to pattern the device in two lithography steps, with concommitant hardmask open etch and resist strip steps. The FIG. 1 stage of preparing metal stack layers of the [0052] magnetic switching device 10 is such that, during processing, the critical lithography level can be made on a planar substrate without any topography.
In the FIG. 1 stage, a magnetic [0053] tunnel junction stack 2 is deposited over an oxide layer 3 containing metal transistors 4 surrounded by Cu lines 5, in which a via 6 connects the pinned magnet P to one of the metal transistors 4. A bi-layer hardmask is formed by depositing a layer of TiN 7 in a thickness of from about 1000 to about 2000 A on the metal tunnel junction stack and a layer of W 8 in a thickness of from about 500 to about 1000 A on the TiN layer.
Proceeding from FIG. 1, FIG. 2, shows the first lithographic step made for patterning the device junction, and illustrates the exposed and developed resist feature on top of the hardmask. This is the critical lithography step since it is used to pattern the device junction and the device parametrics (and tolerance thereof) and is in large part controlled by this pattern transfer step. Further, the fact that the wafer surface is flat allows for the optimal field for exposure. A portion of the W hardmask layer is opened over one of the metal transistors with an etch stop on the TiN hardmask layer, following which an anti-reflective coating (ARC) [0054] 9 is deposited. Next, a resist 11 is deposited on the ARC.
In FIG. 3, the remaining W hardmask layer is opened and the resist [0055] 11 is stripped so as to leave behind a portion of the patterned layer of W 8 from which the resist has been stripped. This first patterning uses fluorinated plasma chemistries in a commercial process tool. Also, the remaining resist and etch residue are stripped with available process chemistries in commercial tools.
Next, as can be seen in FIG. 4 the lithography step is made to etch the magnetic metal stack to isolate one device from the adjacent. At this point the top hardmask (device junction) is patterned and the resist pattern for the device isolation is exposed and developed. A metal etch is performed to complete a tunnel junction W hardmask [0056] 12 followed by depositing an anti-reflection coating 13.
FIG. 5 is a cross-sectional view showing the pattern transfer of this resist pattern into the hardmask, TiN using commercial plasma etch chemistries, such as chlorine-based chemistries commonly used for aluminum etch for chip wiring. The remaining resist and etch residue are also removed using well known processes on these types of process tooling. More specifically, the TiN hardmask is opened to define a [0057] smaller dimension 7′ of the TiN hardmask and open a portion of the W hardmask to a smaller dimension 8′, after which the resist is stripped. Following this step, the wafer is ready for etching the magnetic stack to form the magnetic resistive device.
FIG. 6 illustrates patterning to isolate one device from the adjacent device, to form the memory array wherein chlorine-based etch chemistries are used to etch the magneto-metal stack. Other etch chemistries can also be used. Following the patterning of the magnetic metal stack, the remaining hardmask material (TiN) is removed selective to the W hardmask, that holds the pattern for the device junction. More specifically, FIG. 6 depicts etching portions of the top layer of the magnetic [0058] tunnel junction stack 2 to arrive at the dimension 2′ and opening a portion of the TiN hardmask to arrive at a lesser dimension of the TiN hardmask 7″.
FIG. 7 shows the junction pattern transfer using the W hardmask. At this point the device is formed and subsequent processing to clean the wafer and deposit dielectric insulator materials into which is fabricated metal lines and contacts for the purpose of making electrical wiring between devices is made. Also included, as shown in the enlargement of FIG. 7A is the passivation layer (alumina) for the purpose of reducing sidewall leakage. More particularly, etching of the top and bottom layers of the [0059] tunnel junction stack 2′ and 2″ as well as sidewall passivation is shown in FIG. 7. An enlarged depiction of the bi-layer hardmask after etching of the tunnel junction stack and sidewall passivation is shown in FIG. 7A. In this connection, it should be noted that ion milling may be performed through the magnetic tunnel junction and Al may be utilized to cap the device followed by oxidation to provide Al₂O₃around the patterned metal stack layers of the magnetic switching device, utilizing a bi-layer metal hardmask.
The method described utilizes a bilayer metal hardmask patterned in two lithography steps with concommitant hardmask open etch and resist strip steps. The hardmask materials are chosen (W and TiN) such that mask open etch chemistry may be designed with good selectivity. This enables patterning of the hardmask layers prior to etching of the metal stack layers. [0060]
Several advantages are inherent with this approach. First, the critical lithography level can be made on planar substrates without any topography. The second lithography step sees only little topography from the top patterned hardmask which can be planarized with application of a standard organic ARC. [0061]
Another advantage inherent in the invention method is that the metal stack layers can be etched in one process sequence without exposure to ambient conditions. This is significant in that reaction of ambient water vapor with chlorinated etch byproducts is a standard problem with Cl-based metal etching and reducing or eliminating this problem significantly improves the process yield. [0062]
A final process of capping with deposited aluminum and subsequent formation of Al[0063] ₂O₃around the patterned device is made herein. Thus, gettering of corrosive residuals, and device sidewall passivation enable functional device improvements.
In summary, the advantages of the invention method for formation of the magnetic switching device are: [0064]
1.) the critical lithography level is made on a planar surface; [0065]
2.) the process relies on etch selectivity between the two metal hardmask layers, tungsten and titanium nitride, chosen as an example, to enable practical margins; [0066]
3.) the reactive ion etching of the metal stack is done without breaking the vacuum, thereby mitigating the oxidation and/or corrosion from the ambient. [0067]
4.) the metal stack etch is made without polymers present in the etch chamber, thereby mitigating corrosive residuals; and [0068]
5.) the method is used for formation of Al[0069] ₂O₃layer around the magnetic device to getter corrosive residuals and passivate the metal surface from subsequent oxidation and/or corrosion.

Claims

What is claimed is:

1. A method of patterning metal stack layers of a magnetic switching device to enable the critical lithography level to be made on a planar substrate without any topography and enable a second lithography step substantially without topography from a top patterned hardmask, comprising:

a) depositing a magnetic tunnel junction stack over an oxide layer containing metal transistors surrounded by Cu lines, in which a via connects a pinned magnet to at least one metal transistor, forming a bilayer hardmask by depositing a layer of TiN on the magnetic tunnel junction stack and a layer of W on the TiN layer;

b) patterning a junction of said device by opening a portion of the W hardmask layer over said metal transistor with an etch stop on the TiN hardmask layer, depositing an anti-reflective coating (ARC), depositing a tunnel junction resist and developing a resist feature on top of said hardmask;

c) opening the remaining W hardmask layer and stripping any remaining resist and etch residue;

d) performing a metal etch to isolate one device from an adjacent device and depositing an anti-reflective coating;

e) transferring the resist pattern into the TiN hardmask by opening the TiN hardmask and stripping any remaining resist and etch residue;

f) patterning to isolate one device from an adjacent device to form a memory array by etching a portion of the top layer of the magnetic tunnel junction stack and opening the remaining portion of the TiN hardmask selective to the W hardmask that holds the pattern for the device junction; and

g) affecting the junction pattern transfer using the W hardmask by performing a tunnel junction etch and capping the magnetic switching device by depositing Al and oxidizing said deposited aluminum to form a layer of Al₂O₃to getter corrosive residuals and passivate the metal surface of the device from oxidation and/or corrosion.

2. The method of claim 1 wherein in step a) said magnetic tunnel junction stack comprises a buffer layer of TaN/Ta, a pinning layer of PtMn, and a pinned magnet of NiFe.

3. The method of claim 2 wherein a tunnel barrier of alumina is formed on said pinned magnet.

4. The method of claim 3 wherein a free magnetic layer of NiFe is formed over said tunnel barrier of alumina.

5. The method of claim 4 wherein said free magnetic layer of NiFe is capped with a layer of Ta/TaN.

6. The method of claim 2 wherein said pinned layer of PtMn is of thickness of from between about 175 to about 375 Å.

7. The method of claim 6 wherein said pinned magnet of NiFe is of a thickness of from about 40 to about 60 A.

8. The method of claim 7 wherein said tunnel barrier of alumina is of a thickness of from about 10 to about 18 Å.

9. The method of claim 8 wherein said TiN hardmask layer is of a thickness of from about 1000 to about 2000 Å.

10. The method of claim 9 wherein said W hardmask layer is of a thickness of from about 1000 to about 2000 Å.