US20040183064A1 - Single electron devices - Google Patents

Single electron devices Download PDF

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US20040183064A1
US20040183064A1 US10/814,292 US81429204A US2004183064A1 US 20040183064 A1 US20040183064 A1 US 20040183064A1 US 81429204 A US81429204 A US 81429204A US 2004183064 A1 US2004183064 A1 US 2004183064A1
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forming
single electron
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Lars Ivar Samuelson
Knut Wilfried Deppert
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BTG International Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
    • C30B29/605—Products containing multiple oriented crystallites, e.g. columnar crystallites
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/7613—Single electron transistors; Coulomb blockade devices

Definitions

  • This invention relates to electronic components and, in particular, to so-called single-electron devices and to methods of manufacture thereof.
  • tunnel junction which consists of two electrodes of a conducting material, separated by a thin layer of an insulating material having a thickness of about one nanometre.
  • insulating material having a thickness of about one nanometre.
  • electrons have a small probability of tunnelling through such an insulating layer. If a voltage is applied across the junction, electrons will tunnel preferentially in one particular direction through the insulator. Hence, they will carry an electric current through the junction. The magnitude of the current depends on both the thickness of the insulating layer and the material properties of the conducting electrodes.
  • tunnel junctions must be of a very small area and cooled to ensure that the thermal energy does not influence tunnelling.
  • the device must be cooled to temperatures of about a tenth of a degree above absolute zero if the junction is 100 nanometres in length and width.
  • European Patent Application EP 0 750 353 discloses a single electron tunnel device of this invention which includes a multiple tunnel junction layer including multiple tunnel junctions; and first and second electrodes for applying a voltage to the multiple tunnel junction layer, wherein the multiple tunnel junction layer includes an electrically insulating thin film and metal particles and/or semiconductor particles dispersed in the electrically insulating thin film.
  • the electrically insulating thin film may be made of an oxide and the particles may be of at least one type of metal selected from the group consisting of gold (Au), silver (Ag), copper (Cu), platinum (Pt), and palladium (Pd).of the particles. Their diameter may be 50 nm or less.
  • a single electron tunnelling device comprising a particle of a material having a first conductivity characteristic having a surface layer of a material of a second conductivity characteristic, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough together with first and second electrodes positioned adjacent to said particle to facilitate the flow of current therebetween.
  • Said first and second electrodes may be superconducting.
  • a plurality of such particles is positioned between said first and second electrodes.
  • a method of fabricating single electron devices comprising the steps of forming a plurality of particles forming a layer of a thickness sufficiently small to support quantum mechanical tunnelling on the surface of said particles and positioning at least one of said particles between a pair of electrodes to form a single electron device.
  • FIG. 1 is a flow chart illustrating the method according to one aspect of the present invention
  • FIG. 2 is shows in schematic form apparatus for producing nanocrystals suitable for use for the fabrication of single-electron devices
  • FIG. 3 shows the structure of various nanoparticles
  • FIG. 4 is a micrograph of a nanocrystal produced by the process of aerotaxy
  • FIG. 5 is a schematic diagram of a prior art tunnel junction
  • FIG. 6 is a schematic diagram showing a barrier between a nanoparticle and a conducting substrate
  • FIG. 7 is a diagram illustrating the principle of movement of a nanoparticle by means of an atomic force microscope.
  • FIGS. 8 a and 8 b are schematic diagrams illustrating the principles of device construction in accordance with the invention
  • FIG. 1 of the drawings illustrates a process for controlled formation of simple and multi-layered metallic and semiconducting nanocrystals or nanoparticles suitable for single electron device fabrication.
  • Ultra-fine particles of a Group III element are formed as an aerosol. These are then filtered to select those of a predetermined size.
  • a Group V precursor is then added and the mixture processed to form nanocrystals of a III-V semiconductor.
  • FIG. 2 shows an aerosol production unit in accordance with a specific embodiment of the invention.
  • This comprises a furnace F 1 which generates metallic particles by sublimation. These particles are then carried in a transport gas stream through a charger to a particle size filter DMA 1 and thence to a second furnace F 2 where the gas stream is mixed with the hydride of a Group V element and heated to form nanoparticles of a II-V semiconductor.
  • the nanocrystals are then filtered to select those of a predetermined size which are then deposited on to a substrate, which, preferably is a semiconducting wafer. in a deposition chamber DC.
  • An electrometer E 1 and pump Pu are connectable to the flow line to create and measure the pressure therein.
  • a semiconducting core nanocrystal is coated by a surface layer of a material with different properties, e.g. with a larger fundamental band-gap, fabricating nanocrystals, the composition and size of which is tightly controlled.
  • the approach is unusual in that we have managed to form, in an aerosol phase, metallic nanoparticles (or droplets) having a narrow dimensional spread.
  • the particles of elements from the third column in the periodic table are later allowed to react with a vapour containing selected atoms or molecules from the fifth column in the periodic table, resulting in the production of nanocrystals of III-V semiconductors of uniform size.
  • This control requires a completely saturated conversion of the primary metallic nanoparticle into the corresponding III-V nanocrystal.
  • Gallium arsenide nanocrystals of approximate diameter 10 nm, have been produced and deposited on various substrates.
  • the fabrication route allows the production of nanocrystals with a very narrow size distribution. It utilises the formation of ultrafine gallium particles and their self-limiting reaction with arsine at elevated temperatures.
  • the kinetics of the reaction of gallium to produce gallium arsenide depends on the temperature and the arsine flow. The temperature at which the reaction began was found to be as low as 200° C. This permitted the production of nanocrystals of compound semiconductors of predeternined size in a simple, reliable, and efficient way.
  • An important feature of a further embodiment of this invention is a new technique for controllable formation of a surface layer of a different semiconducting or insulating material on these original nanocrystals. They may have a homogeneous core and a surface layer of a second composition with an appropriate electronic structure for the single-electron device operation.
  • the semiconducting or metallic nanocrystal is exposed to a reacting gas environment while being maintained in the aerosol phase.
  • a mono-disperse aerosol of silicon nanocrystals is allowed to react with oxygen under closely controlled conditions, leading to a controlled thickness of the silicon particle being converted to silica.
  • SiO 2 is an insulator with ideal and well characterised interfaces with silicon.
  • mono-disperse nanocrystals of compound semiconductors such as indium arsenide
  • phosphorus-containing gaseous molecules an interaction which results in exchange processes by which arsenic atoms in a finite depth surface layer are replaced by phosphorus atoms, hence transforming the surface to a surface layer of In(As)P.
  • pre-fabricated nanoparticles of indium react with oxygen to form a skin of InO.
  • the simplest single-electronic building block is formed by producing a homogenous particle, exemplified by a spherical monodisperse particle shown in FIG. 3.
  • the second embodiment involves direct epitaxial deposition of a different material on the surface of a primary core, often called hetero-epitaxy.
  • a different material on the surface of a primary core, often called hetero-epitaxy.
  • the art of hetero-epitaxy on flat surfaces is at a very advanced stage but the use of nanoparticles as “substrates” for aerosol-phase epitaxial crystal growth is very novel.
  • nanoparticles in single-electronics however, this is of great importance. Examples are the coating of a small band-gap semiconductor with a thin epitaxial layer of a larger band-gap material, such as indium phosphide on the surface of indium arsenide or silicon on the surface of a core of germanium.
  • FIG. 4 is a TEM image of an 8 nm indium phosphide particle produced by the process of aerotaxy.
  • the diameter for room temperature operation should be in the range 2-4 nm, corresponding to charging energy of a few hundred meV, to be compared with kT ( ⁇ 26 meV at room temperature).
  • the distances between conducting leads and conducting particle, and the distance between connected particles should support tunnelling, that is it should be in the range 1-3 nm.
  • FIG. 5 illustrates a conventional thin film tunnel junction device.
  • the surface of a deposited film 11 is oxidise to form a thin tunnel barrier 13 and a further conductor 15 is deposited thereon.
  • An analogous device based on a small metallic particle is illustrated in FIG. 6.
  • a thin oxide layer 17 is formed on a conductive substrate 19 .
  • small metallic particle 21 is positioned thereon.
  • Contact is made by means of the tip of a scanning tunnelling microscope 23 .
  • FIG. 7 This principle is extended in the device illustrated in FIG. 7 in which a small metallic particle 25 is positioned between a source electrode 27 and a drain electrode 29 by means of an atomic force microscope.
  • a key feature of one aspect of the present invention is the prefabrication of particles in such a way that they provide the conducting core as well as tightly controlled tunnel-gap, building a network of identical capacitances and tunnelling rates permits randomness in lateral location within an ensemble of nano-particles.
  • FIGS. 8 a and 8 b show a two-dimensional arrangement of nano-particles P between two electrodes E 1 , E 2 with non-identical (FIG.8 a ) vs identical cores (FIG. 8 b ) as well as with random vs well-controlled tunnel barriers 31 .
  • the tunnel barrier in most cases is exactly twice the shell thickness, in two-dimensional as well as three-dimensional randomly arranged arrays.
  • the key feature is that, due to nature of the single-electron tunnelling characteristic, for a macroscopic device the number of nanoparticles (in either two or tlree dimensions) between the electrodes is not critical.

Abstract

A single electron tunnelling device is formed by positioning between first and second electrodes a particle formed of a material having a first conductivity characteristic having a surface layer of a material of a second conductivity characteristic, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough.

Description

  • This invention relates to electronic components and, in particular, to so-called single-electron devices and to methods of manufacture thereof. [0001]
  • The field of single electron devices emerged from investigations of the tunnel junction, which consists of two electrodes of a conducting material, separated by a thin layer of an insulating material having a thickness of about one nanometre. According to the laws of quantum mechanics, electrons have a small probability of tunnelling through such an insulating layer. If a voltage is applied across the junction, electrons will tunnel preferentially in one particular direction through the insulator. Hence, they will carry an electric current through the junction. The magnitude of the current depends on both the thickness of the insulating layer and the material properties of the conducting electrodes. [0002]
  • In early 1985, Averin and Likharev attempted to predict the behaviour of very small tunnel junctions with superconducting electrodes but the equations were too complex to be easily solved. However, for a small tunnel junction with electrodes of normal conductors, if a constant electric current is passed through a junction, it will induce a voltage that oscillates periodically in time. These periodic oscillations have a frequency equal to the current divided by the charge of an electron. This frequency is totally independent of any other parameters of the system. An alternative view is that each oscillation represents the response of the device as a single electron tunnels through the insulating layer. The phenomenon is known as single-electron tunnelling (SET) oscillations. [0003]
  • To understand this effect, one must appreciate how electric charge moves through a normal conductor such as an aluminium wire. An electric current can flow through the conductor because some electrons are free to move through the lattice of atomic nuclei. Despite the motion of the electrons, any given volume of the conductor has virtually no net charge because the negative charge of the moving electrons is always balanced by the positive charge of the atomic nuclei in each small region of the conductor. Hence, the important quantity is not the charge in any given volume but rather how much charge has been carried through the wire. This quantity is designated as the “transferred” charge. This charge may take practically any value, even a fraction of the charge of a single electron. The reason for this is that charge is proportional to the sum of shifts of all the electrons with respect to the lattice of atoms. Because the electrons in a conductor can be shifted as little or as much as desired, this sum can be changed continuously, and therefore so can the transferred charge. [0004]
  • If a normal conductor is interrupted by a tunnel junction, electric charge will move through the system by both a continuous and a discrete process. As the transferred charge flows continuously through the conductor, it will accumulate on the surface of the electrode against the insulating layer of the junction (the adjacent electrode will have equal but opposite surface charge). This surface charge Q may be represented as a slight continuous shift of the electrons near the surface from their equilibrium positions. On the other hand, quantum mechanics shows that the tunnelling can only change Q in a discrete way: when an electron tunnels through the insulating layer, the surface charge Q will change exactly by either +e or −e, depending on the direction of tunnelling. The interplay between continuous charge flow in conductors and discrete transfer of charge through tunnel junctions leads to several interesting effects. These phenomena can be observed when the tunnel junctions are very small and the ambient temperatures are very low. (Low temperatures reduce thermal fluctuations that disturb the motion of electrons.) In this case, if the charge Q at the junction is greater than +e/2, an electron can tunnel through the junction in a particular direction, subtracting e from Q. The electron does so because this process reduces the electrostatic energy of the system. (The energy increases in proportion to the square of the charge and does not depend on the sign of the charge.) Likewise, if Q is less than −e/2, an electron can tunnel through the junction in the opposite direction, adding e to Q, and thus again decrease the energy. But if Q is less than +e/2 and greater than −e/2, tunnelling in any direction would increase the energy of the system. Thus, if the initial charge is within this range, tunnelling will not occur. This suppression of tunnelling is known as the Coulomb blockade. [0005]
  • If the surface charge Q is zero initially, then the system is within the Coulomb blockade limits, and tunnelling is suppressed. Therefore, the current flowing from the source through wires will start to change the charge Q continuously. For convenience, assume that the deposited charge rate is positive rather than negative. If the charge reaches and slightly exceeds +e/ 2, tunnelling becomes possible. One electron will then cross the junction, making its charge slightly greater than −e/2. Hence, the system is within the Coulomb blockade range again, and tunnelling ceases to be possible. The current continues to add positive charge to the junction at a constant rate, and Q grows until it exceeds +e/2 again. The repetition of this process produces the single-electron tunnelling (SET) oscillations: the voltage changes periodically with a frequency equal to the current divided by the fundamental unit of charge, e: [0006]
  • To produce SET oscillations, tunnel junctions must be of a very small area and cooled to ensure that the thermal energy does not influence tunnelling. Typically, the device must be cooled to temperatures of about a tenth of a degree above absolute zero if the junction is 100 nanometres in length and width. [0007]
  • European Patent Application EP 0 750 353 discloses a single electron tunnel device of this invention which includes a multiple tunnel junction layer including multiple tunnel junctions; and first and second electrodes for applying a voltage to the multiple tunnel junction layer, wherein the multiple tunnel junction layer includes an electrically insulating thin film and metal particles and/or semiconductor particles dispersed in the electrically insulating thin film. [0008]
  • The electrically insulating thin film may be made of an oxide and the particles may be of at least one type of metal selected from the group consisting of gold (Au), silver (Ag), copper (Cu), platinum (Pt), and palladium (Pd).of the particles. Their diameter may be 50 nm or less. [0009]
  • Fabrication of suitable structures to support single electron tunnelling has proved difficult. In particular, it has proved difficult to form films having the size and disposition which are suitable for tunnelling. However, we have now devised a method suitable for the fabrication of arrays of these devices. [0010]
  • According to one aspect of the present invention there is provided a single electron tunnelling device comprising a particle of a material having a first conductivity characteristic having a surface layer of a material of a second conductivity characteristic, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough together with first and second electrodes positioned adjacent to said particle to facilitate the flow of current therebetween. [0011]
  • Said first and second electrodes may be superconducting. [0012]
  • In a preferred embodiment of the invention a plurality of such particles is positioned between said first and second electrodes. [0013]
  • There is also provided a method of fabricating single electron devices comprising the steps of forming a plurality of particles forming a layer of a thickness sufficiently small to support quantum mechanical tunnelling on the surface of said particles and positioning at least one of said particles between a pair of electrodes to form a single electron device.[0014]
  • The invention will be particularly described by way of example with reference to the accompanying drawings, in which [0015]
  • FIG. 1 is a flow chart illustrating the method according to one aspect of the present invention; [0016]
  • FIG. 2 is shows in schematic form apparatus for producing nanocrystals suitable for use for the fabrication of single-electron devices; [0017]
  • FIG. 3 shows the structure of various nanoparticles; [0018]
  • FIG. 4 is a micrograph of a nanocrystal produced by the process of aerotaxy [0019]
  • FIG. 5 is a schematic diagram of a prior art tunnel junction [0020]
  • FIG. 6 is a schematic diagram showing a barrier between a nanoparticle and a conducting substrate; [0021]
  • FIG. 7 is a diagram illustrating the principle of movement of a nanoparticle by means of an atomic force microscope; and [0022]
  • FIGS. 8[0023] a and 8 b are schematic diagrams illustrating the principles of device construction in accordance with the invention
  • Referring now to FIG. 1 of the drawings, this illustrates a process for controlled formation of simple and multi-layered metallic and semiconducting nanocrystals or nanoparticles suitable for single electron device fabrication. Ultra-fine particles of a Group III element are formed as an aerosol. These are then filtered to select those of a predetermined size. A Group V precursor is then added and the mixture processed to form nanocrystals of a III-V semiconductor. [0024]
  • FIG. 2 shows an aerosol production unit in accordance with a specific embodiment of the invention. This comprises a furnace F[0025] 1 which generates metallic particles by sublimation. These particles are then carried in a transport gas stream through a charger to a particle size filter DMA1 and thence to a second furnace F2 where the gas stream is mixed with the hydride of a Group V element and heated to form nanoparticles of a II-V semiconductor. The nanocrystals are then filtered to select those of a predetermined size which are then deposited on to a substrate, which, preferably is a semiconducting wafer. in a deposition chamber DC. An electrometer E1 and pump Pu are connectable to the flow line to create and measure the pressure therein.
  • In one embodiment, a semiconducting core nanocrystal is coated by a surface layer of a material with different properties, e.g. with a larger fundamental band-gap, fabricating nanocrystals, the composition and size of which is tightly controlled. The approach is unusual in that we have managed to form, in an aerosol phase, metallic nanoparticles (or droplets) having a narrow dimensional spread. The particles of elements from the third column in the periodic table are later allowed to react with a vapour containing selected atoms or molecules from the fifth column in the periodic table, resulting in the production of nanocrystals of III-V semiconductors of uniform size. This control requires a completely saturated conversion of the primary metallic nanoparticle into the corresponding III-V nanocrystal. [0026]
  • Gallium arsenide nanocrystals, of approximate diameter 10 nm, have been produced and deposited on various substrates. The fabrication route allows the production of nanocrystals with a very narrow size distribution. It utilises the formation of ultrafine gallium particles and their self-limiting reaction with arsine at elevated temperatures. The kinetics of the reaction of gallium to produce gallium arsenide depends on the temperature and the arsine flow. The temperature at which the reaction began was found to be as low as 200° C. This permitted the production of nanocrystals of compound semiconductors of predeternined size in a simple, reliable, and efficient way. [0027]
  • An important feature of a further embodiment of this invention is a new technique for controllable formation of a surface layer of a different semiconducting or insulating material on these original nanocrystals. They may have a homogeneous core and a surface layer of a second composition with an appropriate electronic structure for the single-electron device operation. [0028]
  • After a size selection, the semiconducting or metallic nanocrystal is exposed to a reacting gas environment while being maintained in the aerosol phase. In one embodiment, a mono-disperse aerosol of silicon nanocrystals is allowed to react with oxygen under closely controlled conditions, leading to a controlled thickness of the silicon particle being converted to silica. SiO[0029] 2 is an insulator with ideal and well characterised interfaces with silicon. In a second embodiment, mono-disperse nanocrystals of compound semiconductors, such as indium arsenide, are allowed to interact with phosphorus-containing gaseous molecules, an interaction which results in exchange processes by which arsenic atoms in a finite depth surface layer are replaced by phosphorus atoms, hence transforming the surface to a surface layer of In(As)P. In a third embodiment, pre-fabricated nanoparticles of indium react with oxygen to form a skin of InO. In this embodiment, the simplest single-electronic building block is formed by producing a homogenous particle, exemplified by a spherical monodisperse particle shown in FIG. 3.
  • The second embodiment involves direct epitaxial deposition of a different material on the surface of a primary core, often called hetero-epitaxy. The art of hetero-epitaxy on flat surfaces is at a very advanced stage but the use of nanoparticles as “substrates” for aerosol-phase epitaxial crystal growth is very novel. For the application of nanoparticles in single-electronics, however, this is of great importance. Examples are the coating of a small band-gap semiconductor with a thin epitaxial layer of a larger band-gap material, such as indium phosphide on the surface of indium arsenide or silicon on the surface of a core of germanium. Finally there is a hetero-epitaxy based mechanism for formation of semiconductor particles surrounded by very well controlled insulating layers, which can be achieved by surrounding a nanocrystal of gallium arsenide (for example) with a few monolayers of epitaxially grown aluminium arsenide. At a late stage, this aluminium arsenide layer is allowed to react with oxygen to form a layer of aluminium oxide, most probably Al[0030] 2O3, which is an excellent insulator. Hence, the ideal hetero-expitaxial process will lend itself indirectly to the formation of a few mono-layer-thick insulating layer on semiconductor particles. (FIG. 3)
  • FIG. 4 is a TEM image of an 8 nm indium phosphide particle produced by the process of aerotaxy. [0031]
  • In the mechanism of single-electron devices, the most important fundamental property is the existence of a central conductive island which is coupled by tunnelling to source and drain electrodes and coupled capacitively to a gate electrode. The size-related capacitance of the central island should be sufficiently low that the electrostatic charging energy E=e[0032] 2/2C is much larger than kT and in an energy range suitable for device and circuit biasing. The dimensional requirements can be described as:
  • for particle size, the diameter for room temperature operation should be in the range 2-4 nm, corresponding to charging energy of a few hundred meV, to be compared with kT (˜26 meV at room temperature). [0033]
  • for tunnelling gaps, the distances between conducting leads and conducting particle, and the distance between connected particles should support tunnelling, that is it should be in the range 1-3 nm. [0034]
  • In most prior demonstrations of single-electron phenomena, low temperatures at or below liquid helium boiling temperature (4K) have been employed. The tolerance for lithographic definition of the island size is much relaxed. In these studies, tunnelling distances are often defined by an aluminium film, which is converted by controlled oxidation into an insulating thin film, placed in between the conductors. [0035]
  • Experiments performed at elevated temperatures, such as the boiling point of liquid nitrogen (77K) or at room-temperature (300K) have been performed with the use of small metallic (or semiconducting) particles but with the tunnelling distances controlled by a thin insulating film on which the particle rests and, for the second electrode spacing, by a tunnelling distance which is controlled by a scanning tunnelling microscope. [0036]
  • We have been able to fabricate planar single-electron devices which are controllably created by a “nano-robot”, an atomic force microscope (AFM), by manipulation of size-selected nanometre sized particles relative to pre-fabricated contacts. In this approach capacitances are accurately controlled by the exact particle fabrication (by aerosol technique) and tunnelling gaps are governed by the controlled positioning of the nano-particles to create the proper tunnelling current levels. [0037]
  • FIG. 5 illustrates a conventional thin film tunnel junction device. The surface of a deposited [0038] film 11 is oxidise to form a thin tunnel barrier 13 and a further conductor 15 is deposited thereon. An analogous device based on a small metallic particle is illustrated in FIG. 6. A thin oxide layer 17 is formed on a conductive substrate 19. and small metallic particle 21 is positioned thereon. Contact is made by means of the tip of a scanning tunnelling microscope 23. This principle is extended in the device illustrated in FIG. 7 in which a small metallic particle 25 is positioned between a source electrode 27 and a drain electrode 29 by means of an atomic force microscope.
  • A key feature of one aspect of the present invention is the prefabrication of particles in such a way that they provide the conducting core as well as tightly controlled tunnel-gap, building a network of identical capacitances and tunnelling rates permits randomness in lateral location within an ensemble of nano-particles. [0039]
  • The significance of the above aerosol-based fabrication of granular single-electron circuits is illustrated in FIGS. 8[0040] a and 8 b which show a two-dimensional arrangement of nano-particles P between two electrodes E1, E2 with non-identical (FIG.8a) vs identical cores (FIG. 8b) as well as with random vs well-controlled tunnel barriers 31. The tunnel barrier in most cases is exactly twice the shell thickness, in two-dimensional as well as three-dimensional randomly arranged arrays. The key feature is that, due to nature of the single-electron tunnelling characteristic, for a macroscopic device the number of nanoparticles (in either two or tlree dimensions) between the electrodes is not critical.

Claims (57)

1. A single electron tunnelling device comprising a particle together with first and second electrodes positioned adjacent to said particle to facilitate the flow of current therebetween characterised in that said particle is formed of a material having a first conductivity characteristic having a surface layer of a material of a second conductivity characteristic, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough.
2. A single electron tunnelling device according to claim 1 characterised in that said device includes a plurality of said particles to define a current path between said first and second electrodes.
3. A single electron tunnelling device according to claim 1 characterised in that said material having said first conductivity characteristic is substantially homogenous.
4. A single electron tunnelling device according to any one of claims 1 to 3 characterised in that said surface layer is semiconducting.
5. A single electron tunnelling device according to any one of claims 1 to 3 characterised in that said surface layer is insulating.
6. A single electron tunnelling device according to claim 1 characterised in that said surface layer is gallium arsenide.
7. A single electron tunnelling device according to claim 1 characterised in that said surface layer is indium oxide.
8. A single electron tunnelling device according to claim 1 characterised in that said surface layer is indium arsenide phosphide.
9. A single electron tunnelling device according to claim 1 characterised in that said surface layer is silica.
10. A method of fabricating single electron devices comprising the steps of forming a plurality of particles forming a layer of a thickness sufficiently small to support quantum mechanical tunnelling on the surface of said particles and positioning at least one of said particles between a pair of electrodes to form a single electron device.
11. A method of fabricating single electron devices according to claim 10 characterised in that a further step of selecting particles of predetermined size takes place prior to the step of forming said layer.
12. A method of fabricating single electron devices according to claim 10 or 11 characterised in that said plurality of particles is formed as an aerosol.
13. A method of fabricating single electron devices according to claim 10 or 11 characterised in that said layer is formed by the chemical modification of the surface of said particles.
14. A method of fabricating single electron devices according to claim 10 or 11 characterised in that said layer is formed by the expitaxial deposition of a material on the surface of said particles.
15. A method of fabricating single electron devices according to claim 10 characterised in that the positioning of said particle is performed by means of an atomic force microscope.
16. A method of fabricating a single electron device comprising the steps:
forming a plurality of particles;
forming on the surface of each particle a peripheral layer of a thickness sufficiently small to support quantum mechanical tunnelling therethrough;
providing a pair of electrodes and positioning at least one of said particles between said pair of electrodes to form a single electron device.
17. A method of fabricating a single electron device according to claim 16, wherein a further step of selecting particles of predetermined size takes place prior to the step of forming said peripheral layer.
18. A method of fabricating a single electron device according to claim 16, wherein said plurality of particles is formed as an aerosol.
19. A method of fabricating a single electron device according to claim 16, wherein said peripheral layer is formed by chemical modification of the surface of each of said particles.
20. A method of fabricating a single electron device according to claim 16, wherein said peripheral layer is formed by the epitaxial deposition of a material on the surface of each of said particles.
21. A method of fabricating a single electron device according to claim 16, wherein the positioning of said particle is performed by means of an atomic force microscope.
22. A method of forming a single electron tunnelling device comprising:
forming a particle of a material having a first conductivity characteristic, forming on the particle a semiconducting surface layer of a second conductivity characteristic, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough; and
positioning said particle between first and second electrodes to provide a current path between the electrodes.
23. A method of forming a single electron tunnelling device, comprising:
forming a particle of a material having a first conductivity characteristic;
forming on the surface of the particle a surface layer of gallium arsenide, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough; and
positioning said particle between first and second electrodes to provide a current path therebetween.
24. A method of forming a single electron tunnelling device, comprising:
forming a particle of a material having a first conductivity characteristic;
forming on the surface of the particle a peripheral layer of indium oxide, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling there through;
positioning said particle between first and second electrodes to provide a current path therebetween.
25. A method of forming a single electron tunnelling device, comprising:
forming a particle of a material having a first conductivity characteristic;
forming on the surface of the particle a peripheral layer of indium arsenide phosphide, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough;
positioning said particle between first and second electrodes to provide a current path therebetween.
26. A method of forming a single electron tunnelling device, comprising:
forming a particle of a material having a first conductivity characteristic;
forming on the surface of the particle a peripheral layer of silica, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough;
positioning said particle between first and second electrodes to provide a current path therebetween.
27. A method forming an electronic device, comprising:
forming at least one nanoparticle having an inner core of a conductive material of predetermined size of nanometer dimensions;
forming on the inner core, an outer shell of a controlled thickness of nanometer dimensions and of a further material which is different from that of the inner core; and
providing first and second electrodes, and providing a current flow path therebetween comprising said at least one particle, the characteristics of current flow in the current flow path being determined by electron tunnelling via said outer shell and inner core.
28. A method according to claim 27, wherein said further material is insulating.
29. A method according to claim 28, wherein said further material is an oxide of one of: silicon, indium, aluminium.
30. A method according to claim 27, wherein said further material is semiconducting.
31. A method according to claim 30, wherein said semiconducting material contains one of the following:
indium, silicon.
32. A method according to claim 27, wherein said conductive material contains one of:
silicon, germanium, indium, gallium.
33. A method according to claim 27, comprising providing a multiplicity of said nanoparticles stacked adjacent one another whereby to provide said current flow path.
34. A method of forming a nanocrystal in the form of a particle that is defined by a size of nanometer dimensions, the method comprising:
forming, in an aerosol, a core particle of an electrically conductive material and having a size of predetermined nanometer dimensions; and
forming epitaxially on the core particle, by the action of gas on the aerosol, an outer shell of a further material that is different from that of the core, and having a controlled thickness of nanometer dimensions.
35. A method according to claim 34 wherein said conductive material contains one of:
silicon, germanium, indium, gallium.
36. A method according to claim 34, wherein said further material is semiconducting.
37. A method according to claim 34, wherein said conductive material contains one of the following:
indium, germanium, gallium;
and said further material is semiconducting and comprises one of the following:
indium, silicon, aluminium.
38. A method of forming a nanocrystal in the form of a particle that is defined by a size of nanometer dimensions, the method comprising:
forming in an aerosol, a core particle of an electrically conductive material and having a size of predetermined nanometer dimensions; and
exposing the gas to an aerosol, the gas reacting with the surface of the core particle to form an outer shell of a further material that is different from the material of the core particle, and that has a controlled thickness of nanometer dimensions.
39. A method according to claim 38, wherein the gas reacts with the surface of the core particle to form an oxide of the core material.
40. A method according to claim 39, wherein the core particle contains one of: silicon, indium.
41. A method according to claim 38, wherein the gas reacts with the surface of the core particle by an exchange process, wherein atoms in the surface of the core particle are exchanged for atoms in the gas.
42. A method.according to claim 41, wherein the core material is a compound semiconductor, and the gas comprises molecules containing phosphorus.
43. A method according to claim 42, wherein the core material comprises indium arsenide, and arsenic atoms are replaced by phosphorus atoms.
44. A method of forming a nanocrystal in the form of a particle that is defined by a size of nanometer dimensions, the method comprising:
forming from an aerosol, a core particle of an electrically conductive material and having a size of predetermined nanometer dimensions; and
forming epitaxially on the core, by the action of gas on the aerosol, an outer shell of a further material that is different from that of the core, and having a controlled thickness of nanometer dimensions; and
reacting the outer shell to form an oxide of the further material.
45. A method according to claim 44, wherein the conductive material is gallium arsenide, the further material is aluminium arsenide, and said oxide is aluminium oxide.
46. A method of forming nanocrystals comprising:
a) forming an aerosol of particles of a predetermined conductive material and diameters of nanometer dimensions;
b) filtering said aerosol of particles to provide particles with a narrow predetermined spread of diameters; and
c) processing the filtered aerosol with a vapour of a material in order to form a shell of a further material on each aerosol particle and of a controlled thickness, said further material being different from said predetermined conductive material.
47. A method according to claim 46, wherein said processing in step c) comprises forming by an epitaxial process said shell.
48. A method according to claim 47, wherein said conductive material contains one of:
indium, germanium, gallium;
and said further material includes one of:
indium,silicon, aluminium.
49. A method according to claim 46, including the further step of reacting the further material of the outer shell to form an oxide.
50. A method according to claim 49, wherein said inner core comprises gallium arsenide, said further material comprises aluminium arsenide, and said oxide comprises aluminium oxide.
51. A method according to claim 46, wherein in said step c) said vapour reacts with the surface of the particle in order to form said shell by modification of the surface of the particle.
52. A method according to claim 51, wherein the modification is an exchange process.
53. A method according to claim 51, wherein the particle material is a compound semiconductor, and the vapour comprises molecules containing phosphorus.
54. A method according to claim 53, wherein the particle material comprises indium arsenide, and arsenic atoms are replaced by phosphorus atoms so that the material of the shell is indium arsenide phosphide.
55. A method according to claim 51, wherein the modification is formation of an oxide.
56. A method according to claim 55, wherein the material of the particle is one of: silicon, indium.
57. A method according to claim 46, wherein said step a) comprises:
forming an aerosol of group III metallic particles, and filtering the aerosol to provide particles with a narrow predetermined dimensional spread; and
reacting the aerosol with a group V precursor gas, in order to provide an aerosol of particles consiting og III-V semiconductor material.
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