US20050083760A1 - Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics - Google Patents
Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics Download PDFInfo
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- US20050083760A1 US20050083760A1 US10/986,615 US98661504A US2005083760A1 US 20050083760 A1 US20050083760 A1 US 20050083760A1 US 98661504 A US98661504 A US 98661504A US 2005083760 A1 US2005083760 A1 US 2005083760A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
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Abstract
Description
- The invention relates to magneto-resistive random access memories (MRAMs), and more particularly to MRAM cells having a diode.
- MRAMs are attractive due to being non-volatile and relatively high speed. In any memory, especially large memories, cell density is a significant issue. A smaller cell results in a smaller array for a given memory size. The smaller array results in less area being occupied, which in turn, results in lower cost. One of the higher density memories is constructed by simply connecting the cell, which is the magnetic tunnel junction (MTJ), between the word line and the bit line. This type of memory is known to be dense, but difficulties with being able to provide enough sense signal differentiation in the light of the many alternative current paths in the deselected cells has made such memories difficult to manufacture on a commercial basis.
- One technique to overcome this has been to use a non-linear device in series with the MTJ. The non-linear device provides a first current level at one voltage, but significantly less than half this current at half the voltage. The intent is for this non-linear device to operate in the higher current regime for the selected cells and the lower current regime for the unselected cells. One of the difficulties of this approach is obtaining sufficient non-linearity to provide a sufficient current differential between the selected and unselected cells.
- Thus, there is a need to provide a high density memory array that provides improved margin between the selected and unselected cells.
- The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
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FIG. 1 is a block diagram of a memory for using one of the memory cell types according to various embodiments of the invention; -
FIG. 2 is a cross section of a memory cell useful in the memory ofFIG. 1 according to a first embodiment of the invention; -
FIGS. 3-5 are barrier height diagrams helpful in understanding the operation of the memory cell ofFIG. 2 ; -
FIG. 6 is a graph of current versus voltage showing the asymmetric property of the memory cell ofFIG. 2 ; -
FIG. 7 is a cross section of a memory cell useful in the memory ofFIG. 1 according to a second embodiment of the invention; and -
FIG. 8 is a cross section of a memory cell useful in the memory ofFIG. 1 according to a third embodiment of the invention. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
- A magneto-resistive random access memory (MRAM) uses memory cells connected between rows and columns without requiring a selection transistor. The memory cell comprises a single stack having both a magnetic tunnel junction (MTJ)and an asymmetric device. Because the asymmetric device is conveniently made in the same stack as the MTJ, the addition of the asymmetric device does not sacrifice high density and is achieved with relatively little increased complexity. Being asymmetric, the asymmetric device effectively reduces the parasitic leakage from the unselected cells even with the reverse bias on the asymmetric device of the unselected cells being of a greater magnitude than the forward bias on the asymmetric device of a selected cell. This is better understood with reference to the drawings and the following description.
- Shown in
FIG. 1 is amemory 10 having anarray 12, a row decoder anddrivers 14, and a column decoder andsense amplifier 16.Array 12 comprisesmemory cells word lines drivers 14, andbit lines sense amplifier 16. Memory cells 18-24 have a MTJ with additional features that make it asymmetric in operation. Thus, each cell may be considered an asymmetrical magnetic tunnel junction (AMTJ). Only four memory cells are shown formemory 10 for simplicity, but it is understood that many more cells, word lines, and bit lines would be shown if an entire memory were shown.Cell 18 has an input connected toword line 26 and an output coupled tobit line 30.Cell 20 has an input connected toword line 26 and an output coupled tobit line 32.Cell 22 has an input connected toword line 28 and an output coupled tobit line 30.Cell 24 has an input connected toword line 28 and an output coupled tobit line 32. - In a read operation a bias voltage, for example 500 millivolts (mV), is applied to the selected bit line and ground to the selected word line. The unselected bit lines are at the bias voltage and the unselected word lines are also maintained at the bias voltage, 500 mV. The selected cell then has the bias voltage applied across it. For example, if
cell 18 is selected for reading, thenword line 26 is grounded,word line 28 is at the bias voltage,bit line 30 is at the bias voltage, andbit line 32 is at the bias voltage. Thus, the selected cell is forward biased frombit line 30 toword line 26, and the state ofmemory cell 18 is detected based on the current flowing therethrough. The unselected cells are substantially not biased.Cell 24 is substantially not biased withword line 28 at the bias voltage andbit line 32 at the bias voltage.Cell 20 is forward biased withword line 26 grounded andbit line 32 at the bias voltage.Cell 22 is not biased with bothword line 28 andbit line 30 at the bias voltage. - Effectively, all of the cells on the selected word line are treated the same. Selection is actually based on which of the bit lines are chosen for sensing. Due to the current through a cell on each bit line, there is some voltage drop on these bit lines. This is made as small as reasonably possible, but it is not zero. Further, the voltage drop on each bit line is somewhat different because the state of the cells on the selected word line is variable from bit line to bit line. Also the voltage on the selected word line is not same for each cell because of current flowing through the word line. This voltage drop is made to be as small as reasonably possible but this drop is also not zero. Due to these voltage drops on the bit lines, unselected cells are also biased. The biasing then generates currents on the unselected word lines. These parasitic currents on the unselected word lines and bit lines degrade to some extent the current on the selected bit line, making it more difficult to accurately detect the state of the cell. Even though these parasitic currents can flow through some forward biased cells, each parasitic path, however, has at least one reverse biased cell in it.
- Other alternatives may be used to operate the memory. For example, the unselected bit lines can be left floating instead of being at the bias voltage. The voltage on bit lines would not be truly floating because the memory cells, which are at least a little conductive even in the reverse bias condition, would provide a path to the word lines, which are biased to a specific voltage.
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FIG. 2 shows amemory cell 40 for use as memory cells 18-24.Memory cell 40 comprises a stack of layers shown in cross section. The thicknesses are not to scale, but each is of nearly the same lateral dimension. These layers can be etched using a single mask. The top three layers, 42, 44, and 46 comprise aMTJ 54. These threelayers free layer 42, abarrier 44, and a fixedlayer 46. The fixedlayer 46 is a fixed permanent magnet andfree layer 42 can be programmed to one magnetic state or another. These two different magnetic states in combination with the barrier and fixed layer result in a variation in resistance that can be measured. In addition to theMTJ 54, the stack has anasymmetric tunnel device 56 comprised oflayers layers layer 52 is biased to a positive voltage, e.g., the bias voltage of 500 mV, with respect tolayer 48, the current is about 100 times the current that flows when the same magnitude of bias voltage is applied in the reverse direction. This was analyzed with respect to a 256×256 memory and the result was only a 5% reduction in sensing signal compared to that of a single memory cell that is not part of an array. - Shown in
FIGS. 3, 4 , and 5 are energy band diagrams that illustrate the origin of the asymmetric conduction mechanism. The difference in work function betweeninsulator 50 andlayer 48 is shown as barrier height ΦM1 inFIG. 3 , which shows the situation in which there is no bias voltage betweenlayers insulator 50 andlayer 52 is shown as barrier height ΦM2 inFIG. 3 . The materials forlayers insulator 50 are chosen so that barrier height ΦM1 is much greater than barrier height ΦM2 to achieve the desired asymmetry.FIG. 4 shows the case in whichlayer 52 is biased to a positive voltage compared tolayer 48. This shows the resulting barrier for electrons tunneling fromlayer 48 to layer 52 is sharply triangular, thereby facilitating electron transport (opposite direction from current flow) fromlayer 48 to layer 52. Shown inFIG. 5 is the reverse bias condition in whichlayer 48 is biased to the positive voltage relative to layer 52. In this case the barrier for electron tunneling fromlayer 52 to layer 48 is limited to direct tunneling due to the square barrier shape. The result is that the electrons tunnel at a rate that is about 100 times less than that for the forward biased condition shown inFIG. 4 . - Materials for
layer 48,layer 50, andlayer 52 are chosen so that the barrier height oflayer 48 with respect tolayer 50 and the barrier height oflayer 52 with respect tolayer 50 are both in the range of zero to 0.6 eV. Furthermore, the materials are chosen so that the difference in these two barrier heights is also 0.2 to 0.6 eV. This ensures that even with the small allowed voltages across the MTJs of the cells, there is a two order of magnitude difference between the currents in the forward and reverse bias direction. For this example oflayer 48 being titanium nitride,layer 50 being titanium oxide, andlayer 52 being tantalum, the barrier height ΦM1 is 0.53 eV and ΦM2 is 0.14 eV so that the barrier height betweenlayers insulator 50 must be such that the forward bias resistance ofasymmetric device 56 is preferably less than or equal to the resistance ofMTJ 54. It is beneficial that the forward bias resistance of the asymmetric device not make up a high percentage of the total resistance of the cell and also that the reverse bias resistance of the asymmetric device be large in relation to that of the MTJ. The thicknesses of the metal layers are not particularly significant, 100 Angstroms is an effective thickness. The thickness of theinsulator layer 50 may be 30 Angstroms for this example. Other insulators that should be effective as substitutes for titanium oxide include strontium titanate, tantalum pentoxide, strontium bismuth tantalate. Other alternatives that meet the above criteria may be used as substitutes for the metal layers as well. Metals that can be effective when properly chosen according to the above criteria include titanium, copper, and iron. - Shown in
FIG. 6 is the current versus voltage plot for the forward and reverse bias conditions ofasymmetric device 56 for the case in which the resistance of the MTJ and the forward bias resistance of the asymmetric device are equal. In such case the bias condition on the asymmetric device is half that of the total bias on the cell. This voltage is shown as ½ Vbias inFIG. 6 . Whereas in operation, the reverse bias condition results in a very small current, even if the reverse bias is a full Vbias which explains, even with all of the various leakage paths, the parasitic current degraded the actual cell current by only 5% for a 256×256 array. - Shown in
FIG. 7 is analternative memory cell 70 having aMTJ 71 and anasymmetric device 78 comprising ametal layer 72 underMTJ 71, aninsulator layer 73 underlayer 72, aninsulator layer 74 underlayer 73, and ametal layer 75 underlayer 74. In this case insulator layers 73 and 74 have a barrier heights and thicknesses that can be selected to provide an even greater difference between forward and reverse currents. An effective example forlayers Insulator layer 73 has a barrier height with respect to the metal layers 72 and 75 that is greater than the barrier height ofinsulator layer 74 with respect to these same metals. Using a relatively small thickness forinsulator layer 73, for example 20 Angstroms, and a relatively large thickness forlayer 74, for example 100 Angstroms, generates asymmetric behavior of current flow in response to an applied voltage. For the case in whichterminal 77 is positive with respect to terminal 76 (forward bias), electrons tunnel through thelayer 72 in a manner analogous to that shown inFIG. 4 . Also the voltage differential is chosen to be sufficient that under this bias,insulator 74 does not present a barrier to electron flow because the electron energy is greater than the conductionband energy insulator 74. In the opposite direction, withterminal 76 positive with respect to terminal 77 (reverse bias),insulator layer 74 provides a barrier to electron tunneling. Although the barrier is relatively low, the thickness is relatively large so that even this low barrier greatly restricts the number of electrons that can tunnel. In addition, these electrons lack the energy required to cross the high barrier presented byinsulator layer 73 as well. This results in much less reverse bias current compared to forward bias current. - Shown in
FIG. 8 is anotheralternative memory cell 80 having aMTJ 81 and anasymmetric device 89 comprising ametal layer 82 underMTJ 81, aninsulator layer 83 undermetal layer 82, ametal layer 84 underinsulator layer 83, aninsulator layer 85 undermetal layer 84, and ametal layer 86 underinsulator layer 85. This has the effect of multiplying two asymmetric devices together. The preferred approach is to have a relatively high barrier throughinsulator 83 in the forward direction so that any electrons passing that barrier will also pass through the relatively low barrier throughinsulator 85. In the reverse direction, the combined effect of the two barriers is virtually impenetrable. An effective example forlayers - In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the
asymmetric devices - Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims (8)
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US10/304,625 US6944052B2 (en) | 2002-11-26 | 2002-11-26 | Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics |
US10/986,615 US20050083760A1 (en) | 2002-11-26 | 2004-11-12 | Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics |
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US10/986,615 Abandoned US20050083760A1 (en) | 2002-11-26 | 2004-11-12 | Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics |
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