US20050104224A1 - Bond pad for flip chip package - Google Patents

Bond pad for flip chip package Download PDF

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Publication number
US20050104224A1
US20050104224A1 US10/716,682 US71668203A US2005104224A1 US 20050104224 A1 US20050104224 A1 US 20050104224A1 US 71668203 A US71668203 A US 71668203A US 2005104224 A1 US2005104224 A1 US 2005104224A1
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Prior art keywords
bond pad
integrated circuit
circuit chip
slot
slots
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Granted
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US10/716,682
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US6927498B2 (en
Inventor
Tai-Chun Huang
Chih-Hsiang Yao
Ching-Hua Hsieh
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US10/716,682 priority Critical patent/US6927498B2/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSIEH, CHING-HUA, HUANG, TAI-CHUN, YAO, CHIH-HSIANG
Priority to SG200403785A priority patent/SG121890A1/en
Priority to TW093117175A priority patent/TWI235443B/en
Priority to CNU2004200772329U priority patent/CN2731710Y/en
Priority to CN2004100551068A priority patent/CN1619805B/en
Publication of US20050104224A1 publication Critical patent/US20050104224A1/en
Application granted granted Critical
Publication of US6927498B2 publication Critical patent/US6927498B2/en
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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Definitions

  • the present invention relates to an integrated circuit packaging technology and in particular to a flip chip packaging technology.
  • the flip chip package is the most space efficient package for very large scale integrated (VLSI) circuits.
  • Flip chip technology is compatible with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates.
  • a flip chip is generally a monolithic semiconductor device, such as an integrated circuit (IC), having bead-like terminals formed on one of its surfaces. The terminals, usually in the form of solder bumps, serve to both secure the flip chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board.
  • IC integrated circuit
  • an integrated circuit (IC) device In a flip chip package, an integrated circuit (IC) device usually has a plurality of bond pads distributed over the surface of the device in a rectangular array. These bond pads are used to connect the IC device to the electrical paths on a printed circuit board (PCB). A ball shaped solder bump is formed on each of the bond pads of the IC device. The IC device and the PCB are positioned so that the solder bumps contact the electrical paths on the PCB, and the assembly is heated to reflow the solder, forming electrical and mechanical bonds between the IC device and the PCB.
  • PCB printed circuit board
  • Chittipeddi et al. in U.S. Pat. No. 6,187,658 and in U.S. Pat. No. 6,087,732, discloses a method of forming a bond pad for flip chip package integrating the package process with the semiconductor manufacturing process.
  • FIG. 1A shows a sketch cross-section of a portion of the conventional flip chip package. As well, the cross-section of the entire structure of the conventional flip chip package is shown in FIG. 4 . It is understood that chip 100 is conventionally provided with bond pads 102 and solder bumps 104 . In order to clearly illustrate the structure of the flip chip package, only one bond pad 102 and one solder bump 104 is shown in the figure. Heat is usually produced during operation of the IC device, causing the expansion of the bond pad 100 and the PCB 106 .
  • the thermal expansion coefficient of the bond pad 102 is very different from that of the PCB 106 .
  • the structure of the flip chip package subjected to the thermal stress is distorted.
  • the solder bump 104 easily peels off.
  • an object of the invention is to provide a bond pad for a flip chip packaging, wherein the bond pad is structured to release stress, especially thermal stress, such that peeling of the solder bump can be avoided.
  • One feature of the present invention is to provide slots in a bond pad used in the assembly of a flip chip.
  • the slot extends along a direction which is substantially perpendicular to a radial direction of the center of the chip, same as thermal expansion direction, thermal stress can be released by the slot, such that solder bump peeling due to the difference of the thermal expansion between the bond pad connected with the upper terminal of the solder bump and the PCB connected with the lower terminal of the solder bump can be avoided.
  • the heat produced by operation of the chip radiates from the center of the bond pad.
  • Various embodiments of the orientation of the slots are described hereinafter.
  • an embodiment of the present invention provides a bond pad for a flip chip package.
  • the bond pad is used in the assembly of a flip chip.
  • the bond pad is provided with at least one slot extending along a direction which is perpendicular to a radial direction from the center of the integrated circuit chip.
  • the bond pad is deposed at the corner of the integrated circuit chip.
  • the bond pad with the designed slot can be preferably located substantially at corners of the integrated circuit chip. Also, the number of the bond pad can be more the one, thus the bond pad is preferably arranged substantially in an array.
  • the bond pad is circular or rectangular.
  • the slot is preferably rectangular.
  • the slots in the same bond pad are parallel to each other when the number of the slots is more than one.
  • the slot extends at least partially through the bond pad.
  • Another embodiment of the present invention provides a plurality of bond pads for a flip chip package.
  • the bond pads are used in the assembly of a flip chip.
  • the bond pads are located in each of the quadrants of the integrated circuit chip.
  • Each of the bond pads comprises at least one slot, and each of the slots in the same quadrant extends along a direction which is substantially perpendicular to the diagonal lines of the integrated circuit chip passing through the quadrant in which it is located.
  • the slot is rectangular.
  • Each of the slots extends at least partially through the bond pad.
  • the slots in the same quadrant are parallel to each other.
  • FIG. 1A through 1B are cross-sections illustrating the thermal expansion problem of the conventional flip chip package
  • FIG. 2A through 2B are top-views showing the bond pad for a flip chip package according to one embodiment of the invention, wherein at least one bond pad is deposed at the corner of the integrated circuit chip;
  • FIG. 3A through 3B are top-views showing the bond pad is for flip chip package according to another embodiment of the invention, wherein a plurality of bond pads are located in each of the quadrants of the integrated circuit chip, each of the bond pads has at least one slot, and each of the slots in the same quadrant extends along a direction which is substantially perpendicular to the diagonal line of the integrated circuit chip passing through the quadrant in which the bond pads are located;
  • FIG. 4 is a cross-section showing the flip chip package according to one embodiment of the invention.
  • FIG. 4 shows a cross-section of the conventional bond pad structure.
  • the bond pad structure is constructed on a semiconductor substrate 500 .
  • Multilayers comprising interlayer dielectric layers (ILD) 502 , 504 are disposed on the semiconductor substrate 500 .
  • a lower metal pad 518 is interposed in the interlayer dielectric layers (ILD) 502 .
  • An upper metal pad 510 is disposed on the interlayer dielectric layers (ILD) 504 and surrounded by a passivation layer 506 .
  • the upper metal pad 510 and the lower metal pad 518 are electrically connected by a plurality of plugs 512 .
  • a bond pad 514 is disposed on the upper metal pad 510 .
  • a solder bump 516 is further disposed on the bond pad 514 for flip chip package using known solder bumping reflow techniques.
  • the substrate 500 is understood to possibly contain IC devices, such as MOS transistors, resistors, logic devices, and the like, though they are omitted from the drawings for the sake of clarity.
  • the term “substrate” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.
  • the term “substrate surface” is meant to include the uppermost exposed layers on a semiconductor wafer, such as a Si wafer surface, an insulating layer and metal wires.
  • the interlayer dielectric layers (ILD) 502 , 504 may comprise SiO 2 , phosphosilicate glass (PSG), boro-phospho silicate glass (BPSG), and low k materials, such as fluorinated silicate glass (FSG).
  • the passivation layer 506 may comprise silicon nitride.
  • the metal pads 510 , 518 may comprise Cu, Al or a Cu/Al alloy.
  • the bond pad 514 may comprises Al or an Al based alloy.
  • the thermal generally radiates from a center position of the surface of the IC device.
  • the solder bump and bond pad is subjected to the shear stress.
  • the conventional bond pad architecture described above may be utilized.
  • the surface of the bond pad of the present invention is patterned to reduce the solder bump shear stress.
  • a plurality of slots which are substantially perpendicular to the radiate direction from the center of the surface of the IC device are provided in the bond pad to release the shear stress.
  • the integrated circuit chip 200 is a rectangle shape substrate.
  • the center C of the integrated circuit chip 200 is defined by the intersection of the diagonals of the integrated circuit chip 200 .
  • the integrated circuit chip 200 preferably comprises a plurality of bond pad 204 having at least one slot 202 extending along a direction which is perpendicular to a radial direction T from the center C.
  • the bond pad 204 are preferably located substantially at corners of the integrated circuit chip 200 .
  • the integrated circuit chip 200 can further comprise additional bond pads 210 , as shown in FIG. 2B , wherein all the bond pads 204 and 210 are preferably arranged in an array.
  • the bond pads 204 can comprise a single slot 202 or a plurality of slots 202 .
  • the slots 202 are preferably parallel to each other when the number of the slots is more than one.
  • the bond pad 204 can be a rectangular or circular-shaped structure.
  • the slot 202 preferably is rectangular.
  • the slot 202 extends at least partially through the depth of bond pad 200 .
  • the slots 202 may be formed by known photolithography and etching methods.
  • the slots 202 extend along a direction which is substantially perpendicular to a radiate direction from the center of the surface of the integrated circuit chip 200 . Thereby, thermal stress can be released by the slots 202 , such that solder bump peeling due to the thermal expansion difference between the bond pad connected with the upper terminal of the solder bump and the PCB connected with the lower terminal of the solder bump can be avoided.
  • an integrated circuit chip 400 is used in the assembly of a flip chip.
  • the integrated circuit chip 400 comprises a plurality of bond pads 404 a , 404 b , 404 c , and 404 d located respectively in each of the quadrants of the integrated circuit chip 400 .
  • Each of the bond pads 404 a , 404 b , 404 c , and 404 d comprises at one slot 402 extending along a direction T which is substantially perpendicular to the diagonal line of the integrated circuit chip 400 passing through the quadrant in which it is located. All the slots 402 disposed in the same quadrant extend along the same direction.
  • all of the bond pads 404 a extend along a direction, and all of the bond pads 404 b extend along another direction.
  • the bond pads 404 a , 404 b , 404 c , and 404 d can be arranged substantially in an array. As shown in FIG. 3A , the bond pads 404 a , 404 b , 404 c , and 404 d can be a circular-shaped. As shown in FIG. 3B , the bond pads 404 a , 404 b , 404 c , and 404 d can also be a is rectangle-shaped.
  • the slot 402 preferably is rectangular.
  • the slots 402 of a pattern are parallel to each other when the number of the slots is more than one.
  • the slot 402 extends at least partially through the depth of bond pads 404 a , 404 b , 404 c , and 404 d.
  • the slots 402 may be formed by known photolithography and etching methods.
  • the slots 402 extend along a direction which is substantially perpendicular to a radiate direction from the center of the surface of the integrated circuit chip 400 . Thereby, thermal stress can be released by the slots 402 , such that solder bump peeling due to the thermal expansion difference between the bond pad connected with the upper terminal of the solder bump and the PCB connected with the lower terminal of the solder bump can be avoided.

Abstract

A bond pad for a flip chip package. The bond pad is suitable for an integrated circuit chip. A plurality of slots are designed in the bond pad. Each of the slots extends along a direction which is perpendicular to a radial direction from the center of the bond pad. The bond pad is deposed at the corner of the integrated circuit chip.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to an integrated circuit packaging technology and in particular to a flip chip packaging technology.
  • 2. Description of the Related Art
  • The flip chip package is the most space efficient package for very large scale integrated (VLSI) circuits. Flip chip technology is compatible with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates. A flip chip is generally a monolithic semiconductor device, such as an integrated circuit (IC), having bead-like terminals formed on one of its surfaces. The terminals, usually in the form of solder bumps, serve to both secure the flip chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board.
  • In a flip chip package, an integrated circuit (IC) device usually has a plurality of bond pads distributed over the surface of the device in a rectangular array. These bond pads are used to connect the IC device to the electrical paths on a printed circuit board (PCB). A ball shaped solder bump is formed on each of the bond pads of the IC device. The IC device and the PCB are positioned so that the solder bumps contact the electrical paths on the PCB, and the assembly is heated to reflow the solder, forming electrical and mechanical bonds between the IC device and the PCB.
  • Erickson, in U.S. Pat. No. 6,180,265, discloses a method for converting an aluminum wire bond to a flip chip solder bump pad, so as to enable an IC device originally configured for wire-bonding attachment to be mounted using a flip chip attachment technique.
  • Chittipeddi et al., in U.S. Pat. No. 6,187,658 and in U.S. Pat. No. 6,087,732, discloses a method of forming a bond pad for flip chip package integrating the package process with the semiconductor manufacturing process.
  • The bond pads on the IC device are typically aluminum or an aluminum-base alloy for various known processing and performance-related reasons. FIG. 1A shows a sketch cross-section of a portion of the conventional flip chip package. As well, the cross-section of the entire structure of the conventional flip chip package is shown in FIG. 4. It is understood that chip 100 is conventionally provided with bond pads 102 and solder bumps 104. In order to clearly illustrate the structure of the flip chip package, only one bond pad 102 and one solder bump 104 is shown in the figure. Heat is usually produced during operation of the IC device, causing the expansion of the bond pad 100 and the PCB 106.
  • However, the thermal expansion coefficient of the bond pad 102 is very different from that of the PCB 106. As shown in FIG. 1B, the structure of the flip chip package subjected to the thermal stress is distorted. Thus, the solder bump 104 easily peels off.
    • SUMMARY OF THE INVENTION
  • Accordingly, an object of the invention is to provide a bond pad for a flip chip packaging, wherein the bond pad is structured to release stress, especially thermal stress, such that peeling of the solder bump can be avoided.
  • One feature of the present invention is to provide slots in a bond pad used in the assembly of a flip chip. When the slot extends along a direction which is substantially perpendicular to a radial direction of the center of the chip, same as thermal expansion direction, thermal stress can be released by the slot, such that solder bump peeling due to the difference of the thermal expansion between the bond pad connected with the upper terminal of the solder bump and the PCB connected with the lower terminal of the solder bump can be avoided. The heat produced by operation of the chip radiates from the center of the bond pad. Various embodiments of the orientation of the slots are described hereinafter.
  • To achieve the above objects, an embodiment of the present invention provides a bond pad for a flip chip package. The bond pad is used in the assembly of a flip chip. The bond pad is provided with at least one slot extending along a direction which is perpendicular to a radial direction from the center of the integrated circuit chip. The bond pad is deposed at the corner of the integrated circuit chip.
  • According to the present invention, the bond pad with the designed slot can be preferably located substantially at corners of the integrated circuit chip. Also, the number of the bond pad can be more the one, thus the bond pad is preferably arranged substantially in an array.
  • According to the present invention, the bond pad is circular or rectangular.
  • According to the present invention, the slot is preferably rectangular. The slots in the same bond pad are parallel to each other when the number of the slots is more than one. The slot extends at least partially through the bond pad.
  • Another embodiment of the present invention provides a plurality of bond pads for a flip chip package. The bond pads are used in the assembly of a flip chip. The bond pads are located in each of the quadrants of the integrated circuit chip. Each of the bond pads comprises at least one slot, and each of the slots in the same quadrant extends along a direction which is substantially perpendicular to the diagonal lines of the integrated circuit chip passing through the quadrant in which it is located.
  • According to the present invention, the slot is rectangular. Each of the slots extends at least partially through the bond pad. The slots in the same quadrant are parallel to each other.
  • A detailed description is given in the following embodiments with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIG. 1A through 1B are cross-sections illustrating the thermal expansion problem of the conventional flip chip package;
  • FIG. 2A through 2B are top-views showing the bond pad for a flip chip package according to one embodiment of the invention, wherein at least one bond pad is deposed at the corner of the integrated circuit chip;
  • FIG. 3A through 3B are top-views showing the bond pad is for flip chip package according to another embodiment of the invention, wherein a plurality of bond pads are located in each of the quadrants of the integrated circuit chip, each of the bond pads has at least one slot, and each of the slots in the same quadrant extends along a direction which is substantially perpendicular to the diagonal line of the integrated circuit chip passing through the quadrant in which the bond pads are located;
  • FIG. 4 is a cross-section showing the flip chip package according to one embodiment of the invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Preferred embodiments of the present invention are now described with reference to the figures.
  • FIG. 4 shows a cross-section of the conventional bond pad structure. The bond pad structure is constructed on a semiconductor substrate 500. Multilayers comprising interlayer dielectric layers (ILD) 502, 504 are disposed on the semiconductor substrate 500. A lower metal pad 518 is interposed in the interlayer dielectric layers (ILD) 502. An upper metal pad 510 is disposed on the interlayer dielectric layers (ILD) 504 and surrounded by a passivation layer 506. The upper metal pad 510 and the lower metal pad 518 are electrically connected by a plurality of plugs 512. A bond pad 514 is disposed on the upper metal pad 510. A solder bump 516 is further disposed on the bond pad 514 for flip chip package using known solder bumping reflow techniques. The substrate 500 is understood to possibly contain IC devices, such as MOS transistors, resistors, logic devices, and the like, though they are omitted from the drawings for the sake of clarity. In the following, the term “substrate” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer. The term “substrate surface” is meant to include the uppermost exposed layers on a semiconductor wafer, such as a Si wafer surface, an insulating layer and metal wires. The interlayer dielectric layers (ILD) 502, 504 may comprise SiO2, phosphosilicate glass (PSG), boro-phospho silicate glass (BPSG), and low k materials, such as fluorinated silicate glass (FSG). The passivation layer 506 may comprise silicon nitride. The metal pads 510, 518 may comprise Cu, Al or a Cu/Al alloy. As well, the bond pad 514 may comprises Al or an Al based alloy.
  • During the operation of the IC device, a large amount of heat is produced, inducing shear stress. The thermal generally radiates from a center position of the surface of the IC device. The solder bump and bond pad is subjected to the shear stress. According to the present invention, the conventional bond pad architecture described above may be utilized. However, the surface of the bond pad of the present invention is patterned to reduce the solder bump shear stress. According to an aspect of the present invention, a plurality of slots which are substantially perpendicular to the radiate direction from the center of the surface of the IC device are provided in the bond pad to release the shear stress. Several embodiments of the arrangements of the bond pad are described hereafter in accordance with the present invention.
    • FIRST EMBODIMENT
  • In FIG. 2A through 2B, the integrated circuit chip 200 is a rectangle shape substrate. The center C of the integrated circuit chip 200 is defined by the intersection of the diagonals of the integrated circuit chip 200. The integrated circuit chip 200 preferably comprises a plurality of bond pad 204 having at least one slot 202 extending along a direction which is perpendicular to a radial direction T from the center C. The bond pad 204 are preferably located substantially at corners of the integrated circuit chip 200. The integrated circuit chip 200 can further comprise additional bond pads 210, as shown in FIG. 2B, wherein all the bond pads 204 and 210 are preferably arranged in an array. The bond pads 204 can comprise a single slot 202 or a plurality of slots 202. The slots 202 are preferably parallel to each other when the number of the slots is more than one. The bond pad 204 can be a rectangular or circular-shaped structure. The slot 202 preferably is rectangular. The slot 202 extends at least partially through the depth of bond pad 200.
  • The slots 202 may be formed by known photolithography and etching methods.
  • The slots 202 extend along a direction which is substantially perpendicular to a radiate direction from the center of the surface of the integrated circuit chip 200. Thereby, thermal stress can be released by the slots 202, such that solder bump peeling due to the thermal expansion difference between the bond pad connected with the upper terminal of the solder bump and the PCB connected with the lower terminal of the solder bump can be avoided.
    • SECOND EMBODIMENT
  • In FIGS. 3A and 3B, an integrated circuit chip 400 is used in the assembly of a flip chip. The integrated circuit chip 400 comprises a plurality of bond pads 404 a, 404 b, 404 c, and 404 d located respectively in each of the quadrants of the integrated circuit chip 400. Each of the bond pads 404 a, 404 b, 404 c, and 404 d comprises at one slot 402 extending along a direction T which is substantially perpendicular to the diagonal line of the integrated circuit chip 400 passing through the quadrant in which it is located. All the slots 402 disposed in the same quadrant extend along the same direction. For example, all of the bond pads 404 a extend along a direction, and all of the bond pads 404 b extend along another direction. The bond pads 404 a, 404 b, 404 c, and 404 d can be arranged substantially in an array. As shown in FIG. 3A, the bond pads 404 a, 404 b, 404 c, and 404 d can be a circular-shaped. As shown in FIG. 3B, the bond pads 404 a, 404 b, 404 c, and 404 d can also be a is rectangle-shaped.
  • The slot 402 preferably is rectangular. The slots 402 of a pattern are parallel to each other when the number of the slots is more than one. The slot 402 extends at least partially through the depth of bond pads 404 a, 404 b, 404 c, and 404 d.
  • The slots 402 may be formed by known photolithography and etching methods.
  • The slots 402 extend along a direction which is substantially perpendicular to a radiate direction from the center of the surface of the integrated circuit chip 400. Thereby, thermal stress can be released by the slots 402, such that solder bump peeling due to the thermal expansion difference between the bond pad connected with the upper terminal of the solder bump and the PCB connected with the lower terminal of the solder bump can be avoided.
  • While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (32)

1. A bond pad for a flip chip package, suitable for an integrated circuit chip, comprising:
at least one slot extending along a first direction, which is perpendicular to a second direction radiating from the center of the integrated circuit chip.
2. The bond pad as claimed in claim 1, wherein the bond pad is located substantially at corners of the integrated circuit chip.
3. The bond pad as claimed in claim 1, wherein the patterns are arranged substantially in an array.
4. The bond pad as claimed in claim 1, wherein the bond pad is circular or rectangular.
5. The bond pad as claimed in claim 1, wherein the slot is rectangular.
6. The bond pad as claimed in claim 1, wherein the slot extends at least partially through the bond pad.
7. The bond pad as claimed in claim 1, wherein the slot extends down to the bottom of the bond pad.
8. A bond pad for a flip chip package, suitable for an integrated circuit chip, comprising:
a plurality of parallel slots located in the bond pad, each of the slots extending along a first direction, which is perpendicular to a second direction radiating from the center of the integrated circuit chip, wherein the bond pad is disposed at the corner of the integrated circuit chip.
9. The bond pad as claimed in claim 8, wherein the bond pad is circular or rectangular.
10. The bond pad as claimed in claim 8, wherein the slot is rectangular.
11. The bond pad as claimed in claim 8, wherein the slot extends at least partially through the bond pad.
12. The bond pad as claimed in claim 8, wherein the slot extends down to the bottom of the bond pad.
13. A bond pad structure for a flip chip package, suitable for an integrated circuit chip, the integrated circuit chip having a rectangular shape, comprising:
a plurality of bond pads located in each of the quadrants of the integrated circuit chip, wherein each of the bond pads comprises at least one slot and each of the slots in the same quadrant extending along a direction which is substantially perpendicular to the diagonal lines of the integrated circuit chip passing through the quadrant in which it is located.
14. The bond pad as claimed in claim 13, wherein the patterns are arranged substantially in an array.
15. The bond pad as claimed in claim 13, wherein the slot is rectangular.
16. The bond pad as claimed in claim 13, wherein the slot extends at least partially through the bond pad.
17. The bond pad as claimed in claim 13, wherein the slot extends down to the bottom of the bond pad.
18. The bond pad as claimed in claim 13, wherein the bond pad is circular or rectangular.
19. A semiconductor device, comprising:
a substrate;
a conductive layer, disposed on the substrate; and
at least one bond pad, disposed on the conductive layer, wherein the bond pad comprises at least one slot extending along a first directions which is perpendicular to a second direction radiating from the center of the surface of the substrate.
20. The bond pad as claimed in claim 19, wherein the number of the bond pads located in each quadrant of the integrated circuit chip is more than one, and each of the slots in the same quadrant extending along a direction which is substantially perpendicular to the diagonal lines of the integrated circuit chip passing through the quadrant in which it is located.
21. The bond pad as claimed in claim 19, wherein the slot is rectangular.
22. The bond pad as claimed in claim 19, wherein the slot extends at least partially through the bond pad.
23. The bond pad as claimed in claim 19, wherein the slot extends down to the bottom of the bond pad.
24. A bond pad for a flip chip package, suitable for an integrated circuit chip, comprising:
a slot extending along a first direction, which is perpendicular to a second direction radiating from the center of the integrated circuit chip,
wherein the slot is rectangular.
25. The bond pad of claim 24, wherein the bond pad is deposed at the corner of the integrated circuit chip.
26. The bond pad of claim 24, wherein the slot is one of a plurality of parallel slots located in the bond pad.
27. The bond pad of claim 26, wherein each of the slots is rectangular.
28. The bond pad of claim 26, wherein:
the slot is one of a plurality of slots located in quadrants of the integrated circuit chip; and
each of the slots in the same quadrant extending along a direction, which is substantially perpendicular to a diagonal line of the integrated circuit chip passing through the quadrant in which each of the slots is located.
29. The bond pad of claim 28, wherein the integrated circuit chip is rectangular.
30. A semiconductor device, comprising:
a substrate;
a conductive layer disposed on the substrate; and
bond pads disposed on the conductive layer;
wherein:
at least one of the bond pads comprises at least one slot extending along a direction perpendicular to a radial direction from the center of the surface of the substrate;
each quadrant of the integrated circuit chip comprises at least two of the bond pads; and
slots in the same quadrant extend in a direction that is substantially perpendicular to the diagonal line of the integrated circuit chip passing through the quadrant in which each of the slots is located.
31. The semiconductor device of claim 30, wherein the substrate is rectangular.
32. The semiconductor device of claim 31, wherein the slots are rectangular.
US10/716,682 2003-11-19 2003-11-19 Bond pad for flip chip package Expired - Lifetime US6927498B2 (en)

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US10/716,682 US6927498B2 (en) 2003-11-19 2003-11-19 Bond pad for flip chip package
SG200403785A SG121890A1 (en) 2003-11-19 2004-06-14 Bond pad for flip chip package
TW093117175A TWI235443B (en) 2003-11-19 2004-06-15 Bond pad for flip chip package
CNU2004200772329U CN2731710Y (en) 2003-11-19 2004-08-04 Bond pad for flip chip package and semiconductor assembly
CN2004100551068A CN1619805B (en) 2003-11-19 2004-08-04 Bond pad for flip chip package and semiconductor assembly

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102843858A (en) * 2012-07-30 2012-12-26 友达光电(厦门)有限公司 Line base plate for fixedly providing semiconductor chip and manufacturing method thereof
US9343434B2 (en) 2014-02-27 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
US9589900B2 (en) * 2014-02-27 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9666522B2 (en) 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11011494B2 (en) * 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11728313B2 (en) 2018-06-13 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Offset pads over TSV
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
US11929347B2 (en) 2020-10-20 2024-03-12 Adeia Semiconductor Technologies Llc Mixed exposure for large die
US11955445B2 (en) 2022-06-09 2024-04-09 Adeia Semiconductor Bonding Technologies Inc. Metal pads over TSV

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6927498B2 (en) * 2003-11-19 2005-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad for flip chip package
JP4517843B2 (en) * 2004-12-10 2010-08-04 エルピーダメモリ株式会社 Semiconductor device
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US20070267745A1 (en) * 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
US7859092B2 (en) * 2007-01-02 2010-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures
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US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
CN103021978B (en) * 2011-09-22 2015-02-04 上海华虹宏力半导体制造有限公司 Welding pad structure for packaging on integrated circuit chip
US9548281B2 (en) * 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8912668B2 (en) 2012-03-01 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
CA3015971A1 (en) * 2016-03-01 2017-09-08 Cardlab Aps A circuit layer for an integrated circuit card

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5527999A (en) * 1995-02-21 1996-06-18 Delco Electronics Corp. Multilayer conductor for printed circuits
US5736791A (en) * 1995-02-07 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and bonding pad structure therefor
US5923088A (en) * 1996-08-22 1999-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure for the via plug process
US6087732A (en) * 1998-09-28 2000-07-11 Lucent Technologies, Inc. Bond pad for a flip-chip package
US6180265B1 (en) * 1997-06-27 2001-01-30 Delco Electronics Corporation Flip chip solder bump pad
US6313540B1 (en) * 1998-12-25 2001-11-06 Nec Corporation Electrode structure of semiconductor element

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6329705B1 (en) * 1998-05-20 2001-12-11 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes
CN1225791C (en) * 2002-02-09 2005-11-02 旺宏电子股份有限公司 Semiconductor configuration and making process
TW552688B (en) * 2002-07-30 2003-09-11 Taiwan Semiconductor Mfg Structure for flip chip packaging
US6927498B2 (en) * 2003-11-19 2005-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad for flip chip package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736791A (en) * 1995-02-07 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and bonding pad structure therefor
US5527999A (en) * 1995-02-21 1996-06-18 Delco Electronics Corp. Multilayer conductor for printed circuits
US5923088A (en) * 1996-08-22 1999-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure for the via plug process
US6180265B1 (en) * 1997-06-27 2001-01-30 Delco Electronics Corporation Flip chip solder bump pad
US6087732A (en) * 1998-09-28 2000-07-11 Lucent Technologies, Inc. Bond pad for a flip-chip package
US6187658B1 (en) * 1998-09-28 2001-02-13 Lucent Technologies, Inc. Bond pad for a flip chip package, and method of forming the same
US6313540B1 (en) * 1998-12-25 2001-11-06 Nec Corporation Electrode structure of semiconductor element

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102843858A (en) * 2012-07-30 2012-12-26 友达光电(厦门)有限公司 Line base plate for fixedly providing semiconductor chip and manufacturing method thereof
US10096553B2 (en) 2014-02-27 2018-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9343434B2 (en) 2014-02-27 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
US9508696B2 (en) 2014-02-27 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
US9589900B2 (en) * 2014-02-27 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9721933B2 (en) 2014-02-27 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
US11742298B2 (en) 2014-05-29 2023-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US10522473B2 (en) 2014-05-29 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US10269723B2 (en) 2014-05-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US9666522B2 (en) 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US11552041B2 (en) 2017-09-24 2023-01-10 Adeia Semiconductor Bonding Technologies Inc. Chemical mechanical polishing for hybrid bonding
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11804377B2 (en) 2018-04-05 2023-10-31 Adeia Semiconductor Bonding Technologies, Inc. Method for preparing a surface for direct-bonding
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11728313B2 (en) 2018-06-13 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Offset pads over TSV
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11011494B2 (en) * 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11756880B2 (en) 2018-10-22 2023-09-12 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures
US11929347B2 (en) 2020-10-20 2024-03-12 Adeia Semiconductor Technologies Llc Mixed exposure for large die
US11955445B2 (en) 2022-06-09 2024-04-09 Adeia Semiconductor Bonding Technologies Inc. Metal pads over TSV

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TW200518245A (en) 2005-06-01
SG121890A1 (en) 2006-05-26
TWI235443B (en) 2005-07-01
CN1619805B (en) 2010-04-28
US6927498B2 (en) 2005-08-09
CN1619805A (en) 2005-05-25

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