US20050146927A1 - Spacer integration scheme in MRAM technology - Google Patents
Spacer integration scheme in MRAM technology Download PDFInfo
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- US20050146927A1 US20050146927A1 US11/055,903 US5590305A US2005146927A1 US 20050146927 A1 US20050146927 A1 US 20050146927A1 US 5590305 A US5590305 A US 5590305A US 2005146927 A1 US2005146927 A1 US 2005146927A1
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- the field of the invention is that of magnetic random access memory (MRAM), in particular the design of an array device to improve the fabrication process yield.
- MRAM magnetic random access memory
- Magneto resistive tunnel junction devices used in a random access memory array are formed by depositing a blanket metal stack comprised of a pinned magnetic layer, a tunnel barrier layer and a free magnetic layer, such as that described in U.S. Pat. No. 5,650,958.
- Several process steps are made to define the magneto resistive tunnel junction device that comprises the storage element of a memory array cell.
- the bit is written by orienting the net magnetic moment of the free layer parallel or antiparallel to the pinned layer magnetic moment.
- the bit is read by sensing the amount of current tunneling through the barrier junction from the free layer to the pinned layer.
- the two bit states correspond to the junction resistance of the parallel and antiparallel orientations of the freelayer relative to the pinned layer.
- the operation of the tunnel barrier device is more complicated than the simple model described above.
- variations in the orientation of the freelayer magnetic moment in nominally the same state, introduce additional noise that the sense amplifiers must discern.
- Defects generated in the sidewalls during the fabrication process can impart the tendency of the magnetic domains to orient in offaxis orientations.
- the reduction of these variations by process improvements is desirable as this results in larger signal margins in a product array. Additional performance is obtained by increasing the signal margin.
- the invention relates to a method for fabricating a magneto-resistive tunnel junction device for use in a memory cell, in which a set of sidewalls protects exposed edges of sensitive layers during etching.
- a feature of the invention is the passivation of the external edges of exposed ferromagnetic layers.
- Another feature of the invention is the formation of sidewalls along the edges of a temporary mandrel that supports the sidewalls and provides a contact into the cell.
- FIGS. 1-8 show in partially pictorial, partially schematic form, cross sections of portions of a magneto resistive tunnel junction device, illustrating the process sequence made to define the invention described herein.
- Substrate 10 illustratively silicon, has been prepared by forming wells, threshold implants, etc. as part of standard integrated circuit processing up to at least the first level of interconnect dielectric deposition.
- conductive interconnection members 20 and 22 have been formed in substrate 10 by damascene processing.
- a dielectric layer, e.g. oxide 30 has been put down and a via 44 and local device wiring interconnect 42 have been formed.
- they are TaN, but any other conductive material compatible with standard processing, e.g. copper, tungsten or aluminum, could be used.
- the top surface of the local device wiring interconnect 42 has been planarized by chemical-mechanical polishing (CMP) as is standard in the field. This surface is critical to optimal MRAM device performance and care must be made to mitigate surface roughness.
- CMP chemical-mechanical polishing
- a blanket stack of magnetic material denoted generally by the numeral 100 , has been deposited to form the basis for the array of MRAM devices.
- Stack 100 shows the generic three layers of a magnetic memory cell the pinned layer ( 110 ), the tunnel barrier layer ( 115 ) and the free layer ( 120 ).
- Each of these layers may be a composite of several sublayers, as shown in U.S. Pat. No. 5,650,958, assigned to the assignee hereof.
- layer 110 in the Figures represents schematically the ferromagnetic pinned layer of the cell, plus additional layers such as a buffer layer 101 on the bottom of layer 110 (e.g. TaN), and a pinning layer 105 (e.g.
- a dielectric tunnel barrier layer 115 (e.g. alumina) separates the two magnetic conductive layers.
- the free layer 120 may also include a cap layer 125 .
- Free layer 120 may be, for example, a layer of permalloy (NiFe).
- the tunnel barrier layer 115 is usually alumina (Al2O3) but any other material providing tunnel barrier characteristics may also be used.
- the pinned layer 110 may be a single layer of CoFe or a composite of CoFe/Ru layers, for example.
- Other ferromagnetic materials may be used in place of those described herein to perform the same device function.
- other alloy compositions of CoFe are employed as pinned ferromagnetic layers and also alloys of CoFe alloyed with B, Si, for example are used for the freelayer 120 .
- a layer of appropriate magnetic materials is etched to define sections of appropriate dimension.
- the tunnel junction of the device is defined by etching the free magnetic layer and stopping on the tunnel barrier layer.
- a protective spacer covering the edges of the free layer and tunnel barrier interface is fabricated before a second etch is made to either isolate the devices or to etch through the pinned magnetic layer beneath the junction.
- the second etch process is self-aligned to the first, which improves the symmetry of the magnetic flux that couples the softlayer to the hard or pinned layer on the bottom interface of the tunnel barrier. This improves the electrical switching characteristics of the device.
- An advantageous feature of the invention is a temporary mandrel that enables the formation of a self-aligned vertical electrode for contact to the free layer of the device.
- the disposable mandrel is used to support an etch mask in the form of a spacer along the sidewall of the mandrel and the etched freelayer to the tunnel barrier interface.
- An advantage of this method is that the height if the mandrel can be substantial, which allows the formation of a sufficient etch mask with a thin sidewall. This feature is not required, however, for the sidewall spacer formation and a more traditional approach using a conductive hardmask, such as TiN or TaN, can also be used.
- Another advantage of the invention is the formation of a passivation layer, which reduces pinning of magnetic domains in the free layer from imperfections in the device sidewall. Ideally, this reduction of pinning allows the freelayer to switch into two distinct predefined states thereby providing improved signal-to-noise conditions for the array sense amplifier. It is necessary for such signal improvement that the material surrounding the mandrel be deposited directly onto the exposed surface of the junction which is the case for spacer deposition according to the invention. Utilizing the sidewall spacer to provide junction passivation permits this additional requirement to be satisfied independent of the choice of interlevel dielectric material, e.g. alumina or nitride.
- the junction protection provided by the sidewall spacer of the invention is particularly useful for the formation of a cross point memory array directly on copper wiring.
- This cell architecture requires the fabrication of the magneto-resistive device directly on the interconnect wiring beneath the device. The fabrication of this device requires etching completely through the magnetic metal stack, thereby exposing the copper metal interconnect. The sputter yield of copper is relatively large, which increases the rate of redeposited metal during etch thereby increasing the probability of junction shorting. By providing a dielectric spacer along the sidewall of the tunnel junction, the potential for sidewall shorting is substantially reduced.
- the bit stored in the cell is read by flowing current through the tunnel barrier of the device from a contact shown in later figures through stack 100 and then through interconnections 42 , 44 and 20 .
- the bit is written by flowing a current horizontally in the figure through adjacent interconnect wiring below and above the device, e.g. wiring interconnect 22 and one of the layers in the stack, also as is conventional for the magneto resistive device design illustrated in the figures.
- the so-called offset cell architecture features a magneto resistive device wired in series with a transistor to provide increased signal and faster access time.
- the crosspoint device design wires the magneto resistive device between adjacent wiring levels in an integrated circuit which results in a common bottom contact for the read and write operations.
- an illustrative cell in the array is patterned by first forming a mandrel 60 on the stack of magnetic materials, the mandrel comprising a spinon glass 61 (SOG,) a dielectric mask bottom layer of nitride 62 and an upper layer of oxide 64 .
- Alternative hardmask materials such as TiN or TaN, may similarly be used in the patterning process, as those skilled in the art are aware.
- the mandrel hardmask 60 for the subsequent metal etch process is formed and the magnetic layers are etched using the mandrel as a mask.
- the ferromagnetic freelayer 120 is etched, stopping on the tunnel layer 115 to define cell layers 122 and 117 , respectively, shown in FIG. 3 .
- the freelayer etch process could etch through the tunnel barrier layer 115 and pinned layer 110 stopping on or in the pinning layer that is a lower level in the composite layer 110 .
- the etch proceeds through TaN cap layer 125 and freelayer 120 and stops on the barrier layer 115 , using, for example, a chlorine-based reactive etch chemistry masked by the mandrel structure 60 or alternative conductive hardmask.
- a chlorine-based reactive etch chemistry masked by the mandrel structure 60 or alternative conductive hardmask.
- Another option would employ a similar etch chemistry to etch the freelayer 120 , barrier layer 115 and pinned layer 110 , stopping on or in the pinning layer 105 that is the next level in the composite layer 110 .
- the etch chamber process conditions are adjusted together with plasma emission spectroscopy measurements to facilitate an endpoint signal for an etch stop on the particular layer.
- the freelayer 120 and barrier layer 115 are about forty and ten Angstroms thick, respectively, requiring etch selectivity control to achieve the stop on the barrier in addition to the previous process controls.
- the result is shown in FIG. 3 , with the upper layers of the magnetic stack patterned.
- An important problem addressed by the invention is that of current leakage along these stack edges and also direct shorting of the barrier layer 115 , which are caused in prior art fabrication by sputtering of metal from the pinned layer 110 or pinning layer.
- the sidewall redeposition is more of a problem with the crosspoint device structure since copper, which has a high sputter yield, is exposed during the metal stack etch.
- a blanket dielectric layer 72 such as SiN, Al2O3, or other material that can be deposited at a temperature compatible with back end processing and can be removed with a directional etch, is conformally deposited on the wafer as shown in FIG. 4 .
- the properties of the material are designed to minimize the leakage current along the device sidewalls, in addition to optimizing device characteristics such as reliability.
- This layer is then etched with a suitable fluorine-based dielectric etch chemistry available in commercial etch tooling to form the passivation sidewall spacer 82 shown in FIG. 5 .
- layer 110 is etched outside the sidewall spacer 82 , leaving the structure shown in FIG. 6 , with the cell stack having sidewall spacer 82 that rests on horizontal projections of layer 112 , formed from the composite pinned layer.
- the stack material at the edges of the free and tunnel layers is passivated by dielectric 72 and/or the material of sidewalls 82 . Any sputtering from the exposed surfaces of pinned ferromagnetic layer 110 , the pinning layer 105 , the buffer layer 101 , or metal 42 will not deposit on the exposed edges of layers 122 and 117 because of the protective effect of sidewalls 82 .
- the mandrel hardmask structure 60 with the sidewall spacer 82 formed around the perimeter of the device, illustrated in FIG. 6 is then used to complete the metal etch process for the particular device.
- the additional etch process involves etching through pinned layer 110 stopping on or in the pinning layer. This results in formation of the shaped layers 122 , 117 and 112 , shown also in FIG. 6 . It may also be desirable to etch through the pinning layer 105 , stopping on the TaN buffer layer 101 at the bottom of composite layer 110 . Another option is to etch through the pinned layer 110 , the pinning layer 105 and the TaN buffer layer 101 .
- This last method is preferably used to pattern the crosspoint device or the offset device using a damascene wiring strap 42 illustrated in FIG. 1 .
- the wiring strap is formed prior to deposition of magnetic layer 100 . Any of these options can be used for the offset device structure with appropriate modifications to the device structure. Following patterning of the device junction, the offset cell might require, depending on the etch option chosen from the previous paragraph, an additional lithography and metal etch step for the formation of the local wiring strap.
- a relatively thick dielectric layer 86 is deposited over the entire structure, including the space between cells, to a depth sufficient to allow for formation of a contact. Excess amounts of layer 86 are removed to expose the top surface of mandrel 60 .
- the mandrel is removed in a conventional dielectric etch, leaving an aperture 66 having layer 122 (the top layer of the magnetic stack 100 ) on its bottom, that will be filled with an electrode for the cell.
- the etch is made using a oxygen based plasma strip process, with substantial selectivity to the cap layer material 122 .
- a layer of copper is deposited to form electrode 92 .
- final dielectric 86 is SiLK(TM) or other low-k material for a high-performance integrated circuit.
- Other conventional interlayer dielectric materials could be used, as well, especially if high switching speed is not required in the particular application.
- FIG. 8 A final structure is shown in FIG. 8 , in which a second metal layer 95 has been deposited and planarized, making contact with electrode 92 .
- a second metal layer 95 has been deposited and planarized, making contact with electrode 92 .
- the substrate may be SiGe, GaAs or any other semiconductor.
- the cell has been shown as resting on the substrate, but may be formed at a higher level in the total integrated circuit structure.
- the structure of having the pinned layer on the bottom may be reversed with the free layer on the bottom and the pinned layer on the top.
- the electrical connections are preferably copper in a low-k dielectric, but may be aluminum in oxide or any other combination meeting the electrical requirements of the chip being fabricated.
- the chip may be a magnetic random access memory or may be a logic chip containing an array of memory cells in it.
Abstract
A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.
Description
- The field of the invention is that of magnetic random access memory (MRAM), in particular the design of an array device to improve the fabrication process yield.
- Magneto resistive tunnel junction devices used in a random access memory array are formed by depositing a blanket metal stack comprised of a pinned magnetic layer, a tunnel barrier layer and a free magnetic layer, such as that described in U.S. Pat. No. 5,650,958. Several process steps are made to define the magneto resistive tunnel junction device that comprises the storage element of a memory array cell. The bit is written by orienting the net magnetic moment of the free layer parallel or antiparallel to the pinned layer magnetic moment. The bit is read by sensing the amount of current tunneling through the barrier junction from the free layer to the pinned layer. The two bit states correspond to the junction resistance of the parallel and antiparallel orientations of the freelayer relative to the pinned layer.
- In practice, the operation of the tunnel barrier device is more complicated than the simple model described above. In a product array of magneto resistive tunnel barrier devices, variations in the orientation of the freelayer magnetic moment, in nominally the same state, introduce additional noise that the sense amplifiers must discern. Defects generated in the sidewalls during the fabrication process can impart the tendency of the magnetic domains to orient in offaxis orientations. The reduction of these variations by process improvements is desirable as this results in larger signal margins in a product array. Additional performance is obtained by increasing the signal margin.
- Workers in the field are aware that during the reactive ion etching (or dry etching) process of patterning the stack, the reactive ions cause exposed metal to sputter. Some of the sputtered material lands on the exposed sides of the upper layers of the etched stack. Metal deposited across the tunnel barrier can cause an excessive leakage or shunt path along the exposed vertical etched surface that forms the sidewall of the storage device. This can result in a defective bit in the memory storage array. This problem is more pronounced for the cross point memory architecture, in which the interconnect metal, usually copper, is exposed during the device etch increasing the probability for shorting the junction.
- The invention relates to a method for fabricating a magneto-resistive tunnel junction device for use in a memory cell, in which a set of sidewalls protects exposed edges of sensitive layers during etching.
- A feature of the invention is the passivation of the external edges of exposed ferromagnetic layers.
- Another feature of the invention is the formation of sidewalls along the edges of a temporary mandrel that supports the sidewalls and provides a contact into the cell.
-
FIGS. 1-8 show in partially pictorial, partially schematic form, cross sections of portions of a magneto resistive tunnel junction device, illustrating the process sequence made to define the invention described herein. - Referring to
FIG. 1 , there is shown in cross section a portion of an integrated circuit that is being prepared for construction of an MRAM cell, part of a memory array.Substrate 10, illustratively silicon, has been prepared by forming wells, threshold implants, etc. as part of standard integrated circuit processing up to at least the first level of interconnect dielectric deposition. - In the portion illustrated here,
conductive interconnection members substrate 10 by damascene processing. To form the next wiring layer, a dielectric layer,e.g. oxide 30 has been put down and a via 44 and localdevice wiring interconnect 42 have been formed. Illustratively, they are TaN, but any other conductive material compatible with standard processing, e.g. copper, tungsten or aluminum, could be used. The top surface of the localdevice wiring interconnect 42 has been planarized by chemical-mechanical polishing (CMP) as is standard in the field. This surface is critical to optimal MRAM device performance and care must be made to mitigate surface roughness. - A blanket stack of magnetic material, denoted generally by the numeral 100, has been deposited to form the basis for the array of MRAM devices. Stack 100 shows the generic three layers of a magnetic memory cell the pinned layer (110), the tunnel barrier layer (115) and the free layer (120). Each of these layers may be a composite of several sublayers, as shown in U.S. Pat. No. 5,650,958, assigned to the assignee hereof. For example, as shown in
FIG. 2B ,layer 110 in the Figures represents schematically the ferromagnetic pinned layer of the cell, plus additional layers such as a buffer layer 101 on the bottom of layer 110 (e.g. TaN), and a pinning layer 105 (e.g. PtMn or IrMn,) placed between the buffer layer and the pinned layer, as well as the ferromagneticpinned layer 110 of CoFe. In the middle of the device, a dielectric tunnel barrier layer 115 (e.g. alumina) separates the two magnetic conductive layers. At the top of the device, the free layer (e.g. NiFe permalloy, TaN or bilayer Ta/TaN) 120 may also include a cap layer 125.Free layer 120 may be, for example, a layer of permalloy (NiFe). Thetunnel barrier layer 115 is usually alumina (Al2O3) but any other material providing tunnel barrier characteristics may also be used. The pinnedlayer 110 may be a single layer of CoFe or a composite of CoFe/Ru layers, for example. Other ferromagnetic materials may be used in place of those described herein to perform the same device function. For example, other alloy compositions of CoFe are employed as pinned ferromagnetic layers and also alloys of CoFe alloyed with B, Si, for example are used for thefreelayer 120. - In the course of fabricating a magneto resistive tunnel junction device to form a random access memory cell, a layer of appropriate magnetic materials is etched to define sections of appropriate dimension. The tunnel junction of the device is defined by etching the free magnetic layer and stopping on the tunnel barrier layer. Following the formation of the tunnel junction, a protective spacer covering the edges of the free layer and tunnel barrier interface is fabricated before a second etch is made to either isolate the devices or to etch through the pinned magnetic layer beneath the junction. In this case the second etch process is self-aligned to the first, which improves the symmetry of the magnetic flux that couples the softlayer to the hard or pinned layer on the bottom interface of the tunnel barrier. This improves the electrical switching characteristics of the device.
- An advantageous feature of the invention is a temporary mandrel that enables the formation of a self-aligned vertical electrode for contact to the free layer of the device. The disposable mandrel is used to support an etch mask in the form of a spacer along the sidewall of the mandrel and the etched freelayer to the tunnel barrier interface. An advantage of this method is that the height if the mandrel can be substantial, which allows the formation of a sufficient etch mask with a thin sidewall. This feature is not required, however, for the sidewall spacer formation and a more traditional approach using a conductive hardmask, such as TiN or TaN, can also be used.
- Another advantage of the invention is the formation of a passivation layer, which reduces pinning of magnetic domains in the free layer from imperfections in the device sidewall. Ideally, this reduction of pinning allows the freelayer to switch into two distinct predefined states thereby providing improved signal-to-noise conditions for the array sense amplifier. It is necessary for such signal improvement that the material surrounding the mandrel be deposited directly onto the exposed surface of the junction which is the case for spacer deposition according to the invention. Utilizing the sidewall spacer to provide junction passivation permits this additional requirement to be satisfied independent of the choice of interlevel dielectric material, e.g. alumina or nitride.
- The junction protection provided by the sidewall spacer of the invention is particularly useful for the formation of a cross point memory array directly on copper wiring. This cell architecture requires the fabrication of the magneto-resistive device directly on the interconnect wiring beneath the device. The fabrication of this device requires etching completely through the magnetic metal stack, thereby exposing the copper metal interconnect. The sputter yield of copper is relatively large, which increases the rate of redeposited metal during etch thereby increasing the probability of junction shorting. By providing a dielectric spacer along the sidewall of the tunnel junction, the potential for sidewall shorting is substantially reduced.
- As those skilled in the art are aware, the bit stored in the cell is read by flowing current through the tunnel barrier of the device from a contact shown in later figures through stack 100 and then through
interconnections e.g. wiring interconnect 22 and one of the layers in the stack, also as is conventional for the magneto resistive device design illustrated in the figures. The so-called offset cell architecture features a magneto resistive device wired in series with a transistor to provide increased signal and faster access time. The crosspoint device design wires the magneto resistive device between adjacent wiring levels in an integrated circuit which results in a common bottom contact for the read and write operations. - Referring to
FIG. 3 , an illustrative cell in the array is patterned by first forming amandrel 60 on the stack of magnetic materials, the mandrel comprising a spinon glass 61 (SOG,) a dielectric mask bottom layer of nitride 62 and an upper layer of oxide 64. Alternative hardmask materials, such as TiN or TaN, may similarly be used in the patterning process, as those skilled in the art are aware. In the manufacturing sequence, themandrel hardmask 60 for the subsequent metal etch process is formed and the magnetic layers are etched using the mandrel as a mask. Theferromagnetic freelayer 120 is etched, stopping on thetunnel layer 115 to definecell layers FIG. 3 . Alternatively, the freelayer etch process could etch through thetunnel barrier layer 115 and pinnedlayer 110 stopping on or in the pinning layer that is a lower level in thecomposite layer 110. - Illustratively, the etch proceeds through TaN cap layer 125 and freelayer 120 and stops on the
barrier layer 115, using, for example, a chlorine-based reactive etch chemistry masked by themandrel structure 60 or alternative conductive hardmask. Another option would employ a similar etch chemistry to etch thefreelayer 120,barrier layer 115 and pinnedlayer 110, stopping on or in the pinning layer 105 that is the next level in thecomposite layer 110. The etch chamber process conditions are adjusted together with plasma emission spectroscopy measurements to facilitate an endpoint signal for an etch stop on the particular layer. Thefreelayer 120 andbarrier layer 115 are about forty and ten Angstroms thick, respectively, requiring etch selectivity control to achieve the stop on the barrier in addition to the previous process controls. The result is shown inFIG. 3 , with the upper layers of the magnetic stack patterned. - An important problem addressed by the invention is that of current leakage along these stack edges and also direct shorting of the
barrier layer 115, which are caused in prior art fabrication by sputtering of metal from the pinnedlayer 110 or pinning layer. The sidewall redeposition is more of a problem with the crosspoint device structure since copper, which has a high sputter yield, is exposed during the metal stack etch. - With the
hardmask mandrel 60 and tunnel barrier of the magneto resistive device patterned, as illustrated inFIG. 3 , ablanket dielectric layer 72 such as SiN, Al2O3, or other material that can be deposited at a temperature compatible with back end processing and can be removed with a directional etch, is conformally deposited on the wafer as shown inFIG. 4 . The properties of the material are designed to minimize the leakage current along the device sidewalls, in addition to optimizing device characteristics such as reliability. This layer is then etched with a suitable fluorine-based dielectric etch chemistry available in commercial etch tooling to form thepassivation sidewall spacer 82 shown inFIG. 5 . After the sidewall formation,layer 110 is etched outside thesidewall spacer 82, leaving the structure shown inFIG. 6 , with the cell stack havingsidewall spacer 82 that rests on horizontal projections oflayer 112, formed from the composite pinned layer. - Advantageously, the stack material at the edges of the free and tunnel layers is passivated by
dielectric 72 and/or the material ofsidewalls 82. Any sputtering from the exposed surfaces of pinnedferromagnetic layer 110, the pinning layer 105, the buffer layer 101, ormetal 42 will not deposit on the exposed edges oflayers sidewalls 82. - The
mandrel hardmask structure 60 with thesidewall spacer 82 formed around the perimeter of the device, illustrated inFIG. 6 , is then used to complete the metal etch process for the particular device. For the offset device illustrated herein, the additional etch process involves etching through pinnedlayer 110 stopping on or in the pinning layer. This results in formation of the shapedlayers FIG. 6 . It may also be desirable to etch through the pinning layer 105, stopping on the TaN buffer layer 101 at the bottom ofcomposite layer 110. Another option is to etch through the pinnedlayer 110, the pinning layer 105 and the TaN buffer layer 101. This last method is preferably used to pattern the crosspoint device or the offset device using adamascene wiring strap 42 illustrated inFIG. 1 . The wiring strap is formed prior to deposition of magnetic layer 100. Any of these options can be used for the offset device structure with appropriate modifications to the device structure. Following patterning of the device junction, the offset cell might require, depending on the etch option chosen from the previous paragraph, an additional lithography and metal etch step for the formation of the local wiring strap. - Referring now to
FIG. 6 , a relatively thickdielectric layer 86 is deposited over the entire structure, including the space between cells, to a depth sufficient to allow for formation of a contact. Excess amounts oflayer 86 are removed to expose the top surface ofmandrel 60. The mandrel is removed in a conventional dielectric etch, leaving anaperture 66 having layer 122 (the top layer of the magnetic stack 100) on its bottom, that will be filled with an electrode for the cell. Illustratively, the etch is made using a oxygen based plasma strip process, with substantial selectivity to thecap layer material 122. As shown inFIG. 7 , a layer of copper is deposited to formelectrode 92. - Illustratively,
final dielectric 86 is SiLK(TM) or other low-k material for a high-performance integrated circuit. Other conventional interlayer dielectric materials could be used, as well, especially if high switching speed is not required in the particular application. - A final structure is shown in
FIG. 8 , in which asecond metal layer 95 has been deposited and planarized, making contact withelectrode 92. Those skilled in the art will be aware that the connections for the write currents for the cell have been omitted from these cross sections, (illustratively they extend perpendicular to the plane of the drawing), for clarity in presentation. - Those skilled in the art will be aware that many different combinations of materials may be used, so long as they are compatible with the etching material and other requirements. The substrate may be SiGe, GaAs or any other semiconductor. The cell has been shown as resting on the substrate, but may be formed at a higher level in the total integrated circuit structure. The structure of having the pinned layer on the bottom may be reversed with the free layer on the bottom and the pinned layer on the top. The electrical connections are preferably copper in a low-k dielectric, but may be aluminum in oxide or any other combination meeting the electrical requirements of the chip being fabricated. The chip may be a magnetic random access memory or may be a logic chip containing an array of memory cells in it.
- While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.
Claims (18)
1. (canceled)
2. (canceled)
3. (canceled)
4. (canceled)
5. (canceled)
6. (canceled)
7. (canceled)
8. (canceled)
9. (canceled)
10. (canceled)
11. A magnetic memory cell comprising a free layer, a pinned layer and a tunnel barrier layer disposed on a vertical axis between said free layer and said pinned layer;
a lower cell electrode disposed vertically beneath said pinned layer and in electrical contact therewith;
an upper cell electrode disposed vertically over said free layer and in electrical contact therewith;
a set of dielectric sidewalls enclosing said cell electrode and extending substantially vertically along at least an exposed edge of said free layer, said dielectric sidewalls being disposed substantially vertically above an extension of said pinned layer that extends horizontally past said free layer.
12. A magnetic memory cell according to claim 11 , in which said dielectric sidewalls are formed from a passivation material, whereby said dielectric sidewalls passivate said exposed edge of said free layer.
13. A magnetic memory cell according to claim 11 , in which said dielectric sidewalls extend vertically through a pinning layer that is a sublayer of said pinned layer, whereby said pinning layer has an exposed edge vertically aligned with said exposed edge of said free layer.
14. A magnetic memory cell according to claim 13 , in which said dielectric sidewalls are formed from a passivation material, whereby said dielectric sidewalls passivate said exposed edge of said free layer.
15. A magnetic memory according to claim 11 , in which said dielectric sidewalls are self-aligned with said extension of said pinned layer, whereby said dielectric sidewalls and said pinned layer have substantially vertical outer edges that are vertically aligned.
16. A magnetic memory according to claim 12 , in which said dielectric sidewalls are self-aligned with said extension of said pinned layer, whereby said dielectric sidewalls and said pinned layer have substantially vertical outer edges that are vertically aligned.
17. A magnetic memory according to claim 13 , in which said dielectric sidewalls are self-aligned with said extension of said pinned layer, whereby said dielectric sidewalls and said pinned layer have substantially vertical outer edges that are vertically aligned.
18. A magnetic memory according to claim 14 , in which said dielectric sidewalls are self-aligned with said extension of said pinned layer, whereby said dielectric sidewalls and said pinned layer have substantially vertical outer edges that are vertically aligned.
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050158882A1 (en) * | 2004-01-16 | 2005-07-21 | Samsung Electronics Co., Ltd | Method of forming nano-sized MTJ cell without contact hole |
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US20200220072A1 (en) * | 2019-01-03 | 2020-07-09 | International Business Machines Corporation | Magnetic tunnel junction (mtj) bilayer hard mask to prevent redeposition |
US11056643B2 (en) | 2019-01-03 | 2021-07-06 | International Business Machines Corporation | Magnetic tunnel junction (MTJ) hard mask encapsulation to prevent redeposition |
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Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7220427B2 (en) * | 1998-07-08 | 2007-05-22 | Oryxe | Mixture for transdermal delivery of low and high molecular weight compounds |
US6943039B2 (en) * | 2003-02-11 | 2005-09-13 | Applied Materials Inc. | Method of etching ferroelectric layers |
JP4008857B2 (en) * | 2003-03-24 | 2007-11-14 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
US6911156B2 (en) * | 2003-04-16 | 2005-06-28 | Freescale Semiconductor, Inc. | Methods for fabricating MRAM device structures |
WO2005010998A1 (en) * | 2003-06-24 | 2005-02-03 | International Business Machines Corporation | Self-aligned conductive lines for fet-based magnetic random access memory devices and method of forming the same |
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US7350284B2 (en) * | 2004-10-29 | 2008-04-01 | Hitachi Global Storage Technologies Netherlands B.V. | Methods of making a current-perpendicular-to-the-planes (CPP) type sensor by ion milling to the spacer layer using a mask without undercuts |
TWI266413B (en) * | 2004-11-09 | 2006-11-11 | Ind Tech Res Inst | Magnetic random access memory with lower bit line current and manufacture method thereof |
DE102004054558A1 (en) * | 2004-11-11 | 2006-05-24 | Infineon Technologies Ag | Phase change random access memory cell manufacturing method, involves back etching portion of structured hard mask by isotropic etching and back etching upper electrode layer and switching active layer by dry etching |
US7105903B2 (en) | 2004-11-18 | 2006-09-12 | Freescale Semiconductor, Inc. | Methods and structures for electrical communication with an overlying electrode for a semiconductor element |
JP2006179701A (en) * | 2004-12-22 | 2006-07-06 | Toshiba Corp | Magnetic random access memory |
US7880249B2 (en) | 2005-11-30 | 2011-02-01 | Magic Technologies, Inc. | Spacer structure in MRAM cell and method of its fabrication |
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US7442647B1 (en) * | 2008-03-05 | 2008-10-28 | International Business Machines Corporation | Structure and method for formation of cladded interconnects for MRAMs |
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US8685756B2 (en) | 2011-09-30 | 2014-04-01 | Everspin Technologies, Inc. | Method for manufacturing and magnetic devices having double tunnel barriers |
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US8883520B2 (en) | 2012-06-22 | 2014-11-11 | Avalanche Technology, Inc. | Redeposition control in MRAM fabrication process |
US8747680B1 (en) * | 2012-08-14 | 2014-06-10 | Everspin Technologies, Inc. | Method of manufacturing a magnetoresistive-based device |
US8790935B1 (en) * | 2012-10-22 | 2014-07-29 | Everspin Technologies, Inc. | Method of manufacturing a magnetoresistive-based device with via integration |
US9865806B2 (en) | 2013-06-05 | 2018-01-09 | SK Hynix Inc. | Electronic device and method for fabricating the same |
KR20150102302A (en) * | 2014-02-28 | 2015-09-07 | 에스케이하이닉스 주식회사 | Electronic device and method for fabricating the same |
US10490741B2 (en) | 2013-06-05 | 2019-11-26 | SK Hynix Inc. | Electronic device and method for fabricating the same |
US9318696B2 (en) | 2014-03-03 | 2016-04-19 | Qualcomm Incorporated | Self-aligned top contact for MRAM fabrication |
US9349939B2 (en) | 2014-05-23 | 2016-05-24 | Qualcomm Incorporated | Etch-resistant protective coating for a magnetic tunnel junction device |
US9793470B2 (en) | 2015-02-04 | 2017-10-17 | Everspin Technologies, Inc. | Magnetoresistive stack/structure and method of manufacturing same |
US10483460B2 (en) | 2015-10-31 | 2019-11-19 | Everspin Technologies, Inc. | Method of manufacturing a magnetoresistive stack/ structure using plurality of encapsulation layers |
US9502640B1 (en) | 2015-11-03 | 2016-11-22 | International Business Machines Corporation | Structure and method to reduce shorting in STT-MRAM device |
EP3319134B1 (en) * | 2016-11-02 | 2021-06-09 | IMEC vzw | An sot-stt mram device and a method of forming an mtj |
US10069064B1 (en) * | 2017-07-18 | 2018-09-04 | Headway Technologies, Inc. | Memory structure having a magnetic tunnel junction (MTJ) self-aligned to a T-shaped bottom electrode, and method of manufacturing the same |
US10461251B2 (en) | 2017-08-23 | 2019-10-29 | Everspin Technologies, Inc. | Method of manufacturing integrated circuit using encapsulation during an etch process |
US11476415B2 (en) * | 2018-11-30 | 2022-10-18 | International Business Machines Corporation | Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features |
JP2021044359A (en) * | 2019-09-10 | 2021-03-18 | キオクシア株式会社 | Magnetic storage device |
CN112531106A (en) * | 2019-09-18 | 2021-03-19 | 中电海康集团有限公司 | Preparation method of magnetic tunnel junction |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5650958A (en) * | 1996-03-18 | 1997-07-22 | International Business Machines Corporation | Magnetic tunnel junctions with controlled magnetic response |
US20040061983A1 (en) * | 2002-09-27 | 2004-04-01 | Childress Jeffrey R. | Magnetic tunnel junction device with bottom free layer and improved underlayer |
US6958927B1 (en) * | 2002-10-09 | 2005-10-25 | Grandis Inc. | Magnetic element utilizing spin-transfer and half-metals and an MRAM device using the magnetic element |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5640343A (en) | 1996-03-18 | 1997-06-17 | International Business Machines Corporation | Magnetic memory array using magnetic tunnel junction devices in the memory cells |
US5734605A (en) | 1996-09-10 | 1998-03-31 | Motorola, Inc. | Multi-layer magnetic tunneling junction memory cells |
US5804458A (en) | 1996-12-16 | 1998-09-08 | Motorola, Inc. | Method of fabricating spaced apart submicron magnetic memory cells |
US5828598A (en) | 1997-05-23 | 1998-10-27 | Motorola, Inc. | MRAM with high GMR ratio |
US5838608A (en) | 1997-06-16 | 1998-11-17 | Motorola, Inc. | Multi-layer magnetic random access memory and method for fabricating thereof |
US6097625A (en) | 1998-07-16 | 2000-08-01 | International Business Machines Corporation | Magnetic random access memory (MRAM) array with magnetic tunnel junction (MTJ) cells and remote diodes |
US6034887A (en) | 1998-08-05 | 2000-03-07 | International Business Machines Corporation | Non-volatile magnetic memory cell and devices |
US6252796B1 (en) | 1998-08-14 | 2001-06-26 | U.S. Philips Corporation | Device comprising a first and a second ferromagnetic layer separated by a non-magnetic spacer layer |
US5940319A (en) | 1998-08-31 | 1999-08-17 | Motorola, Inc. | Magnetic random access memory and fabricating method thereof |
JP4560847B2 (en) | 1998-12-28 | 2010-10-13 | ヤマハ株式会社 | Magnetoresistive random access memory |
US6590806B1 (en) * | 2000-03-09 | 2003-07-08 | Hewlett-Packard Development Company, L.P. | Multibit magnetic memory element |
US6365419B1 (en) | 2000-08-28 | 2002-04-02 | Motorola, Inc. | High density MRAM cell array |
US6538919B1 (en) | 2000-11-08 | 2003-03-25 | International Business Machines Corporation | Magnetic tunnel junctions using ferrimagnetic materials |
US6385082B1 (en) | 2000-11-08 | 2002-05-07 | International Business Machines Corp. | Thermally-assisted magnetic random access memory (MRAM) |
US6358756B1 (en) | 2001-02-07 | 2002-03-19 | Micron Technology, Inc. | Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme |
JP5013494B2 (en) | 2001-04-06 | 2012-08-29 | ルネサスエレクトロニクス株式会社 | Manufacturing method of magnetic memory |
US6485989B1 (en) * | 2001-08-30 | 2002-11-26 | Micron Technology, Inc. | MRAM sense layer isolation |
US6680500B1 (en) * | 2002-07-31 | 2004-01-20 | Infineon Technologies Ag | Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers |
-
2002
- 2002-10-01 US US10/261,709 patent/US6985384B2/en not_active Expired - Lifetime
-
2003
- 2003-09-12 TW TW092125274A patent/TWI243430B/en not_active IP Right Cessation
- 2003-09-24 EP EP03779791A patent/EP1547148B1/en not_active Expired - Fee Related
- 2003-09-24 WO PCT/EP2003/010678 patent/WO2004032144A2/en not_active Application Discontinuation
-
2005
- 2005-02-11 US US11/055,903 patent/US20050146927A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5650958A (en) * | 1996-03-18 | 1997-07-22 | International Business Machines Corporation | Magnetic tunnel junctions with controlled magnetic response |
US20040061983A1 (en) * | 2002-09-27 | 2004-04-01 | Childress Jeffrey R. | Magnetic tunnel junction device with bottom free layer and improved underlayer |
US6958927B1 (en) * | 2002-10-09 | 2005-10-25 | Grandis Inc. | Magnetic element utilizing spin-transfer and half-metals and an MRAM device using the magnetic element |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050158882A1 (en) * | 2004-01-16 | 2005-07-21 | Samsung Electronics Co., Ltd | Method of forming nano-sized MTJ cell without contact hole |
US7220601B2 (en) * | 2004-01-16 | 2007-05-22 | Samsung Electronics Co., Ltd. | Method of forming nano-sized MTJ cell without contact hole |
US20070164338A1 (en) * | 2004-01-16 | 2007-07-19 | Samsung Electronics Co., Ltd. | Method of forming nano-sized MTJ cell without contact hole |
US7397099B2 (en) | 2004-01-16 | 2008-07-08 | Samsung Electronics Co., Ltd. | Method of forming nano-sized MTJ cell without contact hole |
US9893272B2 (en) | 2014-07-30 | 2018-02-13 | Samsung Electronics Co., Ltd. | Magnetic memory device comprising oxide patterns |
US9761792B2 (en) | 2014-11-27 | 2017-09-12 | Samsung Electronics Co., Ltd. | Magnetic random access memory devices and methods of manufacturing the same |
US10164173B2 (en) | 2014-11-27 | 2018-12-25 | Samsung Electronics Co., Ltd. | Magnetic random access memory devices and methods of manufacturing the same |
US20200220072A1 (en) * | 2019-01-03 | 2020-07-09 | International Business Machines Corporation | Magnetic tunnel junction (mtj) bilayer hard mask to prevent redeposition |
US10770652B2 (en) * | 2019-01-03 | 2020-09-08 | International Business Machines Corporation | Magnetic tunnel junction (MTJ) bilayer hard mask to prevent redeposition |
US11056643B2 (en) | 2019-01-03 | 2021-07-06 | International Business Machines Corporation | Magnetic tunnel junction (MTJ) hard mask encapsulation to prevent redeposition |
CN110176535A (en) * | 2019-04-08 | 2019-08-27 | 复旦大学 | A kind of three-dimensional storage and preparation method thereof in self-positioning resistive region |
US11594675B2 (en) | 2020-06-04 | 2023-02-28 | Globalfoundries Singapore Pte. Ltd. | Magnetic tunnel junction structure and integration schemes |
Also Published As
Publication number | Publication date |
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US20040063223A1 (en) | 2004-04-01 |
US6985384B2 (en) | 2006-01-10 |
WO2004032144A3 (en) | 2004-08-05 |
EP1547148A2 (en) | 2005-06-29 |
TW200406034A (en) | 2004-04-16 |
EP1547148B1 (en) | 2012-11-28 |
WO2004032144A2 (en) | 2004-04-15 |
TWI243430B (en) | 2005-11-11 |
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