US20050186787A1 - Semiconductor devices and methods to form a contact in a semiconductor device - Google Patents
Semiconductor devices and methods to form a contact in a semiconductor device Download PDFInfo
- Publication number
- US20050186787A1 US20050186787A1 US11/115,516 US11551605A US2005186787A1 US 20050186787 A1 US20050186787 A1 US 20050186787A1 US 11551605 A US11551605 A US 11551605A US 2005186787 A1 US2005186787 A1 US 2005186787A1
- Authority
- US
- United States
- Prior art keywords
- contact hole
- silicon
- spacer
- semiconductor device
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Abstract
Description
- This patent arises from a divisional application of U.S. application Ser. No. 10/721,978, which was filed on Nov. 25, 2003.
- This disclosure relates generally to semiconductor devices, and, more particularly, to methods to form a contact of a semiconductor device.
- As is well known, the demand for semiconductor devices has been increasing. Various types of contacts, (e.g., contact holes), have been recently developed for semiconductor devices. The contact hole is usually filled with a conductive metal, (e.g., tungsten), to thereby electrically connect a silicon substrate with a wiring board.
-
FIG. 1 is a cross-sectional view of a contact of a conventional semiconductor device. A conventional method for forming the contact of the semiconductor device will now be described: - An insulating layer is formed on a
substrate 1. The insulating layer is then etched to thereby form acontact hole 2. An active region of thesubstrate 1 is exposed through thecontact hole 2. Atungsten diffusion barrier 3, (e.g., a CVD TiN (chemical vapor deposition titanium nitride) layer), is deposited on the sidewalls and an undersurface of thecontact hole 2. Thereafter, thecontact hole 2 is filled with tungsten by depositing tungsten on thetungsten diffusion barrier 3 to thereby form atungsten plug 4. Subsequently, anAl line 5 is deposited on thetungsten plug 4. - The above-mentioned deposition of the CVD TiN layer is usually executed by a MOCVD (metal-organic chemical vapor deposition) method. As a result, many impure atoms, (e.g., C, N, O and the like), are left in the CVD TiN layer. Leakage current can flow through these impure atoms. To reduce the leakage current, attributes of the CVD TiN layer may be enhanced by performing an N2/H2 plasma treatment. That is, the impure atoms in the CVD TiN layer can be reduced by the N2/H2 plasma treatment.
- However, because of the anisotropic property of the N2/H2 plasma treatment, the sidewalls of the
contact hole 2 cannot be treated with the N2/H2 plasma treatment. Since the attributes of the sidewalls of thecontact hole 2 are not enhanced by the N2/H2 plasma treatment, the leakage current may flow through the sidewalls. Therefore, the yield and the reliability of the manufactured semiconductor devices are degraded. -
FIG. 1 is a cross-sectional view of a contact of a conventional semiconductor device. -
FIGS. 2A to 2E illustrate an example method for forming a contact of an example semiconductor device. -
FIGS. 2A to 2E are cross-sectional views of an example contact of an example semiconductor device at various formation stages. As shown inFIG. 2A , aninsulating layer 9 is first formed on asubstrate 1. The insulatinglayer 9 is then etched to thereby form acontact hole 2 with a high aspect ratio. An active region of thesubstrate 1 is exposed through thecontact hole 2. - As shown in
FIG. 2A , asilicon layer 6 is deposited on the sidewalls and an undersurface of thecontact hole 2 and on theinsulating layer 9 with a thickness of, for example, about 50˜200 Å in a furnace. At the time of depositing thesilicon layer 6, it is preferable that temperature range and the pressure range in the furnace are about 500˜700° C. and about 0.1˜1 Torr, respectively. It is also preferred that SiH4 gas be injected into the furnace at the time of depositing the silicon layer at a rate of about 1˜5 slm (standard liters per minute). - Thereafter, as shown in
FIG. 2B , thesilicon layer 6 is anisotropically etched in a chamber in a Cl2/HBr gas atmosphere to thereby form aSi spacer 7 only on the sidewalls of thecontact hole 2. The pressure range in the chamber is preferably, for example, about 1˜50 mTorr during this etching process. Preferably the rates of the amounts of Cl2 and HBr injected into the chamber range are about 10˜50 sccm (standard cubic centimeters per minute) and about 100˜300 sccm, respectively. - Thereafter, as shown in
FIG. 2C , theSi spacer 7 undergoes a NH3 plasma treatment in the chamber by using an ICP (inductive coupled plasma) scheme, to thereby transform theSi spacer 7 into aSiN spacer 8 on the sidewalls of thecontact hole 2, (i.e., to nitrify the Si spacer 7). It is preferable that the pressure range and the rate of injection of the NH3 gas atmosphere in the chamber are about 1˜100 mTorr and about 10˜100 sccm, respectively. Leakage current flowing through the sidewalls of thecontact hole 2 can be greatly reduced by forming theSiN spacer 8 on the sidewalls of thecontact hole 2. - It is also possible that, instead of the NH3 plasma treatment, the
SiN spacer 8 can be formed by annealing theSiN spacer 7 through a N2 or NH3 gas atmosphere heat treatment. It is preferable that the rate of N2 or NH3 gas injected into the chamber is about 5˜20 slm and the temperature range in the chamber is about 600˜800° C. - Thereafter, as shown in
FIG. 2D , aCVD TiN layer 3 is deposited on theSiN spacer 8. The SiNspacer 8 serves as a tungsten diffusion barrier. It is preferable that the thickness of the depositedCVD TiN layer 3 is about 25˜150 Å. The deposition of theCVD TiN layer 3 on the sidewalls of thecontact hole 2 is executed by a MOCVD method. As a result, many impure atoms such as C, N, O and the like are contained in the sidewalls. To prevent leakage current from flowing through the impure atoms, attributes of theCVD TiN layer 3 may be enhanced by N2/H2 plasma treatment. Although, in the course of the N2/H2 plasma treatment, the sidewalls of thecontact hole 2 cannot be treated because of anisotropic property of the N2/H2 plasma treatment, leakage current is not caused by the impure atoms, because theSiN spacer 8 formed on the sidewalls of thecontact hole 2 serves as a leakage current blocking layer. Therefore, the yield and the reliability of the manufactured semiconductor devices are enhanced. - As shown in
FIG. 2E , tungsten is deposited on the CVDTiN layer 3 so that thecontact hole 2 is filled with tungsten. Thereafter, the tungsten outside of thecontact hole 2 is removed by a tungsten CMP (chemical mechanical polishing) process, to thereby form atungsten plug 4 in thecontact hole 2. AnAl line 5 is then deposited on thetungsten plug 4. - From the foregoing, persons of ordinary skill in the art will appreciate that example semiconductor devices having a contact hole with a leakage current blocking layer and example methods for forming a contact with a SiN (silicon nitride) layer serving as a leakage current blocking layer deposited on sidewalls of the contact hole have been disclosed.
- An example method for forming a contact includes: forming an insulating layer on a substrate; etching the insulating layer to form a contact hole; depositing a silicon layer on sidewalls and an undersurface of the contact hole; forming a silicon spacer on the sidewalls of the contact hole by etching the silicon layer anisotropically in a chamber; transforming the silicon spacer into a silicon nitride spacer by plasma treatment in the chamber; depositing a diffusion barrier on the silicon nitride spacer; and filling the contact hole with tungsten.
- An example method for forming a contact includes: forming an insulating layer on a substrate; etching the insulating layer to form a contact hole; depositing a silicon layer on sidewalls and an undersurface of the contact hole; forming a silicon spacer on the sidewalls of the contact hole by etching the silicon layer anisotropically in a chamber; forming a silicon nitride spacer by annealing the silicon spacer through a N2 or NH3 gas atmosphere heat treatment in the chamber; depositing a diffusion barrier on the silicon nitride spacer; and filling the contact hole with tungsten.
- Although certain example methods and apparatus have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/115,516 US20050186787A1 (en) | 2002-12-30 | 2005-04-27 | Semiconductor devices and methods to form a contact in a semiconductor device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0086347A KR100523618B1 (en) | 2002-12-30 | 2002-12-30 | Method for forming a contact hole in a semiconductor device |
KR10-2002-0086347 | 2002-12-30 | ||
US10/721,978 US6911382B2 (en) | 2002-12-30 | 2003-11-25 | Method of forming a contact in a semiconductor device utilizing a plasma treatment |
US11/115,516 US20050186787A1 (en) | 2002-12-30 | 2005-04-27 | Semiconductor devices and methods to form a contact in a semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/721,978 Division US6911382B2 (en) | 2002-12-30 | 2003-11-25 | Method of forming a contact in a semiconductor device utilizing a plasma treatment |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050186787A1 true US20050186787A1 (en) | 2005-08-25 |
Family
ID=32653211
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/721,978 Expired - Fee Related US6911382B2 (en) | 2002-12-30 | 2003-11-25 | Method of forming a contact in a semiconductor device utilizing a plasma treatment |
US11/115,516 Abandoned US20050186787A1 (en) | 2002-12-30 | 2005-04-27 | Semiconductor devices and methods to form a contact in a semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/721,978 Expired - Fee Related US6911382B2 (en) | 2002-12-30 | 2003-11-25 | Method of forming a contact in a semiconductor device utilizing a plasma treatment |
Country Status (2)
Country | Link |
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US (2) | US6911382B2 (en) |
KR (1) | KR100523618B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110180895A1 (en) * | 2008-06-11 | 2011-07-28 | Crosstek Capital, LLC | Method of manufacturing a cmos image sensor |
US20150021770A1 (en) * | 2013-07-16 | 2015-01-22 | Taiwan Semiconductor Manufacturing Company Limited | Back-end-of-line (beol) interconnect structure |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050071677A (en) * | 2002-11-08 | 2005-07-07 | 가부시키가이샤 후지미인코퍼레이티드 | Polishing composition and rinsing composition |
US7199498B2 (en) * | 2003-06-02 | 2007-04-03 | Ambient Systems, Inc. | Electrical assemblies using molecular-scale electrically conductive and mechanically flexible beams and methods for application of same |
JP2005268665A (en) * | 2004-03-19 | 2005-09-29 | Fujimi Inc | Polishing composition |
JP2005268667A (en) * | 2004-03-19 | 2005-09-29 | Fujimi Inc | Polishing composition |
US9202758B1 (en) | 2005-04-19 | 2015-12-01 | Globalfoundries Inc. | Method for manufacturing a contact for a semiconductor component and related structure |
US7217660B1 (en) | 2005-04-19 | 2007-05-15 | Spansion Llc | Method for manufacturing a semiconductor component that inhibits formation of wormholes |
US7704878B2 (en) * | 2005-10-03 | 2010-04-27 | Advanced Micro Devices, Inc, | Contact spacer formation using atomic layer deposition |
US8415734B2 (en) * | 2006-12-07 | 2013-04-09 | Spansion Llc | Memory device protection layer |
KR100861837B1 (en) * | 2006-12-28 | 2008-10-07 | 동부일렉트로닉스 주식회사 | Method of forming a metal line in semiconductor device |
KR102004242B1 (en) | 2013-12-13 | 2019-07-26 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
Citations (12)
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US5514900A (en) * | 1994-03-31 | 1996-05-07 | Crosspoint Solutions, Inc. | Mutlilayered antifuse with intermediate metal layer |
US5998873A (en) * | 1998-12-16 | 1999-12-07 | National Semiconductor Corporation | Low contact resistance and low junction leakage metal interconnect contact structure |
US6362012B1 (en) * | 2001-03-05 | 2002-03-26 | Taiwan Semiconductor Manufacturing Company | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications |
US6468858B1 (en) * | 2001-03-23 | 2002-10-22 | Taiwan Semiconductor Manufacturing Company | Method of forming a metal insulator metal capacitor structure |
US20030139034A1 (en) * | 2002-01-22 | 2003-07-24 | Yu-Shen Yuang | Dual damascene structure and method of making same |
US6624066B2 (en) * | 2001-02-14 | 2003-09-23 | Texas Instruments Incorporated | Reliable interconnects with low via/contact resistance |
US20030218256A1 (en) * | 2002-05-21 | 2003-11-27 | Merchant Sailesh Mansinh | Semiconductor device barrier layer |
US6686288B1 (en) * | 1996-02-21 | 2004-02-03 | Micron Technology, Inc. | Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture |
US6790723B2 (en) * | 1999-01-08 | 2004-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6797619B2 (en) * | 2001-12-18 | 2004-09-28 | Hynix Semiconductor, Inc. | Method of forming metal wire of semiconductor device |
US6891244B2 (en) * | 2002-07-12 | 2005-05-10 | Winbond Electronics Corporation | Plug structure having low contact resistance and method of manufacturing |
US20050170648A1 (en) * | 2001-05-24 | 2005-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to solve via poisoning for porous low-k dielectric |
-
2002
- 2002-12-30 KR KR10-2002-0086347A patent/KR100523618B1/en not_active IP Right Cessation
-
2003
- 2003-11-25 US US10/721,978 patent/US6911382B2/en not_active Expired - Fee Related
-
2005
- 2005-04-27 US US11/115,516 patent/US20050186787A1/en not_active Abandoned
Patent Citations (13)
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US5514900A (en) * | 1994-03-31 | 1996-05-07 | Crosspoint Solutions, Inc. | Mutlilayered antifuse with intermediate metal layer |
US5627098A (en) * | 1994-03-31 | 1997-05-06 | Crosspoint Solutions, Inc. | Method of forming an antifuse in an integrated circuit |
US6686288B1 (en) * | 1996-02-21 | 2004-02-03 | Micron Technology, Inc. | Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture |
US5998873A (en) * | 1998-12-16 | 1999-12-07 | National Semiconductor Corporation | Low contact resistance and low junction leakage metal interconnect contact structure |
US6790723B2 (en) * | 1999-01-08 | 2004-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6624066B2 (en) * | 2001-02-14 | 2003-09-23 | Texas Instruments Incorporated | Reliable interconnects with low via/contact resistance |
US6362012B1 (en) * | 2001-03-05 | 2002-03-26 | Taiwan Semiconductor Manufacturing Company | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications |
US6468858B1 (en) * | 2001-03-23 | 2002-10-22 | Taiwan Semiconductor Manufacturing Company | Method of forming a metal insulator metal capacitor structure |
US20050170648A1 (en) * | 2001-05-24 | 2005-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to solve via poisoning for porous low-k dielectric |
US6797619B2 (en) * | 2001-12-18 | 2004-09-28 | Hynix Semiconductor, Inc. | Method of forming metal wire of semiconductor device |
US20030139034A1 (en) * | 2002-01-22 | 2003-07-24 | Yu-Shen Yuang | Dual damascene structure and method of making same |
US20030218256A1 (en) * | 2002-05-21 | 2003-11-27 | Merchant Sailesh Mansinh | Semiconductor device barrier layer |
US6891244B2 (en) * | 2002-07-12 | 2005-05-10 | Winbond Electronics Corporation | Plug structure having low contact resistance and method of manufacturing |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110180895A1 (en) * | 2008-06-11 | 2011-07-28 | Crosstek Capital, LLC | Method of manufacturing a cmos image sensor |
US20150021770A1 (en) * | 2013-07-16 | 2015-01-22 | Taiwan Semiconductor Manufacturing Company Limited | Back-end-of-line (beol) interconnect structure |
US9093455B2 (en) * | 2013-07-16 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company Limited | Back-end-of-line (BEOL) interconnect structure |
US20150318207A1 (en) * | 2013-07-16 | 2015-11-05 | Taiwan Semiconductor Manufacturing Company Limited | Back-end-of-line (beol) interconnect structure |
US9870944B2 (en) * | 2013-07-16 | 2018-01-16 | Taiwan Semiconductor Manufacturing Company Limited | Back-end-of-line (BEOL) interconnect structure |
Also Published As
Publication number | Publication date |
---|---|
KR20040059842A (en) | 2004-07-06 |
US6911382B2 (en) | 2005-06-28 |
KR100523618B1 (en) | 2005-10-24 |
US20040127017A1 (en) | 2004-07-01 |
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Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:DONGANAM SEMICONDUCTOR INC.;REEL/FRAME:017703/0499 Effective date: 20060328 |
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Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017703 FRAME 0499;ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;REEL/FRAME:017854/0297 Effective date: 20060328 |
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STCB | Information on status: application discontinuation |
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