US20050196960A1 - Method of forming metal silicide film and method of manufacturing semiconductor device having metal silicide film - Google Patents
Method of forming metal silicide film and method of manufacturing semiconductor device having metal silicide film Download PDFInfo
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- US20050196960A1 US20050196960A1 US11/113,980 US11398005A US2005196960A1 US 20050196960 A1 US20050196960 A1 US 20050196960A1 US 11398005 A US11398005 A US 11398005A US 2005196960 A1 US2005196960 A1 US 2005196960A1
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- Prior art keywords
- metal
- film
- containing film
- silicon
- semiconductor substrate
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 89
- 239000002184 metal Substances 0.000 title claims abstract description 89
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 77
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 77
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims description 68
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 239000010936 titanium Substances 0.000 claims description 51
- 230000008569 process Effects 0.000 claims description 37
- 230000015572 biosynthetic process Effects 0.000 claims description 30
- 238000004140 cleaning Methods 0.000 claims description 30
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 19
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 18
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 17
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 14
- 239000000203 mixture Substances 0.000 claims description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 229910015421 Mo2N Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 6
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
- 239000000908 ammonium hydroxide Substances 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 229910052758 niobium Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 241000849798 Nita Species 0.000 claims description 3
- 229910019899 RuO Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910008764 WNx Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 48
- 229910017052 cobalt Inorganic materials 0.000 description 46
- 239000010941 cobalt Substances 0.000 description 46
- 239000000523 sample Substances 0.000 description 28
- 238000012360 testing method Methods 0.000 description 28
- 239000000243 solution Substances 0.000 description 26
- 239000013068 control sample Substances 0.000 description 24
- 238000000992 sputter etching Methods 0.000 description 21
- 239000012535 impurity Substances 0.000 description 19
- 238000000151 deposition Methods 0.000 description 15
- 230000008021 deposition Effects 0.000 description 9
- 125000006850 spacer group Chemical group 0.000 description 9
- 229910019001 CoSi Inorganic materials 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 238000004151 rapid thermal annealing Methods 0.000 description 8
- 238000001878 scanning electron micrograph Methods 0.000 description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 230000007423 decrease Effects 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 201000010384 renal tubular acidosis Diseases 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000002829 reductive effect Effects 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 229910021244 Co2Si Inorganic materials 0.000 description 5
- 238000011068 loading method Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 238000003917 TEM image Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 3
- -1 argon ions Chemical class 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 239000010955 niobium Substances 0.000 description 3
- 238000001552 radio frequency sputter deposition Methods 0.000 description 3
- 238000005001 rutherford backscattering spectroscopy Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 3
- 229910000531 Co alloy Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000979 retarding effect Effects 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- 238000010005 wet pre-treatment Methods 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/58—After-treatment
- C23C14/5806—Thermal treatment
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/02—Pretreatment of the material to be coated
- C23C14/021—Cleaning or etching treatments
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
- C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/58—After-treatment
- C23C14/5873—Removal of material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Definitions
- the present invention generally relates to the fabrication of semiconductor devices, and more particularly, the present invention relates to a method of forming a metal-containing film and to a method of manufacturing a semiconductor device having a metal silicide film.
- MOS metal oxide semiconductor
- Si 2 monocobalt disilicide
- CoSi 2 monocobalt disilicide
- a cobalt silicide film having poor characteristics can result if impurities such as silicon oxide and silicon nitride are present at a surface of a silicon region on which the cobalt silicide film is formed. For this reason, prior to deposition of the cobalt silicide film, a substrate surface is conventionally wet-cleaned and then etched by radio frequency (RF) sputtering. Unfortunately, however, substrate surface defects can result since RF sputter etching using argon ions (Ar + ) is a physical etching process. In addition, resputtering occurs during the RF sputter etching which can result in a poorly formed cobalt silicide film, which can create short-circuits between active regions.
- RF radio frequency
- FIG. 1 is a plan view of a semiconductor device in which a cobalt silicide film has created a short-circuit between active regions.
- reference numeral 3 denotes an active region
- reference numeral 4 is a well region boundary
- reference numeral 5 denotes a gate
- reference numeral 7 denotes a gate spacer
- reference numeral 11 c indicates a cobalt silicide film.
- the colbalt silicide film 11 c is defective in that it connects adjacent active regions 3 across the well region boundary 4 .
- FIG. 2 is a diagram to illustrate the occurrence of resputtering during RF sputter etching
- FIG. 3 is a diagram illustrating a poorly formed cobalt silicide film resulting from the resputtering.
- FIGS. 2 and 3 are sectional views taken along line 11 - 11 ′ of FIG. 1 .
- an oxide 2 a of a shallow trench device isolation region (STI) 2 and/or a nitride 7 a of a spacer 7 is resputtered onto an active region 3 or a gate 5 of a semiconductor device. Also, silicon 3 a of the active region 3 is resputtered on the spacer 7 .
- STI shallow trench device isolation region
- the resputtered oxide 2 a and nitride 7 a cause a cobalt silicide film 11 a formed on the active region 3 and a cobalt silicide film 11 b formed on the gate 5 to have a nonuniform thickness.
- the resputtered silicon 3 a causes a cobalt silicide film 11 c to be formed along sidewalls of the spacer 7 . This can result in the short-circuiting of active regions 3 as shown in FIG. 1 .
- transformation of a cobalt film 11 formed on the front surface of a substrate into a cobalt silicide film mainly takes place at the edges of a gate 5 a pattern and the edges at which the STI 2 and active region 3 are in contact with each other.
- This phenomenon is called an “edge effect” and is denoted by reference number 13 in FIG. 4 .
- the edge effect causes the thickness of the cobalt silicide film 11 d to increase, which in turn causes loading of the Rs of the silicide film, making it difficult to adjust the Rs value.
- the edge effect can cause leakage current at the source/drain region 8 .
- the thickness of a cobalt silicide film 11 e formed at the gate 5 b having a small CD is almost twice as large as that of the cobalt silicide film 11 d formed at the gate 5 a having a larger CD. This creates a limitation in decreasing the aspect ratio of the gate 5 b pattern, which adversely affects the process margin for subsequent processes.
- the present invention provides a method of forming a metal silicide film having favorable characteristics.
- An embodiment of the present invention provides a method of forming a silicide film by forming a metal-containing film on a surface of a semiconductor substrate having an insulating region and a silicon-containing conductive region, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the silicon-containing conductive region, and annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
- Another embodiment of the present invention provides a method of manufacturing a semiconductor device by forming an isolation region defining an active region on a semiconductor substrate, forming on the active region a transistor having source/source regions and a gate, forming a metal-containing film on a surface of the semiconductor substrate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the semiconductor substrate with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate, and annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
- FIG. 1 is a plan view illustrating a short-circuit between active regions resulting from a conventional method of forming a cobalt silicide film
- FIG. 2 is a sectional view illustrating a resputtering that occurs during a conventional method of forming a cobalt silicide
- FIG. 3 is a sectional view illustrating a poorly formed cobalt silicide film formed by resputtering
- FIG. 4 is a sectional view to illustrate an edge effect resulting from a conventional method of forming a cobalt silicide film, and a loading of the sheet resistance (Rs) of the silicide film caused by the edge effect;
- FIG. 5 is a flow chart of a method of forming a cobalt silicide film according to one embodiment of the present invention.
- FIGS. 6A through 6D are sectional views of intermediate structures formed in the steps disclosed in FIG. 5 ;
- FIG. 7 is a sectional view to illustrate a diffusion restraint characteristic of an interface film formed in the deposition of a cobalt film at a high temperature
- FIGS. 8A and 8B are scanning electron microphotographs (SEMs) of cobalt silicide films formed according to an embodiment of the present invention.
- FIGS. 9A and 9B are SEMs of control sample cobalt silicide films for comparison with the films of FIGS. 8A and 8B ;
- FIGS. 10A and 10B are graphs showing Rs values of gates having cobalt silicide films according to an embodiment of the present invention and according to a conventional method;
- FIG. 11A is a graph showing secondary ion-mass spectrometric (SIMS) results after primary rapid thermal annealing (RTA) according to an embodiment of the present invention and according to a conventional method;
- SIMS secondary ion-mass spectrometric
- FIG. 11B is a graph showing SIMS results after a selective wet etching according to an embodiment of the present invention and according to a conventional method;
- FIG. 12 is a graph showing a leakage current of a test sample which has been pretreated by a wet-clean process only according to the present invention, and a leakage current of a control sample which has been pretreated by a wet-clean process and then etched by radio frequency (RF) sputtering according to a conventional method;
- RF radio frequency
- FIG. 13A is a transmission electron microphotograph (TEM) of a sample formed after depositing a cobalt film at a high temperature according to an embodiment of the present invention
- FIGS. 13B and 13C show selected area diffraction (SAD) patterns of an interface film formed by the high temperature deposition in FIG. 13A ;
- FIG. 14 is a graph showing leakage current characteristics in the case of depositing a cobalt film at a high temperature according to an embodiment of the present invention and in the case of depositing a cobalt film according to a conventional method.
- Embodiments of the present invention disclose the deposition of a titanium (Ti) rich film on a previously formed metal-containing film.
- Ti which is abundantly present in a capping film, diffuses toward an interface between the metal-containing film and an underlying silicon containing layer, such as a bulk Si film or a (poly)Si film, which assists in the removal of oxides and nitrides at the interface.
- the removal of oxides and nitrides results in high quality metal silicide film.
- the present invention further discloses the use of a wet pretreatment process that sufficiently removes a natural oxide film formed at a surface intended for formation of the metal silicide film. Pretreatment by radio frequency (RF) sputter etching may or may not be required.
- RF radio frequency
- the phrase “wet cleaning is used/carried out alone” means that a RF sputter etching is omitted in the pretreatment process. Still further, the present invention discloses the formation of a metal film at a high temperature to compensate for the small process window for formation of a metal silicide film resulting from the edge effect.
- the metal-containing film can be selected from TaN, NiTa, Ti, TiN, Ta, W, WN, Hf, Nb, Mo, RuO 2 , Mo 2 N, Ni , Ir, Pt, Cr, RuO, Mo 2 N, WNx, and combination thereof.
- FIG. 5 is a flow chart of a method of forming a cobalt silicide film according to an embodiment of the present invention.
- FIGS. 6A through 6D are sectional views of intermediate products resulting from the process steps of FIG. 5 .
- a transistor is formed (step S 1 ).
- a shallow trench isolation (STI) region 102 using a conventional process
- an N-well 101 and a P-well are formed on a p-type Si substrate 100 by ion injection.
- an oxide film is formed to a thickness of 110 to 130 ⁇ and a poly-Si film is formed to a thickness of 1,500 to 2,500 ⁇ , followed by successive patterning, to form a gate 105 and a gate oxide film 104 .
- the gate oxide film 104 may be formed by depositing an oxide such as silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, and lanthanum oxide using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD).
- the gate 105 made of poly-Si may be formed by depositing poly-Si doped with impurity using low pressure CVD (LPCVD). Poly-Si may be simultaneously deposited with impurity doping, or may be doped with impurity after deposition. Then, ion injection is carried out to form a lightly doped drain (LDD) region.
- LDD lightly doped drain
- a LDD 106 n for an NMOS transistor is formed by injecting an n-type ion such as As + , and then a LDD 106 p for a PMOS transistor is formed by injecting a p-type ion such as BF 2 + . Then, a spacer 107 is formed at a sidewall of the gate 105 .
- the spacer 107 may be a silicon nitride film or may be a laminated structure of a middle temperature oxide (MTO) film and a silicon nitride film.
- MTO middle temperature oxide
- an n+ source/drain region 108 n is formed by injecting an n-type ion such as As +
- a p+ source/drain region 108 p is formed by injecting a p-type ion such as BF 2 +.
- an NMOS source/drain ( 109 n ) and a PMOS source/drain ( 109 p ) are formed.
- FIGS. 5 and 6 B illustrates a pretreatment process (steps S 2 and S 3 ′).
- a Co-containing film 111 is formed (step S 3 ) is formed followed by the formation of a Ti-rich capping film 113 (step S 4 ).
- impurities for example, natural oxide films formed on the source/drain regions 109 n and 109 p and the gate 105 , and/or nitride particles remaining from formation of the spacer 107 , are removed.
- a wet cleaning (step S 2 ) may be used alone or in combination with RF sputter etching (step S 3 ′).
- Impurities such as oxide and nitride may also be generated due to resputtering caused after RF sputter etching. However, as will be described later, these impurities are typically removed by Ti which is abundantly present in the capping film 113 .
- the RF sputter etching can be selectively carried out as required. Various modifications in the wet cleaning may be made according to whether or not the subsequent RF sputter etching is carried out. In a case where the RF sputter etching is carried out, the wet cleaning may be lightly carried out. On the other hand, in a case where the RF sputter etching is omitted, the wet cleaning is carried out so that impurities such as a natural oxide film are completely removed.
- the wet cleaning may be carried out in two processes.
- the first process for the wet cleaning is divided into three steps: using a hydrogen fluoride (HF) solution diluted with deionized (DI) water (first step); using a mixture solution (also known as SC1 solution) of ammonium hydroxide, hydrogen peroxide (H 2 O 2 ), and water (second step); and, using a HF solution diluted with DI water.
- HF hydrogen fluoride
- DI deionized
- second step a mixture solution
- a HF solution diluted with DI water A 100:1 diluted HF solution or a 200:1 diluted HF solution may be used as the diluted HF solution.
- the first step is carried out for about 10 to 300 seconds, preferably about 150 seconds
- the second step is carried out at a temperature of 40 to 90° C., preferably 70° C., for about 1 to 60 minutes, preferably about 30 minutes
- the third step is carried out for about 10 to 300 seconds, preferably about 60 seconds.
- the second process for the wet cleaning is divided into two steps: using a mixture solution of sulfuric acid and H 2 O 2 (first step) and using a HF solution diluted with DI water (second step).
- the ratio of sulfuric acid to H 2 O 2 is 6 to 1.
- a 100:1 diluted HF solution or a 200:1 diluted HF solution may be used as the diluted HF solution.
- the first step is carried out at 120° C. for about 500 to 700 seconds, preferably 600 seconds
- the second step is carried out for 150 to 300 seconds, preferably 250 seconds.
- the steps in the above-described two wet cleaning processes may be carried out for a shorter time.
- the wet cleaning may be carried out only using a diluted HF solution.
- the Co-containing film 111 is conformally formed along an exposed stepped surface of the substrate 100 (step S 3 ).
- the Co-containing film 111 may be a pure Co film made of 100% Co or a Co alloy film.
- the Co alloy film contains 20 or less atomic % of one selected from tantalum (Ta), zirconium (Zr), titanium (Ti), nickel (Ni), hafnium (Hf), tungsten (W), platinum (Pt), palladium (Pd), vanadium (V), niobium (Nb), and mixtures thereof.
- the Co-containing film 111 is formed by sputtering.
- the thickness of the Co-containing film 111 is determined according to the critical dimension (CD) or height of the gate 105 .
- CD critical dimension
- the CD of the gate is 100 nm, it is preferable to form the Co-containing film to a thickness of less than 150 ⁇ .
- the Co-containing film 111 may be deposited at a temperature higher than room temperature. However, it is preferable to deposit the Co-containing film 111 at a high temperature of 300 to 500° C.
- Co of the Co-containing film 11 reacts with Si of the source/drain regions 109 n and 109 p and poly-Si of the gate 105 , to thereby form an interface film 115 a made of dicobalt monosilicide (Co 2 Si) or monocobalt monosilicide (CoSi).
- the interface film 115 a serves to restrain diffusion of Co during a subsequent annealing process. The detailed description thereof will be described later.
- Ti-rich capping film 113 is formed on the Co-containing film 111 (step S 4 ).
- Ti-rich capping film indicates a film with a Ti/other elements atomic % ratio of more than 1.
- the Ti-rich capping film may be one selected from the group consisting of a titanium nitride film with a Ti/nitrogen (N) atomic % ratio of more than 1, a titanium tungsten film with a Ti/W atomic % ratio of more than 1, a laminated structure of a pure Ti film and a titanium nitride film with a Ti/N atomic % ratio of more than 1, a laminated structure of a pure Ti film and a titanium nitride film with a Ti/N atomic % ratio of less than 1, a laminated structure of a pure Ti film and a titanium tungsten film with a Ti/W atomic % ratio of more than 1, and a laminated structure of a pure Ti film and a titanium tungsten film with a Ti/W atomic % ratio of less than 1.
- the Ti-rich capping film 113 may also be a pure Ti film made of 100% Ti.
- the capping film 113 is also formed by sputtering.
- the capping film 113 with a desired composition ratio can be formed by depositing a Ti target while adjusting the flow rate of a nitrogen gas supplied into a sputtering apparatus. The function of the capping film 113 will be described later.
- the RF sputter etching (step S 3 ′), the formation of the Co-containing film (step S 3 ), and the formation of the Ti-rich capping film (step S 4 ) are formed in situ.
- the resultant structure having the Co-containing film 111 and the Ti-rich capping film 113 are annealed at a low temperature (step S 5 ).
- the low temperature annealing may be a rapid thermal annealing (RTA) at a temperature range of 350 to 650° C.
- Ti in the capping film 113 efficiently removes residual impurities on upper surfaces of the source/drain regions 109 n and 109 p, and the gate 105 , which are in contact with the Co-containing film 111 .
- the Ti removes impurities such as oxide, nitride, and silicon, which are generated by the RF sputter etching for pretreatment carried out before the formation of the Co-containing film 111 .
- Ti also removes impurities generated on an exposed surface of the substrate 100 during a delay time between the wet cleaning and the formation of the Co-containing film 111 when the RF sputter etching is omitted. Such a delay time is caused because the wet cleaning and the formation of the Co-containing film are not carried out in situ.
- the Ti-rich capping film 113 serves to prevent formation of poor quality cobalt silicide film otherwise caused by impurities generated by the RF sputter etching.
- the Ti can remove impurities generated on the surface of the substrate 100 as a result of the exposure. Therefore, a process window for a delay time between the wet cleaning and the formation of the Co-containing film 111 is increased.
- Co of the Co-containing film 111 diffuses toward the source/drain regions 109 n and 109 p and the gate 105 and then reacts with (poly)Si to thereby form a high quality CoSi film 115 b.
- the diffusion restraint interface film 115 a made of Co 2 Si or CoSi formed upon the formation of the Co-containing film 111 at 300 to 500° C. serves to decrease the diffusion speed of the Co, thereby retarding the formation of a cobalt silicide film. That is, referring to FIG. 7 , Co 2 Si or CoSi that constitutes the diffusion restraint interface film 115 a is in a polycrystalline phase. For this reason, Co of the Co-containing film 111 placed on the interface film 115 a can diffuse toward the substrate 100 only through diffusion paths 200 , i.e., polycrystalline grain boundaries. The number of diffusion paths 200 in the presence of the interface film 115 a is less than the number of diffusion paths 250 in the absence of the interface film 115 a. For this reason, in the presence of the interface film 115 a, less of the Co reacts with Si. Therefore, Rs loading and an increase in leakage current caused by the edge effect can be inhibited.
- a wet etching is carried out to selectively remove the capping film 113 and any remaining unreacted Co-containing film 111 by the low temperature annealing (step S 6 ).
- the wet etching is carried out using a mixture solution of sulfuric acid and ammonium hydroxide or a mixture solution of phosphoric acid, acetic acid, nitric acid, and H 2 O 2 .
- an annealing at a high temperature is carried out (step S 7 ).
- the CoSi film 115 b is transformed into a CoSi 2 film 115 c having low resistance.
- the CoSi 2 film 115 c is more stable and has a lower resistance, when compared to the CoSi film 115 b.
- the high temperature annealing may be a rapid thermal anneal (RTA) at a temperature range of 700 to 900° C.
- Embodiments described with reference to FIGS. 5 through 7 are directed to a self-align silicide process. If required, a silicide blocking film may be formed to protect regions which do not require cobalt silicidation.
- a silicide film is formed only on a gate to decrease a gate resistance and to maintain an optimal refresh time. Therefore, a silicide film is not formed on an active region.
- a silicide film is formed both on an active region and a gate or on a part of the active region and a part of the gate to reduce a contact resistance or a sheet resistance of the gate and source/drain.
- a silicide film is formed only on a gate to maintain an optimal refresh time.
- a silicide film is formed only on a gate to prevent a resistance increase resulting from a decrease in gate length accompanying an increase in pattern density.
- a silicide film may be formed only on a source/drain region.
- the silicide blocking film is used to expose only regions intended for formation of a silicide film.
- the formation of the silicide blocking film may be carried out prior to the wet cleaning.
- a cobalt silicide film on a source/drain and a gate has been described. However, it is understood that a cobalt silicide film can be formed at any conductive regions made of (poly) Si that require a low resistance.
- a six-transistor (6Tr)-SRAM cell was manufactured on a semiconductor wafer substrate according to 110 nm design rules using the following method of forming a cobalt silicide film according to the present invention to prepare a test sample.
- the front surface of the substrate having a poly-Si gate pattern with a sidewall spacer and a source/drain region was wet-cleaned using a SC1 solution and then a HF solution.
- the substrate was etched by RF sputtering using argon (Ar) gas to remove an oxide film to a thickness of 50 ⁇ , a Co film was formed to a thickness of 100 ⁇ by sputtering, and a Ti-rich, titanium nitride capping film was formed to a thickness of 100 ⁇ with N 2 gas.
- the RF sputter etching, the formation of the Co film, and the formation of the titanium nitride capping film were formed in situ. According to a Rutherfold backscattering spectroscopy (RBS) analysis, a Ti/N atomic % ratio in the capping film was 3.33.
- a primary RTA was carried out at 450° C. for 90 seconds, the capping film and unreacted Co film were removed by a mixture solution of sulfuric acid and H 2 O 2 , and then a secondary RTA was carried out at 800° C. for 30 seconds.
- FIGS. 8A and 8B The scanning electron microphotographs (SEMs) of CoSi 2 films obtained are illustrated in FIGS. 8A and 8B .
- FIG. 8A is a top plan view of a gate and
- FIG. 8B is a top plan view of an active region exposed by a contact pattern.
- a control sample was prepared under the above-described process conditions except that the capping film was formed at an N 2 flow rate of 85 sccm. According to a RBS analysis, a Ti/N atomic % ratio in the capping film of the control sample was 0.89.
- FIGS. 9A and 9B The SEMs of CoSi 2 films of the control sample are illustrated in FIGS. 9A and 9B .
- FIG. 9A is a top plan view of a gate and
- FIG. 9B is a top plan view of an active region.
- the CoSi 2 films formed by using the Ti-rich capping film according to the present invention exhibited better morphologies than those formed by using the N-rich capping films.
- FIGS. 10A and 10B show the sheet resistances (Rs) of NMOS gates and PMOS gates in the test sample and the control sample prepared in Experimental Example 1 and the results are illustrated in FIGS. 10A and 10B .
- FIG. 10A shows the Rs of NMOS gates and
- FIG. 10B shows the Rs of PMOS gates.
- - ⁇ represents the test sample and - ⁇ —represents the control sample.
- the Ti-rich capping film efficiently removes impurities such as oxide and nitrogen present in an interface between the Co film and a source/drain region or a gate.
- a test sample and a control sample were prepared in the same manner as Experimental Example 1.
- Secondary ion-mass spectrometric (SIMS) results after primary RTA and after a selective wet etching are respectively shown in FIGS. 11A and 11B .
- FIGS. 11A and 11B - ⁇ —and - ⁇ —represent the test sample and - ⁇ —and - ⁇ —represent the control sample.
- the surface of the test sample (using Ti-rich capping film) had a higher Ti content than that of the control sample (using N-rich capping film), by as much as 10 2 .
- a region having the depth of 0 ⁇ m corresponds to the surface of a Si region before a primary RTA and, at the same time, to an interface of a Co film and a cobalt silicide film before a selective wet etching.
- the front surface of a substrate having underlying structures was wet-cleaned by using a SC1 solution and then a HF solution and etched by RF sputtering in an Ar gas. Then, a Co film was formed to a thickness of 100 ⁇ by sputtering, and an N-rich, titanium nitride capping film was formed to a thickness of 100 ⁇ at N 2 flow rate of 85 sccm. Subsequent processes were carried out in the same manner as those of the above test sample. A p+/n junction leakage current was measured in a PMOS.
- the measured leakage current is shown in FIG. 12 .
- - ⁇ represents the test sample
- - ⁇ represents the control sample.
- the test sample exhibited an enhanced leakage current and a uniform leakage current distribution.
- FIG. 1 3 A A Co film was deposited to a thickness of 80 ⁇ on a Si substrate at a high temperature of 400° C. and a transmission electron microphotograph (TEM) of the obtained structure is shown in FIG. 1 3 A. As shown in FIG. 1 3 A, an interface film with a thickness of 20 to 28 ⁇ was observed between the Co film and the Si substrate.
- TEM transmission electron microphotograph
- the selected area diffraction (SAD) patterns of the interface film were measured and the results are shown in FIGS. 13B and 13C . It was demonstrated that the interface film formed by the high temperature deposition was made of Co 2 Si and CoSi.
- a Si substrate having underlying structures was treated with a SC1 solution and then a HF solution and then etched by RF sputtering with Ar gas. Then, a Co film was deposited to a thickness of 100 ⁇ at 400° C., and a Ti-rich capping film was deposited to a thickness of 100 ⁇ . Then, a primary RTA was carried out at 450° C. for 90 seconds, the capping film and unreacted Co film were removed using a mixture solution of sulfuric acid and H 2 O 2 , and then a secondary RTA was carried out at 800° C. for 30 seconds. As a result, a test sample 1 was prepared.
- test sample 2 was prepared in the same manner as in the preparation of the test sample 1 except that the primary RTA was carried out for 30 seconds.
- a control sample 1 was prepared in the same manner as in the preparation of the test sample 1 except that the Co film was deposited at 150° C.
- a control sample 2 was prepared in the same manner as in the preparation of the test sample 2 except that the Co film was deposited at 150° C.
- FIG. 14 Leakage current characteristics of the test sample 1 and the control sample 1 prepared in Experimental Example 6 was measured and the results are shown in FIG. 14 .
- - ⁇ represents the test sample 1
- - ⁇ represents the control sample 1.
- the test sample 1 exhibited substantially enhanced leakage current characteristics, relative to the control sample 1. While a cobalt silicide film was formed to a thickness of 300 to 360 ⁇ in an active region and a STI edge region of the test sample 1, a cobalt silicide film was deeply formed to a thickness of 370 to 700 ⁇ in an active region and a STI edge region of the control sample 1.
- the present invention provides a method of forming a metal silicide film.
- a capping film is formed in the form of a Ti-rich film and a RF sputter etching that generates impurities can be omitted. Therefore, formation of low quality metal silicide film otherwise caused by impurities at an interface between a metal film and a Si-containing conductive region is prevented.
- a reaction velocity for formation of a metal silicide film can be adjusted by use of an interface film formed upon the formation of a metal film at a high temperature. Therefore, a small process window for formation of a metal silicide film resulting from the edge effect can be efficiently solved.
Abstract
A metal-containing film is formed on a silicon-containing conductive region at a temperature where the metal of the metal-containing film and silicon of the semiconductor substrate react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate. The resultant structure is annealed so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a metal silicide film.
Description
- This is a continuation application of U.S. patent application Ser. No. 10/686,768, filed on Oct. 17, 2003, which is a continuation-in-part of U.S. patent application Ser. No.10/457,449, filed Jun. 10, 2003, now abandoned, the entire contents of which are incorporated herein by reference. In addition, a claim of priority is made to Korean Patent Application Nos. 2002-63567 and 2003-66498, filed Oct. 17, 2002 and Sep. 25, 2003, respectively, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention generally relates to the fabrication of semiconductor devices, and more particularly, the present invention relates to a method of forming a metal-containing film and to a method of manufacturing a semiconductor device having a metal silicide film.
- 2. Description of the Related Art
- As the gate resistance and source/drain contact resistance of a metal oxide semiconductor (MOS) increases, the operation speed of a semiconductor device containing the MOS transistor decreases. Accordingly, silicide films have been widely used to decrease these resistances. Metal silicide films, such as cobalt silicide films, in particular monocobalt disilicide (CoSi2) films, are especially useful in view of their low resistance (16 to 18 μΩ cm), good thermal stability, and reduced sheet resistance (Rs) dependency to size. Cobalt silicide films have been used in static random access memory (SRAM) devices and in logic devices that require high operational speeds.
- A cobalt silicide film having poor characteristics can result if impurities such as silicon oxide and silicon nitride are present at a surface of a silicon region on which the cobalt silicide film is formed. For this reason, prior to deposition of the cobalt silicide film, a substrate surface is conventionally wet-cleaned and then etched by radio frequency (RF) sputtering. Unfortunately, however, substrate surface defects can result since RF sputter etching using argon ions (Ar+) is a physical etching process. In addition, resputtering occurs during the RF sputter etching which can result in a poorly formed cobalt silicide film, which can create short-circuits between active regions.
-
FIG. 1 is a plan view of a semiconductor device in which a cobalt silicide film has created a short-circuit between active regions. InFIG. 1 ,reference numeral 3 denotes an active region,reference numeral 4 is a well region boundary,reference numeral 5 denotes a gate,reference numeral 7 denotes a gate spacer, andreference numeral 11 c indicates a cobalt silicide film. As shown, thecolbalt silicide film 11 c is defective in that it connects adjacentactive regions 3 across thewell region boundary 4. -
FIG. 2 is a diagram to illustrate the occurrence of resputtering during RF sputter etching, andFIG. 3 is a diagram illustrating a poorly formed cobalt silicide film resulting from the resputtering.FIGS. 2 and 3 are sectional views taken along line 11-11′ ofFIG. 1 . - As shown in
FIG. 2 , during the RF sputter etching 10, anoxide 2 a of a shallow trench device isolation region (STI) 2 and/or anitride 7 a of aspacer 7 is resputtered onto anactive region 3 or agate 5 of a semiconductor device. Also,silicon 3 a of theactive region 3 is resputtered on thespacer 7. - As shown in
FIG. 3 , theresputtered oxide 2 a andnitride 7 a cause acobalt silicide film 11 a formed on theactive region 3 and acobalt silicide film 11 b formed on thegate 5 to have a nonuniform thickness. Also, the resputteredsilicon 3 a causes acobalt silicide film 11 c to be formed along sidewalls of thespacer 7. This can result in the short-circuiting ofactive regions 3 as shown inFIG. 1 . - Meanwhile, referring to
FIG. 4 , transformation of acobalt film 11 formed on the front surface of a substrate into a cobalt silicide film mainly takes place at the edges of agate 5 a pattern and the edges at which theSTI 2 andactive region 3 are in contact with each other. This phenomenon is called an “edge effect” and is denoted byreference number 13 inFIG. 4 . The edge effect causes the thickness of thecobalt silicide film 11 d to increase, which in turn causes loading of the Rs of the silicide film, making it difficult to adjust the Rs value. Furthermore, the edge effect can cause leakage current at the source/drain region 8. These drawbacks are intensified as the critical dimension (CD) of the gate is reduced to less than 100 nm. As shown inFIG. 4 , the thickness of acobalt silicide film 11 e formed at thegate 5 b having a small CD is almost twice as large as that of thecobalt silicide film 11 d formed at thegate 5 a having a larger CD. This creates a limitation in decreasing the aspect ratio of thegate 5 b pattern, which adversely affects the process margin for subsequent processes. - The present invention provides a method of forming a metal silicide film having favorable characteristics.
- An embodiment of the present invention provides a method of forming a silicide film by forming a metal-containing film on a surface of a semiconductor substrate having an insulating region and a silicon-containing conductive region, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the silicon-containing conductive region, and annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
- Another embodiment of the present invention provides a method of manufacturing a semiconductor device by forming an isolation region defining an active region on a semiconductor substrate, forming on the active region a transistor having source/source regions and a gate, forming a metal-containing film on a surface of the semiconductor substrate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the semiconductor substrate with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate, and annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
- The above and other aspects of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which:
-
FIG. 1 is a plan view illustrating a short-circuit between active regions resulting from a conventional method of forming a cobalt silicide film; -
FIG. 2 is a sectional view illustrating a resputtering that occurs during a conventional method of forming a cobalt silicide; -
FIG. 3 is a sectional view illustrating a poorly formed cobalt silicide film formed by resputtering; -
FIG. 4 is a sectional view to illustrate an edge effect resulting from a conventional method of forming a cobalt silicide film, and a loading of the sheet resistance (Rs) of the silicide film caused by the edge effect; -
FIG. 5 is a flow chart of a method of forming a cobalt silicide film according to one embodiment of the present invention; -
FIGS. 6A through 6D are sectional views of intermediate structures formed in the steps disclosed inFIG. 5 ; -
FIG. 7 is a sectional view to illustrate a diffusion restraint characteristic of an interface film formed in the deposition of a cobalt film at a high temperature; -
FIGS. 8A and 8B are scanning electron microphotographs (SEMs) of cobalt silicide films formed according to an embodiment of the present invention; -
FIGS. 9A and 9B are SEMs of control sample cobalt silicide films for comparison with the films ofFIGS. 8A and 8B ; -
FIGS. 10A and 10B are graphs showing Rs values of gates having cobalt silicide films according to an embodiment of the present invention and according to a conventional method; -
FIG. 11A is a graph showing secondary ion-mass spectrometric (SIMS) results after primary rapid thermal annealing (RTA) according to an embodiment of the present invention and according to a conventional method; -
FIG. 11B is a graph showing SIMS results after a selective wet etching according to an embodiment of the present invention and according to a conventional method; -
FIG. 12 is a graph showing a leakage current of a test sample which has been pretreated by a wet-clean process only according to the present invention, and a leakage current of a control sample which has been pretreated by a wet-clean process and then etched by radio frequency (RF) sputtering according to a conventional method; -
FIG. 13A is a transmission electron microphotograph (TEM) of a sample formed after depositing a cobalt film at a high temperature according to an embodiment of the present invention; -
FIGS. 13B and 13C show selected area diffraction (SAD) patterns of an interface film formed by the high temperature deposition inFIG. 13A ; and -
FIG. 14 is a graph showing leakage current characteristics in the case of depositing a cobalt film at a high temperature according to an embodiment of the present invention and in the case of depositing a cobalt film according to a conventional method. - Embodiments of the present invention disclose the deposition of a titanium (Ti) rich film on a previously formed metal-containing film. Ti, which is abundantly present in a capping film, diffuses toward an interface between the metal-containing film and an underlying silicon containing layer, such as a bulk Si film or a (poly)Si film, which assists in the removal of oxides and nitrides at the interface. The removal of oxides and nitrides results in high quality metal silicide film. Further, the present invention further discloses the use of a wet pretreatment process that sufficiently removes a natural oxide film formed at a surface intended for formation of the metal silicide film. Pretreatment by radio frequency (RF) sputter etching may or may not be required. In this regard, as used herein, the phrase “wet cleaning is used/carried out alone” means that a RF sputter etching is omitted in the pretreatment process. Still further, the present invention discloses the formation of a metal film at a high temperature to compensate for the small process window for formation of a metal silicide film resulting from the edge effect.
- Hereinafter, by way of example, a method of forming a cobalt silicide film on a gate and an active region in a full CMOS (complementary metal oxide semiconductor)-type SRAM (static random access memory) device will be described. However, it is generally understood that the metal-containing film can be selected from TaN, NiTa, Ti, TiN, Ta, W, WN, Hf, Nb, Mo, RuO2, Mo2N, Ni, Ir, Pt, Cr, RuO, Mo2N, WNx, and combination thereof.
-
FIG. 5 is a flow chart of a method of forming a cobalt silicide film according to an embodiment of the present invention.FIGS. 6A through 6D are sectional views of intermediate products resulting from the process steps ofFIG. 5 . - Referring to
FIGS. 5 and 6 A, first, a transistor (Tr) is formed (step S1). In detail, after forming a shallow trench isolation (STI)region 102 using a conventional process, an N-well 101 and a P-well (not shown) are formed on a p-type Si substrate 100 by ion injection. Then, on thesubstrate 100, an oxide film is formed to a thickness of 110 to 130 Å and a poly-Si film is formed to a thickness of 1,500 to 2,500 Å, followed by successive patterning, to form agate 105 and agate oxide film 104. Thegate oxide film 104 may be formed by depositing an oxide such as silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, and lanthanum oxide using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD). Thegate 105 made of poly-Si may be formed by depositing poly-Si doped with impurity using low pressure CVD (LPCVD). Poly-Si may be simultaneously deposited with impurity doping, or may be doped with impurity after deposition. Then, ion injection is carried out to form a lightly doped drain (LDD) region. ALDD 106 n for an NMOS transistor is formed by injecting an n-type ion such as As+, and then aLDD 106 p for a PMOS transistor is formed by injecting a p-type ion such as BF2 +. Then, aspacer 107 is formed at a sidewall of thegate 105. Thespacer 107 may be a silicon nitride film or may be a laminated structure of a middle temperature oxide (MTO) film and a silicon nitride film. After the formation of thespacer 107, an n+ source/drain region 108 n is formed by injecting an n-type ion such as As+, and a p+ source/drain region 108 p is formed by injecting a p-type ion such as BF2+. Finally, an NMOS source/drain (109 n) and a PMOS source/drain (109 p) are formed. -
FIGS. 5 and 6 B illustrates a pretreatment process (steps S2 and S3′). After the pretreatment process, aCo-containing film 111 is formed (step S3) is formed followed by the formation of a Ti-rich capping film 113 (step S4). In the pretreatment process (steps S2 and S3′), impurities, for example, natural oxide films formed on the source/drain regions gate 105, and/or nitride particles remaining from formation of thespacer 107, are removed. For the pretreatment process, a wet cleaning (step S2) may be used alone or in combination with RF sputter etching (step S3′). - Impurities such as oxide and nitride may also be generated due to resputtering caused after RF sputter etching. However, as will be described later, these impurities are typically removed by Ti which is abundantly present in the
capping film 113. - The RF sputter etching can be selectively carried out as required. Various modifications in the wet cleaning may be made according to whether or not the subsequent RF sputter etching is carried out. In a case where the RF sputter etching is carried out, the wet cleaning may be lightly carried out. On the other hand, in a case where the RF sputter etching is omitted, the wet cleaning is carried out so that impurities such as a natural oxide film are completely removed.
- In a case where the RF sputter etching is omitted, the wet cleaning may be carried out in two processes. The first process for the wet cleaning is divided into three steps: using a hydrogen fluoride (HF) solution diluted with deionized (DI) water (first step); using a mixture solution (also known as SC1 solution) of ammonium hydroxide, hydrogen peroxide (H2O2), and water (second step); and, using a HF solution diluted with DI water. A 100:1 diluted HF solution or a 200:1 diluted HF solution may be used as the diluted HF solution. The first step is carried out for about 10 to 300 seconds, preferably about 150 seconds, the second step is carried out at a temperature of 40 to 90° C., preferably 70° C., for about 1 to 60 minutes, preferably about 30 minutes, and the third step is carried out for about 10 to 300 seconds, preferably about 60 seconds. The second process for the wet cleaning is divided into two steps: using a mixture solution of sulfuric acid and H2O2 (first step) and using a HF solution diluted with DI water (second step). Preferably, the ratio of sulfuric acid to H2O2 is 6 to 1. A 100:1 diluted HF solution or a 200:1 diluted HF solution may be used as the diluted HF solution. The first step is carried out at 120° C. for about 500 to 700 seconds, preferably 600 seconds, and the second step is carried out for 150 to 300 seconds, preferably 250 seconds.
- On the other hand, in a case where the RF sputter etching is carried out, the steps in the above-described two wet cleaning processes may be carried out for a shorter time. Alternatively, the wet cleaning may be carried out only using a diluted HF solution.
- Next, the
Co-containing film 111 is conformally formed along an exposed stepped surface of the substrate 100 (step S3). - The
Co-containing film 111 may be a pure Co film made of 100% Co or a Co alloy film. Preferably, the Co alloy film contains 20 or less atomic % of one selected from tantalum (Ta), zirconium (Zr), titanium (Ti), nickel (Ni), hafnium (Hf), tungsten (W), platinum (Pt), palladium (Pd), vanadium (V), niobium (Nb), and mixtures thereof. - The
Co-containing film 111 is formed by sputtering. The thickness of theCo-containing film 111 is determined according to the critical dimension (CD) or height of thegate 105. For example, if the CD of the gate is 100 nm, it is preferable to form the Co-containing film to a thickness of less than 150 Å. - The
Co-containing film 111 may be deposited at a temperature higher than room temperature. However, it is preferable to deposit theCo-containing film 111 at a high temperature of 300 to 500° C. When theCo-containing film 111 is deposited at a high temperature, as shown in an enlarged circle ofFIG. 6B , Co of theCo-containing film 11 reacts with Si of the source/drain regions gate 105, to thereby form aninterface film 115 a made of dicobalt monosilicide (Co2Si) or monocobalt monosilicide (CoSi). Theinterface film 115 a serves to restrain diffusion of Co during a subsequent annealing process. The detailed description thereof will be described later. - Next, a Ti-
rich capping film 113 is formed on the Co-containing film 111 (step S4). As used herein, the term, “Ti-rich capping film” indicates a film with a Ti/other elements atomic % ratio of more than 1. The Ti-rich capping film may be one selected from the group consisting of a titanium nitride film with a Ti/nitrogen (N) atomic % ratio of more than 1, a titanium tungsten film with a Ti/W atomic % ratio of more than 1, a laminated structure of a pure Ti film and a titanium nitride film with a Ti/N atomic % ratio of more than 1, a laminated structure of a pure Ti film and a titanium nitride film with a Ti/N atomic % ratio of less than 1, a laminated structure of a pure Ti film and a titanium tungsten film with a Ti/W atomic % ratio of more than 1, and a laminated structure of a pure Ti film and a titanium tungsten film with a Ti/W atomic % ratio of less than 1. The Ti-rich capping film 113 may also be a pure Ti film made of 100% Ti. - The
capping film 113 is also formed by sputtering. For example, in the case of a titanium nitride film with a Ti/N atomic % ratio of more than 1, thecapping film 113 with a desired composition ratio can be formed by depositing a Ti target while adjusting the flow rate of a nitrogen gas supplied into a sputtering apparatus. The function of thecapping film 113 will be described later. - Preferably, the RF sputter etching (step S3′), the formation of the Co-containing film (step S3), and the formation of the Ti-rich capping film (step S4) are formed in situ.
- Referring to
FIGS. 5 and 6 C, the resultant structure having theCo-containing film 111 and the Ti-rich capping film 113 are annealed at a low temperature (step S5). The low temperature annealing may be a rapid thermal annealing (RTA) at a temperature range of 350 to 650° C. - When the low temperature annealing begins, Ti in the
capping film 113 efficiently removes residual impurities on upper surfaces of the source/drain regions gate 105, which are in contact with theCo-containing film 111. - The Ti removes impurities such as oxide, nitride, and silicon, which are generated by the RF sputter etching for pretreatment carried out before the formation of the
Co-containing film 111. - Ti also removes impurities generated on an exposed surface of the
substrate 100 during a delay time between the wet cleaning and the formation of theCo-containing film 111 when the RF sputter etching is omitted. Such a delay time is caused because the wet cleaning and the formation of the Co-containing film are not carried out in situ. - Therefore, the Ti-
rich capping film 113 serves to prevent formation of poor quality cobalt silicide film otherwise caused by impurities generated by the RF sputter etching. In addition, in the case where the wet cleaning pretreatment is used alone to prevent the generation of impurities, even though a surface of thesubstrate 100 is exposed to air for a long period of time after the wet cleaning, the Ti can remove impurities generated on the surface of thesubstrate 100 as a result of the exposure. Therefore, a process window for a delay time between the wet cleaning and the formation of theCo-containing film 111 is increased. - When Ti efficiently removes impurities, Co of the
Co-containing film 111 diffuses toward the source/drain regions gate 105 and then reacts with (poly)Si to thereby form a highquality CoSi film 115 b. - Meanwhile, the diffusion
restraint interface film 115 a made of Co2Si or CoSi formed upon the formation of theCo-containing film 111 at 300 to 500° C. serves to decrease the diffusion speed of the Co, thereby retarding the formation of a cobalt silicide film. That is, referring toFIG. 7 , Co2Si or CoSi that constitutes the diffusionrestraint interface film 115 a is in a polycrystalline phase. For this reason, Co of theCo-containing film 111 placed on theinterface film 115 a can diffuse toward thesubstrate 100 only throughdiffusion paths 200, i.e., polycrystalline grain boundaries. The number ofdiffusion paths 200 in the presence of theinterface film 115 a is less than the number ofdiffusion paths 250 in the absence of theinterface film 115 a. For this reason, in the presence of theinterface film 115 a, less of the Co reacts with Si. Therefore, Rs loading and an increase in leakage current caused by the edge effect can be inhibited. - As a result of the low temperature annealing, Co2Si of the
interface film 115 a is transformed into CoSi. - Referring to
FIGS. 5 and 6 D, a wet etching is carried out to selectively remove thecapping film 113 and any remaining unreactedCo-containing film 111 by the low temperature annealing (step S6). The wet etching is carried out using a mixture solution of sulfuric acid and ammonium hydroxide or a mixture solution of phosphoric acid, acetic acid, nitric acid, and H2O2. - Next, an annealing at a high temperature is carried out (step S7). As a result of the high temperature annealing, the
CoSi film 115 b is transformed into a CoSi2 film 115 c having low resistance. The CoSi2 film 115 c is more stable and has a lower resistance, when compared to theCoSi film 115 b. The high temperature annealing may be a rapid thermal anneal (RTA) at a temperature range of 700 to 900° C. - Embodiments described with reference to
FIGS. 5 through 7 are directed to a self-align silicide process. If required, a silicide blocking film may be formed to protect regions which do not require cobalt silicidation. - In a dynamic random access memory (DRAM), a silicide film is formed only on a gate to decrease a gate resistance and to maintain an optimal refresh time. Therefore, a silicide film is not formed on an active region. In the case of a merged DRAM with logic (MDL) device which have recently gained notoriety in terms of high performance and small chip size, in a peripheral circuit and a logic, a silicide film is formed both on an active region and a gate or on a part of the active region and a part of the gate to reduce a contact resistance or a sheet resistance of the gate and source/drain. On the other hand, in a memory cell array, a silicide film is formed only on a gate to maintain an optimal refresh time. In the case of a nonvolatile memory device, a silicide film is formed only on a gate to prevent a resistance increase resulting from a decrease in gate length accompanying an increase in pattern density. In addition, when needed, instead of forming a silicide film on a gate, a silicide film may be formed only on a source/drain region.
- Therefore, the silicide blocking film is used to expose only regions intended for formation of a silicide film. The formation of the silicide blocking film may be carried out prior to the wet cleaning.
- Hitherto, the formation of a cobalt silicide film on a source/drain and a gate has been described. However, it is understood that a cobalt silicide film can be formed at any conductive regions made of (poly) Si that require a low resistance.
- Hereinafter, the present invention will be described in more detail with reference to non-limiting experimental examples.
- A six-transistor (6Tr)-SRAM cell was manufactured on a semiconductor wafer substrate according to 110 nm design rules using the following method of forming a cobalt silicide film according to the present invention to prepare a test sample.
- The front surface of the substrate having a poly-Si gate pattern with a sidewall spacer and a source/drain region (hereinafter, referred to as “underlying structure(s)”) was wet-cleaned using a SC1 solution and then a HF solution. The substrate was etched by RF sputtering using argon (Ar) gas to remove an oxide film to a thickness of 50 Å, a Co film was formed to a thickness of 100 Å by sputtering, and a Ti-rich, titanium nitride capping film was formed to a thickness of 100 Å with N2 gas. The RF sputter etching, the formation of the Co film, and the formation of the titanium nitride capping film were formed in situ. According to a Rutherfold backscattering spectroscopy (RBS) analysis, a Ti/N atomic % ratio in the capping film was 3.33.
- A primary RTA was carried out at 450° C. for 90 seconds, the capping film and unreacted Co film were removed by a mixture solution of sulfuric acid and H2O2, and then a secondary RTA was carried out at 800° C. for 30 seconds.
- The scanning electron microphotographs (SEMs) of CoSi2 films obtained are illustrated in
FIGS. 8A and 8B .FIG. 8A is a top plan view of a gate andFIG. 8B is a top plan view of an active region exposed by a contact pattern. - Meanwhile, a control sample was prepared under the above-described process conditions except that the capping film was formed at an N2 flow rate of 85 sccm. According to a RBS analysis, a Ti/N atomic % ratio in the capping film of the control sample was 0.89.
- The SEMs of CoSi2 films of the control sample are illustrated in
FIGS. 9A and 9B .FIG. 9A is a top plan view of a gate andFIG. 9B is a top plan view of an active region. - In comparison between the SEMs of the test sample (
FIGS. 8A and 8B ) and the SEMs of the control sample (FIGS. 9A and 9B ), the CoSi2 films formed by using the Ti-rich capping film according to the present invention exhibited better morphologies than those formed by using the N-rich capping films. - The sheet resistances (Rs) of NMOS gates and PMOS gates in the test sample and the control sample prepared in Experimental Example 1 were measured and the results are illustrated in
FIGS. 10A and 10B .FIG. 10A shows the Rs of NMOS gates andFIG. 10B shows the Rs of PMOS gates. InFIGS. 10A and 10B , -◯—represents the test sample and -□—represents the control sample. - As shown in
FIGS. 10A and 10B , while the test sample exhibited a very low, uniform Rs distribution, the control sample exhibited a very high, nonuniform Rs distribution. This result demonstrates that the Ti-rich capping film efficiently removes impurities such as oxide and nitrogen present in an interface between the Co film and a source/drain region or a gate. - A test sample and a control sample were prepared in the same manner as Experimental Example 1. Secondary ion-mass spectrometric (SIMS) results after primary RTA and after a selective wet etching are respectively shown in
FIGS. 11A and 11B . - In
FIGS. 11A and 11B , -♦—and -▾—represent the test sample and -∘—and -□—represent the control sample. As shown inFIG. 11B , the surface of the test sample (using Ti-rich capping film) had a higher Ti content than that of the control sample (using N-rich capping film), by as much as 102. InFIG. 11B , a region having the depth of 0 μm corresponds to the surface of a Si region before a primary RTA and, at the same time, to an interface of a Co film and a cobalt silicide film before a selective wet etching. Judging from the fact that a Si region is transformed into a cobalt silicide film while Co diffuses toward the Si region and the result ofFIG. 11B , it can be seen that a large amount of Ti diffuses toward an interface between a Co film and a source/drain region or a gate region and then efficiently removes impurities at the interface. - A test sample was prepared in the same manner as in the preparation of the test sample in Experimental Example 1 except that a wet cleaning was carried out alone in the pretreatment process, i.e., the pretreatment did not include RF sputter etching. The wet cleaning was carried out by using a 200:1 diluted HF solution for 150 seconds, using a SC1 solution for 30 minutes, and then using a 200:1 diluted HF solution for 90 seconds. After a cobalt silicide film was formed, a p+/n junction leakage current was measured in a PMOS.
- As a control sample, the front surface of a substrate having underlying structures was wet-cleaned by using a SC1 solution and then a HF solution and etched by RF sputtering in an Ar gas. Then, a Co film was formed to a thickness of 100 Å by sputtering, and an N-rich, titanium nitride capping film was formed to a thickness of 100 Å at N2 flow rate of 85 sccm. Subsequent processes were carried out in the same manner as those of the above test sample. A p+/n junction leakage current was measured in a PMOS.
- The measured leakage current is shown in
FIG. 12 . InFIG. 12 , -□—represents the test sample and -∘—represents the control sample. The test sample exhibited an enhanced leakage current and a uniform leakage current distribution. - A Co film was deposited to a thickness of 80 Å on a Si substrate at a high temperature of 400° C. and a transmission electron microphotograph (TEM) of the obtained structure is shown in
FIG. 1 3A. As shown inFIG. 1 3A, an interface film with a thickness of 20 to 28 Å was observed between the Co film and the Si substrate. - In order to determine the type of the formed interface film, the selected area diffraction (SAD) patterns of the interface film were measured and the results are shown in
FIGS. 13B and 13C . It was demonstrated that the interface film formed by the high temperature deposition was made of Co2Si and CoSi. - A Si substrate having underlying structures was treated with a SC1 solution and then a HF solution and then etched by RF sputtering with Ar gas. Then, a Co film was deposited to a thickness of 100 Å at 400° C., and a Ti-rich capping film was deposited to a thickness of 100 Å. Then, a primary RTA was carried out at 450° C. for 90 seconds, the capping film and unreacted Co film were removed using a mixture solution of sulfuric acid and H2O2, and then a secondary RTA was carried out at 800° C. for 30 seconds. As a result, a
test sample 1 was prepared. - A
test sample 2 was prepared in the same manner as in the preparation of thetest sample 1 except that the primary RTA was carried out for 30 seconds. - A
control sample 1 was prepared in the same manner as in the preparation of thetest sample 1 except that the Co film was deposited at 150° C. - A
control sample 2 was prepared in the same manner as in the preparation of thetest sample 2 except that the Co film was deposited at 150° C. - The Rs values for conductive regions of the
test samples control samples TABLE 1 Sheet resistance (Rs) (Ω/sq.) N-active region N-gate N-gate P-active region P-gate P-gate Sample (CD = 0.26 μm) (CD = 0.13 μm) (CD = 0.65 μm) (CD = 0.26 μm) (CD = 0.13 μm) (CD = 0.65 μm) Control sample 17.8 6.2 8.0 7.8 6.2 8.0 Control sample 28.2 7.0 8.4 7.8 7.0 8.4 Test sample 18.2 7.8 8.2 8.0 7.8 8.2 Test sample 212.2 9.0 8.7 12.0 9.2 8.6
CD: critical dimension
- In the
control sample 1, the Rs value of the 0.13 μm gate was smaller than that of the 0.65 μm gate. From this result, it can be seen that as the CD of a gate decreases, the thickness of a cobalt silicide film increases. Therefore, it can be anticipated that this phenomenon will be intensified as the CD of a gate reduces to less than 100 nm. - In a comparison between the
control samples - In a comparison between the
control sample 1 and thetest sample 1, it can be seen that when a Co film is deposited at a high temperature (400° C.) according to the present invention, a variation in the Rs values according to the CD significantly decreases, thereby minimizing the loading of the Rs of a silicide film. This result demonstrates that a cobalt silicide interface film generated by a high temperature deposition serves as a diffusion restraint film. - In a comparison between the
test samples - Leakage current characteristics of the
test sample 1 and thecontrol sample 1 prepared in Experimental Example 6 was measured and the results are shown inFIG. 14 . InFIG. 14 , -□—represents thetest sample 1 and -∘—represents thecontrol sample 1. Thetest sample 1 exhibited substantially enhanced leakage current characteristics, relative to thecontrol sample 1. While a cobalt silicide film was formed to a thickness of 300 to 360 Å in an active region and a STI edge region of thetest sample 1, a cobalt silicide film was deeply formed to a thickness of 370 to 700 Å in an active region and a STI edge region of thecontrol sample 1. - These facts demonstrate that a cobalt silicide interface film formed upon a high temperature Co deposition efficiently restrains diffusion of Co into a Si-containing conductive region.
- As apparent from the above description, the present invention provides a method of forming a metal silicide film. According to this method, a capping film is formed in the form of a Ti-rich film and a RF sputter etching that generates impurities can be omitted. Therefore, formation of low quality metal silicide film otherwise caused by impurities at an interface between a metal film and a Si-containing conductive region is prevented. Furthermore, a reaction velocity for formation of a metal silicide film can be adjusted by use of an interface film formed upon the formation of a metal film at a high temperature. Therefore, a small process window for formation of a metal silicide film resulting from the edge effect can be efficiently solved.
- While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Claims (19)
1. A method of forming a metal silicide film, comprising:
forming a metal-containing film on a surface of a semiconductor substrate having an insulating region and a silicon-containing conductive region, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the silicon-containing conductive region; and
annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
2. The method of claim 1 , further comprising forming a titanium-rich capping film on the metal-containing film prior to the annealing.
3. The method of claim 1 , wherein metal-containing film is at least one selected from the group consisting of TaN, NiTa, Ti, TiN, Ta, W, WN, Hf, Nb, Mo, RuO2, Mo2N, Ni, Ir, Pt, Cr, RuO, Mo2N, WNx, NiPt, or a combination thereof.
4. The method of claim 2 , wherein the annealing, comprises:
a first annealing at a temperature range of 350 to 650° C.;
removing the titanium-rich capping film; and
a second annealing at a temperature range of 700-900° C.
5. The method of claim 1 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate; and
etching the semiconductor substrate by radio frequency (RF) sputtering.
6. The method of claim 1 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a hydrogen fluoride (HF) solution diluted with deionized (DI) water;
wet-cleaning the surface of the semiconductor substrate using a mixture solution of ammonium hydroxide, hydrogen peroxide (H2O2), and water; and
wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
7. The method of claim 1 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a mixture solution of sulfuric acid and H2O2; and
wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
8. The method of claim 1 , wherein the metal-containing film is formed at a temperature range of 300-500° C.
9. A method of manufacturing a semiconductor device, said method comprising:
forming an isolation region defining an active region on a semiconductor substrate;
forming on the active region a transistor having source/source regions and a gate;
forming a metal-containing film on a surface of the semiconductor substrate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the semiconductor substrate react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate; and
annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
10. The method of claim 9 , further comprising forming a titanium-rich capping film on the metal-containing film.
11. The method of claim 9 , wherein forming of the metal-containing film comprises forming the metal-containing film exclusively on a surface of the gate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the gate to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the gate.
12. The method of claim 9 , wherein forming of the metal-containing film comprises forming the metal-containing film exclusively on a surface of the source/drain region, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the source/drain regions to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the source/drain region.
13. The method of claim 9 , wherein forming of the metal-containing film comprises forming the metal-containing film on a surface of the source/drain region and the gate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the source/drain regions and the gate to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the source/drain region and the gate.
14. The method of claim 9 , wherein metal-containing film is at least one selected from the group consisting of TaN, NiTa, Ti, TiN, Ta, W, WN, Hf, Nb, Mo, RuO2, Mo2N, Ir, Pt, Cr, RuO, Mo2N, WNx, NiPt, or a combination thereof.
15. The method of claim 10 , wherein the annealing, comprises:
a first annealing at a temperature range of 350 to 650° C.;
removing the titanium-rich capping film; and
a second annealing at a temperature range of 700-900° C.
17. The method of claim 9 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate; and
etching the semiconductor substrate by radio frequency (RF) sputtering.
18. The method of claim 9 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a hydrogen fluoride (HF) solution diluted with deionized (DI) water;
wet-cleaning the surface of the semiconductor substrate using a mixture solution of ammonium hydroxide, hydrogen peroxide (H2O2), and water; and
wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
19. The method of claim 9 , wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a mixture solution of sulfuric acid and H2O2; and
wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
20. The method of claim 9 , wherein the metal-containing film is formed at a temperature range of 300-500° C.
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US20040132268A1 (en) | 2004-07-08 |
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