US20050213393A1 - States encoding in multi-bit flash cells for optimizing error rate - Google Patents

States encoding in multi-bit flash cells for optimizing error rate Download PDF

Info

Publication number
US20050213393A1
US20050213393A1 US11/061,634 US6163405A US2005213393A1 US 20050213393 A1 US20050213393 A1 US 20050213393A1 US 6163405 A US6163405 A US 6163405A US 2005213393 A1 US2005213393 A1 US 2005213393A1
Authority
US
United States
Prior art keywords
bit
bits
ordering
bit ordering
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/061,634
Inventor
Menahem Lasser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Western Digital Israel Ltd
Original Assignee
M Systems Flash Disk Pionners Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/035,807 external-priority patent/US7310347B2/en
Application filed by M Systems Flash Disk Pionners Ltd filed Critical M Systems Flash Disk Pionners Ltd
Priority to US11/061,634 priority Critical patent/US20050213393A1/en
Assigned to M-SYSTEMS FLASH DISK PIONEERS, LTD. reassignment M-SYSTEMS FLASH DISK PIONEERS, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LASSER, MENAHEM
Priority to PCT/IL2005/001001 priority patent/WO2006033099A2/en
Priority to KR1020077006271A priority patent/KR20070054659A/en
Publication of US20050213393A1 publication Critical patent/US20050213393A1/en
Priority to US11/923,725 priority patent/US8055972B2/en
Assigned to SANDISK IL LTD. reassignment SANDISK IL LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MSYSTEMS LTD.
Assigned to MSYSTEMS LTD. reassignment MSYSTEMS LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: M-SYSTEMS FLASH DISK PIONEERS LTD.
Priority to US13/243,836 priority patent/US8245099B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564Miscellaneous aspects
    • G11C2211/5648Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Definitions

  • the present invention relates to flash memories and, more particularly, to a method of storing data in multi-bit flash cells.
  • Flash memory devices have been known for many years. Typically, each cell within a flash memory stores one bit of information. Traditionally, the way to store a bit has been by supporting two states of the cell—one state represents a logical “0” and the other state represents a logical “1”. In a flash memory cell the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within this floating gate. Typically, one state is with zero charge in the floating gate and is the initial unwritten state of the cell after being erased (commonly defined to represent the “1” state) and another state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state).
  • the threshold voltage of the cell's transistor i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct
  • the threshold voltage of the cell's transistor i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct
  • FIG. 1A shows graphically how this works. Specifically, FIG. 1A shows the distribution of the threshold voltages of a large population of cells. Because the cells in a flash memory are not exactly identical in their characteristics and behavior (due, for example, to small variations in impurities concentrations or to defects in the silicon structure), applying the same programming operation to all the cells does not cause all of the cells to have exactly the same threshold voltage. (Note that, for historical reasons, writing data to a flash memory is commonly referred to as “programming” the flash memory.) Instead, the threshold voltage is distributed similar to the way shown in FIG. 1A . Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the left peak of FIG.
  • cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the right peak of FIG. 1A , with some smaller numbers of cells having lower or higher threshold voltages.
  • MLC Multi Level Cells
  • FIG. 1B shows the threshold voltage distribution for a typical 2-bit MBC cell. As expected, FIG. 1B has four peaks, each corresponding to one state. As for the SBC case, each state is actually a range and not a single number. When reading the cell's contents, all that must be guaranteed is that the range that the cell's threshold voltage is in is correctly identified. For a prior art example of an MBC flash memory see U.S. Pat. No. 5,434,825 to Harari.
  • FIG. 1C shows the threshold voltage distribution for a typical 3-bit MBC cell. As expected, FIG. 1C has eight peaks, each corresponding to one state.
  • FIG. 1D shows the threshold voltage distribution for a 4-bit MBC cell, for which sixteen states, represented by sixteen threshold voltage ranges, are required.
  • the left-most state in FIG. 1B When encoding two bits in an MBC cell via the four states, it is common to have the left-most state in FIG. 1B (typically having a negative threshold voltage) represent the case of both bits having a value of “1”.
  • the two bits of a cell are called the “lower bit” and the “upper bit”.
  • An explicit value of the bits is written in the form [“upper bit” “lower bit”], with the lower bit value on the right. So the case of the lower bit being “0” and the upper bit being “1” is written as “10”.
  • the left-most state represents the case of “11”.
  • the other three states are typically assigned by the following order from left to right: “10”, “00”, “01”.
  • U.S. Pat. No. 6,643,188 to Tanaka also shows a similar implementation of an MBC NAND flash memory, but see FIG. 7 there for a different assignment of the states to bit encodings: “11”, “10”, “01”, “00”.
  • the Chen encoding is the one illustrated in FIG. 1B .
  • the left-most unwritten state represents “all ones” (“1 . . . 1”)
  • the string “1 . . . 10” represents the case of only the lowest bit of the cell being written to “0”
  • the string “01 . . . 1” represents the case of only the most upper bit of the cell being written to “0”.
  • the range that the cell's threshold voltage is in must be identified correctly; only in this case this cannot always be achieved by comparing to only one reference voltage. Instead, several comparisons may be necessary. For example, in the case illustrated in FIG. 1B , to read the lower bit, the cell's threshold voltage first is compared to a reference comparison voltage V 1 and then, depending on the outcome of the comparison, to either a zero reference comparison voltage or a reference comparison voltage V 2 . Alternatively, the lower bit is read by unconditionally comparing the threshold voltage to both a zero reference voltage and a reference comparison voltage V 2 , again requiring two comparisons. For more than two bits per cell, even more comparisons might be required.
  • the bits of a single MBC cell may all belong to the same flash page, or they may be assigned to different pages so that, for example in a 4-bit cell, the lowest bit is in page 0, the next bit is in page 1, the next bit in page 2, and the highest bit is in page 3. (A page is the smallest portion of data that can be separately written in a flash memory). Both methods are in use. While the methods of the present invention are explained here in the context of the “each bit in its own page” approach, these methods also can be applied to the case of all bits residing in the same page.
  • N Factorial The number of permutations of N elements is equal to N! (“N Factorial”).
  • the left-most state always corresponds to the “all ones” bit pattern.
  • programming can only increase the threshold voltage of a cell, not reduce it. Reduction of the threshold voltage can only be done when erasing, but erasing can be applied only to large groups of cells (“blocks” in common terminology). Therefore, any ordering of the bit patterns that requires the threshold voltage to decrease when writing a bit to “0” cannot be used.
  • a 2-bit MBC cell Suppose we selected the following order from left to right—“11”, “00”, “10”, “01”.
  • FIG. 2 shows a graphical representation of the restrictions applicable to the ordering of bit patterns in a 2-bit MBC cell.
  • Each bit pattern is shown by its binary representation within a circle, and by its decimal representation outside the circle. Both numerical representations are equivalent, but it is more convenient to use the binary representation for understanding the ordering restrictions, and to use the decimal representation for talking about a certain pattern.
  • An arrow connecting two circles in FIG. 2 means that the state from which the arrow originates must precede the state to which the arrow points.
  • FIG. 3 shows the corresponding graphical representation for the case of 3-bit MBC cells
  • FIG. 4 shows the corresponding graphical representation for the case of 4-bit MBC cells. Both cases are much more complex than the 2-bit case and allow many more valid orderings.
  • FIG. 3 Now let us move to the less trivial 3-bit cell ( FIG. 3 ). We notice that after writing the lowest bit of a 3-bit cell, the other 2 bits (still unwritten) represent the same problem of ordering as a 2-bit cell. This can be seen in FIG. 3 by noticing that the “branch” containing ⁇ 6,4,0,2 ⁇ has exactly the same structure as the whole of FIG. 2 . But we already know this problem has exactly three different solutions. So let us start the construction of an ordering by selecting positions for the four members of the ⁇ 6,4,0,2 ⁇ branch out of the seven available positions (recall that the all-ones pattern always has its left-most reserved position). There are C(7,4) ways of doing this.
  • Appendices list 3-bit and 4-bit orderings along with analyses of these orderings, as described below.
  • Appendix A lists all 315 3-bit orderings.
  • Appendices B, C, D and E are partial lists of the 4-bit orderings.
  • FIGS. 86A to 86 C of Takeuchi apply the method to 3-bit cells.
  • FIGS. 88A to 88 D of Takeuchi apply the method to 4-bit cells.
  • FIGS. 90A to 90 E of Takeuchi show how to apply the method to the general M-bit case.
  • the method proposed by Takeuchi results in an ordering that is not optimal.
  • a method of storing N bits of data including the steps of: (a) providing ⁇ N/M ⁇ cells, wherein M is at least 3; and (b) programming each cell with up to M of the bits according to a valid physical bit ordering, and according to a logical bit ordering that is different from the physical bit ordering and that distributes error probabilities of the up to M bits more evenly than the physical bit ordering.
  • a method of storing N bits of data including the steps of: (a) providing ⁇ N/M ⁇ cells, wherein M is at least 3; and (b) programming each cell with up to M of the bits according to a valid physical bit ordering, and according to an evenly distributed logical bit ordering that is different from the physical bit ordering.
  • a method of storing N bits of data including the steps of: (a) providing ⁇ N/M ⁇ cells, wherein M is at least 3; and (b) programming each cell with up to M of the bits according to a valid, nonserial bit ordering that distributes error probabilities of all the up to M bits substantially evenly.
  • a method of of storing N bits of data including the steps of: (a) providing ⁇ N/M ⁇ cells, wherein M is at least 3; and (b) programming each cell with up to M of the bits according to a valid, nonserial, error-rate-optimal bit ordering.
  • Each cell is programmed with up to M of the data bits according to a valid physical bit ordering, and according to a different logical bit ordering that provides a more even distribution of the error probabilities of all the up to M bits than would be provided by the physical bit ordering alone. This more even error distribution is relative to the probability distribution of the N data bits and relative to the probability distribution of the state errors of the cells.
  • bit orderings are “error-rate optimal”, in the sense defined below, then if all data bits are equally probable and all state errors are equally probable, it is shown below that a truly even distribution of the error probabilities can not be achieved; whereas other probability distributions of the data bits and of the state errors may allow a truly even distribution of the error probabilities of all the up to M bits. Indeed, at the end of the description of the preferred embodiments, an artificial example with error-rate optimal bit orderings and a truly even error distribution is presented.
  • the programming includes, for each cell, translating the up to M bits, as listed in the logical bit ordering, into a corresponding entry in the physical bit ordering.
  • the method also includes the step of reading the N bits from the cells, as the purpose of storing the N bits usually is to provide the possibility of reading the N bits.
  • this reading includes, for each cell, translating an entry, in the physical bit ordering, that corresponds to the state of the cell as programmed, into a corresponding entry in the logical bit ordering.
  • the logical bit ordering substantially equalizes probability-weighted numbers of transitions of all the up to M bits, relative to the probability distribution of the data bits and relative to the probability distribution of the state errors.
  • the total number of transitions of the physical bit ordering and the total number of transitions of the logical bit ordering both are equal to 2 M ⁇ 1, which is one less than the number of states.
  • the physical bit ordering is nonserial.
  • the controller includes a mechanism for translating between the physical bit ordering and the logical bit ordering.
  • this mechanism effects the translating by executing software.
  • the controller includes dedicated hardware (as opposed to a general purpose processor that executes software) for effecting the translating.
  • the memory includes such dedicated hardware.
  • the memory is a flash memory.
  • the physical bit ordering is nonserial.
  • a system of the present invention for storing data, includes a memory device that includes a memory with K cells, and a host of the memory device that provides N bits of data to be stored in the memory device.
  • the logical bit ordering provides a more even distribution of error probabilities of all the up to M bits than would be provided by the physical bit ordering alone.
  • the translation mechanism effects the translation by executing software.
  • a translation mechanism may be included in the host, or alternatively may be included in a controller, of the memory, that is included in the memory device.
  • the translation mechanism includes dedicated hardware. Such a translation mechanism may be included in the memory, or may be included in a controller, of the memory, that is included in the memory device.
  • the memory is a flash memory.
  • the physical bit ordering is nonserial.
  • a special case of the first method of the present invention and of the corresponding memory device and system ignores both the probability distribution of the N data bits and the probability distribution of the cells' state errors, and just requires that the logical bit ordering be evenly distributed.
  • Each cell is programmed with up to M of the data bits according to a valid, nonserial bit ordering that distributes the bit error probabilities of all M bits substantially evenly. Note that whether a valid physical bit ordering can achieve such an even distribution of bit error probabilities depends on the probability distribution of the N data bits and relative to the probability distribution of the state errors of the cells.
  • the artificial example at the end of the description of the preferred embodiments is one such case.
  • the bit ordering is a physical bit ordering.
  • Each cell is programmed with up to M of the data bits according to a valid, nonserial, error-rate-optimal bit ordering.
  • FIGS. 1A-1D show threshold voltage distributions in a one-bit flash cell, a two-bit flash cell, a three-bit flash cell and a four-bit flash cell;
  • FIG. 2 is a precedence tree for programming a two-bit cell
  • FIG. 3 is a precedence tree for programming a three-bit cell
  • FIG. 4 is a precedence tree for programming a four-bit cell
  • FIG. 5 is a flowchart of writing to a memory cell via a logical bit ordering and a physical bit ordering
  • FIG. 6 is a flowchart of reading from a memory cell via a physical bit ordering and a logical bit ordering
  • FIGS. 7-11 are high level block diagrams of systems of the present invention.
  • the present invention is of a method of programming multi-bit flash cells.
  • At least one reference voltage value used during the reading process is determined based on the result of a previous comparison done during the same reading operation. For example, reading the lower bit of the 2-bit MBC cell whose encoding is as shown in FIG. 1B by first comparing to V 1 , and then depending on the outcome of that comparison, comparing to either 0 or V 2 , is a dynamic reading method that uses two comparisons.
  • the number of comparisons required for reading a single bit using static reading depends on the way the value of the bit changes when moving from state to state along the threshold voltage axis.
  • 2-bit MBC case with the ordering of ⁇ 3,2,0,1 ⁇ .
  • that ordering is ⁇ 11,10,00,01 ⁇ .
  • decimal notation is used for bit orderings.
  • the numbers of transitions (and therefore the number of comparisons) are 2 for the lower bit, 3 for the middle bit and 5 for the upper bit.
  • the number of comparisons required for reading a single bit using dynamic reading also depends on the number of transitions the bit incurs when traversing all states along the threshold voltage axis from left to right, but in a different way than for static reading.
  • Appendix A lists all the valid orderings for the 3-bit case.
  • Each of the 315 orderings has one line in the table, showing the sequences for each of the three bits, the number of static reading comparisons for each bit (the three columns under the heading “static comp”), and the number of dynamic reading comparisons for each bit (the three columns under the heading “dynamic comp”). Also shown are the total, minimum and maximum numbers for each of the two reading methods, statistics that are referenced in the discussion below.
  • Criterion A Minimize the number of comparisons for sequentially reading all the bits in a cell (that is, reading the bits one by one and not in one operation) using static reading.
  • the 36 orderings listed in Appendix B are optimal according to this criterion. Each such ordering has a total of 15 comparisons.
  • the encoding illustrated in FIG. 1D corresponds to the first of these orderings, ⁇ 15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1 ⁇ .
  • Criterion B Minimize the maximum number of comparisons for reading a single bit of a cell using static reading.
  • Appendix A lists ten optimal orderings under this criterion, with a maximum number of comparisons of three: ⁇ 7,6,2,4,5,1,3,0 ⁇ , ⁇ 7,6,2,4,5,3,1,0 ⁇ , ⁇ 7,6,4,2,3,5,1,0 ⁇ , ⁇ 7,6,4,0,2,3,5,1 ⁇ , ⁇ 7,6,4,0,5,1,3,2 ⁇ , ⁇ 7,6,4,5,1,3,2,0 ⁇ , ⁇ 7,6,5,1,3,2,4,0 ⁇ , ⁇ 7,5,6,2,3,1,4,0 ⁇ , ⁇ 7,5,6,2,3,1,4,0 ⁇ , ⁇ 7,3,6,4,5,1,2,0 ⁇ and ⁇ 7,3,6,4,5,1,0,2 ⁇ .
  • Criterion C Minimize the minimum number of comparisons for reading a single bit of a cell, using static reading.
  • Such an ordering requires one comparison for the last bit to be written into the cell, three comparisons for the next-to-last bit, seven comparisons for the third bit from the end, and 2 M ⁇ 1 comparisons for the M-th bit from the end. While it is true the Takeuchi ordering provides one bit with only one comparison, the first bit to be written into the cell has the highest number of comparisons possible (seven for the 3-bit case, 15 for the 4-bit case). This creates a large difference in the reading time of different bits of the cell and is not desirable, and therefore such ordering is not considered optimal in spite of having one bit with the minimal number of comparisons.
  • serial assignment for referring to an assignment that results in an ordering such as Takeuchi, having the form ⁇ 2 M ⁇ 1,2 M ⁇ 2, . . . , 4,3,2,1,0 ⁇ .
  • the corresponding bit ordering is called herein a “serial” bit ordering. All other orderings are called “nonserial” herein.
  • Criterion D Achieve equal number of comparisons for reading a single bit of a cell (regardless which bit is read), using static reading.
  • Appendix D lists all valid orderings with a total of 17 comparisons in which the difference between the lowest and highest bit is not more than one comparison, and one can see that there are really orderings in which the difference between lowest and highest is only one comparison, resulting in more constant reading response time than can be achieved with either a 15-comparison ordering or a 16-comparison ordering.
  • Criterion E Minimize the number of comparisons for sequentially reading all bits in a cell, using dynamic reading.
  • Appendix A shows that there is one optimal ordering ( ⁇ 7,6,4,5,1,3,2,0 ⁇ ), with a total of five comparisons. There also are many orderings with a total of six comparisons.
  • Criterion F Minimize the maximum number of comparisons for reading a single bit of a cell, using dynamic reading.
  • Appendix A shows that there are ten optimal orderings with a maximum number of comparisons of two: ⁇ 7,6,2,4,5,1,3,0 ⁇ , ⁇ 7,6,2,4,5,3,1,0 ⁇ , ⁇ 7,6,4,2,3,5,1,0 ⁇ , ⁇ 7,6,4,0,2,3,5,1 ⁇ , ⁇ 7,6,4,0,5,1,3,2 ⁇ , ⁇ 7,6,4,5,1,3,2,0 ⁇ , ⁇ 7,6,5,1,3,2,4,0 ⁇ , ⁇ 7,5,6,2,3,1,4,0 ⁇ , ⁇ 7,5,6,2,3,1,4,0 ⁇ , ⁇ 7,3,6,4,5,1,2,0 ⁇ and ⁇ 7,3,6,4,5,1,0,2 ⁇ .
  • Criterion G Minimize the minimum number of comparisons for reading a single bit of a cell, using dynamic reading.
  • Appendix A shows that the best minimum number is again one, but there are many orderings that result in a higher minimum number, meaning a slower reading operation.
  • Criterion H Achieve equal number of comparisons for reading a single bit of a cell (regardless which bit is read), using dynamic reading.
  • Appendix A shows that there are nine orderings in which all bits require two comparisons: ⁇ 7,6,2,4,5,1,3,0 ⁇ , ⁇ 7,6,2,4,5,3,1,0 ⁇ , ⁇ 7,6,4,2,3,5,1,0 ⁇ , ⁇ 7,6,4,0,2,3,5,1 ⁇ , ⁇ 7,6,4,0,5,1,3,2 ⁇ , ⁇ 7,6,5,1,3,2,4,0 ⁇ , ⁇ 7,5,6,2,3,1,4,0 ⁇ , ⁇ 7,3,6,4,5,1,2,0 ⁇ and ⁇ 7,3,6,4,5,1,0,2 ⁇ .
  • Appendix E lists some valid 4-bit orderings for which the difference between the largest number of comparisons and the smallest number of comparisons is 1.
  • FIGS. 2-4 as well as the examples and explanations above, all assume the first implementation.
  • the threshold voltage that is—to move left on the voltage axis
  • the concept of “validity” still is applicable, but the exact rules of which ordering or allocation is valid and which is not may be different.
  • the rules depend on the exact way the intermediate states are defined. The more to the right an intermediate state is, the fewer transitions from it remain valid.
  • Criteria A-H relate to performance issues. However, it may be the case that reliability issues are much more important than performance. In such case one should optimize the selection of the allocation and encoding according to its influence on the number and distribution of expected bit errors when reading the data stored in the cell. The following embodiment of the present invention attains this end.
  • this bit will be in error if a state error occurs at that position. For example, if a state error moves this 2-bit cell between the second and third states, the lower bit will not be in error (no transition at this point in ⁇ 1,0,0,1 ⁇ ) but the upper bit will be in error (there is a transition at the middle of ⁇ 1,1,0,0 ⁇ ).
  • an ordering to be optimal is that the total number of bit transitions is equal to the number of states minus one.
  • for a 4-bit MBC this means the total number of transitions is 15.
  • an ordering is error-rate optimal if and only if its total number of transitions over all bit positions is equal to the number of states of the cell minus one.
  • each bit position of a 4-bit MBC belongs to a different logical page.
  • the flash memory architecture is based on groups of 15,000 cells each storing 4 bits, so each group stores 4 pages of 15,000 bits.
  • the probability of a state error is 1 in 1,000, that is—on average one cell out of each 1,000 cells will be read in an incorrect state. If the ordering used is error-rate optimal, each state error generates exactly one bit error and therefore the bit error rate is also 1 per 1,000 cells and there will be on average 15 bit errors when reading the full group.
  • ECC Error Correction Code
  • the expected average of bit errors is a most crucial factor in the design of ECC circuitry.
  • the larger the number of expected errors the more redundancy is needed for storing extra parity or check bits, and the more complex is the circuitry for both encoding and decoding the stored bits.
  • the dependency of ECC complexity and redundancy cost, on the error rate is quite significant, and it is highly advantageous if one can somehow reduce the bit error rate one has to protect against. Therefore, from the ECC design point of view the two cases of even and uneven errors distribution among the pages are very much different. In the even case the design has to protect against an expected average number of 3.75 errors per page, while in the uneven case the design must protect against an expected average number of 6 errors per page, which is a much more difficult and costly task.
  • Appendix A lists all valid orderings of the 3-bit MBC case. We already mentioned above only two of these orderings are error-rate optimal. However we find out neither of these two satisfies the even distribution requirement. ⁇ 7 , 6 , 4 , 5 , 1 , 0 , 2 , 3 ⁇ has a distribution of (4,2,1) transitions, while ⁇ 7,6,4,5,1,3,2,0 ⁇ has a distribution of (3,3,1) transitions.
  • Appendix B lists all valid 4-bit orderings that are error-rate optimal. There are 36 of those. Again we realize none of them is evenly distributed, or even close to evenly distributed. The most evenly distributed orderings have a distribution of (5,5,4,1) transitions, and this is very far from our goal.
  • Appendix F lists some 3-bit orderings which have a (3,2,2) distribution.
  • Appendix G lists some 4-bit orderings which have a (4,4,4,3) distribution.
  • a non-valid ordering is one in which there are cases in which a bit cannot be written because writing the bit would require moving the cell's threshold to the left (i.e. lowering the threshold voltage), which is not possible.
  • the 4-bit ordering ⁇ 15,11,3,1,0,2,6,14,10,8,9,13,12,4,5,7 ⁇ is shown in Appendix G to have a distribution of (4,4,4,3).
  • Appendix G suppose we have to write a value of “0000” into a cell, one bit at a time.
  • the following aspect of the present invention allows us to achieve the goals of error-optimal and even distribution without violating the validity requirement imposed by the cell's physical method of operation.
  • the solution is based upon a distinction to be made between the physical representation of the bits in the cells and their logical meaning as interpreted by the user of the data.
  • the validity restriction is imposed by the physical level, while the error rate restriction is imposed by the logical level. Therefore we solve the seemingly contradictory requirements by using a different ordering at the logical level than at the physical level.
  • the method is best understood with reference to a specific example. Assume we choose ⁇ 15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1 ⁇ as our physical-level ordering and ⁇ 15,11,3,1,0,2,6,14,10,8,9,13,12,4,5,7 ⁇ as our logical-level ordering.
  • the following table shows the correspondence between the two levels, and is used as a translation table for both writing and reading, as will be explained below.
  • the left column of the table lists each of the physical states the cell can be in, starting from the left-most state number 15 (representing the erased state) up to the right-most state number 0 having the highest threshold voltage. Actually this column is not required for using the table, but is shown for clarity.
  • the center column of the table is titled “Logical level interpretation” and shows how the logical level ordering is matched to the physical states of the cell.
  • the right column of the table is titled “Physical level interpretation” and shows how the physical level ordering is matched to the physical states of the cell.
  • Physical state Logical level interpretation Physical level interpretation 15 15 15 14 11 14 13 3 12 12 1 13 11 0 9 10 2 8 9 6 10 8 14 11 7 10 3 6 8 2 5 9 0 4 13 4 3 12 6 2 4 7 1 5 5 0 7 1
  • FIG. 5 is a flowchart of writing to a cell according to this aspect of the present invention.
  • Move to the right (“physical”) column of the same row, and find the corresponding physical level interpretation (“0001” “1” in this example) (block 14 ).
  • the physical mechanism of the cells is designed to work according to the physical level ordering shown in the right column of the table. So instructing the physical writing mechanism to write a “1” results in the cell being brought to the rightmost state.
  • the intermediate states on the way to the rightmost state are the fourth state from the left when the second lowest bit is programmed and the fifth state from the left when the second highest bit is programmed. Programming the highest bit puts the cell in the rightmost state.
  • FIG. 6 is a flowchart of reading a cell according to this aspect of the present invention.
  • FIG. 7 is a high-level block diagram of a system 30 according to the first case.
  • FIG. 8 is a high-level block diagram of a system 40 according to the second case.
  • Flash management software 34 includes a translation module 36 for translating between logical level ordering and physical level ordering as illustrated in FIGS. 5 and 6 .
  • Flash memory device 52 uses a flash controller 44 to manage a flash memory 50 by executing flash management software 46 .
  • Flash management software 46 includes a translation module 48 for translating between logical level ordering and physical level ordering as illustrated in FIGS. 5 and 6 .
  • FIG. 9 is a high-level block diagram of a system 60 according to the first case.
  • FIGS. 10 and 11 are high-level block diagrams of a system 80 and of a system 100 according to the second case.
  • a host computer 62 sends read and write instructions to a flash memory device 72 .
  • Flash memory device 72 uses a flash controller 64 to manage a flash memory 70 by executing flash management software 66 .
  • flash controller 64 writes to flash memory 70
  • logical level ordering generated by flash management software 66 is translated to physical level ordering by translation hardware 68 in flash controller 64 as illustrated in FIG. 5 .
  • flash controller 64 reads from flash memory 70
  • physical level ordering received from flash memory 70 is translated to logical level ordering by translation hardware 68 as illustrated in FIG. 6 .
  • a host computer 82 sends read and write instructions to a flash memory device 92 .
  • Flash memory device 92 uses a flash controller 84 to manage a flash memory 90 by executing flash management software 86 .
  • flash controller 84 writes to flash memory 90
  • flash memory 90 receives logical level ordering from flash controller 84 and translation hardware 88 in flash memory 90 translates the logical level ordering to physical level ordering as illustrated in FIG. 5 .
  • translation hardware 88 translates the physical level ordering of flash memory 90 to logical level ordering for presentation to flash controller 84 , as illustrated in FIG. 6 .
  • a host computer 82 executes flash management software 104 to manage a flash memory device 110 .
  • Host computer 102 reads and writes flash memory device 110 according to logical level ordering.
  • translation hardware 106 in a flash memory 108 of flash memory device 110 translates the logical level ordering to physical level ordering as in FIG. 5 .
  • translation hardware 106 translates the physical level ordering of flash memory 108 to logical level ordering for presentation to host computer 102 as illustrated in FIG. 6 .
  • the translation requires all the data bits, that are targeted to the cells to be written, to be available before the writing operation begins. This is so because in order to know which row in the translation table we are in we need all the bits of the logical data.
  • the host should have all 4 logical pages that will eventually reside in the same group of cells to be available before programming can start. Then the data of any one of the 4 pages is viewed as one row in a 4-rows table, and then each 4-bit column of the table serves as an input to the translation process described above.
  • K cells Lowest page 0 1 0 . . .
  • Cell #0 stores a binary 6
  • cell # 1 stores a binary 3
  • cell # 2 stores a binary 8, etc.
  • Such an ordering is called herein an ordering that evenly distributes the error probabilities of the bits, or equivalently, that provides an even distribution of the error probabilities of the bits, given the probability distributions of the data bits and of the state errors.
  • an ordering that evenly distributes the error probabilities of the bits is not necessarily an “evenly distributed” ordering, as defined above, although as we have seen if the data bits and the state errors are uniformly distributed then an evenly distributed ordering does distribute the error probabilities evenly. If the ordering resulting from this optimality criteria is valid, it can be used as the only ordering at all levels, with no translation needed.
  • the average number of errors in the logical page to which the lowest bit is assigned is 15,000 times the sum of the transition error probabilities of the transitions that change the lowest bit.
  • the ⁇ 15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1 ⁇ bit ordering is valid and error-rate optimal and also distributes the bit error probabilities evenly, and no translation is needed.
  • optimal ordering may be found to be non-valid and therefore not possible to use at the physical cells level.

Abstract

Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

Description

  • This patent application claims the benefit of U.S. Provisional Patent Application No. 60/553,798, filed Mar. 14, 2004. This patent application also claims the benefit of U.S. Provisional Patent Application No. 60/611,873, filed Sep. 22, 2004. This patent application also is a continuation-in-part of US patent application Ser. No. 11/035,807 filed Jan. 18, 2005.
  • FIELD AND BACKGROUND OF THE INVENTION
  • The present invention relates to flash memories and, more particularly, to a method of storing data in multi-bit flash cells.
  • Flash memory devices have been known for many years. Typically, each cell within a flash memory stores one bit of information. Traditionally, the way to store a bit has been by supporting two states of the cell—one state represents a logical “0” and the other state represents a logical “1”. In a flash memory cell the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within this floating gate. Typically, one state is with zero charge in the floating gate and is the initial unwritten state of the cell after being erased (commonly defined to represent the “1” state) and another state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state). Having negative charge in the gate causes the threshold voltage of the cell's transistor (i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct) to increase. Now it is possible to read the stored bit by checking the threshold voltage of the cell: if the threshold voltage is in the higher state then the bit value is “0” and if the threshold voltage is in the lower state then the bit value is “1”. Actually there is no need to accurately read the cell's threshold voltage. All that is needed is to correctly identify in which of the two states the cell is currently located. For that purpose it is enough to make a comparison against a reference voltage value that is in the middle between the two states, and thus to determine if the cell's threshold voltage is below or above this reference value.
  • FIG. 1A shows graphically how this works. Specifically, FIG. 1A shows the distribution of the threshold voltages of a large population of cells. Because the cells in a flash memory are not exactly identical in their characteristics and behavior (due, for example, to small variations in impurities concentrations or to defects in the silicon structure), applying the same programming operation to all the cells does not cause all of the cells to have exactly the same threshold voltage. (Note that, for historical reasons, writing data to a flash memory is commonly referred to as “programming” the flash memory.) Instead, the threshold voltage is distributed similar to the way shown in FIG. 1A. Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the left peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages. Similarly, cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the right peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages.
  • In recent years a new kind of flash memory has appeared on the market, using a technique conventionally called “Multi Level Cells” or MLC for short. (This nomenclature is misleading, because the previous type of flash cells also have more than one level: they have two levels, as described above. Therefore, the two kinds of flash cells are referred to herein as “Single Bit Cells” (SBC) and “Multi-Bit Cells” (MBC).) The improvement brought by the MBC flash is the storing of two or more bits in each cell. In order for a single cell to store two bits of information the cell must be able to be in one of four different states. As the cell's “state” is represented by its threshold voltage, it is clear that a 2-bit MBC cell should support four different valid ranges for its threshold voltage. FIG. 1B shows the threshold voltage distribution for a typical 2-bit MBC cell. As expected, FIG. 1B has four peaks, each corresponding to one state. As for the SBC case, each state is actually a range and not a single number. When reading the cell's contents, all that must be guaranteed is that the range that the cell's threshold voltage is in is correctly identified. For a prior art example of an MBC flash memory see U.S. Pat. No. 5,434,825 to Harari.
  • Similarly, in order for a single cell to store three bits of information the cell must be able to be in one of eight different states. So a 3-bit MBC cell should support eight different valid ranges for its threshold voltage. FIG. 1C shows the threshold voltage distribution for a typical 3-bit MBC cell. As expected, FIG. 1C has eight peaks, each corresponding to one state. FIG. 1D shows the threshold voltage distribution for a 4-bit MBC cell, for which sixteen states, represented by sixteen threshold voltage ranges, are required.
  • When encoding two bits in an MBC cell via the four states, it is common to have the left-most state in FIG. 1B (typically having a negative threshold voltage) represent the case of both bits having a value of “1”. (In the discussion below the following notation is used—the two bits of a cell are called the “lower bit” and the “upper bit”. An explicit value of the bits is written in the form [“upper bit” “lower bit”], with the lower bit value on the right. So the case of the lower bit being “0” and the upper bit being “1” is written as “10”. One must understand that the selection of this terminology and notation is arbitrary, and other names and encodings are possible). Using this notation, the left-most state represents the case of “11”. The other three states are typically assigned by the following order from left to right: “10”, “00”, “01”. One can see an example of an implementation of an MBC NAND flash memory using this encoding in U.S. Pat. No. 6,522,580 to Chen, which patent is incorporated by reference for all purposes as if fully set forth herein. See in particular FIG. 8 of the Chen patent. U.S. Pat. No. 6,643,188 to Tanaka also shows a similar implementation of an MBC NAND flash memory, but see FIG. 7 there for a different assignment of the states to bit encodings: “11”, “10”, “01”, “00”. The Chen encoding is the one illustrated in FIG. 1B.
  • We extend the above terminology and notation to the cases of more than two bits per cell, as follows. The left-most unwritten state represents “all ones” (“1 . . . 1”), the string “1 . . . 10” represents the case of only the lowest bit of the cell being written to “0”, and the string “01 . . . 1” represents the case of only the most upper bit of the cell being written to “0”.
  • When reading an MBC cell's content, the range that the cell's threshold voltage is in must be identified correctly; only in this case this cannot always be achieved by comparing to only one reference voltage. Instead, several comparisons may be necessary. For example, in the case illustrated in FIG. 1B, to read the lower bit, the cell's threshold voltage first is compared to a reference comparison voltage V1 and then, depending on the outcome of the comparison, to either a zero reference comparison voltage or a reference comparison voltage V2. Alternatively, the lower bit is read by unconditionally comparing the threshold voltage to both a zero reference voltage and a reference comparison voltage V2, again requiring two comparisons. For more than two bits per cell, even more comparisons might be required.
  • The bits of a single MBC cell may all belong to the same flash page, or they may be assigned to different pages so that, for example in a 4-bit cell, the lowest bit is in page 0, the next bit is in page 1, the next bit in page 2, and the highest bit is in page 3. (A page is the smallest portion of data that can be separately written in a flash memory). Both methods are in use. While the methods of the present invention are explained here in the context of the “each bit in its own page” approach, these methods also can be applied to the case of all bits residing in the same page.
  • As was shown above for the 2-bit MBC cell, there is more than one option in how to define the correspondence between the cell's threshold voltage states and the bit encodings they represent. Each such correspondence is equivalent to a specific ordering of the encoded bit patterns along the threshold voltage axis. We saw above that Chen and Tanaka, while disclosing very similar cell designs, used different assignments (and hence different orderings), both equally usable. The object of the current invention is to provide good orderings that are better than other orderings in some sense.
  • At first glance, one might think that every permutation of ordering all n-bit patterns should be considered for the n-bit MBC cell. The number of permutations of N elements is equal to N! (“N Factorial”). A cell with n bits has 2n different bit patterns, and therefore has 2n! permutations. So this would lead to the 2-bit cell having 4!=24 possible orderings, the 3-bit cell having 8!=40,320 possible orderings, and so on. However, there are restrictions put on the ordering because of the way the flash cells are programmed, and these restrictions reduce the number of orderings that can actually be used.
  • First, according to the conventions we defined above, the left-most state always corresponds to the “all ones” bit pattern. Second, assuming a design in which each bit resides in a different page, there are restrictions caused by the bits of a cell being written sequentially rather than all at once. One must remember that programming can only increase the threshold voltage of a cell, not reduce it. Reduction of the threshold voltage can only be done when erasing, but erasing can be applied only to large groups of cells (“blocks” in common terminology). Therefore, any ordering of the bit patterns that requires the threshold voltage to decrease when writing a bit to “0” cannot be used. Consider for example a 2-bit MBC cell. Suppose we selected the following order from left to right—“11”, “00”, “10”, “01”. Assume we first wrote the lower bit to “0”, so the cell was brought to the “10” state. Now we want to write the upper bit to “0”. This requires changing the threshold downward, from the state representing “10” to the state representing “00”, but as we noted above, this is impossible to do in typical flash memories. Therefore we should select our ordering of bit patterns in a way that for every legal sequence of bit programming operations, it will never be required to reduce the threshold voltage. An ordering that satisfies these two restrictions is called herein a “valid” ordering. Similarly, an assignment of bit patterns to cell's states that results in a valid ordering is called herein a “valid” assignment.
  • It is common, in MBC flash memories that assign a cell's bits to different pages, to have a lower bit in a lower-numbered page and to require the user to write the pages in sequential order so that a lower-numbered page is written before a higher-numbered page. We use this practice in the explanations here, but one must understand that the methods of the present invention are equally applicable to other practices of assigning bits to pages and of ordering the writing of pages.
  • FIG. 2 shows a graphical representation of the restrictions applicable to the ordering of bit patterns in a 2-bit MBC cell. Each bit pattern is shown by its binary representation within a circle, and by its decimal representation outside the circle. Both numerical representations are equivalent, but it is more convenient to use the binary representation for understanding the ordering restrictions, and to use the decimal representation for talking about a certain pattern. An arrow connecting two circles in FIG. 2 means that the state from which the arrow originates must precede the state to which the arrow points.
  • One can see in FIG. 2 that, as expected, “11” must be the first state. This is seen from the fact this state must precede all other states. Also, “10” must preceded “00”, as shown above. Because of the simplicity of the 2-bit case, it is easy to realize there are only three orderings that satisfy all restrictions:
      • a. 11, 10, 00, 01 (this is what Chen used)
      • b. 11, 10, 01, 00 (this is what Tanaka used)
      • c. 11, 01, 10, 00
  • FIG. 3 shows the corresponding graphical representation for the case of 3-bit MBC cells, and FIG. 4 shows the corresponding graphical representation for the case of 4-bit MBC cells. Both cases are much more complex than the 2-bit case and allow many more valid orderings.
  • Let us find out how many legal orderings we have in each case. Consider first the 2-bit case (FIG. 2). As “11” always comes first, we ignore it and consider the equivalent question of how many options we have to put the other three patterns in the right-most three states, while satisfying the restrictions shown in FIG. 2. As “10” and “00” have a strict mandatory order between them, we start by selecting two positions out of the three for putting those two pattern. We designate the number of combinations of n elements taken k at a time as C(n,k), which is equal to (n!)/((n−k)!)/(k!). In this case, k=2 and n=3, and the number of ways to put “10” and “00” in place is 3!/1!/2!=3. The last pattern (“01”) must now be put in the only position left, so we are left with three legal orderings, as we already saw above.
  • Now let us move to the less trivial 3-bit cell (FIG. 3). We notice that after writing the lowest bit of a 3-bit cell, the other 2 bits (still unwritten) represent the same problem of ordering as a 2-bit cell. This can be seen in FIG. 3 by noticing that the “branch” containing {6,4,0,2} has exactly the same structure as the whole of FIG. 2. But we already know this problem has exactly three different solutions. So let us start the construction of an ordering by selecting positions for the four members of the {6,4,0,2} branch out of the seven available positions (recall that the all-ones pattern always has its left-most reserved position). There are C(7,4) ways of doing this. Each such way has three valid internal orderings of the branch members, so in total we have C(7,4)×3 ways of assigning these four patterns. Now for each such selection, we choose two of the three still unassigned positions for representing the {5,1} branch members. This can be done in C(3,2)=3 ways. The last pattern (3) must go into the only position left. The total product is C(7,4)×3×3=315 valid orderings for a 3-bit MBC cell.
  • We can make the calculation similarly for a 4-bit MBC cell (FIG. 4). The positions for the eight members of the {14,12,10,6,8,4,2,0} branch can be selected in C(15,8) ways, each one to be multiplied by the 315 possible internal orderings we found above for the 3-bit case. Then we multiply again by 315, which is the number of arrangements we have for putting the remaining seven states into the remaining seven positions. The end result is C(15,8)×315×315=638,512,875. The number of valid orderings of yet larger numbers of bits is enormous.
  • The Appendices list 3-bit and 4-bit orderings along with analyses of these orderings, as described below. Appendix A lists all 315 3-bit orderings. Appendices B, C, D and E are partial lists of the 4-bit orderings.
  • The large number of possible bit orderings for MBC cells of more than 2 bits brings up the question which is the best one to use. U.S. Pat. No. 6,046,935 to Takeuchi proposes one method of constructing a bit patterns ordering for MBC cells. FIGS. 86A to 86C of Takeuchi apply the method to 3-bit cells. FIGS. 88A to 88D of Takeuchi apply the method to 4-bit cells. FIGS. 90A to 90E of Takeuchi show how to apply the method to the general M-bit case. However, as will be explained below, the method proposed by Takeuchi results in an ordering that is not optimal.
  • There is thus a widely recognized need for, and it would be highly advantageous to have, an optimal method of ordering the bits in an MBC cell.
  • SUMMARY OF THE INVENTION
  • According to the present invention there is provided a method of storing N bits of data, including the steps of: (a) providing ┌N/M┐ cells, wherein M is at least 3; and (b) programming each cell with up to M of the bits according to a valid physical bit ordering, and according to a logical bit ordering that is different from the physical bit ordering and that distributes error probabilities of the up to M bits more evenly than the physical bit ordering.
  • According to the present invention there is provided a memory device including: (a) a memory that includes K cells; and (b) a controller operative to store N bits of data in the cells by programming each cell with up to M=┌N/K┐ of the bits according to a valid physical bit ordering, and according to a logical bit ordering that is different from the physical bit ordering and that distributes error probabilities of the up to M bits more evenly than the physical bit ordering, wherein M is at least 3.
  • According to the present invention there is provided a system for storing data, including: (a) a memory device that includes a memory, the memory including K cells; (b) a host of the memory device, for providing N bits of data to store; and (c) a mechanism for translating, for each cell, up to M=┌N/K┐ of the bits, as listed in a logical bit ordering, into a corresponding entry in a valid physical bit ordering that is different from the logical bit ordering, wherein M is at least 3, the each cell then being programmed according to the entry in the physical bit ordering, the logical bit ordering distributing error probabilities of the up to M bits more evenly than the physical bit ordering.
  • According to the present invention there is provided a method of storing N bits of data, including the steps of: (a) providing ┌N/M┐ cells, wherein M is at least 3; and (b) programming each cell with up to M of the bits according to a valid physical bit ordering, and according to an evenly distributed logical bit ordering that is different from the physical bit ordering.
  • According to the present invention there is provided a memory device including: (a) a memory that includes K cells; and (b) a controller operative to store N bits of data in the cells by programming each cell with up to M=┌N/K┐ of the bits according to a valid physical bit ordering, and according to an evenly distributed logical bit ordering, wherein M is at least 3.
  • According to the present invention there is provided a system for storing data, including: (a) a memory device that includes a memory, the memory including K cells; (b) a host of the memory device, for providing N bits of data to store; and (c) a mechanism for translating, for each cell, up to M=┌N/K┐ of the bits, as listed in an evenly distributed logical bit ordering, into a corresponding entry in a valid physical bit ordering that is different from the logical bit ordering, wherein M is at least 3, the each cell then being programmed according to the entry in the physical bit ordering.
  • According to the present invention there is provided a method of storing N bits of data, including the steps of: (a) providing ┌N/M┐ cells, wherein M is at least 3; and (b) programming each cell with up to M of the bits according to a valid, nonserial bit ordering that distributes error probabilities of all the up to M bits substantially evenly.
  • According to the present invention there is provided a memory device including: (a) a memory that includes K cells; and (b) a controller operative to store N bits of data in the cells by programming each cell with up to M=┌N/K┐ of the bits according to a valid, nonserial bit ordering that distributes error probabilities of all the up to Mbits substantially evenly, wherein M is at least 3.
  • According to the present invention there is provided a method of of storing N bits of data, including the steps of: (a) providing ┌N/M┐ cells, wherein M is at least 3; and (b) programming each cell with up to M of the bits according to a valid, nonserial, error-rate-optimal bit ordering.
  • According to the present invention there is provided a memory device including: (a) a memory tht includes K cells; and (b) a controller operative to store N bits of data in the cells by programming each cell with up to M=┌N/K┐ of the bits according to a valid, nonserial, error-rate-optimal. bit ordering, wherein M is at least 3.
  • The first method of the present invention is a method of storing N bits of data in K=┌N/M┐ cells, with M≧3. (The notation “┌x┐” means the smallest integer that is at least as large as the real number x. For example, ┌3┐=3 and ┌3.5┐=4.) Each cell is programmed with up to M of the data bits according to a valid physical bit ordering, and according to a different logical bit ordering that provides a more even distribution of the error probabilities of all the up to M bits than would be provided by the physical bit ordering alone. This more even error distribution is relative to the probability distribution of the N data bits and relative to the probability distribution of the state errors of the cells. For example, if the bit orderings are “error-rate optimal”, in the sense defined below, then if all data bits are equally probable and all state errors are equally probable, it is shown below that a truly even distribution of the error probabilities can not be achieved; whereas other probability distributions of the data bits and of the state errors may allow a truly even distribution of the error probabilities of all the up to M bits. Indeed, at the end of the description of the preferred embodiments, an artificial example with error-rate optimal bit orderings and a truly even error distribution is presented.
  • Preferably, the programming includes, for each cell, translating the up to M bits, as listed in the logical bit ordering, into a corresponding entry in the physical bit ordering.
  • Preferably, the method also includes the step of reading the N bits from the cells, as the purpose of storing the N bits usually is to provide the possibility of reading the N bits. Most preferably, this reading includes, for each cell, translating an entry, in the physical bit ordering, that corresponds to the state of the cell as programmed, into a corresponding entry in the logical bit ordering.
  • Preferably, the logical bit ordering substantially equalizes probability-weighted numbers of transitions of all the up to M bits, relative to the probability distribution of the data bits and relative to the probability distribution of the state errors.
  • Preferably, the total number of transitions of the physical bit ordering and the total number of transitions of the logical bit ordering both are equal to 2M−1, which is one less than the number of states. Bit orderings with 2M−1 transitions are “error-rate optimal” in the sense defined below. For example, when M=3, both the preferred physical bit ordering and the preferred logical bit ordering have 7 transitions. The corresponding physical. bit orderings are {7,6,4,5,1,0,2,3} and {7,6,4,5,1,3,2,0}. Similarly, when M=4, both the physical bit ordering and the logical bit ordering have 15 transitions. Most preferably, the logical bit ordering is evenly distributed. For example, when M=4 the number of transitions of any bit of the most preferred logical bit ordering is either 3 or 4.
  • Preferably, the physical bit ordering is nonserial.
  • A memory device of the present invention, for implementing the first method of the present invention, includes a memory with K cells and a controller that is operative to store N bits of data in the cells by programming each cell with up to M=┌N/K┐≧3 of the bits according to a valid physical bit ordering, and also according to a different logical bit ordering that provides a more even distribution of the error probabilities of all the up to M bits than would be provided by the physical bit ordering alone.
  • Preferably, the controller includes a mechanism for translating between the physical bit ordering and the logical bit ordering. In one class of preferred embodiments of the memory device of the present invention, this mechanism effects the translating by executing software. In another class of preferred embodiments of the memory device of the present invention, the controller includes dedicated hardware (as opposed to a general purpose processor that executes software) for effecting the translating. Alternatively, the memory includes such dedicated hardware.
  • Preferably, the memory is a flash memory.
  • Preferably, the physical bit ordering is nonserial.
  • A system of the present invention, for storing data, includes a memory device that includes a memory with K cells, and a host of the memory device that provides N bits of data to be stored in the memory device. The system also includes a mechanism for translating, for each of the K cells, up to M=┌N/K┐≧3 of the bits, as listed in a logical bit ordering, into a corresponding entry in a different valid physical bit ordering, that cell then being programmed according to that entry in the physical bit ordering. The logical bit ordering provides a more even distribution of error probabilities of all the up to M bits than would be provided by the physical bit ordering alone.
  • In one class of preferred embodiments of the system of the present invention, the translation mechanism effects the translation by executing software. Such a translation mechanism may be included in the host, or alternatively may be included in a controller, of the memory, that is included in the memory device. In another class of preferred embodiments of the system of the present invention, the translation mechanism includes dedicated hardware. Such a translation mechanism may be included in the memory, or may be included in a controller, of the memory, that is included in the memory device.
  • Preferably, the memory is a flash memory.
  • Preferably, the physical bit ordering is nonserial.
  • A special case of the first method of the present invention and of the corresponding memory device and system ignores both the probability distribution of the N data bits and the probability distribution of the cells' state errors, and just requires that the logical bit ordering be evenly distributed.
  • The second method of the present invention also is a method of storing N bits of data in K=┌N/M┐ cells, with M≧3. Each cell is programmed with up to M of the data bits according to a valid, nonserial bit ordering that distributes the bit error probabilities of all M bits substantially evenly. Note that whether a valid physical bit ordering can achieve such an even distribution of bit error probabilities depends on the probability distribution of the N data bits and relative to the probability distribution of the state errors of the cells. The artificial example at the end of the description of the preferred embodiments is one such case.
  • A memory device of the present invention, for implementing the second method of the present invention, includes a memory with K cells and a controller that is operative to store N bits of data in the cells by programming each cell with up to M=┌N/K┐≧3 of the bits according to a valid, nonserial bit ordering that distributes the error probabilities of all M bits substantially evenly. Preferably, the bit ordering is a physical bit ordering.
  • Gonzalez et al., in U.S. Pat. No. 6,684,289, also teaches mapping between logical bit orderings and physical bit orderings in reading and writing a flash memory, for purposes such as wear leveling and encryption, but not for equalizing the distribution of error probabilities of the stored bits.
  • The third method of the present invention also is a method of storing N bits of data in K=┌N/M┐ cells, with M≧3. Each cell is programmed with up to M of the data bits according to a valid, nonserial, error-rate-optimal bit ordering. The total number of transitions in the bit ordering is the minimum such number for the selected value of M, i.e., 2M−1. For example, when M=3 the bit ordering has seven transitions and when M=4 the bit ordering has fifteen transitions. For M=3, there are two such bit orderings, as listed in Appendix A.
  • Preferably, the bit ordering is evenly distributed. For example, when M=4, each bit of the bit ordering has either three transitions or four transitions.
  • A memory device of the present invention, for implementing the third method of the present invention, includes a memory with K cells and a controller that is operative to store N bits of data in the cells by programming each cell with up to M=┌N/K┐≧3 of the bits according to a valid, nonserial, error-rate-optimal bit ordering.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
  • FIGS. 1A-1D show threshold voltage distributions in a one-bit flash cell, a two-bit flash cell, a three-bit flash cell and a four-bit flash cell;
  • FIG. 2 is a precedence tree for programming a two-bit cell;
  • FIG. 3 is a precedence tree for programming a three-bit cell;
  • FIG. 4 is a precedence tree for programming a four-bit cell;
  • FIG. 5 is a flowchart of writing to a memory cell via a logical bit ordering and a physical bit ordering;
  • FIG. 6 is a flowchart of reading from a memory cell via a physical bit ordering and a logical bit ordering;
  • FIGS. 7-11 are high level block diagrams of systems of the present invention.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention is of a method of programming multi-bit flash cells.
  • The principles and operation of a multi-bit-cell flash memory device according to the present invention may be better understood with reference to the drawings and the accompanying description.
  • We now consider the question of what is a good ordering of the bit patterns in an n-bit MBC cell. There is no one clear-cut criterion to use for deciding what is “best”. Instead we present several different criteria to choose from. The best criterion to use in an actual design depends upon the requirements of the overall storage system, as is made clear in the discussion below.
  • We base our evaluation of orderings on the number of comparison operations required for reading the bits contained in an MBC cell. As already explained above, an SBC cell requires just one comparison of its threshold voltage value against a reference in order to determine the cell's data contents. A 2-bit MBC cell may require two comparisons. Cells with more bits generally require more than two comparisons.
  • We distinguish between two methods of using comparisons in the reading process: static reading and dynamic reading.
  • In static reading, all reference voltage values used during the reading process are fully determined prior to starting the reading. Such reading can be implemented either by using one comparator that does all comparisons one by one by changing the reference voltage value to which it compares a cell's threshold voltage, or by using a number of comparators equal to the number of comparisons (in which case all comparators may operate in parallel). It is also possible to use an intermediate scheme in which the number of comparators is less than the number of comparisons but greater than one, thereby providing be some parallelism in the process. All such implementations are considered static methods for the purpose of this invention, as long as all reference values are fully determined prior to reading. For example, reading the lower bit of the 2-bit MBC cell whose encoding is as shown in FIG. 1B by always comparing to both 0 and V2 is a static reading method that uses two comparisons.
  • In dynamic reading, at least one reference voltage value used during the reading process is determined based on the result of a previous comparison done during the same reading operation. For example, reading the lower bit of the 2-bit MBC cell whose encoding is as shown in FIG. 1B by first comparing to V1, and then depending on the outcome of that comparison, comparing to either 0 or V2, is a dynamic reading method that uses two comparisons.
  • The number of comparisons required for reading a single bit using static reading depends on the way the value of the bit changes when moving from state to state along the threshold voltage axis. As a first example let us consider the 2-bit MBC case with the ordering of {3,2,0,1}. In binary notation, that ordering is {11,10,00,01}. (Note that in the appended claims, decimal notation is used for bit orderings.) Now we separate the bits, each into its own sequence. When we move along the states from left to right the lower bit passes through the values {1,0,0,1} while the upper bits passes through {1,1,0,0}. It is easy to see that we can determine the value of the upper bit by just a single comparison, with the reference value positioned to separate between the two left states and the two right states. The lower bit, however, cannot be determined by any single comparison; the best we can do is to use two comparisons (one separating the left-most state from all other states, and one separating the right-most state from all other states).
  • If, however, the ordering of states is {3,2,1,0}={11,10,01,00}, then the lower bit sequence is now {1,0,1,0} and the upper bit sequence is again {1,1,0,0}. So using this ordering the lower bit requires three comparisons and the upper bit requires one comparison.
  • The third and last valid 2-bit ordering is {3,1,2,0}={11,01,10,00}, giving {1,1,0,0} for the lower bit and {1,0,1,0} for the upper bit. This translates to one comparison for the lower bit and three comparisons for the upper bit.
  • It is easy to realize that the number of comparisons required for reading a single bit using static reading is equal to the number of transitions the bit incurs when traversing all states along the threshold voltage axis from left to right. {1,1,0,0} has just one transition and requires one comparison, while {1,0,1,0} has three transitions and requires three comparisons.
  • The same rules also apply to reading a cell with more than two bits. For example, a 3-bit cell with the ordering {7,6,2,4,0,5,3,1}={111,110,010,100,000,101,011,001} produces the sequence {1,0,0,0,0,1,1,1} for the lower bit, {1,1,1,0,0,0,1,0} for the middle bit, and {1,1,0,1,0,1,0,0} for the upper bit. The numbers of transitions (and therefore the number of comparisons) are 2 for the lower bit, 3 for the middle bit and 5 for the upper bit.
  • The number of comparisons required for reading a single bit using dynamic reading also depends on the number of transitions the bit incurs when traversing all states along the threshold voltage axis from left to right, but in a different way than for static reading. For dynamic reading, the number of comparisons is the logarithm to base two of the number of transitions plus one, rounded up. For example, for a 2-bit MBC cell with the ordering of {3,2,0,1}={11,10,00,01} and bit sequences of {1,0,0,1} (two transitions) and {1,1,0,0} (one transition), the numbers of comparisons are two and one, respectively. Note that the ordering of {3,2,1,0}={1,10,01,00} with the bit sequences of {1,0,1,0} (three transitions) and {1,1,0,0} (one transition) also results in two and one comparisons, respectively, even though its number of transitions is different.
  • Again, the same rules also apply for cells with more than two bits each. For example, reading a 3-bit cell with the ordering {7,6,2,4,0,5,3,1}={111,110,010,100,000,101,011,001} that produces the bit sequences {1,0,0,0,0,1,1,1} (two transitions), {1,1,1,0,0,0,1,0} (three transitions), and {1,1,0,1,0,1,0,0} (five transitions), requires two, two and three comparisons, respectively.
  • Appendix A lists all the valid orderings for the 3-bit case. Each of the 315 orderings has one line in the table, showing the sequences for each of the three bits, the number of static reading comparisons for each bit (the three columns under the heading “static comp”), and the number of dynamic reading comparisons for each bit (the three columns under the heading “dynamic comp”). Also shown are the total, minimum and maximum numbers for each of the two reading methods, statistics that are referenced in the discussion below.
  • We now investigate several criteria for selecting the ordering of bit patterns in an MBC cell. These criteria all relate to the number of comparisons required for reading. Generally speaking, the fewer comparisons to be done the better. A higher number of comparisons implies either a longer time for completing the operation (if using a single comparator) or a larger number of comparators (or both).
  • Criterion A. Minimize the number of comparisons for sequentially reading all the bits in a cell (that is, reading the bits one by one and not in one operation) using static reading.
  • In a cell that uses static reading with a single comparator, the time required for sequentially reading all the bits of a cell increases as the sum of the number of comparisons of all bits. Therefore a good criterion for selecting an ordering is to minimize the sum of comparisons of all bits.
  • Looking at the results above, we see that for the 2-bit case we get a total of three comparisons for {3,2,0,1} and four comparisons for the other two alternatives. Therefore {3,2,0,1} provides the fastest sequential reading of all bits of a cell, and is thus optimal according to this criterion.
  • For the 3-bit case, we see in Appendix A that there are two optimal orderings with a total of seven comparisons ({7,6,4,5,1,0,2,3} and {7,6,4,5,1,3,2,0}). The encoding illustrated in FIG. 1C corresponds to the {7,6,4,5,1,0,2,3} ordering. There also are 15 orderings that have a total of eight comparisons, which is close to optimal.
  • For the 4-bit case, the 36 orderings listed in Appendix B are optimal according to this criterion. Each such ordering has a total of 15 comparisons. The encoding illustrated in FIG. 1D corresponds to the first of these orderings, {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1}.
  • Criterion B. Minimize the maximum number of comparisons for reading a single bit of a cell using static reading.
  • In a cell that uses static reading with a single comparator, the maximum time required for reading any bit of a cell increases with the maximum number of comparisons of any bit. Therefore a good criterion for selecting an ordering is to minimize the maximum number of comparisons for any bit.
  • For the 2-bit case this maximum number is two for {3,2,0,1} and three for the other two alternatives. Therefore {3,2,0,1} is optimal according to this criterion too.
  • For the 3-bit case, Appendix A lists ten optimal orderings under this criterion, with a maximum number of comparisons of three: {7,6,2,4,5,1,3,0}, {7,6,2,4,5,3,1,0}, {7,6,4,2,3,5,1,0}, {7,6,4,0,2,3,5,1}, {7,6,4,0,5,1,3,2}, {7,6,4,5,1,3,2,0}, {7,6,5,1,3,2,4,0}, {7,5,6,2,3,1,4,0}, {7,3,6,4,5,1,2,0} and {7,3,6,4,5,1,0,2}.
  • A complete enumeration of all valid 4-bit orderings shows that the minimum for this criterion is five comparisons. Some of these orderings are listed in Appendix B.
  • Criterion C. Minimize the minimum number of comparisons for reading a single bit of a cell, using static reading.
  • In a cell that uses static reading with a single comparator, the minimum time required for reading any bit of a cell increases with the minimum number of comparisons of any bit. Therefore a good criterion for selecting an ordering is to minimize the minimum number of comparisons for any bit.
  • For the 2-bit case this minimum number is one, and is the same for all three valid orderings. For the 3-bit case Appendix A shows that the best minimum number is again one, but there are many orderings that result in a higher minimum number, meaning a slower reading operation.
  • A complete enumeration of all valid 4-bit orderings shows that the minimum for this criterion for the 4-bit case also is one comparison. Some of these orderings are listed in Appendix B.
  • The method of Takeuchi mentioned above results in an ordering that gives the upper bit only one comparison (note that Takeuchi uses a terminology that is the opposite of the one we use: he calls the first bit that is written into the cell “the upper bit” and not “the lower bit”. We continue to use our terminology when discussing Takeuchi method). This implies that the Takeuchi method may be considered optimal in this sense. However, the Takeuchi method is based on assigning the states in a very simple and straight-forward manner—writing the first bit brings the threshold to one of the two left-most states, writing the second bit brings the threshold to one of the four left-most states, writing the third bit brings the threshold to one of the eight left-most states, and writing the M-th bit brings the threshold to one of the 2M left-most bits. The way this is done (see FIGS. 90A to 90E in Takeuchi) always results in the trivial serial ordering in which we start with the highest value for the left-most state and go down by one on each move to the right. For example, the Takeuchi ordering for the 3-bit case is {7,6,5,4,3,2,1,0}, and the Takeuchi ordering for the 4-bit case is {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0}.
  • Such an ordering requires one comparison for the last bit to be written into the cell, three comparisons for the next-to-last bit, seven comparisons for the third bit from the end, and 2M−1 comparisons for the M-th bit from the end. While it is true the Takeuchi ordering provides one bit with only one comparison, the first bit to be written into the cell has the highest number of comparisons possible (seven for the 3-bit case, 15 for the 4-bit case). This creates a large difference in the reading time of different bits of the cell and is not desirable, and therefore such ordering is not considered optimal in spite of having one bit with the minimal number of comparisons.
  • We use herein the term “serial assignment” for referring to an assignment that results in an ordering such as Takeuchi, having the form {2M−1,2M−2, . . . , 4,3,2,1,0}. The corresponding bit ordering is called herein a “serial” bit ordering. All other orderings are called “nonserial” herein.
  • Criterion D. Achieve equal number of comparisons for reading a single bit of a cell (regardless which bit is read), using static reading.
  • In a cell that uses static reading with a single comparator, it might be beneficial to have all bits being read using the same number of comparisons, so as to provide the same response time regardless of which bit is being read. Therefore a good criterion for selecting an ordering is to achieve the same number of comparisons for all bits.
  • For the 2-bit case no ordering satisfies this criterion. For the 3-bit case Appendix A shows that there are four orderings in which all bits require three comparisons: {7,6,2,4,5,1,3,0}, {7,6,2,4,5,3,1,0}, {7,6,4,2,3,5,1,0} and {7,6,5,1,3,2,4,0}.
  • Obviously, there can be no 4-bit ordering with a total of 15 comparisons in which all bits have the same number of comparisons, because 15 is not divisible by 4. Appendix C lists all 4-bit valid orderings with a total of 16 comparisons in which the difference between the lowest and highest bit is not more than two comparisons, and we see that even in this case there is no valid ordering which satisfies this optimization criterion. The best that can be achieved is a difference of two comparisons between the bit with the lowest number of comparisons and the bit with the highest number of comparisons. Actually, if there is a strong desire to get as close as possible to an equal spread of comparisons over all bits, one would do better to choose a 17-comparison 4-bit ordering. Appendix D lists all valid orderings with a total of 17 comparisons in which the difference between the lowest and highest bit is not more than one comparison, and one can see that there are really orderings in which the difference between lowest and highest is only one comparison, resulting in more constant reading response time than can be achieved with either a 15-comparison ordering or a 16-comparison ordering.
  • Criterion E. Minimize the number of comparisons for sequentially reading all bits in a cell, using dynamic reading.
  • This is the equivalent of criterion A, but for dynamic reading.
  • For the 2-bit case, all valid orderings result in the same number of comparisons and therefore there is no one optimal ordering.
  • For the 3-bit case, Appendix A shows that there is one optimal ordering ({7,6,4,5,1,3,2,0}), with a total of five comparisons. There also are many orderings with a total of six comparisons.
  • A complete enumeration of all valid 4-bit orderings shows that the minimum for this criterion for the 4-bit case is nine comparisons. Some of these orderings are listed in Appendix B.
  • Criterion F. Minimize the maximum number of comparisons for reading a single bit of a cell, using dynamic reading.
  • This is the equivalent of criterion B, but for dynamic reading.
  • For the 2-bit case, all valid orderings result in the same number of comparisons (two) and therefore there is no one optimal ordering.
  • For the 3-bit case, Appendix A shows that there are ten optimal orderings with a maximum number of comparisons of two: {7,6,2,4,5,1,3,0}, {7,6,2,4,5,3,1,0}, {7,6,4,2,3,5,1,0}, {7,6,4,0,2,3,5,1}, {7,6,4,0,5,1,3,2}, {7,6,4,5,1,3,2,0}, {7,6,5,1,3,2,4,0}, {7,5,6,2,3,1,4,0}, {7,3,6,4,5,1,2,0} and {7,3,6,4,5,1,0,2}.
  • A complete enumeration of all valid 4-bit orderings shows that the minimum for this criterion for the 4-bit case is three comparisons. Some of these orderings are listed in Appendix B.
  • Criterion G. Minimize the minimum number of comparisons for reading a single bit of a cell, using dynamic reading.
  • This is the equivalent of criterion C, but for dynamic reading.
  • For the 2-bit case, all valid orderings result in the same minimum number of comparisons (one) and therefore there is no one optimal ordering.
  • For the 3-bit case, Appendix A shows that the best minimum number is again one, but there are many orderings that result in a higher minimum number, meaning a slower reading operation.
  • A complete enumeration of all valid 4-bit orderings shows that the minimum for this criterion for the 4-bit case is one comparison. Some of these orderings are listed in Appendix B.
  • Criterion H. Achieve equal number of comparisons for reading a single bit of a cell (regardless which bit is read), using dynamic reading.
  • This is the equivalent of criterion D, but for dynamic reading.
  • For the 2-bit case no ordering satisfies this criterion. For the 3-bit case, Appendix A shows that there are nine orderings in which all bits require two comparisons: {7,6,2,4,5,1,3,0}, {7,6,2,4,5,3,1,0}, {7,6,4,2,3,5,1,0}, {7,6,4,0,2,3,5,1}, {7,6,4,0,5,1,3,2}, {7,6,5,1,3,2,4,0}, {7,5,6,2,3,1,4,0}, {7,3,6,4,5,1,2,0} and {7,3,6,4,5,1,0,2}.
  • Appendix E lists some valid 4-bit orderings for which the difference between the largest number of comparisons and the smallest number of comparisons is 1.
  • One point of clarification should be added to the definition of the concept of valid allocations and valid orderings. It is assumed above that any intermediate step resulting from programming only some of the bits of a cell (but not all) is identical to the state that would be created if the still not written bits will be written as “1”. In other words, programming the last bits of a cell to “1” is actually “doing nothing” but keeping the cell's state unchanged. This is really a convenient way to implement the cell, and this is how typical MBC cells are currently built. However, it is possible to design an MBC cell a bit differently. If we assume the cell is always programmed with the full number of bits it can store, we can rely on the last programming operations to shift the state (the threshold voltage) even if a “1” is to be programmed. This means, for example, that a 4-bit MBC that was programmed with three “0” bits and is waiting to be programmed with the fourth bit will have a different state than the same cell after being programmed with “0001”. In such a design either we do not allow not programming all bits, or we devise a different reading scheme for reading cells that were not “filled” with all bits.
  • FIGS. 2-4, as well as the examples and explanations above, all assume the first implementation. For the second implementation it is still not allowed to decrease the threshold voltage (that is—to move left on the voltage axis) when programming each bit, but there may be more flexibility in the sense that transitions that are impossible in the first implementation are possible in the second one. Therefore the concept of “validity” still is applicable, but the exact rules of which ordering or allocation is valid and which is not may be different. Unlike the first implementation, to which the precedence trees of FIGS. 2-4 apply, it is not possible here to draw similar generic diagrams, as the rules depend on the exact way the intermediate states are defined. The more to the right an intermediate state is, the fewer transitions from it remain valid.
  • It should be understood that all the methods of the first implementation of the present invention are equally applicable to the second implementation, except that the validity of an allocation or ordering must be checked against its specific transition rules and not against FIGS. 2-4.
  • Criteria A-H relate to performance issues. However, it may be the case that reliability issues are much more important than performance. In such case one should optimize the selection of the allocation and encoding according to its influence on the number and distribution of expected bit errors when reading the data stored in the cell. The following embodiment of the present invention attains this end.
  • When reading the values of the bits previously stored in an MBC cell we are attempting to find out in which of the voltage bands is the cell located. After the band is found, it is converted into the corresponding bits represented by that band according to the allocation and ordering used when writing the cell. It might happen that an error had occurred and the cell's state was changed since it was written. The most common source of such an error in a flash cell is the leakage of electrons stored in the cell's floating gate. This will typically result in the threshold voltage of the cell shifting a bit, resulting in the cell moving from the band it was written into to another band. There are also other error mechanisms in flash cells, for example disturbances of various kinds (e.g write disturb, read disturb) in which an operation that is not intended to change the state of a certain cell unintentionally changes the state of that cell because of side-effects of the signals and voltages applied to neighboring cells or to the same cell.
  • Extensive tests of statistics of flash MBC errors have shown that the overwhelming majority of errors involve the shift of the cell's state by one band along the voltage axis. For example, assuming the 2-bit MBC of FIG. 1B, a cell programmed to the “00” state might eventually be read to be in the immediately neighboring “01” or “10” states, but almost never in the “11” state that is two states away from the written state. Similarly, in a 4-bit MBC whose states ordering is {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1} if the cell was written to state 3 we can expect the most common errors to bring it to either state 11 or state 2, both of which are the immediate neighbors of state 3. Only rarely does an error lead to reading the cell as being in any of the other 13 states.
  • Let us investigate the effect of such an error in which a cell is read in a different state than the one it was written in. We start with the simple case of the 2-bit MBC of FIG. 1B. If the written state was “00” and the read state is “01”, we shall correctly report the upper bit to be “0” but the lower bit will be wrong: we shall get a “1” instead of “0”. If the written state was “00” and the read state is “10”, we shall correctly report the lower bit to be “0” but the upper bit will be wrong: we shall get a “1” instead of “0”. We are not exploring the implications of a “00” to “11” error because, as we explained above, this 2-states-away error is rare.
  • The above argument could lead us to the conclusion that each error in reading the cell's state results in one bit being wrong. However, this is an incorrect conclusion. Let us examine a 2-bit MBC using the ordering of Tanaka ({11,10,01,00}). Suppose the physical phenomenon is exactly the same as in the previous example—the cell was written to be in the third state from the left and ended up being in the second state from the left. In the previous example this meant a transition from “00” to “10”. However, in this case there is a different bit assignment which makes this error correspond to a shift from “01” to “10”. What we end up with are errors in both lower and upper bits—the lower bit is reported as “0” instead of “1” and the upper bit is reported as “1” instead of “0”. So we see that the selection of bit allocation and ordering has an influence on the number of bit errors we shall get when reading the stored data.
  • Let us now look at the more complicated case of a 4-bit MBC. Consider a 4-bit cell using the serial ordering of {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0}. Suppose the cell was written as “0” and read as “1”. This means we wrote “0000” and read “0001”. So the lowest bit is in error but the other three bits are still correct. One state error was translated into one bit error. This seems a good result, so is this specific ordering a good one? Suppose now the cell was written as “1” and read as “2”. This means we wrote “0001” and read “0010”. So now the two lowest bits are in error, while the two upper bits are correct. One state error was translated into two bit errors. This certainly raises questions about the optimality of this ordering, so let us continue the analysis. Suppose the cell was written as “3” and read as “4”. This means we wrote “0011” and read “0100”. Now all three lowest bits are in error, leaving only the upper bit correct. One state error was translated into three bit errors, certainly not a good result. But we are not finished yet. Suppose the cell was written as “7” and read as “8”. This means we wrote “0111” and read “1000”. Now all four bits are incorrect. One state error was translated into four bit errors, showing that the serial ordering is not a good one when considering the storage bit error rate.
  • To see that such “error amplification” is not inevitable and there really are orderings that are better than the serial ordering, let us return to the {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1} ordering already mentioned above. By trying out each and every one-state-away error we verify the following fact: each state error results in exactly one bit error. Let us write down all the possible state transitions to show this fact:
      • i. 15<-->14, “1111”<-->“1110”, only lowest bit affected
      • ii. 14<-->12, “1110”<-->“1100”, only second lowest bit affected
      • iii. 12<-->13, “1100”<-->“1101”, only lowest bit affected
      • iv. 13<-->9, “1101”<-->“1001”, only second highest bit affected
      • v. 9<-->8, “1001”<-->“1000”, only lowest bit affected
      • vi. 8<-->10, “1000”<-->“1010”, only second lowest bit affected
      • vii. 10<-->11, “1010”<-->“1011”, only lowest bit affected
      • viii. 11<-->3, “1011”<-->“0011”, only highest bit affected
      • ix. 3<-->2, “0011”<-->“0010”, only lowest bit affected
      • x. 2<-->0, “0010”<-->“0000”, only second lowest bit affected
      • xi. 0<-->4, “0000”<-->“0100”, only second highest bit affected
      • xii. 4<-->6, “0100”<-->“0110”, only second lowest bit affected
      • xiii. 6<-->7, “0110”<-->“0111”, only lowest bit affected
      • xiv. 7<-->5, “0111”<-->“0101”, only second lowest bit affected
      • xv. 5<-->1, “0101”<-->“0001”, only second highest bit affected
  • It is important to understand that what we are comparing are different orderings over the same physical cells. The physical phenomena which are the source of the errors are not affected by how we interpret the states to represent bits. The number of cells that end up being in an incorrect state is dictated by the laws of physics and not by the bit assignments. Nevertheless, the same physical fact of a given number of erroneous cells translates into different numbers of erroneous bits depending on the way the bits were allocated to the physical states. So a flash memory designer has an influence on the bit error rate of the data and can reduce the number of bit errors using an appropriately optimized bit allocation.
  • As it is obvious that each error in a cell's state must generate at least one bit error (or otherwise two different states would represent exactly the same bits), we conclude that the above {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1} ordering is optimal in this sense. We define an ordering to be “error-rate optimal” if it satisfies the condition that every error in reading the cell's state that results in reading an incorrect state that is one state away from the correct state generates exactly one bit error. It is easy to identify such an ordering: when looking at the ordering as a sequence of binary numbers, the difference between any two directly adjacent numbers is limited to one bit position. Any ordering satisfying this condition is error-rate optimal, and any ordering that is error-rate optimal must have this feature. This type of binary coding is well known in the mathematical literature and is called a “Gray code”, after the inventor of U.S. Pat. No. 2,632,058, which patent is incorporated by reference for all purposes as if fully set forth herein.
  • There is another way to look at the above error rate optimality condition that is sometimes easier to work with, based on the notion of “transitions” as defined above. As we saw above, the number of bit errors generated in a certain bit position of a cell depends on the way the value of the bit changes when moving from state to state along the threshold voltage axis. As a first example let us consider the 2-bit MBC case with the ordering of {3,2,0,1}. Writing that same ordering using binary notation provides {11,10,00,01}. Now we separate the bits, each into its own sequence. When we move along the states from left to right the lower bit passes through the values {1,0,0,1} while the upper bits passes through {1,1,0,0}. It is easy to see that whenever there is a transition in the sequence of a bit, this bit will be in error if a state error occurs at that position. For example, if a state error moves this 2-bit cell between the second and third states, the lower bit will not be in error (no transition at this point in {1,0,0,1}) but the upper bit will be in error (there is a transition at the middle of {1,1,0,0}). Similarly, let us look at a 3-bit cell with the ordering {7,6,2,4,0,5,3,1}={111,110,010,100,000,101,011,001} that produces the sequence {1,0,0,0,0,1,1,1} for the lower bit, {1,1,1,0,0,0,1,0} for the middle bit, and {1,1,0,1,0,1,0,0} for the upper bit. A state error between the third and fourth states from the right results in bit errors in both the lower and upper bits but not in the middle bit, as there are transitions at this point at the lower and upper bits sequences but not at the middle bit sequence.
  • The implication of this is that location of transitions in the sequence of a bit position determines if it will incur an error upon a state error at that position. If we assume that all the states of a cell are equally likely to occur when the cell is used (in other words—we have no prior knowledge of the data stored in the cells) and also that the state errors in both directions (right and left) are approximately equally likely to occur, then we can conclude that the probability of an error in a certain bit is directly proportional to the number of transitions along its sequence. Also, the total probability of a bit error in any bit position is directly proportional to the total number of transitions in all the bit sequences together. This leads to the conclusion that the lower the total number of transitions, the better is the ordering from the bit errors point of view. As we previously concluded that an optimal ordering generates exactly one bit transition from each state transition, an equivalent condition for an ordering to be optimal is that the total number of bit transitions is equal to the number of states minus one. For a 3-bit MBC this means the total number of transitions is 7, and for a 4-bit MBC this means the total number of transitions is 15. To summarize—an ordering is error-rate optimal if and only if its total number of transitions over all bit positions is equal to the number of states of the cell minus one.
  • It is interesting to note that the above error rate optimality condition is equivalent to performance optimality criterion A, the minimization of the number of comparisons for sequentially reading all bits in a cell using static reading. Any ordering that is optimal according to that criterion is also optimal according to the bit error rate criterion, and vice versa.
  • From Appendix A one can see there are only two valid orderings that are error-rate optimal for a 3-bit MBC: {7,6,4,5,1,0,2,3} and {7,6,4,5,1,3,2,0}. For the 4-bit MBC case one can see by complete enumeration of all valid orderings that there are 36 valid orderings that are error-rate optimal, as listed in Appendix B.
  • We showed above that the 4-bit ordering of {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1} is optimal for bit errors reduction. If we take 15 cells of 4 bits each using that ordering and cause each one of them to exhibit one of the 15 possible state errors (for this purpose we consider errors of crossing the same boundary between states to be the same, regardless if the crossing is left-to-right or right-to-left), the total number of bit errors in all cells will be 15, which is the lowest number possible.
  • Let us look at which bit positions (out of the 4 bit positions of the cells) these 15 bit errors appear. We already listed above which one of the 4 bits of the cell is affected upon each of the state errors. We see that the lowest bit suffers an error in 6 of the cases, the second lowest bit in 5 of the cases, the second highest bit in 3 of the cases, and the highest bit in one case. This means that the distribution of the bit errors between the bit positions is not even, so that some bit positions encounter many more errors than others.
  • Consider the case in which each bit position of a 4-bit MBC belongs to a different logical page. Suppose the flash memory architecture is based on groups of 15,000 cells each storing 4 bits, so each group stores 4 pages of 15,000 bits. Suppose further that the probability of a state error is 1 in 1,000, that is—on average one cell out of each 1,000 cells will be read in an incorrect state. If the ordering used is error-rate optimal, each state error generates exactly one bit error and therefore the bit error rate is also 1 per 1,000 cells and there will be on average 15 bit errors when reading the full group. However, the distribution of those 15 bit errors is not even—instead of each of the 4 pages including 15/4=3.75 errors on average, we have one page with 15*6/15=6 errors, one page with 15*5/15=5 errors, one page with 15*3/15=3 errors, and one page with 15*1/15=1 error (again, we assume here all state errors are equally likely to occur).
  • At first thought one might say this uneven distribution is not important—after all why should we care where are the errors located if their total number is the same. But suppose that we have to design Error Correction Code (ECC) circuitry for correcting the errors in the data read from the flash memory. As a page is the unit of data that is read at one time, the correction circuitry should be designed to handle one page at a time. If the errors were distributed evenly among the pages residing in the same cells then the expected error rate when reading each single page (specified in bit errors per bits read) would be the same as the expected error rate calculated over the 4 pages together. In the above example this results in 3.75 bit errors per each page of 15,000 bits. But if the errors are distributed as in the {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1} ordering, we have different error rates for different pages: one page with an average of 6 errors, one page with an average of 5 errors, one page with an average of 3 errors, and one page with an average of 1 error.
  • The expected average of bit errors is a most crucial factor in the design of ECC circuitry. The larger the number of expected errors, the more redundancy is needed for storing extra parity or check bits, and the more complex is the circuitry for both encoding and decoding the stored bits. When working with relatively high error rates (1 per 1,000 and higher) the dependency of ECC complexity and redundancy cost, on the error rate is quite significant, and it is highly advantageous if one can somehow reduce the bit error rate one has to protect against. Therefore, from the ECC design point of view the two cases of even and uneven errors distribution among the pages are very much different. In the even case the design has to protect against an expected average number of 3.75 errors per page, while in the uneven case the design must protect against an expected average number of 6 errors per page, which is a much more difficult and costly task.
  • The bottom line of all this is that while the error-rate optimal ordering {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1} is an optimal ordering when looking at the total number of errors, it is not optimal when looking at each page separately. In order to satisfy both optimality criteria we need to find a valid ordering that satisfies the following two conditions:
      • a. The total number of transitions is the lowest possible. In other words, the ordering is error-rate optimal.
      • b. Those transitions are evenly spread over the different bit positions.
  • For the 3-bit MBC case the minimal number of transitions is 7. Unfortunately 7 is not divisible by 3, so there is no way to achieve an optimal overall error rate with completely even distribution. The best we can hope for is an ordering with one bit having 3 transitions and the other two bits having two transitions each.
  • For the 4-bit MBC case the minimal number of transitions is 15. Unfortunately 15 is not divisible by 4, so there is no way to achieve an optimal overall error rate with completely even distribution. The best we can hope for is an ordering with one bit having 3 transitions and the other 3 bits having 4 transitions each. Returning to our previous example, such ordering will result in one page having 3 errors and 3 pages having 4 errors, as compared with overall average of 3.75 errors per page.
  • We define an ordering to be “evenly distributed” if the ordering results in the number of transitions of any bit position being different from the number of transitions of any other bit position by no more than one transition.
  • Appendix A lists all valid orderings of the 3-bit MBC case. We already mentioned above only two of these orderings are error-rate optimal. However we find out neither of these two satisfies the even distribution requirement. {7,6,4,5,1,0,2,3} has a distribution of (4,2,1) transitions, while {7,6,4,5,1,3,2,0} has a distribution of (3,3,1) transitions.
  • Appendix B lists all valid 4-bit orderings that are error-rate optimal. There are 36 of those. Again we realize none of them is evenly distributed, or even close to evenly distributed. The most evenly distributed orderings have a distribution of (5,5,4,1) transitions, and this is very far from our goal.
  • One could wonder why we can't find an ordering that has the minimal number of transitions but is more evenly distributed. Indeed, Appendix F lists some 3-bit orderings which have a (3,2,2) distribution. Appendix G lists some 4-bit orderings which have a (4,4,4,3) distribution. However, not a single one of these evenly-distributed orderings is valid, and therefore none of them can be used for representing bit encodings in the MBC. Recalling from above, a non-valid ordering is one in which there are cases in which a bit cannot be written because writing the bit would require moving the cell's threshold to the left (i.e. lowering the threshold voltage), which is not possible.
  • For example, the 4-bit ordering {15,11,3,1,0,2,6,14,10,8,9,13,12,4,5,7} is shown in Appendix G to have a distribution of (4,4,4,3). However, suppose we have to write a value of “0000” into a cell, one bit at a time. In order to achieve this, we first have to program the lowest bit (getting to an intermediate value of “1110”=“14”), then program the second lowest bit (getting to an intermediate value of “1100”=“12”), then program the second highest bit (getting to an intermediate value of “1000”=“8”), and then finally program the highest bit and get to our desired value of “0000”. In the third stage of this sequence the cell should move from state “12” to state “8”. In the last stage of this sequence the cell should move from state “8” to state “0”. But state 12 lies to the right of state 8 and state 8 lies to the right of state 0 in this ordering, so these changes of state are impossible to do.
  • So we see we are facing a dilemma. On the one hand we wish to use an ordering that is both error-rate optimal and evenly distributed, while on the other hand we need to use a valid ordering, and there is no ordering satisfying both requirements.
  • The following aspect of the present invention allows us to achieve the goals of error-optimal and even distribution without violating the validity requirement imposed by the cell's physical method of operation. The solution is based upon a distinction to be made between the physical representation of the bits in the cells and their logical meaning as interpreted by the user of the data. The validity restriction is imposed by the physical level, while the error rate restriction is imposed by the logical level. Therefore we solve the seemingly contradictory requirements by using a different ordering at the logical level than at the physical level.
  • When physically storing the bits into the cells (physical level) we use an ordering that is valid and is also error-rate optimal, but is not necessarily evenly distributed. When inputting and outputting data to/from the flash memory (logical level) we use an ordering that is evenly distributed and also error-rate optimal, but is not necessarily valid. We establish a one-to-one mapping between the two orderings and switch between them before accessing the cells for writing or after accessing the cells for reading.
  • The method is best understood with reference to a specific example. Assume we choose {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1} as our physical-level ordering and {15,11,3,1,0,2,6,14,10,8,9,13,12,4,5,7} as our logical-level ordering. The following table shows the correspondence between the two levels, and is used as a translation table for both writing and reading, as will be explained below. The left column of the table lists each of the physical states the cell can be in, starting from the left-most state number 15 (representing the erased state) up to the right-most state number 0 having the highest threshold voltage. Actually this column is not required for using the table, but is shown for clarity. The center column of the table is titled “Logical level interpretation” and shows how the logical level ordering is matched to the physical states of the cell. The right column of the table is titled “Physical level interpretation” and shows how the physical level ordering is matched to the physical states of the cell.
    Physical state Logical level interpretation Physical level interpretation
    15 15 15
    14 11 14
    13 3 12
    12 1 13
    11 0 9
    10 2 8
    9 6 10
    8 14 11
    7 10 3
    6 8 2
    5 9 0
    4 13 4
    3 12 6
    2 4 7
    1 5 5
    0 7 1
  • Let us see what can be learned from studying the table. If a cell is in the right-most (highest threshold voltage) state 0, then we are to look at the last row in the table corresponding to physical state number 0. We see there that the logical level interpretation of this physical state is “7”=“0111”, and therefore such a cell contains data which to the user of the storage system means “0111”. The physical level interpretation of that same state is shown in the table to be “1”=“0001”, and this is what the physical layer has to write into the cell in order to guarantee the writing can be completed without violating the validity conditions.
  • Returning now to the drawings, FIG. 5 is a flowchart of writing to a cell according to this aspect of the present invention. Suppose the user of the storage system requests to write the bits “0111”=“7” into a cell (block 10). Locate the value 7 in the center (“logical”) column of the table (block 12). Move to the right (“physical”) column of the same row, and find the corresponding physical level interpretation (“0001”=“1” in this example) (block 14). This is what is actually written into the cell (block 16). It should be understood that the physical mechanism of the cells is designed to work according to the physical level ordering shown in the right column of the table. So instructing the physical writing mechanism to write a “1” results in the cell being brought to the rightmost state. By identifying the sequence of the 15-13-9-1 branch of FIG. 4 in the right column of the table, we see that the intermediate states on the way to the rightmost state are the fourth state from the left when the second lowest bit is programmed and the fifth state from the left when the second highest bit is programmed. Programming the highest bit puts the cell in the rightmost state.
  • FIG. 6 is a flowchart of reading a cell according to this aspect of the present invention. Suppose the user of the storage system requests to read the cell written above (block 20). Doing the reading at the physical level returns a value of “1”. Locate this value in the right column of the table (block 22). Move to the center column of the same row, and find the corresponding logical level interpretation (“0111”=“7” in this example) (block 24). This is what is returned to the user (block 26), and indeed this is what the user had previously stored in that cell.
  • The advantage of this dual-level system is seen when we consider the example that was used above to demonstrate the difficulty with the logical level ordering: writing a value of “0” that required an intermediate step of writing “8” which was impossible to do because it required reducing the cell's threshold voltage from the threshold voltage of the state that represented “12”. Using the dual-level method writing a logical value of “0” is translated into writing a “9” at the physical level, and as the physical level ordering is valid, there will be no difficulty in writing this value (or indeed any other value) into the cell. Indeed, as seen in FIG. 4, programming an initially erased cell to contain “9” passes only through the intermediate value of “13”, and “13” is to the left of “9” in the physical level ordering.
  • In order to employ the methods of this aspect of the present invention there is a need to have a translation stage carried out in both writing and reading. It is possible in principle to have this translation carried out by software, where the software is executed by a host computer (where the flash memory is controlled directly by the host) or by a stand-alone controller (where the flash memory is controlled by a controller in the flash device that serves as the interface for the host). FIG. 7 is a high-level block diagram of a system 30 according to the first case. FIG. 8 is a high-level block diagram of a system 40 according to the second case.
  • In system 30, a host computer 32 executes flash management software 34 to manage the flash memory of a flash memory device 38. Flash management software 34 includes a translation module 36 for translating between logical level ordering and physical level ordering as illustrated in FIGS. 5 and 6.
  • In system 40, a host computer 42 sends read and write instructions to a flash memory device 52. Flash memory device 52 uses a flash controller 44 to manage a flash memory 50 by executing flash management software 46. Flash management software 46 includes a translation module 48 for translating between logical level ordering and physical level ordering as illustrated in FIGS. 5 and 6.
  • Implementing the translation in software is inefficient, especially when taking into account that the translation has to be applied to each and every cell that is to be written or read. Therefore it is better to have the translation performed in hardware, either within a stand-alone controller die or within the same die as the flash cells. FIG. 9 is a high-level block diagram of a system 60 according to the first case. FIGS. 10 and 11 are high-level block diagrams of a system 80 and of a system 100 according to the second case.
  • In system 60, a host computer 62 sends read and write instructions to a flash memory device 72. Flash memory device 72 uses a flash controller 64 to manage a flash memory 70 by executing flash management software 66. When flash controller 64 writes to flash memory 70, logical level ordering generated by flash management software 66 is translated to physical level ordering by translation hardware 68 in flash controller 64 as illustrated in FIG. 5. When flash controller 64 reads from flash memory 70, physical level ordering received from flash memory 70 is translated to logical level ordering by translation hardware 68 as illustrated in FIG. 6.
  • In system 80, a host computer 82 sends read and write instructions to a flash memory device 92. Flash memory device 92 uses a flash controller 84 to manage a flash memory 90 by executing flash management software 86. When flash controller 84 writes to flash memory 90, flash memory 90 receives logical level ordering from flash controller 84 and translation hardware 88 in flash memory 90 translates the logical level ordering to physical level ordering as illustrated in FIG. 5. When flash controller 84 reads from flash memory 90, translation hardware 88 translates the physical level ordering of flash memory 90 to logical level ordering for presentation to flash controller 84, as illustrated in FIG. 6.
  • In system 100, a host computer 82 executes flash management software 104 to manage a flash memory device 110. Host computer 102 reads and writes flash memory device 110 according to logical level ordering. When host computer 102 writes to flash memory device 110, translation hardware 106 in a flash memory 108 of flash memory device 110 translates the logical level ordering to physical level ordering as in FIG. 5. When host computer 102 reads from flash memory device 110, translation hardware 106 translates the physical level ordering of flash memory 108 to logical level ordering for presentation to host computer 102 as illustrated in FIG. 6.
  • It should be understood that no matter what system architecture is chosen, the translation requires all the data bits, that are targeted to the cells to be written, to be available before the writing operation begins. This is so because in order to know which row in the translation table we are in we need all the bits of the logical data. This means that if for example we implement a 4-bit MBC using the methods of this invention, the host should have all 4 logical pages that will eventually reside in the same group of cells to be available before programming can start. Then the data of any one of the 4 pages is viewed as one row in a 4-rows table, and then each 4-bit column of the table serves as an input to the translation process described above. The following is an example of such a table, for K cells:
    Lowest page 0 1 0 . . . 1 1 1
    2nd lowest page 1 1 0 . . . 1 1 0
    2nd highest page 1 0 0 . . . 1 0 0
    Highest page 0 0 1 . . . 0 1 0
    Cell # 0 1 2 . . . K − 3 K − 2 K − 1
  • Cell #0 stores a binary 6, cell # 1 stores a binary 3, cell # 2 stores a binary 8, etc.
  • In the above discussion we assumed that all state errors are equally likely. That is, a cell is equally likely to be in any of its possible states (meaning we have no prior knowledge of the data to be stored) and also that each of the states is equally reliable and has the same probability of error. It is possible that either one (or both) of these assumptions is not true. In such case the optimal ordering is not necessarily the one providing even spread of transitions across the bits, as not all transitions are equally likely to occur. The same principles as discussed above are also applicable to that case. The optimal ordering to use in the logical level is one in which the overall probability of having a transition in any bit position is the same, or as close to this as possible. Such an ordering is called herein an ordering that evenly distributes the error probabilities of the bits, or equivalently, that provides an even distribution of the error probabilities of the bits, given the probability distributions of the data bits and of the state errors. Note that an ordering that evenly distributes the error probabilities of the bits is not necessarily an “evenly distributed” ordering, as defined above, although as we have seen if the data bits and the state errors are uniformly distributed then an evenly distributed ordering does distribute the error probabilities evenly. If the ordering resulting from this optimality criteria is valid, it can be used as the only ordering at all levels, with no translation needed. For example, in the above example of an error-rate optimal M=4 bit ordering, {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1}, suppose that the state transition error probabilities are as in the following table:
    State transition Error probability
    i .00005
    ii .00006
    iii .00005
    iv .0001
    v .00005
    vi .00006
    vii .00005
    viii .0003
    ix .00005
    x .00006
    xi .0001
    xii .00006
    xiii .00005
    xiv .00006
    xv .0001

    Assume further that all data bits are equally probable. If these probabilities are applied to the above 15,000 cell example, each page has on the average 0.0003×15,000=4.5 errors. For example, the average number of errors in the logical page to which the lowest bit is assigned is 15,000 times the sum of the transition error probabilities of the transitions that change the lowest bit. There are six such transitions: transitions i, iii, v, vii, ix and xiii. Each of these transitions has an error probability of 0.00005. So the average number of errors in the page that stores the lowest bit is 6×0.00005×15,000=4.5 errors. So in this case the {15,14,12,13,9,8,10,11,3,2,0,4,6,7,5,1} bit ordering is valid and error-rate optimal and also distributes the bit error probabilities evenly, and no translation is needed. However, such optimal ordering may be found to be non-valid and therefore not possible to use at the physical cells level. In that case we use a translation that maps the logical bit pattern to be stored in a cell into a physical bit pattern that is the one actually written into the cell and that represents a valid ordering, thus achieving a better spread of bit error probability across the different bit positions while not violating the restrictions of the physical cells implementation.
  • While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made.

Claims (42)

1. A method of storing N bits of data, comprising the steps of:
(a) providing ┌N/M┐ cells, wherein M is at least 3; and
(b) programming each cell with up to M of the bits according to a valid physical bit ordering, and according to a logical bit ordering that is different from said physical bit ordering and that distributes error probabilities of said up to M bits more evenly than said physical bit ordering.
2. The method of claim 1, wherein said programming includes, for each cell, translating said up to M bits, as listed in said logical bit ordering, into a corresponding entry in said physical bit ordering.
3. The method of claim 1, further comprising the step of:
(c) reading said N bits from said cells.
4. The method of claim 3, wherein said reading includes, for each cell, translating an entry, in said physical bit ordering, that corresponds to a state of said each cell, into a corresponding entry in said logical bit ordering.
5. The method of claim 1, wherein said logical bit ordering substantially equalizes probability-weighted numbers of transitions of all said up to M bits.
6. The method of claim 1, wherein both said physical bit ordering and said logical bit ordering have a total number of transitions equal to 2M−1.
7. The method of claim 6, wherein M=3 and wherein both said physical bit ordering and said logical bit ordering have 7 transitions.
8. The method of claim 7, wherein said physical bit ordering is one of {7,6,4,5,1,0,2,3} and {7,6,4,5,1,3,2,0}.
9. The method of claim 6, wherein M=4 and wherein both said physical bit ordering and said logical bit ordering have 15 transitions.
10. The method of claim 6, wherein said logical bit ordering is evenly distributed.
11. The method of claim 10, wherein M=4, wherein a number of transitions of any bit of said logical bit ordering is selected from the group consisting of 3 and 4.
12. The method of claim 1, wherein said physical bit ordering is nonserial.
13. A memory device comprising:
(a) a memory that includes K cells; and
(b) a controller operative to store N bits of data in said cells by programming each said cell with up to M=┌N/K┐ of said bits according to a valid physical bit ordering, and according to a logical bit ordering that is different from said physical bit ordering and that distributes error probabilities of said up to M bits more evenly than said physical bit ordering, wherein M is at least 3.
14. The memory device of claim 13, wherein said controller includes a mechanism for translating between said physical bit ordering and said logical bit ordering.
15. The memory device of claim 14, wherein said mechanism effects said translating by executing software.
16. The memory device of claim 14, wherein said controller includes dedicated hardware for effecting said translating.
17. The memory device of claim 13, wherein said memory includes dedicated hardware for translating between said physical bit ordering and said logical bit ordering.
18. The memory device of claim 13, wherein said memory is a flash memory.
19. The memory device of claim 13, wherein said physical bit ordering is nonserial.
20. A system for storing data, comprising:
(a) a memory device that includes a memory, said memory including K cells;
(b) a host of said memory device, for providing N bits of data to store; and
(c) a mechanism for translating, for each said cell, up to M=┌N/K┐ of said bits, as listed in a logical bit ordering, into a corresponding entry in a valid physical bit ordering that is different from said logical bit ordering, wherein M is at least 3, said each cell then being programmed according to said entry in said physical bit ordering, said logical bit ordering distributing error probabilities of said up to M bits more evenly than said physical bit ordering.
21. The system of claim 20, wherein said mechanism effects said translating by executing software.
22. The system of claim 21, wherein said mechanism is included in said host.
23. The system of claim 21, wherein said mechanism is included in a controller of said memory, said controller being included in said memory device.
24. The system of claim 20, wherein said mechanism includes dedicated hardware for effecting said translating.
25. The system of claim 24, wherein said mechanism is included in said memory.
26. The system of claim 24, wherein said mechanism is included in a controller of said memory, said controller being included in said memory device.
27. The system of claim 20, wherein said memory is a flash memory.
28. The system of claim 20, wherein said physical bit ordering is nonserial.
29. A method of storing N bits of data, comprising the steps of:
(a) providing ┌N/M┐ cells, wherein M is at least 3; and
(b) programming each cell with up to M of the bits according to a valid physical bit ordering, and according to an evenly distributed logical bit ordering that is different from said physical bit ordering.
30. A memory device comprising:
(a) a memory that includes K cells; and
(b) a controller operative to store N bits of data in said cells by programming each said cell with up to M==┌N/K┐ of said bits according to a valid physical bit ordering, and according to an evenly distributed logical bit ordering, wherein M is at least 3.
31. A system for storing data, comprising:
(a) a memory device that includes a memory, said memory including K cells;
(b) a host of said memory device, for providing N bits of data to store; and
(c) a mechanism for translating, for each said cell, up to M=┌N/K┐ of said bits, as listed in an evenly distributed logical bit ordering, into a corresponding entry in a valid physical bit ordering that is different from said logical bit ordering, wherein M is at least 3, said each cell then being programmed according to said entry in said physical bit ordering.
32. A method of storing N bits of data, comprising the steps of:
(a) providing ┌N/M┐ cells, wherein M is at least 3; and
(b) programming each cell with up to M of the bits according to a valid, nonserial bit ordering that distributes error probabilities of all said up to M bits substantially evenly.
33. A memory device comprising:
(a) a memory that includes K cells; and
(b) a controller operative to store N bits of data in said cells by programming each said cell with up to M=┌N/K┐ of said bits according to a valid, nonserial bit ordering that distributes error probabilities of all said up to M bits substantially evenly, wherein M is at least 3.
34. A method of of storing N bits of data, comprising the steps of:
(a) providing ┌N/M┐ cells, wherein M is at least 3; and
(b) programming each cell with up to M of the bits according to a valid, nonserial, error-rate-optimal bit ordering.
35. The method of claim 34, wherein a total number of transitions in said bit ordering is a minimum said number of transitions.
36. The method of claim 34, wherein said bit ordering has a total number of transitions equal to 2M−1.
37. The method of claim 36, wherein M=3 and wherein said bit ordering has seven said transitions.
38. The method of claim 37, wherein said bit ordering is selected from the group consisting of {7,6,4,5,1,0,2,3} and {7,6,4,5,1,3,2,0}.
39. The method of claim 36, wherein M=4 and wherein said bit ordering has fifteen said transitions.
40. The method of claim 34, wherein said bit ordering is evenly distributed.
41. The method of claim 40, wherien M=4 and wherein each bit of said bit ordering has at least three transitions and at most four transitions.
42. A memory device comprising:
(a) a memory that includes K cells; and
(b) a controller operative to store N bits of data in said cells by programming each cell with up to M=┌N/K┐ of said bits according to a valid, nonserial, error-rate-optimal bit ordering, wherein M is at least 3.
US11/061,634 2004-03-14 2005-02-22 States encoding in multi-bit flash cells for optimizing error rate Abandoned US20050213393A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US11/061,634 US20050213393A1 (en) 2004-03-14 2005-02-22 States encoding in multi-bit flash cells for optimizing error rate
PCT/IL2005/001001 WO2006033099A2 (en) 2004-09-22 2005-09-19 States encoding in multi-bit flash cells for optimizing error rate
KR1020077006271A KR20070054659A (en) 2004-09-22 2005-09-19 States encoding in multi-bit flash cells for optimizing error rate
US11/923,725 US8055972B2 (en) 2004-03-14 2007-10-25 States encoding in multi-bit flash cells for optimizing error rate
US13/243,836 US8245099B2 (en) 2004-03-14 2011-09-23 States encoding in multi-bit flash cells for optimizing error rate

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US55379804P 2004-03-14 2004-03-14
US61187304P 2004-09-22 2004-09-22
US11/035,807 US7310347B2 (en) 2004-03-14 2005-01-18 States encoding in multi-bit flash cells
US11/061,634 US20050213393A1 (en) 2004-03-14 2005-02-22 States encoding in multi-bit flash cells for optimizing error rate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/035,807 Continuation-In-Part US7310347B2 (en) 2004-03-14 2005-01-18 States encoding in multi-bit flash cells

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/923,725 Continuation US8055972B2 (en) 2004-03-14 2007-10-25 States encoding in multi-bit flash cells for optimizing error rate

Publications (1)

Publication Number Publication Date
US20050213393A1 true US20050213393A1 (en) 2005-09-29

Family

ID=36090394

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/061,634 Abandoned US20050213393A1 (en) 2004-03-14 2005-02-22 States encoding in multi-bit flash cells for optimizing error rate
US11/923,725 Active 2027-10-16 US8055972B2 (en) 2004-03-14 2007-10-25 States encoding in multi-bit flash cells for optimizing error rate
US13/243,836 Active US8245099B2 (en) 2004-03-14 2011-09-23 States encoding in multi-bit flash cells for optimizing error rate

Family Applications After (2)

Application Number Title Priority Date Filing Date
US11/923,725 Active 2027-10-16 US8055972B2 (en) 2004-03-14 2007-10-25 States encoding in multi-bit flash cells for optimizing error rate
US13/243,836 Active US8245099B2 (en) 2004-03-14 2011-09-23 States encoding in multi-bit flash cells for optimizing error rate

Country Status (3)

Country Link
US (3) US20050213393A1 (en)
KR (1) KR20070054659A (en)
WO (1) WO2006033099A2 (en)

Cited By (207)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060251386A1 (en) * 2005-04-15 2006-11-09 Sony Corporation Data processing apparatus, data reproduction apparatus, data processing method and data processing program
US20070086239A1 (en) * 2005-10-17 2007-04-19 M-Systems Flash Disk Pioneers, Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US20070266296A1 (en) * 2006-05-15 2007-11-15 Conley Kevin M Nonvolatile Memory with Convolutional Coding
US20070266295A1 (en) * 2006-05-15 2007-11-15 Conley Kevin M Convolutional Coding Methods for Nonvolatile Memory
US20080082897A1 (en) * 2006-09-28 2008-04-03 Yigal Brandman Soft-Input Soft-Output Decoder for Nonvolatile Memory
US20080092026A1 (en) * 2006-09-28 2008-04-17 Yigal Brandman Methods of Soft-Input Soft-Output Decoding for Nonvolatile Memory
US20080092015A1 (en) * 2006-09-28 2008-04-17 Yigal Brandman Nonvolatile memory with adaptive operation
US20080109703A1 (en) * 2006-11-03 2008-05-08 Yigal Brandman Nonvolatile Memory With Modulated Error Correction Coding
US20080123419A1 (en) * 2006-11-03 2008-05-29 Yigal Brandman Methods of Varying Read Threshold Voltage in Nonvolatile Memory
US20080123420A1 (en) * 2006-11-03 2008-05-29 Yigal Brandman Nonvolatile Memory With Variable Read Threshold
US20080151618A1 (en) * 2006-12-24 2008-06-26 Sandisk Il Ltd. Flash memory device and system with randomizing for suppressing errors
US20080158948A1 (en) * 2006-12-31 2008-07-03 Sandisk Il Ltd. Avoiding errors in a flash memory by using substitution transformations
US20080158951A1 (en) * 2006-12-28 2008-07-03 Micron Technology, Inc. Non-volatile multilevel memory cell programming
US20080177934A1 (en) * 2007-01-24 2008-07-24 Samsung Electronics. Co., Ltd. Memory systems having a multilevel cell flash memory and programming methods thereof
EP1952290A2 (en) * 2005-10-17 2008-08-06 Ramot at Tel-Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US20080215798A1 (en) * 2006-12-24 2008-09-04 Sandisk Il Ltd. Randomizing for suppressing errors in a flash memory
US20090070657A1 (en) * 2005-10-13 2009-03-12 Ramot At Tel Aviv University Ltd. Method of error correction in mbc flash memory
US20090109746A1 (en) * 2007-10-31 2009-04-30 Micron Technology, Inc. Memory cell programming
US20090182934A1 (en) * 2008-01-14 2009-07-16 Samsung Electronics Co., Ltd. Memory device and method of multi-bit programming
US20090204824A1 (en) * 2007-12-31 2009-08-13 Lin Jason T System, method and memory device providing data scrambling compatible with on-chip copy operation
US20090279362A1 (en) * 2008-05-09 2009-11-12 Ori Stern Partial scrambling to reduce correlation
US7697326B2 (en) 2006-05-12 2010-04-13 Anobit Technologies Ltd. Reducing programming error in memory devices
US7751240B2 (en) 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
US7805663B2 (en) 2006-09-28 2010-09-28 Sandisk Corporation Methods of adapting operation of nonvolatile memory
US7821826B2 (en) 2006-10-30 2010-10-26 Anobit Technologies, Ltd. Memory cell readout using successive approximation
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
US20110007573A1 (en) * 2008-06-27 2011-01-13 Idan Alrod Gain control for read operations in flash memory
US7900102B2 (en) 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US7904780B2 (en) 2006-11-03 2011-03-08 Sandisk Corporation Methods of modulating error correction coding
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US7924587B2 (en) 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
WO2011062917A1 (en) * 2009-11-20 2011-05-26 Sandisk Corporation Data coding for improved ecc eddiciency in a nonvolatile storage system
WO2011075572A1 (en) 2009-12-18 2011-06-23 Sandisk Corporation Maintaining updates of multi-level non-volatile memory in binary non-volatile memory
WO2011075594A1 (en) 2009-12-18 2011-06-23 Sandisk Corporation Non-volatile memory with multi-gear control using on-chip folding of data
WO2011075597A1 (en) 2009-12-18 2011-06-23 Sandisk Corporation Data transfer flows for on-chip folding
US7975192B2 (en) 2006-10-30 2011-07-05 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
US7995388B1 (en) 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
US8001320B2 (en) 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8010755B2 (en) 2004-11-08 2011-08-30 Sandisk Il Ltd States encoding in multi-bit flash cells for optimizing error rate
US8027195B2 (en) 2009-06-05 2011-09-27 SanDisk Technologies, Inc. Folding data stored in binary format into multi-state format within non-volatile memory devices
US8050086B2 (en) 2006-05-12 2011-11-01 Anobit Technologies Ltd. Distortion estimation and cancellation in memory devices
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8060806B2 (en) 2006-08-27 2011-11-15 Anobit Technologies Ltd. Estimation of non-linear distortion in memory devices
US8068360B2 (en) 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8085586B2 (en) 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
WO2012009318A1 (en) 2010-07-13 2012-01-19 Sandisk Technologies Inc. Dynamic optimization of back-end memory system interface
US8102705B2 (en) 2009-06-05 2012-01-24 Sandisk Technologies Inc. Structure and method for shuffling data within non-volatile memory devices
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
US8151163B2 (en) 2006-12-03 2012-04-03 Anobit Technologies Ltd. Automatic defect management in memory devices
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US8156403B2 (en) 2006-05-12 2012-04-10 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8239735B2 (en) 2006-05-12 2012-08-07 Apple Inc. Memory Device with adaptive capacity
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8261159B1 (en) 2008-10-30 2012-09-04 Apple, Inc. Data scrambling schemes for memory devices
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8270246B2 (en) 2007-11-13 2012-09-18 Apple Inc. Optimized selection of memory chips in multi-chips memory devices
US8276051B2 (en) 2007-12-12 2012-09-25 Densbits Technologies Ltd. Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications
US8305812B2 (en) 2009-08-26 2012-11-06 Densbits Technologies Ltd. Flash memory module and method for programming a page of flash memory cells
US8321625B2 (en) 2007-12-05 2012-11-27 Densbits Technologies Ltd. Flash memory device with physical cell value deterioration accommodation and methods useful in conjunction therewith
US8327246B2 (en) 2007-12-18 2012-12-04 Densbits Technologies Ltd. Apparatus for coding at a plurality of rates in multi-level flash memory systems, and methods useful in conjunction therewith
US8332725B2 (en) 2008-08-20 2012-12-11 Densbits Technologies Ltd. Reprogramming non volatile memory portions
US8335977B2 (en) 2007-12-05 2012-12-18 Densbits Technologies Ltd. Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
US8341502B2 (en) 2010-02-28 2012-12-25 Densbits Technologies Ltd. System and method for multi-dimensional decoding
US8359516B2 (en) 2007-12-12 2013-01-22 Densbits Technologies Ltd. Systems and methods for error correction and decoding on multi-level physical media
US20130024605A1 (en) * 2011-07-22 2013-01-24 Sandisk Technologies Inc. Systems and methods of storing data
US8365040B2 (en) 2007-09-20 2013-01-29 Densbits Technologies Ltd. Systems and methods for handling immediate data errors in flash memory
WO2013016393A1 (en) 2011-07-28 2013-01-31 Sandisk Technologies Inc. Data recovery for defective word lines during programming of non-volatile memory arrays
US8369141B2 (en) 2007-03-12 2013-02-05 Apple Inc. Adaptive estimation of memory cell read thresholds
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US8417876B2 (en) 2010-06-23 2013-04-09 Sandisk Technologies Inc. Use of guard bands and phased maintenance operations to avoid exceeding maximum latency requirements in non-volatile memory systems
US8429493B2 (en) 2007-05-12 2013-04-23 Apple Inc. Memory device with internal signap processing unit
US8427867B2 (en) * 2007-10-22 2013-04-23 Densbits Technologies Ltd. Systems and methods for averaging error rates in non-volatile devices and storage systems
US8443242B2 (en) 2007-10-25 2013-05-14 Densbits Technologies Ltd. Systems and methods for multiple coding rates in flash devices
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8458574B2 (en) 2009-04-06 2013-06-04 Densbits Technologies Ltd. Compact chien-search based decoding apparatus and method
US8464135B2 (en) 2010-07-13 2013-06-11 Sandisk Technologies Inc. Adaptive flash interface
CN103151069A (en) * 2011-12-06 2013-06-12 三星电子株式会社 Memory systems and block copy methods thereof
US8467249B2 (en) 2010-07-06 2013-06-18 Densbits Technologies Ltd. Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system
US8468431B2 (en) 2010-07-01 2013-06-18 Densbits Technologies Ltd. System and method for multi-dimensional encoding and decoding
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8508995B2 (en) 2010-09-15 2013-08-13 Densbits Technologies Ltd. System and method for adjusting read voltage thresholds in memories
US8516274B2 (en) 2010-04-06 2013-08-20 Densbits Technologies Ltd. Method, system and medium for analog encryption in a flash memory
US8527840B2 (en) 2010-04-06 2013-09-03 Densbits Technologies Ltd. System and method for restoring damaged data programmed on a flash device
US8527819B2 (en) 2007-10-19 2013-09-03 Apple Inc. Data storage in analog memory cell arrays having erase failures
US8531877B2 (en) 2007-10-31 2013-09-10 Micron Technology, Inc. Fractional bits in memory cells
US8539311B2 (en) 2010-07-01 2013-09-17 Densbits Technologies Ltd. System and method for data recovery in multi-level cell memories
US8553468B2 (en) 2011-09-21 2013-10-08 Densbits Technologies Ltd. System and method for managing erase operations in a non-volatile memory
US8566510B2 (en) 2009-05-12 2013-10-22 Densbits Technologies Ltd. Systems and method for flash memory management
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
US8588003B1 (en) 2011-08-01 2013-11-19 Densbits Technologies Ltd. System, method and computer program product for programming and for recovering from a power failure
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US8607128B2 (en) 2007-12-05 2013-12-10 Densbits Technologies Ltd. Low power chien-search based BCH/RS decoding system for flash memory, mobile communications devices and other applications
US8607124B2 (en) 2009-12-24 2013-12-10 Densbits Technologies Ltd. System and method for setting a flash memory cell read threshold
US8611152B2 (en) 2007-10-31 2013-12-17 Micron Technology, Inc. Non-volatile multilevel memory cells
US8626988B2 (en) 2009-11-19 2014-01-07 Densbits Technologies Ltd. System and method for uncoded bit error rate equalization via interleaving
US8645794B1 (en) 2010-07-31 2014-02-04 Apple Inc. Data storage in analog memory cells using a non-integer number of bits per cell
US8650352B2 (en) 2007-09-20 2014-02-11 Densbits Technologies Ltd. Systems and methods for determining logical values of coupled flash memory cells
US8667211B2 (en) 2011-06-01 2014-03-04 Densbits Technologies Ltd. System and method for managing a non-volatile memory
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8683147B2 (en) 2008-07-09 2014-03-25 Phison Electronics Corp. Data accessing method for flash memory storage device having data perturbation module, and storage system and controller using the same
US8681548B2 (en) 2012-05-03 2014-03-25 Sandisk Technologies Inc. Column redundancy circuitry for non-volatile memory
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US8693258B2 (en) 2011-03-17 2014-04-08 Densbits Technologies Ltd. Obtaining soft information using a hard interface
US8694715B2 (en) 2007-10-22 2014-04-08 Densbits Technologies Ltd. Methods for adaptively programming flash memory devices and flash memory systems incorporating same
US8711624B2 (en) 2010-09-20 2014-04-29 Samsung Electronics Co., Ltd. Memory device and self interleaving method thereof
US8711625B2 (en) 2009-07-06 2014-04-29 Sandisk Technologies Inc. Bad column management with bit information in non-volatile memory systems
US8725935B2 (en) 2009-12-18 2014-05-13 Sandisk Technologies Inc. Balanced performance for on-chip folding of non-volatile memories
US8724387B2 (en) 2009-10-22 2014-05-13 Densbits Technologies Ltd. Method, system, and computer readable medium for reading and programming flash memory cells using multiple bias voltages
US8730729B2 (en) 2009-10-15 2014-05-20 Densbits Technologies Ltd. Systems and methods for averaging error rates in non-volatile devices and storage systems
US8745317B2 (en) 2010-04-07 2014-06-03 Densbits Technologies Ltd. System and method for storing information in a multi-level cell memory
US8819385B2 (en) 2009-04-06 2014-08-26 Densbits Technologies Ltd. Device and method for managing a flash memory
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8838937B1 (en) 2012-05-23 2014-09-16 Densbits Technologies Ltd. Methods, systems and computer readable medium for writing and reading data
US20140281820A1 (en) * 2013-03-15 2014-09-18 Idan Alrod Method and system for adaptive setting of verify levels in flash memory
US8842473B2 (en) 2012-03-15 2014-09-23 Sandisk Technologies Inc. Techniques for accessing column selecting shift register with skipped entries in non-volatile memories
US8850100B2 (en) 2010-12-07 2014-09-30 Densbits Technologies Ltd. Interleaving codeword portions between multiple planes and/or dies of a flash memory device
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8868821B2 (en) 2009-08-26 2014-10-21 Densbits Technologies Ltd. Systems and methods for pre-equalization and code design for a flash memory
US8879325B1 (en) 2012-05-30 2014-11-04 Densbits Technologies Ltd. System, method and computer program product for processing read threshold information and for reading a flash memory module
US20140337564A1 (en) * 2011-08-31 2014-11-13 Micron Technology, Inc. Apparatuses and methods of operating for memory endurance
US8897080B2 (en) 2012-09-28 2014-11-25 Sandisk Technologies Inc. Variable rate serial to parallel shift register
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
US8947941B2 (en) 2012-02-09 2015-02-03 Densbits Technologies Ltd. State responsive operations relating to flash memory cells
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8964464B2 (en) 2010-08-24 2015-02-24 Densbits Technologies Ltd. System and method for accelerated sampling
US8972472B2 (en) 2008-03-25 2015-03-03 Densbits Technologies Ltd. Apparatus and methods for hardware-efficient unbiased rounding
US8990665B1 (en) 2011-04-06 2015-03-24 Densbits Technologies Ltd. System, method and computer program product for joint search of a read threshold and soft decoding
US8996788B2 (en) 2012-02-09 2015-03-31 Densbits Technologies Ltd. Configurable flash interface
US8995197B1 (en) 2009-08-26 2015-03-31 Densbits Technologies Ltd. System and methods for dynamic erase and program control for flash memory device memories
US8996793B1 (en) 2012-04-24 2015-03-31 Densbits Technologies Ltd. System, method and computer readable medium for generating soft information
US8996790B1 (en) 2011-05-12 2015-03-31 Densbits Technologies Ltd. System and method for flash memory management
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
US9021177B2 (en) 2010-04-29 2015-04-28 Densbits Technologies Ltd. System and method for allocating and using spare blocks in a flash memory
US9037777B2 (en) 2009-12-22 2015-05-19 Densbits Technologies Ltd. Device, system, and method for reducing program/read disturb in flash arrays
US9063878B2 (en) 2010-11-03 2015-06-23 Densbits Technologies Ltd. Method, system and computer readable medium for copy back
US9069659B1 (en) 2013-01-03 2015-06-30 Densbits Technologies Ltd. Read threshold determination using reference read threshold
US9069688B2 (en) 2011-04-15 2015-06-30 Sandisk Technologies Inc. Dynamic optimization of back-end memory system interface
US9076506B2 (en) 2012-09-28 2015-07-07 Sandisk Technologies Inc. Variable rate parallel to serial shift register
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US9110785B1 (en) 2011-05-12 2015-08-18 Densbits Technologies Ltd. Ordered merge of data sectors that belong to memory space portions
US9117514B2 (en) 2013-06-19 2015-08-25 Sandisk Technologies Inc. Data encoding for non-volatile memory
US9117520B2 (en) 2013-06-19 2015-08-25 Sandisk Technologies Inc. Data encoding for non-volatile memory
US9128623B2 (en) 2011-04-15 2015-09-08 Samsung Electronics Co., Ltd. Non-volatile memory devices, methods of operating non-volatile memory devices, and systems including the same
US9136876B1 (en) 2013-06-13 2015-09-15 Densbits Technologies Ltd. Size limited multi-dimensional decoding
US9195592B1 (en) 2011-05-12 2015-11-24 Densbits Technologies Ltd. Advanced management of a non-volatile memory
US9224502B1 (en) 2015-01-14 2015-12-29 Sandisk Technologies Inc. Techniques for detection and treating memory hole to local interconnect marginality defects
US9269446B1 (en) 2015-04-08 2016-02-23 Sandisk Technologies Inc. Methods to improve programming of slow cells
US20160062907A1 (en) * 2014-09-03 2016-03-03 Apple Inc. Multi-phase programming schemes for nonvolatile memories
US9330767B1 (en) 2009-08-26 2016-05-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Flash memory module and method for programming a page of flash memory cells
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
US9348694B1 (en) 2013-10-09 2016-05-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Detecting and managing bad columns
US9368225B1 (en) 2012-11-21 2016-06-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Determining read thresholds based upon read error direction statistics
US9372792B1 (en) 2011-05-12 2016-06-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Advanced management of a non-volatile memory
US9384128B2 (en) 2014-04-18 2016-07-05 SanDisk Technologies, Inc. Multi-level redundancy code for non-volatile memory controller
US9390008B2 (en) 2013-12-11 2016-07-12 Sandisk Technologies Llc Data encoding for non-volatile memory
US9397706B1 (en) 2013-10-09 2016-07-19 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for irregular multiple dimension decoding and encoding
US9396106B2 (en) 2011-05-12 2016-07-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Advanced management of a non-volatile memory
US9407291B1 (en) 2014-07-03 2016-08-02 Avago Technologies General Ip (Singapore) Pte. Ltd. Parallel encoding method and system
US9413491B1 (en) 2013-10-08 2016-08-09 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for multiple dimension decoding and encoding a message
US9449702B1 (en) 2014-07-08 2016-09-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Power management
US9489299B2 (en) 2013-06-19 2016-11-08 Sandisk Technologies Llc Data encoding for non-volatile memory
US9489300B2 (en) 2013-06-19 2016-11-08 Sandisk Technologies Llc Data encoding for non-volatile memory
US9490035B2 (en) 2012-09-28 2016-11-08 SanDisk Technologies, Inc. Centralized variable rate serializer and deserializer for bad column management
US9489294B2 (en) 2013-06-19 2016-11-08 Sandisk Technologies Llc Data encoding for non-volatile memory
US9501392B1 (en) 2011-05-12 2016-11-22 Avago Technologies General Ip (Singapore) Pte. Ltd. Management of a non-volatile memory module
US9524211B1 (en) 2014-11-18 2016-12-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Codeword management
US9536612B1 (en) 2014-01-23 2017-01-03 Avago Technologies General Ip (Singapore) Pte. Ltd Digital signaling processing for three dimensional flash memory arrays
US9542262B1 (en) 2014-05-29 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Error correction
US9564219B2 (en) 2015-04-08 2017-02-07 Sandisk Technologies Llc Current based detection and recording of memory hole-interconnect spacing defects
US9786388B1 (en) 2013-10-09 2017-10-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Detecting and managing bad columns
US9851921B1 (en) 2015-07-05 2017-12-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Flash memory chip processing
US9892033B1 (en) 2014-06-24 2018-02-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Management of memory units
US9921954B1 (en) 2012-08-27 2018-03-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for split flash memory management between host and storage controller
US9934872B2 (en) 2014-10-30 2018-04-03 Sandisk Technologies Llc Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
US9954558B1 (en) 2016-03-03 2018-04-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Fast decoding of data stored in a flash memory
US9972393B1 (en) 2014-07-03 2018-05-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Accelerating programming of a flash memory module
US10032524B2 (en) 2015-02-09 2018-07-24 Sandisk Technologies Llc Techniques for determining local interconnect defects
US10079068B2 (en) 2011-02-23 2018-09-18 Avago Technologies General Ip (Singapore) Pte. Ltd. Devices and method for wear estimation based memory management
US10120792B1 (en) 2014-01-29 2018-11-06 Avago Technologies General Ip (Singapore) Pte. Ltd. Programming an embedded flash storage device
US10305515B1 (en) 2015-02-02 2019-05-28 Avago Technologies International Sales Pte. Limited System and method for encoding using multiple linear feedback shift registers
US10628255B1 (en) 2015-06-11 2020-04-21 Avago Technologies International Sales Pte. Limited Multi-dimensional decoding
US11507448B2 (en) 2019-04-05 2022-11-22 Samsung Electronics Co., Ltd. Non-volatile memory device, method of operating the device, and memory system including the device
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
EP4202934A1 (en) * 2021-12-24 2023-06-28 Kioxia Corporation Memory device
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7539052B2 (en) 2006-12-28 2009-05-26 Micron Technology, Inc. Non-volatile multilevel memory cell programming
KR101403314B1 (en) 2008-05-23 2014-06-05 삼성전자주식회사 Memory device and method of storing data bit
US8054691B2 (en) 2009-06-26 2011-11-08 Sandisk Technologies Inc. Detecting the completion of programming for non-volatile storage
KR20120137354A (en) 2010-01-28 2012-12-20 샌디스크 아이엘 엘티디 Sliding-window error correction
KR101818443B1 (en) 2011-07-08 2018-01-16 삼성전자주식회사 Memory controller, and Memory system having the memory controller
US8832506B2 (en) 2012-01-20 2014-09-09 International Business Machines Corporation Bit error rate based wear leveling for solid state drive memory
KR102068519B1 (en) 2013-07-01 2020-01-21 삼성전자주식회사 Storage device for enhancing read performance, writing method and reading method thereof
KR102157875B1 (en) 2013-12-19 2020-09-22 삼성전자주식회사 Non-volatile memory device and memory system including the same
US9548107B1 (en) 2015-07-09 2017-01-17 Kabushiki Kaisha Toshiba Semiconductor memory device
KR20170058482A (en) * 2015-11-18 2017-05-29 에스케이하이닉스 주식회사 Memory system and operating method of memory system
KR102451154B1 (en) 2015-12-07 2022-10-06 삼성전자주식회사 Nonvolatile memory device and operating method of nonvolatile memory device
KR102547713B1 (en) * 2016-09-01 2023-06-26 삼성전자주식회사 Semiconductor memory device and method of operating the same
US10878912B1 (en) 2019-08-02 2020-12-29 Kabushiki Kaisha Toshiba Multi-cell modulation for flash memory
US11263079B2 (en) 2020-06-30 2022-03-01 Kabushiki Kaisha Toshiba Endurance modulation for flash storage

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2632058A (en) * 1946-03-22 1953-03-17 Bell Telephone Labor Inc Pulse code communication
US5434825A (en) * 1988-06-08 1995-07-18 Harari; Eliyahou Flash EEPROM system cell array with more than two storage states per memory cell
US6046935A (en) * 1996-03-18 2000-04-04 Kabushiki Kaisha Toshiba Semiconductor device and memory system
US6522580B2 (en) * 2001-06-27 2003-02-18 Sandisk Corporation Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US6529405B2 (en) * 2000-12-30 2003-03-04 Hynix Semiconductor, Inc. Circuit and method for programming and reading multi-level flash memory
US6601211B1 (en) * 1996-10-15 2003-07-29 Micron Technology, Inc. Write reduction in flash memory systems through ECC usage
US6643188B2 (en) * 2001-12-27 2003-11-04 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
US6684289B1 (en) * 2000-11-22 2004-01-27 Sandisk Corporation Techniques for operating non-volatile memory systems with data sectors having different sizes than the sizes of the pages and/or blocks of the memory

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043940A (en) * 1988-06-08 1991-08-27 Eliyahou Harari Flash EEPROM memory systems having multistate storage cells
US5404485A (en) 1993-03-08 1995-04-04 M-Systems Flash Disk Pioneers Ltd. Flash file system
US5673224A (en) * 1996-02-23 1997-09-30 Micron Quantum Devices, Inc. Segmented non-volatile memory array with multiple sources with improved word line control circuitry
WO1997032253A1 (en) 1996-02-29 1997-09-04 Hitachi, Ltd. Semiconductor memory device having faulty cells
US6088261A (en) * 1997-08-12 2000-07-11 Nippon Steel Corporation Semiconductor storage device
US5909449A (en) 1997-09-08 1999-06-01 Invox Technology Multibit-per-cell non-volatile memory with error detection and correction
CN1235343C (en) * 1997-11-10 2006-01-04 Ntt移动通信网株式会社 Interleaving method, interleaving apparatus, and recording medium in which interleave pattern generating program is recorded
US6314026B1 (en) 1999-02-08 2001-11-06 Kabushiki Kaisha Toshiba Nonvolatile semiconductor device using local self boost technique
US6772383B1 (en) * 1999-05-27 2004-08-03 Intel Corporation Combined tag and data ECC for enhanced soft error recovery from cache tag errors
JP4023953B2 (en) 1999-06-22 2007-12-19 株式会社ルネサステクノロジ Nonvolatile semiconductor memory device
US6707713B1 (en) * 2000-03-01 2004-03-16 Advanced Micro Devices, Inc. Interlaced multi-level memory
US6493266B1 (en) 2001-04-09 2002-12-10 Advanced Micro Devices, Inc. Soft program and soft program verify of the core cells in flash memory array
US6847550B2 (en) 2002-10-25 2005-01-25 Nexflash Technologies, Inc. Nonvolatile semiconductor memory having three-level memory cells and program and read mapping circuits therefor
US7020026B2 (en) * 2004-05-05 2006-03-28 Sandisk Corporation Bitline governed approach for program control of non-volatile memory
US7023733B2 (en) * 2004-05-05 2006-04-04 Sandisk Corporation Boosting to control programming of non-volatile memory

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2632058A (en) * 1946-03-22 1953-03-17 Bell Telephone Labor Inc Pulse code communication
US5434825A (en) * 1988-06-08 1995-07-18 Harari; Eliyahou Flash EEPROM system cell array with more than two storage states per memory cell
US6046935A (en) * 1996-03-18 2000-04-04 Kabushiki Kaisha Toshiba Semiconductor device and memory system
US6601211B1 (en) * 1996-10-15 2003-07-29 Micron Technology, Inc. Write reduction in flash memory systems through ECC usage
US6684289B1 (en) * 2000-11-22 2004-01-27 Sandisk Corporation Techniques for operating non-volatile memory systems with data sectors having different sizes than the sizes of the pages and/or blocks of the memory
US6529405B2 (en) * 2000-12-30 2003-03-04 Hynix Semiconductor, Inc. Circuit and method for programming and reading multi-level flash memory
US6522580B2 (en) * 2001-06-27 2003-02-18 Sandisk Corporation Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US6643188B2 (en) * 2001-12-27 2003-11-04 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell

Cited By (293)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8010755B2 (en) 2004-11-08 2011-08-30 Sandisk Il Ltd States encoding in multi-bit flash cells for optimizing error rate
US20060251386A1 (en) * 2005-04-15 2006-11-09 Sony Corporation Data processing apparatus, data reproduction apparatus, data processing method and data processing program
US20090070657A1 (en) * 2005-10-13 2009-03-12 Ramot At Tel Aviv University Ltd. Method of error correction in mbc flash memory
US8261157B2 (en) * 2005-10-13 2012-09-04 Ramot et Tel Aviv University Ltd. Method of error correction in MBC flash memory
EP2287740A1 (en) * 2005-10-13 2011-02-23 Ramot at Tel-Aviv University Ltd. Method of error correction in MBC flash memory
CN101536109A (en) * 2005-10-13 2009-09-16 特拉维夫大学拉莫特有限公司 Method of error correction in MBC flash memory
US9094047B2 (en) 2005-10-17 2015-07-28 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US20090183049A1 (en) * 2005-10-17 2009-07-16 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US8966342B2 (en) 2005-10-17 2015-02-24 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US8990658B2 (en) 2005-10-17 2015-03-24 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
EP1952290A4 (en) * 2005-10-17 2009-11-25 Univ Ramot Probabilistic error correction in multi-bit-per-cell flash memory
US8788909B2 (en) 2005-10-17 2014-07-22 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US20090217131A1 (en) * 2005-10-17 2009-08-27 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US20090327841A1 (en) * 2005-10-17 2009-12-31 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
EP1952290A2 (en) * 2005-10-17 2008-08-06 Ramot at Tel-Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US20070086239A1 (en) * 2005-10-17 2007-04-19 M-Systems Flash Disk Pioneers, Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US8650462B2 (en) 2005-10-17 2014-02-11 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US7526715B2 (en) 2005-10-17 2009-04-28 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US20100005370A1 (en) * 2005-10-17 2010-01-07 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US20100005367A1 (en) * 2005-10-17 2010-01-07 Ramot At Tel Aviv University Ltd. Probabilistic error correction in multi-bit-per-cell flash memory
US8599611B2 (en) 2006-05-12 2013-12-03 Apple Inc. Distortion estimation and cancellation in memory devices
US7697326B2 (en) 2006-05-12 2010-04-13 Anobit Technologies Ltd. Reducing programming error in memory devices
US8156403B2 (en) 2006-05-12 2012-04-10 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US8239735B2 (en) 2006-05-12 2012-08-07 Apple Inc. Memory Device with adaptive capacity
US8570804B2 (en) 2006-05-12 2013-10-29 Apple Inc. Distortion estimation and cancellation in memory devices
US8050086B2 (en) 2006-05-12 2011-11-01 Anobit Technologies Ltd. Distortion estimation and cancellation in memory devices
US20070266296A1 (en) * 2006-05-15 2007-11-15 Conley Kevin M Nonvolatile Memory with Convolutional Coding
US7840875B2 (en) 2006-05-15 2010-11-23 Sandisk Corporation Convolutional coding methods for nonvolatile memory
US20070266295A1 (en) * 2006-05-15 2007-11-15 Conley Kevin M Convolutional Coding Methods for Nonvolatile Memory
US8060806B2 (en) 2006-08-27 2011-11-15 Anobit Technologies Ltd. Estimation of non-linear distortion in memory devices
US7904783B2 (en) 2006-09-28 2011-03-08 Sandisk Corporation Soft-input soft-output decoder for nonvolatile memory
US20080092026A1 (en) * 2006-09-28 2008-04-17 Yigal Brandman Methods of Soft-Input Soft-Output Decoding for Nonvolatile Memory
US20080092015A1 (en) * 2006-09-28 2008-04-17 Yigal Brandman Nonvolatile memory with adaptive operation
US20080082897A1 (en) * 2006-09-28 2008-04-03 Yigal Brandman Soft-Input Soft-Output Decoder for Nonvolatile Memory
US7818653B2 (en) 2006-09-28 2010-10-19 Sandisk Corporation Methods of soft-input soft-output decoding for nonvolatile memory
US7805663B2 (en) 2006-09-28 2010-09-28 Sandisk Corporation Methods of adapting operation of nonvolatile memory
US8145984B2 (en) 2006-10-30 2012-03-27 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
USRE46346E1 (en) 2006-10-30 2017-03-21 Apple Inc. Reading memory cells using multiple thresholds
US7975192B2 (en) 2006-10-30 2011-07-05 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
US7821826B2 (en) 2006-10-30 2010-10-26 Anobit Technologies, Ltd. Memory cell readout using successive approximation
US20080123420A1 (en) * 2006-11-03 2008-05-29 Yigal Brandman Nonvolatile Memory With Variable Read Threshold
US8001441B2 (en) 2006-11-03 2011-08-16 Sandisk Technologies Inc. Nonvolatile memory with modulated error correction coding
US7904780B2 (en) 2006-11-03 2011-03-08 Sandisk Corporation Methods of modulating error correction coding
US20080109703A1 (en) * 2006-11-03 2008-05-08 Yigal Brandman Nonvolatile Memory With Modulated Error Correction Coding
US20080123419A1 (en) * 2006-11-03 2008-05-29 Yigal Brandman Methods of Varying Read Threshold Voltage in Nonvolatile Memory
US7558109B2 (en) 2006-11-03 2009-07-07 Sandisk Corporation Nonvolatile memory with variable read threshold
US7904788B2 (en) 2006-11-03 2011-03-08 Sandisk Corporation Methods of varying read threshold voltage in nonvolatile memory
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
US8151163B2 (en) 2006-12-03 2012-04-03 Anobit Technologies Ltd. Automatic defect management in memory devices
US7900102B2 (en) 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US20080151618A1 (en) * 2006-12-24 2008-06-26 Sandisk Il Ltd. Flash memory device and system with randomizing for suppressing errors
US8370561B2 (en) 2006-12-24 2013-02-05 Sandisk Il Ltd. Randomizing for suppressing errors in a flash memory
US20080215798A1 (en) * 2006-12-24 2008-09-04 Sandisk Il Ltd. Randomizing for suppressing errors in a flash memory
US8127200B2 (en) 2006-12-24 2012-02-28 Sandisk Il Ltd. Flash memory device and system with randomizing for suppressing errors
US8369147B2 (en) 2006-12-28 2013-02-05 Micron Technology, Inc. Non-volatile multilevel memory cell programming
US20100182832A1 (en) * 2006-12-28 2010-07-22 Micron Technology, Inc. Non-volatile multilevel memory cell programming
US7701765B2 (en) * 2006-12-28 2010-04-20 Micron Technology, Inc. Non-volatile multilevel memory cell programming
US20080158951A1 (en) * 2006-12-28 2008-07-03 Micron Technology, Inc. Non-volatile multilevel memory cell programming
US7984360B2 (en) 2006-12-31 2011-07-19 Ramot At Tel Aviv University Ltd. Avoiding errors in a flash memory by using substitution transformations
US20080158948A1 (en) * 2006-12-31 2008-07-03 Sandisk Il Ltd. Avoiding errors in a flash memory by using substitution transformations
US7751240B2 (en) 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
US7755950B2 (en) 2007-01-24 2010-07-13 Samsung Electronics Co., Ltd. Programming methods of memory systems having a multilevel cell flash memory
US20080177934A1 (en) * 2007-01-24 2008-07-24 Samsung Electronics. Co., Ltd. Memory systems having a multilevel cell flash memory and programming methods thereof
US7881107B2 (en) 2007-01-24 2011-02-01 Anobit Technologies Ltd. Memory device with negative thresholds
US8369141B2 (en) 2007-03-12 2013-02-05 Apple Inc. Adaptive estimation of memory cell read thresholds
US8001320B2 (en) 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
US8429493B2 (en) 2007-05-12 2013-04-23 Apple Inc. Memory device with internal signap processing unit
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US8650352B2 (en) 2007-09-20 2014-02-11 Densbits Technologies Ltd. Systems and methods for determining logical values of coupled flash memory cells
US8365040B2 (en) 2007-09-20 2013-01-29 Densbits Technologies Ltd. Systems and methods for handling immediate data errors in flash memory
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
US8068360B2 (en) 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8527819B2 (en) 2007-10-19 2013-09-03 Apple Inc. Data storage in analog memory cell arrays having erase failures
US8427867B2 (en) * 2007-10-22 2013-04-23 Densbits Technologies Ltd. Systems and methods for averaging error rates in non-volatile devices and storage systems
US8694715B2 (en) 2007-10-22 2014-04-08 Densbits Technologies Ltd. Methods for adaptively programming flash memory devices and flash memory systems incorporating same
US8799563B2 (en) 2007-10-22 2014-08-05 Densbits Technologies Ltd. Methods for adaptively programming flash memory devices and flash memory systems incorporating same
US8443242B2 (en) 2007-10-25 2013-05-14 Densbits Technologies Ltd. Systems and methods for multiple coding rates in flash devices
US7668012B2 (en) 2007-10-31 2010-02-23 Micron Technology, Inc. Memory cell programming
US8611152B2 (en) 2007-10-31 2013-12-17 Micron Technology, Inc. Non-volatile multilevel memory cells
US8154926B2 (en) 2007-10-31 2012-04-10 Micron Technology, Inc. Memory cell programming
TWI401686B (en) * 2007-10-31 2013-07-11 Micron Technology Inc Memory cell programming
US20100128528A1 (en) * 2007-10-31 2010-05-27 Micron Technology, Inc. Memory cell programming
WO2009058196A1 (en) * 2007-10-31 2009-05-07 Micron Technology, Inc. Memory cell programming
US9070450B2 (en) 2007-10-31 2015-06-30 Micron Technology, Inc. Non-volatile multilevel memory cells
US9349441B2 (en) 2007-10-31 2016-05-24 Micron Technology, Inc. Fractional bits in memory cells
US8964465B2 (en) 2007-10-31 2015-02-24 Micron Technology, Inc. Fractional bits in memory cells
US20090109746A1 (en) * 2007-10-31 2009-04-30 Micron Technology, Inc. Memory cell programming
US8531877B2 (en) 2007-10-31 2013-09-10 Micron Technology, Inc. Fractional bits in memory cells
KR101160754B1 (en) 2007-10-31 2012-06-28 마이크론 테크놀로지, 인크. Memory cell programming
US8270246B2 (en) 2007-11-13 2012-09-18 Apple Inc. Optimized selection of memory chips in multi-chips memory devices
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8453022B2 (en) 2007-12-05 2013-05-28 Densbits Technologies Ltd. Apparatus and methods for generating row-specific reading thresholds in flash memory
US8335977B2 (en) 2007-12-05 2012-12-18 Densbits Technologies Ltd. Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
US8341335B2 (en) 2007-12-05 2012-12-25 Densbits Technologies Ltd. Flash memory apparatus with a heating system for temporarily retired memory portions
US8751726B2 (en) 2007-12-05 2014-06-10 Densbits Technologies Ltd. System and methods employing mock thresholds to generate actual reading thresholds in flash memory devices
US9104550B2 (en) 2007-12-05 2015-08-11 Densbits Technologies Ltd. Physical levels deterioration based determination of thresholds useful for converting cell physical levels into cell logical values in an array of digital memory cells
US8843698B2 (en) 2007-12-05 2014-09-23 Densbits Technologies Ltd. Systems and methods for temporarily retiring memory portions
US8627188B2 (en) 2007-12-05 2014-01-07 Densbits Technologies Ltd. Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
US8607128B2 (en) 2007-12-05 2013-12-10 Densbits Technologies Ltd. Low power chien-search based BCH/RS decoding system for flash memory, mobile communications devices and other applications
US8321625B2 (en) 2007-12-05 2012-11-27 Densbits Technologies Ltd. Flash memory device with physical cell value deterioration accommodation and methods useful in conjunction therewith
US8359516B2 (en) 2007-12-12 2013-01-22 Densbits Technologies Ltd. Systems and methods for error correction and decoding on multi-level physical media
US8782500B2 (en) 2007-12-12 2014-07-15 Densbits Technologies Ltd. Systems and methods for error correction and decoding on multi-level physical media
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8276051B2 (en) 2007-12-12 2012-09-25 Densbits Technologies Ltd. Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8327246B2 (en) 2007-12-18 2012-12-04 Densbits Technologies Ltd. Apparatus for coding at a plurality of rates in multi-level flash memory systems, and methods useful in conjunction therewith
US8085586B2 (en) 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US20090204824A1 (en) * 2007-12-31 2009-08-13 Lin Jason T System, method and memory device providing data scrambling compatible with on-chip copy operation
US8301912B2 (en) 2007-12-31 2012-10-30 Sandisk Technologies Inc. System, method and memory device providing data scrambling compatible with on-chip copy operation
USRE45697E1 (en) 2007-12-31 2015-09-29 Sandisk Technologies Inc. System, method and memory device providing data scrambling compatible with on-chip copy operation
US20090182934A1 (en) * 2008-01-14 2009-07-16 Samsung Electronics Co., Ltd. Memory device and method of multi-bit programming
US8230157B2 (en) * 2008-01-14 2012-07-24 Samsung Electronics Co., Ltd. Memory device and method of multi-bit programming
US8762800B1 (en) 2008-01-31 2014-06-24 Densbits Technologies Ltd. Systems and methods for handling immediate data errors in flash memory
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US7924587B2 (en) 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8972472B2 (en) 2008-03-25 2015-03-03 Densbits Technologies Ltd. Apparatus and methods for hardware-efficient unbiased rounding
US20090279362A1 (en) * 2008-05-09 2009-11-12 Ori Stern Partial scrambling to reduce correlation
US8059455B2 (en) 2008-05-09 2011-11-15 Sandisk Il Ltd. Partial scrambling to reduce correlation
US20090282267A1 (en) * 2008-05-09 2009-11-12 Ori Stern Partial scrambling to reduce correlation
US20110007573A1 (en) * 2008-06-27 2011-01-13 Idan Alrod Gain control for read operations in flash memory
US8040737B2 (en) * 2008-06-27 2011-10-18 Sandisk Il Ltd. Gain control for read operations in flash memory
US8683147B2 (en) 2008-07-09 2014-03-25 Phison Electronics Corp. Data accessing method for flash memory storage device having data perturbation module, and storage system and controller using the same
US7995388B1 (en) 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US8498151B1 (en) 2008-08-05 2013-07-30 Apple Inc. Data storage in analog memory cells using modified pass voltages
US8332725B2 (en) 2008-08-20 2012-12-11 Densbits Technologies Ltd. Reprogramming non volatile memory portions
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8261159B1 (en) 2008-10-30 2012-09-04 Apple, Inc. Data scrambling schemes for memory devices
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8397131B1 (en) 2008-12-31 2013-03-12 Apple Inc. Efficient readout schemes for analog memory cell devices
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8819385B2 (en) 2009-04-06 2014-08-26 Densbits Technologies Ltd. Device and method for managing a flash memory
US8850296B2 (en) 2009-04-06 2014-09-30 Densbits Technologies Ltd. Encoding method and system, decoding method and system
US8458574B2 (en) 2009-04-06 2013-06-04 Densbits Technologies Ltd. Compact chien-search based decoding apparatus and method
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8566510B2 (en) 2009-05-12 2013-10-22 Densbits Technologies Ltd. Systems and method for flash memory management
US8102705B2 (en) 2009-06-05 2012-01-24 Sandisk Technologies Inc. Structure and method for shuffling data within non-volatile memory devices
US8228729B2 (en) 2009-06-05 2012-07-24 Sandisk Technologies Inc. Structure and method for shuffling data within non-volatile memory devices
EP2469540A2 (en) 2009-06-05 2012-06-27 SanDisk Technologies, Inc. Folding data stored in binary format into multi-state format within non-volatile memory devices
US8027195B2 (en) 2009-06-05 2011-09-27 SanDisk Technologies, Inc. Folding data stored in binary format into multi-state format within non-volatile memory devices
US8711625B2 (en) 2009-07-06 2014-04-29 Sandisk Technologies Inc. Bad column management with bit information in non-volatile memory systems
US9748001B2 (en) 2009-07-06 2017-08-29 Sandisk Technologies Llc Bad column management with bit information in non-volatile memory systems
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8995197B1 (en) 2009-08-26 2015-03-31 Densbits Technologies Ltd. System and methods for dynamic erase and program control for flash memory device memories
US8305812B2 (en) 2009-08-26 2012-11-06 Densbits Technologies Ltd. Flash memory module and method for programming a page of flash memory cells
US9330767B1 (en) 2009-08-26 2016-05-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Flash memory module and method for programming a page of flash memory cells
US8868821B2 (en) 2009-08-26 2014-10-21 Densbits Technologies Ltd. Systems and methods for pre-equalization and code design for a flash memory
US8730729B2 (en) 2009-10-15 2014-05-20 Densbits Technologies Ltd. Systems and methods for averaging error rates in non-volatile devices and storage systems
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8724387B2 (en) 2009-10-22 2014-05-13 Densbits Technologies Ltd. Method, system, and computer readable medium for reading and programming flash memory cells using multiple bias voltages
US8626988B2 (en) 2009-11-19 2014-01-07 Densbits Technologies Ltd. System and method for uncoded bit error rate equalization via interleaving
US8473809B2 (en) 2009-11-20 2013-06-25 Sandisk Technologies Inc. Data coding for improved ECC efficiency
WO2011062917A1 (en) * 2009-11-20 2011-05-26 Sandisk Corporation Data coding for improved ecc eddiciency in a nonvolatile storage system
US20110126080A1 (en) * 2009-11-20 2011-05-26 Jun Wan Data coding for improved ecc efficiency
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
WO2011075594A1 (en) 2009-12-18 2011-06-23 Sandisk Corporation Non-volatile memory with multi-gear control using on-chip folding of data
US8468294B2 (en) 2009-12-18 2013-06-18 Sandisk Technologies Inc. Non-volatile memory with multi-gear control using on-chip folding of data
US8725935B2 (en) 2009-12-18 2014-05-13 Sandisk Technologies Inc. Balanced performance for on-chip folding of non-volatile memories
WO2011075572A1 (en) 2009-12-18 2011-06-23 Sandisk Corporation Maintaining updates of multi-level non-volatile memory in binary non-volatile memory
US8144512B2 (en) 2009-12-18 2012-03-27 Sandisk Technologies Inc. Data transfer flows for on-chip folding
WO2011075597A1 (en) 2009-12-18 2011-06-23 Sandisk Corporation Data transfer flows for on-chip folding
US9037777B2 (en) 2009-12-22 2015-05-19 Densbits Technologies Ltd. Device, system, and method for reducing program/read disturb in flash arrays
US8607124B2 (en) 2009-12-24 2013-12-10 Densbits Technologies Ltd. System and method for setting a flash memory cell read threshold
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8677203B1 (en) 2010-01-11 2014-03-18 Apple Inc. Redundant data storage schemes for multi-die memory systems
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
US8700970B2 (en) 2010-02-28 2014-04-15 Densbits Technologies Ltd. System and method for multi-dimensional decoding
US8341502B2 (en) 2010-02-28 2012-12-25 Densbits Technologies Ltd. System and method for multi-dimensional decoding
US8516274B2 (en) 2010-04-06 2013-08-20 Densbits Technologies Ltd. Method, system and medium for analog encryption in a flash memory
US8527840B2 (en) 2010-04-06 2013-09-03 Densbits Technologies Ltd. System and method for restoring damaged data programmed on a flash device
US9104610B2 (en) 2010-04-06 2015-08-11 Densbits Technologies Ltd. Method, system and medium for analog encryption in a flash memory
US8745317B2 (en) 2010-04-07 2014-06-03 Densbits Technologies Ltd. System and method for storing information in a multi-level cell memory
US9021177B2 (en) 2010-04-29 2015-04-28 Densbits Technologies Ltd. System and method for allocating and using spare blocks in a flash memory
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8417876B2 (en) 2010-06-23 2013-04-09 Sandisk Technologies Inc. Use of guard bands and phased maintenance operations to avoid exceeding maximum latency requirements in non-volatile memory systems
US8510639B2 (en) 2010-07-01 2013-08-13 Densbits Technologies Ltd. System and method for multi-dimensional encoding and decoding
US8468431B2 (en) 2010-07-01 2013-06-18 Densbits Technologies Ltd. System and method for multi-dimensional encoding and decoding
US8539311B2 (en) 2010-07-01 2013-09-17 Densbits Technologies Ltd. System and method for data recovery in multi-level cell memories
US8621321B2 (en) 2010-07-01 2013-12-31 Densbits Technologies Ltd. System and method for multi-dimensional encoding and decoding
US8850297B1 (en) 2010-07-01 2014-09-30 Densbits Technologies Ltd. System and method for multi-dimensional encoding and decoding
US8467249B2 (en) 2010-07-06 2013-06-18 Densbits Technologies Ltd. Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
WO2012009318A1 (en) 2010-07-13 2012-01-19 Sandisk Technologies Inc. Dynamic optimization of back-end memory system interface
US8464135B2 (en) 2010-07-13 2013-06-11 Sandisk Technologies Inc. Adaptive flash interface
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8645794B1 (en) 2010-07-31 2014-02-04 Apple Inc. Data storage in analog memory cells using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US8964464B2 (en) 2010-08-24 2015-02-24 Densbits Technologies Ltd. System and method for accelerated sampling
US8508995B2 (en) 2010-09-15 2013-08-13 Densbits Technologies Ltd. System and method for adjusting read voltage thresholds in memories
US8711624B2 (en) 2010-09-20 2014-04-29 Samsung Electronics Co., Ltd. Memory device and self interleaving method thereof
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
US9063878B2 (en) 2010-11-03 2015-06-23 Densbits Technologies Ltd. Method, system and computer readable medium for copy back
US8850100B2 (en) 2010-12-07 2014-09-30 Densbits Technologies Ltd. Interleaving codeword portions between multiple planes and/or dies of a flash memory device
US10079068B2 (en) 2011-02-23 2018-09-18 Avago Technologies General Ip (Singapore) Pte. Ltd. Devices and method for wear estimation based memory management
US8693258B2 (en) 2011-03-17 2014-04-08 Densbits Technologies Ltd. Obtaining soft information using a hard interface
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
US8990665B1 (en) 2011-04-06 2015-03-24 Densbits Technologies Ltd. System, method and computer program product for joint search of a read threshold and soft decoding
US9069688B2 (en) 2011-04-15 2015-06-30 Sandisk Technologies Inc. Dynamic optimization of back-end memory system interface
US9128623B2 (en) 2011-04-15 2015-09-08 Samsung Electronics Co., Ltd. Non-volatile memory devices, methods of operating non-volatile memory devices, and systems including the same
US8996790B1 (en) 2011-05-12 2015-03-31 Densbits Technologies Ltd. System and method for flash memory management
US9195592B1 (en) 2011-05-12 2015-11-24 Densbits Technologies Ltd. Advanced management of a non-volatile memory
US9501392B1 (en) 2011-05-12 2016-11-22 Avago Technologies General Ip (Singapore) Pte. Ltd. Management of a non-volatile memory module
US9110785B1 (en) 2011-05-12 2015-08-18 Densbits Technologies Ltd. Ordered merge of data sectors that belong to memory space portions
US9396106B2 (en) 2011-05-12 2016-07-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Advanced management of a non-volatile memory
US9372792B1 (en) 2011-05-12 2016-06-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Advanced management of a non-volatile memory
US8667211B2 (en) 2011-06-01 2014-03-04 Densbits Technologies Ltd. System and method for managing a non-volatile memory
US9311969B2 (en) * 2011-07-22 2016-04-12 Sandisk Technologies Inc. Systems and methods of storing data
US9390774B2 (en) 2011-07-22 2016-07-12 Sandisk Technologies Llc Systems and methods of storing data
US8880977B2 (en) 2011-07-22 2014-11-04 Sandisk Technologies Inc. Systems and methods of storing data
US8874994B2 (en) 2011-07-22 2014-10-28 Sandisk Technologies Inc. Systems and methods of storing data
US9311970B2 (en) 2011-07-22 2016-04-12 Sandisk Technologies Inc. Systems and methods of storing data
US9032269B2 (en) 2011-07-22 2015-05-12 Sandisk Technologies Inc. Systems and methods of storing data
US20130024605A1 (en) * 2011-07-22 2013-01-24 Sandisk Technologies Inc. Systems and methods of storing data
US9318166B2 (en) 2011-07-22 2016-04-19 SanDisk Technologies, Inc. Systems and methods of storing data
WO2013016393A1 (en) 2011-07-28 2013-01-31 Sandisk Technologies Inc. Data recovery for defective word lines during programming of non-volatile memory arrays
US8588003B1 (en) 2011-08-01 2013-11-19 Densbits Technologies Ltd. System, method and computer program product for programming and for recovering from a power failure
US20140337564A1 (en) * 2011-08-31 2014-11-13 Micron Technology, Inc. Apparatuses and methods of operating for memory endurance
US9105350B2 (en) * 2011-08-31 2015-08-11 Micron Technology, Inc. Apparatuses and methods of operating for memory endurance
US8553468B2 (en) 2011-09-21 2013-10-08 Densbits Technologies Ltd. System and method for managing erase operations in a non-volatile memory
CN103151069A (en) * 2011-12-06 2013-06-12 三星电子株式会社 Memory systems and block copy methods thereof
US8947941B2 (en) 2012-02-09 2015-02-03 Densbits Technologies Ltd. State responsive operations relating to flash memory cells
US8996788B2 (en) 2012-02-09 2015-03-31 Densbits Technologies Ltd. Configurable flash interface
US8842473B2 (en) 2012-03-15 2014-09-23 Sandisk Technologies Inc. Techniques for accessing column selecting shift register with skipped entries in non-volatile memories
US8996793B1 (en) 2012-04-24 2015-03-31 Densbits Technologies Ltd. System, method and computer readable medium for generating soft information
US8681548B2 (en) 2012-05-03 2014-03-25 Sandisk Technologies Inc. Column redundancy circuitry for non-volatile memory
US8838937B1 (en) 2012-05-23 2014-09-16 Densbits Technologies Ltd. Methods, systems and computer readable medium for writing and reading data
US9431118B1 (en) 2012-05-30 2016-08-30 Avago Technologies General Ip (Singapore) Pte. Ltd. System, method and computer program product for processing read threshold information and for reading a flash memory module
US8879325B1 (en) 2012-05-30 2014-11-04 Densbits Technologies Ltd. System, method and computer program product for processing read threshold information and for reading a flash memory module
US9921954B1 (en) 2012-08-27 2018-03-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for split flash memory management between host and storage controller
US9490035B2 (en) 2012-09-28 2016-11-08 SanDisk Technologies, Inc. Centralized variable rate serializer and deserializer for bad column management
US8897080B2 (en) 2012-09-28 2014-11-25 Sandisk Technologies Inc. Variable rate serial to parallel shift register
US9076506B2 (en) 2012-09-28 2015-07-07 Sandisk Technologies Inc. Variable rate parallel to serial shift register
US9368225B1 (en) 2012-11-21 2016-06-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Determining read thresholds based upon read error direction statistics
US9069659B1 (en) 2013-01-03 2015-06-30 Densbits Technologies Ltd. Read threshold determination using reference read threshold
US9431125B2 (en) * 2013-03-15 2016-08-30 Sandisk Technologies Llc Method and system for adaptive setting of verify levels in flash memory
US20140281820A1 (en) * 2013-03-15 2014-09-18 Idan Alrod Method and system for adaptive setting of verify levels in flash memory
US9136876B1 (en) 2013-06-13 2015-09-15 Densbits Technologies Ltd. Size limited multi-dimensional decoding
US9489300B2 (en) 2013-06-19 2016-11-08 Sandisk Technologies Llc Data encoding for non-volatile memory
US9489299B2 (en) 2013-06-19 2016-11-08 Sandisk Technologies Llc Data encoding for non-volatile memory
US9489294B2 (en) 2013-06-19 2016-11-08 Sandisk Technologies Llc Data encoding for non-volatile memory
US9117520B2 (en) 2013-06-19 2015-08-25 Sandisk Technologies Inc. Data encoding for non-volatile memory
US9117514B2 (en) 2013-06-19 2015-08-25 Sandisk Technologies Inc. Data encoding for non-volatile memory
US9413491B1 (en) 2013-10-08 2016-08-09 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for multiple dimension decoding and encoding a message
US9786388B1 (en) 2013-10-09 2017-10-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Detecting and managing bad columns
US9348694B1 (en) 2013-10-09 2016-05-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Detecting and managing bad columns
US9397706B1 (en) 2013-10-09 2016-07-19 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for irregular multiple dimension decoding and encoding
US9390008B2 (en) 2013-12-11 2016-07-12 Sandisk Technologies Llc Data encoding for non-volatile memory
US9536612B1 (en) 2014-01-23 2017-01-03 Avago Technologies General Ip (Singapore) Pte. Ltd Digital signaling processing for three dimensional flash memory arrays
US10120792B1 (en) 2014-01-29 2018-11-06 Avago Technologies General Ip (Singapore) Pte. Ltd. Programming an embedded flash storage device
US9384128B2 (en) 2014-04-18 2016-07-05 SanDisk Technologies, Inc. Multi-level redundancy code for non-volatile memory controller
US9542262B1 (en) 2014-05-29 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Error correction
US9892033B1 (en) 2014-06-24 2018-02-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Management of memory units
US9972393B1 (en) 2014-07-03 2018-05-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Accelerating programming of a flash memory module
US9584159B1 (en) 2014-07-03 2017-02-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Interleaved encoding
US9407291B1 (en) 2014-07-03 2016-08-02 Avago Technologies General Ip (Singapore) Pte. Ltd. Parallel encoding method and system
US9449702B1 (en) 2014-07-08 2016-09-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Power management
US9817751B2 (en) * 2014-09-03 2017-11-14 Apple Inc. Multi-phase programming schemes for nonvolatile memories
US20160062907A1 (en) * 2014-09-03 2016-03-03 Apple Inc. Multi-phase programming schemes for nonvolatile memories
US9934872B2 (en) 2014-10-30 2018-04-03 Sandisk Technologies Llc Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
US9524211B1 (en) 2014-11-18 2016-12-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Codeword management
US9224502B1 (en) 2015-01-14 2015-12-29 Sandisk Technologies Inc. Techniques for detection and treating memory hole to local interconnect marginality defects
US10305515B1 (en) 2015-02-02 2019-05-28 Avago Technologies International Sales Pte. Limited System and method for encoding using multiple linear feedback shift registers
US10032524B2 (en) 2015-02-09 2018-07-24 Sandisk Technologies Llc Techniques for determining local interconnect defects
US9269446B1 (en) 2015-04-08 2016-02-23 Sandisk Technologies Inc. Methods to improve programming of slow cells
US9564219B2 (en) 2015-04-08 2017-02-07 Sandisk Technologies Llc Current based detection and recording of memory hole-interconnect spacing defects
US10628255B1 (en) 2015-06-11 2020-04-21 Avago Technologies International Sales Pte. Limited Multi-dimensional decoding
US9851921B1 (en) 2015-07-05 2017-12-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Flash memory chip processing
US9954558B1 (en) 2016-03-03 2018-04-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Fast decoding of data stored in a flash memory
US11507448B2 (en) 2019-04-05 2022-11-22 Samsung Electronics Co., Ltd. Non-volatile memory device, method of operating the device, and memory system including the device
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory
EP4202934A1 (en) * 2021-12-24 2023-06-28 Kioxia Corporation Memory device

Also Published As

Publication number Publication date
US20080104312A1 (en) 2008-05-01
WO2006033099A2 (en) 2006-03-30
US20120042219A1 (en) 2012-02-16
KR20070054659A (en) 2007-05-29
US8245099B2 (en) 2012-08-14
US8055972B2 (en) 2011-11-08
WO2006033099A3 (en) 2007-05-18

Similar Documents

Publication Publication Date Title
US8245099B2 (en) States encoding in multi-bit flash cells for optimizing error rate
US8010755B2 (en) States encoding in multi-bit flash cells for optimizing error rate
US7310347B2 (en) States encoding in multi-bit flash cells
US8019928B2 (en) Method of managing a multi-bit-cell flash memory
US7716413B2 (en) Method of making a multi-bit-cell flash memory
JP4653738B2 (en) Method of operating flash memory cell and flash memory device
US7984360B2 (en) Avoiding errors in a flash memory by using substitution transformations
US7729166B2 (en) Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same
US8040737B2 (en) Gain control for read operations in flash memory
US20070279982A1 (en) Semiconductor memory device capable of correcting a read level properly
KR101544607B1 (en) Memory device and program method thereof
US11264090B2 (en) Memory system
KR102182225B1 (en) Reprogram without erase using capacity in multi-level nand cells
CN110795270A (en) Solid state storage device and read retry method thereof
KR100719381B1 (en) Mlc nand flash memory with address setting flag
KR20100013947A (en) Multi level cell programming method of non volatile memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: M-SYSTEMS FLASH DISK PIONEERS, LTD., ISRAEL

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LASSER, MENAHEM;REEL/FRAME:016312/0706

Effective date: 20050213

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: MSYSTEMS LTD., ISRAEL

Free format text: CHANGE OF NAME;ASSIGNOR:M-SYSTEMS FLASH DISK PIONEERS LTD.;REEL/FRAME:021682/0024

Effective date: 20060504

Owner name: SANDISK IL LTD., ISRAEL

Free format text: CHANGE OF NAME;ASSIGNOR:MSYSTEMS LTD.;REEL/FRAME:021682/0045

Effective date: 20070101