US20050285106A1 - Method of reworking structures incorporating low-k dielectric materials - Google Patents

Method of reworking structures incorporating low-k dielectric materials Download PDF

Info

Publication number
US20050285106A1
US20050285106A1 US11/205,522 US20552205A US2005285106A1 US 20050285106 A1 US20050285106 A1 US 20050285106A1 US 20552205 A US20552205 A US 20552205A US 2005285106 A1 US2005285106 A1 US 2005285106A1
Authority
US
United States
Prior art keywords
processing chamber
accordance
semiconductor structure
layer
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/205,522
Inventor
Terence Kane
Chung-Ping Eng
Brett Engel
Barry Ginsberg
Dermott Macpherson
John Petrus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US11/205,522 priority Critical patent/US20050285106A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PETRUS, JOHN C., ENG, CHUNG-PING, ENGEL, BRETT H., GINSBERG, BARRY J., KANE, TERENCE L., MACPHERSON, DERMOTT A.
Publication of US20050285106A1 publication Critical patent/US20050285106A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/62—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light
    • G01N21/66—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light electrically excited, e.g. electroluminescence
    • G01N21/68—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light electrically excited, e.g. electroluminescence using high frequency electric fields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to methods and systems for unlayering multi-layer structures incorporating low-k dielectric materials.
  • Advanced semiconductor designs typically incorporate planarized multilevel structures including alternating layers of insulating materials supporting dual damascene and single damascene metal interconnections.
  • Exemplary structures include alternating layers of insulating films, for example low-k dielectric films, with alternating chemical-mechanical hardmask endstop layers, for example silicon nitride and/or high density plasma oxide.
  • Damascene metal can comprise, for example, copper.
  • Unlayering multi-layer structures including low-k dielectric materials is problematic using known layer removal techniques.
  • the fragile nature of the low-k dielectric materials cause them to react poorly to processes effective for oxides.
  • the lower modulus of low-k dielectric films are susceptible to damage when exposed to conventional chemical-mechanical polish processes. Wafer delayering for manufacturing rework or recovery of wafers cannot employ conventional delayering processes using plasma, or reactive ion etching or chemical-mechanical polish removal for planar deprocessing low-k films without damaging underlying films and undercutting metal layers. Still other techniques involving incident gallium ion beams can result in undesirable implantation of gallium into the low-k films or produce beam interactions (i.e. chemical bond breakdown in organic components present in some low-k films) producing unwanted electrical leakage paths and electrical shorts.
  • New and improved processes are thus desirable which facilitate the selective planar de-processing of metal layers, hardmask materials and chemical-mechanical endstop materials over low-k dielectric films without damaging the underlying low-k dielectric layers.
  • a new and improved apparatus and methods involving collimated Argon ion beam milling/Chemical assisted Argon Ion beam etching is provided for unlayering multi-layer structures including low-k dielectric layers with mininal damage to the low-k dielectric films while maintaining planarity of the unlayered surface.
  • Such methods and apparatus are applicable, for example, to unlayering back-end multilevel metallurgy found in semiconductor devices.
  • a method of ion beam etching a semiconductor structure including a first layer of material overlaying a second layer of low-k dielectric film comprising the steps of: ion beam-milling the first layer of material; and detecting, with an optical detector positioned in the ion beam adjacent the first layer of material, an endpoint of the first layer; whereby to expose the second layer of low-k dielectric film.
  • a system for delayering a semiconductor structure including a first layer of material overlaying a second layer of low-k dielectric film comprising: a processing chamber; an ion beam milling source in the processing chamber for generating a beam of ions to mill the semiconductor structure; a platen in the processing chamber for supporting the semiconductor structure in the beam of ions; a sapphire crystal endpoint detector in the processing chamber; a photospectrometer outside of the processing chamber; means for connecting the sapphire crystal endpoint detector to the photospectrometer; and means for positioning the sapphire crystal endpoint detector proximate the platen to monitor milling of the semiconductor structure.
  • FIG. 1 is a cross-sectional view of a semiconductor device including a back-end, multilevel metal contact structure exemplary of one type to which the invention is applicable;
  • FIGS. 2-7 are cross-sectional views of the multilevel metal contact structure of FIG. 1 showing successive processing steps in accordance with one embodiment of the invention.
  • Front end 20 comprises a conventional silicon-on-insulator (SOI) construction including a device-bearing, doped semiconductor layer 26 overlying an insulator layer 24 over a single-crystal silicon layer 22 .
  • SOI silicon-on-insulator
  • Semiconductor devices formed by implantation and processing in layer 26 are contacted through back-end structure 18 in the manner described below.
  • back-end structure 18 is seen to comprise a first-level connector layer including an insulator layer 28 A, such as an oxide, having a metal-filled via 28 B for contacting semiconductor devices on doped silicon layer 26 .
  • Metal-filled via 28 B contacts a source/drain region on the surface of doped silicon layer 26 adjoining a gate structure 28 C of a semiconductor field-effect transistor (FET). If the gate material is silicon oxide, this device is further identified as a metal-oxide FET, or MOSFET.
  • Insulator layers 30 B- 36 B each comprises a hardmask, chemical-mechanical endstop, such as a nitride, which will be used, in a manner described below, as an etching mask in a process for exposing the underlying low-k dielectric layer.
  • Each series of low-k film/insulator layers 30 A/B- 36 A/B includes a metal-filled via interconnect extending there through, the metal-filled vias indicated respectively at 30 D, 32 D, 34 D and 36 D.
  • a series of metal connector layers, indicated respectively at 30 C, 32 C, 34 C and 36 C, are interposed between adjacent vias.
  • oxide layers indicated respectively at 38 and 40 , overlie insulator layer 36 , each oxide layer including a metal-filled via 38 D, 40 D and overlying metal layer 38 C, 40 C.
  • back-end structure 18 illustrates a conventional multilevel metal structure with a first interconnect 28 B, for example comprising tungsten, overlaid by six, and optionally more, levels of metal vias and connectors graphically represented by 30 C/D, 32 C/D, 34 C/D, 36 C/D, 38 C/D and 40 C/D.
  • these metal interconnections comprise dual damascene copper and single damascene copper.
  • the tungsten metal wiring level identified as 28 B combined with the successive overlying copper metal lands identified as 30 C, 32 C, 34 C, 36 C, 38 C and 40 C would comprise what is known in the art as ‘seven level metal.’
  • Various methods and materials are known in the art for fabricating this type of structure.
  • low-k dielectric layers are identified at 30 A- 36 A.
  • these low-k dielectric layers comprise materials having a k factor of about 2.85 or less.
  • Such films typically comprise PECVD-deposited SiCOH films and compounds thereof, PECVD-deposited carbon-doped oxides and other organic polymers and porous oxides.
  • Commercially available low-k dielectric products and materials include Dow Corning's SiLKTM and porous SiLKTM, Applied Materials' Black DiamondTM, Novellus' CoralTM, Honeywell's HOSPTM, and Trikon Technologies FLOWFILLTM, among others.
  • Low-k dielectric films have desirable electrical characteristics effective to significantly reduce the lateral and inter-level capacitive effects between closely spaced electrical conductors of multilevel metal.
  • Such conductors include, for example, the dual damascene-formed copper conductors described above.
  • these low-k dielectric materials possess certain chemical and mechanical characteristics that make them prone to damage from certain common semiconductor processes. They are, for example, soft, pliable and porous as well as susceptible to damage through the use of typical semiconductor processes. Processes typically used to remove or unlayer low-k dielectric materials, such as mechanical unlayering, reactive ion etching (RIE), focused ion beam (FIB) techniques, chemical-mechanical polishing and wet chemical removal processes may damage the low-k or cause conductive leakage paths within the dielectric layers themselves.
  • RIE reactive ion etching
  • FIB focused ion beam
  • the terms “layer” and “film,” and variants thereof, are used interchangeably herein to describe the thin, conformal sheets of semiconductor, insulator and conductive materials that comprise a semiconductor device structure. It will be further understood that the terms “low-k dielectric material” and “SiLK,” and variants thereof, are used interchangeably herein to described the low-k dielectric materials described above.
  • Partial oxide layer 40 may be removed using one of many known processes including, for example, chemical-mechanical polishing or reactive ion etching.
  • structure 16 is situated in a processing chamber 48 , comprising, for example, one of many commercially known vacuum chambers available with a vacuum feedthrough and a tungsten filament ion beam source or a filament-less source.
  • Processing chamber 48 supports structure 16 on a liquid-cooled platen 46 capable of full rotation and full tilt and of cooling in a range of ⁇ 15 to +35 degrees centigrade.
  • a cooling media of 50% di-ionized water and 50% ethylene glycol-antifreeze is used to control the temperature of structure 16 , preventing damaging overheating from incident ion beam energy by heat exchange cooling of platen 46 .
  • Structure 16 is attached to platen 46 , for example, using heat dissipating grease.
  • a cooling helium gas can be metered into a fixture (not shown) holding structure 16 for incident ion beam delayering.
  • Processing chamber 48 accommodates a line 50 for introducing a focused input of a controlled mixture of a selected processing gas(es) 51 into the chamber.
  • Processing chamber 48 further supports an argon ion beam milling source 52 .
  • ion beam milling source 52 is manufactured by milling tool manufacturer VEECO instruments.
  • the system has been modified with the addition of a gas nozzle for introducing gases into the chamber.
  • a gas nozzle for introducing gases into the chamber.
  • four individual mass flow controllers for metering separate gases controlled via an external computer (not shown) having a conventional RS232 interface to monitor gas flow rates.
  • milling source 52 comprises a 400 watt pulse-mode 30 kHz switchable DC power supply, avoiding the risk of charge-inducted damage that may be associated with conventional 13.56 mHZ RF generators typically used in RIE/PLASMA etching systems.
  • Milling source 52 preferably includes a circumferential charge neutralizing filament 53 surrounding the collimated Argon beam. Milling source 52 is capable of currents in the range of 300 eV-3 KeV for a full range of incident beam energies.
  • any inert noble gas species found in the same column of the periodic table as Argon including helium, neon, xenon, and radon would work.
  • Noble gases ionize in a plasma to form non reactive, inert ions.
  • Argon gas is typically selected for all plasma processes because it is inexpensive and requires the least energy to disassociate into ions and form a plasma.
  • Processing chamber 48 further includes a fiber optic photospectrometer endpoint detector system 54 .
  • Endpoint detector system 54 includes a sapphire tip detector 56 positioned within the argon ion beam near the region of interest on semiconductor structure 16 .
  • Sapphire tip detector 56 is connected, through a ferro-fluidic vacuum feed-through accommodating a stainless steel tube housing an appropriate fiber optic cable, the tube and cable assembly indicated at 57 , to a personal-computer based charge-coupled device (CCD) CCD UV-VIS array spectrophotometer 58 located outside of chamber 48 .
  • CCD charge-coupled device
  • a standard PCI card is used for interfacing spectrophotometer 58 with a computer (PC) 60 .
  • the tube/cable 57 is preferably motor operated in a conventional manner by an electromechanical positioning device 59 so that detector 56 can be repositioned at various process steps to be proximate regions of interest on semiconductor substrate 16 .
  • spectrophotometer 58 can be tuned to various peak sensitivities, including copper peak sensitivity, tantalum liner peak sensitivity, carbon peak sensitivity (for such organic low-k dielectric films as SiLK), silicon peak sensitivity (for PECVD silicon oxide and LPCVD/HDP silicon nitride dielectrics), as well as tungsten peak sensitivity for tungsten interconnection, to detect different types of endpoint materials.
  • This spectrophotometer may, for example, be controlled using PC 60 running Visual C++ software code.
  • the above-described equipment is used in an argon ion beam milling process to etch back end structure 18 , including the various insulator, metal and low-k dielectric film layers. It will be seen that the etching process results in highly controllable, essentially planar delayering, while avoiding the damage to low-k materials typically associated with prior art processes, including: damage caused by FIB gallium beam induced charge implantation, undesirable anisotropic etch profiles associated with reactive ion etching (RIE) etch profiles, oxygen and H2O uptake in SiLK low-k films, solvent uptake in low-k dielectric films as well as susceptibility to scratching/slurry particle embodiment damage by chemical-mechanical processing.
  • RIE reactive ion etching
  • assembly 57 is used to position sapphire detector 56 proximate the upper surface of remaining oxide layer 38 .
  • Spectrophotometer 58 is adjusted to sense nitride, by optimizing the signal to detect silicon nitride.
  • a selected gas 51 for example a mixture of CF4 and oxygen, is introduced into chamber 48 and the parameters of ion beam milling source 52 and platen 46 are adjusted in a conventional manner to optimize the etching of oxide and copper.
  • the mixture of CF4 gas and oxygen will preferentially etch oxide and nitride without attacking copper.
  • Ion beam milling would mill copper at one rate while ionized gas would preferentially etch oxide and nitride.
  • Milling source 52 is operated to remove the remaining portion of oxide layer 40 along with the copper in copper-filled via 40 .
  • photospectrometer 58 is adjusted to sense oxide by optimizing the signal to sense oxygen or silicon but NOT nitride, and the parameters of gas 51 , milling source 52 and platen 46 are optimized in a conventional manner to etch nitride and copper.
  • Nitride layer 38 A is thus removed along with copper conductor 38 C, exposing the upper surface of remaining oxide layer 38 and copper filled via 38 D as shown in FIG. 3 .
  • assembly 54 and platen 46 are manipulated to place semiconductor structure 16 and endpoint detector 56 in the optimum physical position for the next etch step.
  • Endpoint detector 56 can be placed directly within the ion beam of milling source 52 proximate the areas of interest being etched. The temperature, angle and position of platen 46 are adjusted to optimize the etch process for the materials being etched.
  • photospectrometer 58 is adjusted to sense a low-k dielectric film such as SiLK by optimizing for sensing a carbon peak, the principal elemental component of an organic low-k film.
  • the appropriate principal elemental component i.e. for conventional oxides, this would be oxygen or silicon; for silicon nitride, this would be nitrogen, the above-described etching processes are used to remove the remaining portion of oxide layer 38 , nitride layer 36 and the copper connectors and copper-filled vias there through, exposing low-k dielectric layer 36 A and copper-filled via 36 D as shown in FIG. 4 .
  • etching systems and processes that are the subject of the present invention yield highly planar exposed surfaces, regardless of the materials being etched. Further, the processes can be controlled to accurately etch very thin films and very small depths within films, thus enabling the exposure of substantially any desired layers or features within a semiconductor structure.
  • structure 16 is shown with the above-described process steps repeated to expose low-k dielectric layers 34 A ( FIG. 5 ) and 32 A ( FIG. 6 ), respectively.
  • the etching processes used to remove the intermediate nitride layers and copper metallurgy are substantially identical to those described above.
  • Endpoint detector 56 and platen 46 are repositioned intermediate each etching step, in the manner described above, to optimize both the etching process and the endpoint detection.
  • semiconductor structure 16 is shown with all of back-end structure 18 removed excepting a remaining portion of layer 30 A overlying layer 28 A, and the associated metallurgy 30 D, 28 B and FET gate 28 C.
  • RIE etch ie. CF4 process gas
  • hardmask ie. Applied Materials BLOKTM
  • TEOS oxide or tetraothrosilicate
  • RIE etch ie. CF4 process gas
  • hard mask ie. Applied Materials BLOKTM
  • RIE etch ie. CF4 process gas
  • etch ie. CF4 process gas
  • hard mask ie. Applied Materials BLOKTM
  • RIE etch ie. CF4 process gas
  • etch ie. CF4 process gas
  • hard mask ie. Applied Materials BLOKTM
  • Deposit CVD nitride cap layer Resume normal spun-on low k dielectric film (ie. Dow Corning SiLK) film deposition.
  • RIE ie. CF4 process gas
  • wet etch to remove nitride cap and hardmask layer
  • mechanically polish to remove nitride cap layer and hardmask layer
  • wet etch barrier liner ie. Ta/TaN
  • Plasma etch with oxygen process gas to remove low-k spun on dielectric film. Mechanically polish/remove residual metal interconnection layer and stop at hardmask material.
  • Complete BEOL build cycle ie. CF4 process gas
  • RIE ie. CF4 process gas
  • wet etch to remove nitride cap and hardmask layer
  • mechanical polish removal of the cap nitride and hardmask could be substituted, instead.
  • a slow copper etchant to controllably remove the copper metal wiring levels and copper interconnection without etching into the underlying copper metal lands. Once the copper lands and copper interconnection levels are etched away (using a timed etch process), employ a different chemical etchant to remove the barrier liner metallurgy (typically a tantalum/tantalum nitride material) without attacking the underlying copper metal wiring.
  • barrier liner metallurgy typically a tantalum/tantalum nitride material
  • the systems and methods of the present invention enable highly selective and controllable planar removal of different types of materials, including oxides, nitrides, metals and low-k dielectrics such as SiLK. They further permit such removal without damaging the soft, fragile, low-k dielectric materials.
  • the present invention can be used to facilitate, for example, the reworking and/or evaluation of semiconductor devices, particularly those incorporating low-k dielectric films.
  • the invention thus has application in the manufacture, rework and analysis of semiconductor devices.

Abstract

Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion beam mills a first layer and detects an endpoint thereof using an optical detector positioned within the ion beam adjacent the first layer to expose a second layer of low-k dielectric film. Once the low-k dielectric film is exposed, a portion of the low-k dielectric film may be removed to provide spaces therein, which are backfilled with a material and polished to remove the backfill material and a layer of the multiple interconnect metal layers. Still further, the exposed low-k dielectric film may then be removed, and the exposed metal vias polished.

Description

    FIELD OF THE INVENTION
  • The present invention relates to methods and systems for unlayering multi-layer structures incorporating low-k dielectric materials.
    • BACKGROUND OF THE INVENTION
  • Advanced semiconductor designs typically incorporate planarized multilevel structures including alternating layers of insulating materials supporting dual damascene and single damascene metal interconnections. Exemplary structures include alternating layers of insulating films, for example low-k dielectric films, with alternating chemical-mechanical hardmask endstop layers, for example silicon nitride and/or high density plasma oxide. Damascene metal can comprise, for example, copper.
  • Selective unlayering of these multilayer structures is often necessary for purposes of manufacturing rework or recovery of wafers, to perform defect yield analysis, and/or for electrical characterization or physical failure analysis of wafers, wafer fragments, individual dies, or packaged dies to perform reliability defect root cause analysis. Regular unlayering of these multi-layer structures can also be done in the course of automated pattern recognition inspection of defects in comparison with electrical test maps.
  • Unlayering multi-layer structures including low-k dielectric materials is problematic using known layer removal techniques. In particular, the fragile nature of the low-k dielectric materials cause them to react poorly to processes effective for oxides. For example, the lower modulus of low-k dielectric films are susceptible to damage when exposed to conventional chemical-mechanical polish processes. Wafer delayering for manufacturing rework or recovery of wafers cannot employ conventional delayering processes using plasma, or reactive ion etching or chemical-mechanical polish removal for planar deprocessing low-k films without damaging underlying films and undercutting metal layers. Still other techniques involving incident gallium ion beams can result in undesirable implantation of gallium into the low-k films or produce beam interactions (i.e. chemical bond breakdown in organic components present in some low-k films) producing unwanted electrical leakage paths and electrical shorts.
  • Further, conventional processes used to remove overlying metal layers, particularly copper single damascene and copper dual damascene metal, can result in damage to the underlying low-k dielectric layers. For example, conventional chemical-mechanical removal of copper layers can easily scratch, or embed polishing media or slurry into, underlying low-k films, by compromising hardmask endstop materials. Attempts to unlayer multilevel structures using conventional reactive ion etching can produce non-planar etch results due to the presence of porous regions within the low-k film as well as the in-homogenity of the low-k films, themselves.
  • Conventional reactive ion etching of copper requires elevated temperatures, producing nonvolatile species that can contaminate low-k dielectric films. Further, reactive ion etch removal of overlying insulating films can result in undercutting of underlying copper metal layers resulting in non-uniform etch removal of underlying low-k dielectric films.
  • New and improved processes are thus desirable which facilitate the selective planar de-processing of metal layers, hardmask materials and chemical-mechanical endstop materials over low-k dielectric films without damaging the underlying low-k dielectric layers.
    • SUMMARY OF THE INVENTION
  • Two proposed methods involving deprocessing low-k structures with copper metallurgy/copper interconnections are described.
  • First, a new and improved apparatus and methods involving collimated Argon ion beam milling/Chemical assisted Argon Ion beam etching is provided for unlayering multi-layer structures including low-k dielectric layers with mininal damage to the low-k dielectric films while maintaining planarity of the unlayered surface. Such methods and apparatus are applicable, for example, to unlayering back-end multilevel metallurgy found in semiconductor devices.
  • In accordance with one embodiment of the invention, there is provided a method of ion beam etching a semiconductor structure including a first layer of material overlaying a second layer of low-k dielectric film, comprising the steps of: ion beam-milling the first layer of material; and detecting, with an optical detector positioned in the ion beam adjacent the first layer of material, an endpoint of the first layer; whereby to expose the second layer of low-k dielectric film.
  • In another embodiment of the invention, there is provided a system for delayering a semiconductor structure including a first layer of material overlaying a second layer of low-k dielectric film, comprising: a processing chamber; an ion beam milling source in the processing chamber for generating a beam of ions to mill the semiconductor structure; a platen in the processing chamber for supporting the semiconductor structure in the beam of ions; a sapphire crystal endpoint detector in the processing chamber; a photospectrometer outside of the processing chamber; means for connecting the sapphire crystal endpoint detector to the photospectrometer; and means for positioning the sapphire crystal endpoint detector proximate the platen to monitor milling of the semiconductor structure.
  • Secondly, a set of processes for deprocessing spun-on low-k structures with copper metallurgy/copper interconnections is described.
    • DESCRIPTION OF THE DRAWING FIGURES
  • These and other objects, features and advantages of the invention will be apparent from a consideration of the Detailed Description of the Invention when read with consideration of the drawing Figures, in which:
  • FIG. 1 is a cross-sectional view of a semiconductor device including a back-end, multilevel metal contact structure exemplary of one type to which the invention is applicable; and
  • FIGS. 2-7 are cross-sectional views of the multilevel metal contact structure of FIG. 1 showing successive processing steps in accordance with one embodiment of the invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Methodology for Reworking/Recovering Whole Wafers/Wafer Fragments/Individual Die:
  • With reference now to FIG. 1, there is shown a semiconductor structure 16 including a silicon device front-end 20 overlain by a multilevel metal back-end structure 18. Front end 20 comprises a conventional silicon-on-insulator (SOI) construction including a device-bearing, doped semiconductor layer 26 overlying an insulator layer 24 over a single-crystal silicon layer 22. Semiconductor devices formed by implantation and processing in layer 26 are contacted through back-end structure 18 in the manner described below.
  • Continuing with reference to FIG. 1, back-end structure 18 is seen to comprise a first-level connector layer including an insulator layer 28A, such as an oxide, having a metal-filled via 28B for contacting semiconductor devices on doped silicon layer 26. Metal-filled via 28B contacts a source/drain region on the surface of doped silicon layer 26 adjoining a gate structure 28C of a semiconductor field-effect transistor (FET). If the gate material is silicon oxide, this device is further identified as a metal-oxide FET, or MOSFET.
  • A series of four layers of a low-k dielectric material, indicated at 30A, 32A, 34A and 36A, respectively, overlay layer 28A, each low-k layer in turn overlain by an insulator layer 30B, 32B, 34B and 36B. Insulator layers 30B-36B each comprises a hardmask, chemical-mechanical endstop, such as a nitride, which will be used, in a manner described below, as an etching mask in a process for exposing the underlying low-k dielectric layer. Each series of low-k film/insulator layers 30A/B-36A/B includes a metal-filled via interconnect extending there through, the metal-filled vias indicated respectively at 30D, 32D, 34D and 36D. A series of metal connector layers, indicated respectively at 30C, 32C, 34C and 36C, are interposed between adjacent vias.
  • Two oxide layers, indicated respectively at 38 and 40, overlie insulator layer 36, each oxide layer including a metal-filled via 38D, 40D and overlying metal layer 38C, 40C. A respective silicon nitride chemical-mechanical etch stop layer, 38A, 40A, overlies each oxide layer 38,40.
  • It will be appreciated that back-end structure 18 illustrates a conventional multilevel metal structure with a first interconnect 28B, for example comprising tungsten, overlaid by six, and optionally more, levels of metal vias and connectors graphically represented by 30C/D, 32C/D, 34C/D, 36C/D, 38C/D and 40C/D. Typically, these metal interconnections comprise dual damascene copper and single damascene copper. In the described embodiment of the invention, the tungsten metal wiring level identified as 28B combined with the successive overlying copper metal lands identified as 30C, 32C, 34C, 36C, 38C and 40C would comprise what is known in the art as ‘seven level metal.’ Various methods and materials are known in the art for fabricating this type of structure.
  • As described above, low-k dielectric layers are identified at 30A-36A. Typically, these low-k dielectric layers comprise materials having a k factor of about 2.85 or less. Such films typically comprise PECVD-deposited SiCOH films and compounds thereof, PECVD-deposited carbon-doped oxides and other organic polymers and porous oxides. Commercially available low-k dielectric products and materials include Dow Corning's SiLK™ and porous SiLK™, Applied Materials' Black Diamond™, Novellus' Coral™, Honeywell's HOSP™, and Trikon Technologies FLOWFILL™, among others.
  • Low-k dielectric films have desirable electrical characteristics effective to significantly reduce the lateral and inter-level capacitive effects between closely spaced electrical conductors of multilevel metal. Such conductors include, for example, the dual damascene-formed copper conductors described above.
  • As noted above, however, these low-k dielectric materials possess certain chemical and mechanical characteristics that make them prone to damage from certain common semiconductor processes. They are, for example, soft, pliable and porous as well as susceptible to damage through the use of typical semiconductor processes. Processes typically used to remove or unlayer low-k dielectric materials, such as mechanical unlayering, reactive ion etching (RIE), focused ion beam (FIB) techniques, chemical-mechanical polishing and wet chemical removal processes may damage the low-k or cause conductive leakage paths within the dielectric layers themselves.
  • It will be understood that the terms “layer” and “film,” and variants thereof, are used interchangeably herein to describe the thin, conformal sheets of semiconductor, insulator and conductive materials that comprise a semiconductor device structure. It will be further understood that the terms “low-k dielectric material” and “SiLK,” and variants thereof, are used interchangeably herein to described the low-k dielectric materials described above.
  • With reference now to FIG. 2, there is shown semiconductor structure 16 having hardstop layer 40A and oxide layer 40 removed down to via 40D. Partial oxide layer 40 may be removed using one of many known processes including, for example, chemical-mechanical polishing or reactive ion etching.
  • As further shown in FIG. 2, structure 16 is situated in a processing chamber 48, comprising, for example, one of many commercially known vacuum chambers available with a vacuum feedthrough and a tungsten filament ion beam source or a filament-less source. Processing chamber 48 supports structure 16 on a liquid-cooled platen 46 capable of full rotation and full tilt and of cooling in a range of −15 to +35 degrees centigrade.
  • In the described embodiment, a cooling media of 50% di-ionized water and 50% ethylene glycol-antifreeze is used to control the temperature of structure 16, preventing damaging overheating from incident ion beam energy by heat exchange cooling of platen 46. Structure 16 is attached to platen 46, for example, using heat dissipating grease. Alternatively, a cooling helium gas can be metered into a fixture (not shown) holding structure 16 for incident ion beam delayering. Processing chamber 48 accommodates a line 50 for introducing a focused input of a controlled mixture of a selected processing gas(es) 51 into the chamber. Processing chamber 48 further supports an argon ion beam milling source 52.
  • In the described embodiment, ion beam milling source 52 is manufactured by milling tool manufacturer VEECO instruments. The system has been modified with the addition of a gas nozzle for introducing gases into the chamber. Further included are four individual mass flow controllers for metering separate gases controlled via an external computer (not shown) having a conventional RS232 interface to monitor gas flow rates.
  • In the described embodiment, milling source 52 comprises a 400 watt pulse-mode 30 kHz switchable DC power supply, avoiding the risk of charge-inducted damage that may be associated with conventional 13.56 mHZ RF generators typically used in RIE/PLASMA etching systems. Milling source 52 preferably includes a circumferential charge neutralizing filament 53 surrounding the collimated Argon beam. Milling source 52 is capable of currents in the range of 300 eV-3 KeV for a full range of incident beam energies.
  • While the invention is described with respect to Argon ion beam milling, any inert noble gas species found in the same column of the periodic table as Argon, including helium, neon, xenon, and radon would work. Noble gases ionize in a plasma to form non reactive, inert ions. Argon gas is typically selected for all plasma processes because it is inexpensive and requires the least energy to disassociate into ions and form a plasma.
  • Processing chamber 48 further includes a fiber optic photospectrometer endpoint detector system 54. Endpoint detector system 54 includes a sapphire tip detector 56 positioned within the argon ion beam near the region of interest on semiconductor structure 16. Sapphire tip detector 56 is connected, through a ferro-fluidic vacuum feed-through accommodating a stainless steel tube housing an appropriate fiber optic cable, the tube and cable assembly indicated at 57, to a personal-computer based charge-coupled device (CCD) CCD UV-VIS array spectrophotometer 58 located outside of chamber 48. In the described embodiment, a standard PCI card is used for interfacing spectrophotometer 58 with a computer (PC) 60. The tube/cable 57 is preferably motor operated in a conventional manner by an electromechanical positioning device 59 so that detector 56 can be repositioned at various process steps to be proximate regions of interest on semiconductor substrate 16.
  • In a manner known in the art, spectrophotometer 58 can be tuned to various peak sensitivities, including copper peak sensitivity, tantalum liner peak sensitivity, carbon peak sensitivity (for such organic low-k dielectric films as SiLK), silicon peak sensitivity (for PECVD silicon oxide and LPCVD/HDP silicon nitride dielectrics), as well as tungsten peak sensitivity for tungsten interconnection, to detect different types of endpoint materials. This spectrophotometer may, for example, be controlled using PC 60 running Visual C++ software code.
  • As is further described below, the above-described equipment is used in an argon ion beam milling process to etch back end structure 18, including the various insulator, metal and low-k dielectric film layers. It will be seen that the etching process results in highly controllable, essentially planar delayering, while avoiding the damage to low-k materials typically associated with prior art processes, including: damage caused by FIB gallium beam induced charge implantation, undesirable anisotropic etch profiles associated with reactive ion etching (RIE) etch profiles, oxygen and H2O uptake in SiLK low-k films, solvent uptake in low-k dielectric films as well as susceptibility to scratching/slurry particle embodiment damage by chemical-mechanical processing.
  • Applicant has developed the following, exemplary operating parameters for planarizing low-k dielectric films:
  • For planarizing Dow Corning Porous SiLK (porous methyl silsequioxane; k=2.2)
      • Argon ion beam currents in the range of 100 mA/cm2 to 150 mA/cm2 (maximum of 300 mA/cm2)
      • Accelerating voltages in the range of 300 eV to 400 eV (maximum of 650 eV)
      • Angle of Incidence of Argon Beam to stage/sample surface in the range of 7 degrees up to 21 degrees (93 degrees from normal to 79 degrees from normal);
      • Chuck temperature control in the range of 0 degrees centigrade to 15 degrees centigrade (maximum)
      • Heat transfer/heat conduction to liquid cooled chuck; Silicone based grease such as MUX for minimum out-gassing and greatest heat dissipation
      • Stage rotation: about 10 rpm
      • Charge Neutralizing Current: about 300 uA (maximum)
      • Argon Magnet Voltage Level: in the range of about 0.80 mV to 0.85 mVolts
        These parameters will result in an etch rate in the range of 250 A/minute to 440 A/minute, depending on incident angle and beam current.
  • For planarizing Dow Corning SiLK (k=2.65)
      • Beam Currents in the range of 150 mA/cm2 to 250 mA/cm cm2
      • Accelerating voltages in the range of 400 eV to 500 eV (maximum of 650 eV)
      • Angle of Incidence of Argon Beam to stage/sample surface in the range of 7 degrees up to 21 degrees (93 degrees from normal to 79 degrees from normal);
      • Chuck temperature control in the range of 0 degrees centigrade to 15 degrees centigrade (maximum)
      • Heat transfer/heat conduction to liquid cooled chuck; Silicone based grease such as MUX for minimum out-gassing and greatest heat dissipation
      • Stage rotation; about 10 rpm
      • Charge Neutralizing Current: about 300 uA (maximum)
      • Argon Magnet Voltage Level; in the range of about 0.80 to 0.85 mV
        These parameters will result in an etch rate in the range of 225 A/minute to 400 A/minute, depending on incident angle and beam current.
  • Still with reference to FIG. 2, assembly 57 is used to position sapphire detector 56 proximate the upper surface of remaining oxide layer 38. Spectrophotometer 58 is adjusted to sense nitride, by optimizing the signal to detect silicon nitride. A selected gas 51, for example a mixture of CF4 and oxygen, is introduced into chamber 48 and the parameters of ion beam milling source 52 and platen 46 are adjusted in a conventional manner to optimize the etching of oxide and copper. The mixture of CF4 gas and oxygen will preferentially etch oxide and nitride without attacking copper. Ion beam milling would mill copper at one rate while ionized gas would preferentially etch oxide and nitride. Milling source 52 is operated to remove the remaining portion of oxide layer 40 along with the copper in copper-filled via 40. When photospectrometer 58 detects nitride from nitride layer 38, the process is terminated.
  • With reference now to FIG. 3, photospectrometer 58 is adjusted to sense oxide by optimizing the signal to sense oxygen or silicon but NOT nitride, and the parameters of gas 51, milling source 52 and platen 46 are optimized in a conventional manner to etch nitride and copper. Nitride layer 38A is thus removed along with copper conductor 38C, exposing the upper surface of remaining oxide layer 38 and copper filled via 38D as shown in FIG. 3.
  • It will be understood that following each etching step, assembly 54 and platen 46 are manipulated to place semiconductor structure 16 and endpoint detector 56 in the optimum physical position for the next etch step. Endpoint detector 56 can be placed directly within the ion beam of milling source 52 proximate the areas of interest being etched. The temperature, angle and position of platen 46 are adjusted to optimize the etch process for the materials being etched.
  • With reference now to FIG. 4, photospectrometer 58 is adjusted to sense a low-k dielectric film such as SiLK by optimizing for sensing a carbon peak, the principal elemental component of an organic low-k film. By sensing the appropriate principal elemental component, i.e. for conventional oxides, this would be oxygen or silicon; for silicon nitride, this would be nitrogen, the above-described etching processes are used to remove the remaining portion of oxide layer 38, nitride layer 36 and the copper connectors and copper-filled vias there through, exposing low-k dielectric layer 36A and copper-filled via 36D as shown in FIG. 4.
  • It will be appreciated from a consideration of the process description and drawings that the etching systems and processes that are the subject of the present invention yield highly planar exposed surfaces, regardless of the materials being etched. Further, the processes can be controlled to accurately etch very thin films and very small depths within films, thus enabling the exposure of substantially any desired layers or features within a semiconductor structure.
  • With reference now to FIGS. 5 and 6, structure 16 is shown with the above-described process steps repeated to expose low-k dielectric layers 34A (FIG. 5) and 32A (FIG. 6), respectively. The etching processes used to remove the intermediate nitride layers and copper metallurgy are substantially identical to those described above. Endpoint detector 56 and platen 46 are repositioned intermediate each etching step, in the manner described above, to optimize both the etching process and the endpoint detection.
  • With reference now to FIG. 7, semiconductor structure 16 is shown with all of back-end structure 18 removed excepting a remaining portion of layer 30A overlying layer 28A, and the associated metallurgy 30D, 28B and FET gate 28C.
  • Methodology for Unlayering/Reworking Individual Die and Wafer Fragments with Low-K Dielectric Films Using Mechanical Polish/Removal of Metal/Metal Interconnects Combined with RIE or Plasma Deprocessing Steps:
  • The following methods allow for unlayering/deprocessing of Low-K spun-on dielectric films where each low k dielectric level has been built (ie. Hardmask, CMP endstop layer is intact) before unlayering/deprocessing is initiated.
  • Method (a)
  • Using a RIE etch (ie. CF4 process gas) or wet etch, remove nitride cap layer and hardmask (ie. Applied Materials BLOK™). Next remove spun-on Low-K Dielectric with Oxygen Plasma Next deposit an oxide or tetraothrosilicate (TEOS) CVD layer to permit mechanical polish removal of metal/metal interconnection through the underlying SiLK layer to the hardmask or cap nitride layer. Next, deposit replacement cap layer. Resume normal spun on low k Dielectric film deposition.
  • Method (b)
  • Using a RIE etch (ie. CF4 process gas) or wet etch, remove nitride cap and hard mask (ie. Applied Materials BLOK™). Partially remove spun on low-K Film to top level of metal interconnection. Deposit oxide or CVD tetraorthosilicate insulator film in gap formerly occupied by low k spun-on dielectric film. Mechanically polish/remove via level/metal interconnection and metal level itself. Deposit CVD nitride cap layer. Resume normal spun-on low k dielectric film (ie. Dow Corning SiLK) film deposition.
  • Method (c)
  • Mechanically polish to remove the nitride cap and hardmask layer overlying metal and low-K spun on dielectric film. Remove spun-on low K dielectric film with oxygen plasma process. Deposit oxide layer or CVD tetraorthosilicate (TEOS) dielectric film in the gap formerly occupied by spun-on Low-k dielectric film. Mechanically polish to remove metal level along with deposited oxide/TEOS layer through underlying nitride cap and stop on hardmask. Deposit new CVD nitride cap layer. Resume normal spun-on low k dielectric film (ie. Dow Corning SiLK) deposition.
  • Method (d)
  • Mechanically polish to remove nitride cap and hardmask layer overlying metal and low-K spun on dielectric film. Partially remove spun-on low K dielectric film with oxygen plasma process to top of metal interconnection level. Deposit oxide layer or CVD tetraorthosilicate (TEOS) dielectric film in gap formerly occupied by spun-on Low-k dielectric film. Mechanically polish/remove metal level lines along with deposited oxide/TEOS layer. Deposit new CVD nitride cap layer. Resume normal spun-on low k dielectric film (ie. Dow Corning SiLK) deposition.
  • Method (e)
  • Use RIE (ie. CF4 process gas) or wet etch to remove nitride cap and hardmask layer (ie. BLOK ™). Alternatively, mechanically polish to remove nitride cap layer and hardmask layer (ie. BLOK™). Immerse sample in copper wet etch bath in order to remove metal and metal interconnection levels. Next, wet etch barrier liner (ie. Ta/TaN) material. Next, Plasma etch with oxygen process gas to remove low-k spun on dielectric film. Mechanically polish/remove residual metal interconnection layer and stop at hardmask material. Deposit replacement nitride cap layer. Resume normal spun-on low k dielectric film (ie. Dow Corning SiLK) deposition. Complete BEOL build cycle.
  • Method (f)
  • Use RIE (ie. CF4 process gas) or wet etch to remove nitride cap and hardmask layer (ie. BLOK ™). Alternatively, mechanical polish removal of the cap nitride and hardmask could be substituted, instead. First, expose wafer to a slow copper etchant to controllably remove the copper metal wiring levels and copper interconnection without etching into the underlying copper metal lands. Once the copper lands and copper interconnection levels are etched away (using a timed etch process), employ a different chemical etchant to remove the barrier liner metallurgy (typically a tantalum/tantalum nitride material) without attacking the underlying copper metal wiring. Next, perform an oxygen plasma etch to remove the spun on low-k dielectric film (ie. Dow Corning SiLK film) which will selectively stop on the underlying silicon nitride cap layer. Mechanically polish off the cap nitride along with any residual copper metallurgy and tantalum/tantalum nitride liner material. Redeposit CVD nitride cap layer. Resume normal spun-on low k dielectric film (ie. Dow Corning SiLK) deposition. Complete BEOL build cycle.
  • There have thus been described systems and methods using ion beam etching with endpoint detection for selectively etching multi-layer structures on semiconductor devices. The systems and methods of the present invention enable highly selective and controllable planar removal of different types of materials, including oxides, nitrides, metals and low-k dielectrics such as SiLK. They further permit such removal without damaging the soft, fragile, low-k dielectric materials. There have further been a set of processes for deprocessing spun-on low-k structures with copper metallurgy/copper interconnections.
  • The present invention can be used to facilitate, for example, the reworking and/or evaluation of semiconductor devices, particularly those incorporating low-k dielectric films. The invention thus has application in the manufacture, rework and analysis of semiconductor devices.

Claims (22)

1-6. (canceled)
15. A system for delayering a semiconductor structure including a first layer of material overlaying a second layer of low-k dielectric film, comprising:
a processing chamber;
an ion beam milling source in said processing chamber for generating a beam of ions to mill said semiconductor structure;
a platen in said processing chamber for supporting said semiconductor structure in said beam of ions;
a crystal endpoint detector in said processing chamber;
a photospectrometer outside of said processing chamber;
means for connecting said crystal endpoint detector to said photospectrometer; and
means for positioning said crystal endpoint detector proximate said platen to monitor milling of said semiconductor structure.
16. A system in accordance with claim 15 wherein said crystal endpoint detector comprises a sapphire crystal.
17. A system in accordance with claim 15 and further including means for introducing a gas into said processing chamber.
18. A system in accordance with claim 15 wherein said ion beam milling source comprises an Argon ion beam-milling source.
19. A system in accordance with claim 18 and further comprising a charge-neutralizing filament positioned to enclose the Argon ion beam when said Argon ion beam milling source is in operation.
20. A system in accordance with claim 15 wherein and further including means for cooling said semiconductor structure.
21-27. (canceled)
28. A system in accordance with claim 15 wherein said platen comprises a liquid-cooled platen.
29. A system in accordance with claim 28 wherein said liquid-cooled platen is capable of cooling in a range of −15 to +35 degrees centigrade.
30. A system in accordance with claim 15 wherein said ion beam milling source comprises an inert noble gas.
31. A system in accordance with claim 15 wherein said inert noble gas is selected from the group consisting of helium, neon, xenon, and radon.
32. A system in accordance with claim 15 further including a circumferential charge neutralizing filament surrounding said ion beam milling source.
33. A system in accordance with claim 15 wherein said crystal endpoint detector is positioned within said beam of ions for milling said semiconductor structure.
34. A system for delayering a semiconductor structure including a first layer of material overlaying a second layer of low-k dielectric film, comprising:
a processing chamber;
an ion beam milling source in said processing chamber for generating a beam of ions to mill said semiconductor structure;
a platen in said processing chamber for supporting said semiconductor structure in said beam of ions; and
a fiber optic photospectrometer endpoint detector system of said processing chamber having a crystal endpoint detector residing within said beam of ions for milling said semiconductor structure.
35. A system for delayering a semiconductor structure including a first layer of material overlaying a second layer of low-k dielectric film, comprising:
a processing chamber;
an ion beam milling source in said processing chamber for generating a beam of ions to mill said semiconductor structure;
a platen in said processing chamber for supporting said semiconductor structure in said beam of ions;
a sapphire crystal endpoint detector in said processing chamber;
a photospectrometer outside of said processing chamber;
means for connecting said sapphire crystal endpoint detector to said photospectrometer; and
means for positioning said sapphire crystal endpoint detector proximate said platen to monitor milling of said semiconductor structure,
wherein said sapphire crystal endpoint detector resides within said beam of ions for milling said semiconductor structure.
36. A system in accordance with claim 35 wherein said ion beam milling source comprises an inert noble gas selected from the group consisting of argon, helium, neon, xenon, and radon.
37. A system in accordance with claim 35 further including a circumferential charge neutralizing filament surrounding said ion beam milling source.
38. A system in accordance with claim 35 wherein said means for connecting said sapphire crystal endpoint detector to said photospectrometer comprises a fiber optic cable.
39. A system in accordance with claim 38 wherein said fiber optic cable is connected at a first end to said sapphire crystal endpoint detector within said processing chamber and at a second end to said photospectrometer outside of said processing chamber.
40. A system in accordance with claim 38 further including a ferro-fluidic vacuum feed-through accommodating a stainless steel tube housing said fiber optic cable.
41. A system in accordance with claim 40 wherein said stainless steel tube housing said fiber optic cable are motor operated, said method further including an electromechanical positioning device for positioning said sapphire crystal endpoint detector to regions of interest on semiconductor substrate.
US11/205,522 2002-10-24 2005-08-17 Method of reworking structures incorporating low-k dielectric materials Abandoned US20050285106A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/205,522 US20050285106A1 (en) 2002-10-24 2005-08-17 Method of reworking structures incorporating low-k dielectric materials

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/280,513 US7008803B2 (en) 2002-10-24 2002-10-24 Method of reworking structures incorporating low-k dielectric materials
US11/205,522 US20050285106A1 (en) 2002-10-24 2005-08-17 Method of reworking structures incorporating low-k dielectric materials

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/280,513 Division US7008803B2 (en) 2002-10-24 2002-10-24 Method of reworking structures incorporating low-k dielectric materials

Publications (1)

Publication Number Publication Date
US20050285106A1 true US20050285106A1 (en) 2005-12-29

Family

ID=32106961

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/280,513 Expired - Fee Related US7008803B2 (en) 2002-10-24 2002-10-24 Method of reworking structures incorporating low-k dielectric materials
US11/205,522 Abandoned US20050285106A1 (en) 2002-10-24 2005-08-17 Method of reworking structures incorporating low-k dielectric materials

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/280,513 Expired - Fee Related US7008803B2 (en) 2002-10-24 2002-10-24 Method of reworking structures incorporating low-k dielectric materials

Country Status (1)

Country Link
US (2) US7008803B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080156987A1 (en) * 2006-12-28 2008-07-03 International Business Machines Corporation Method of tem sample preparation for electron holography for semiconductor devices
US20150160261A1 (en) * 2013-12-09 2015-06-11 International Business Machines Corporation High frequency capacitance-voltage nanoprobing characterization
US20160035633A1 (en) * 2013-03-27 2016-02-04 International Business Machines Corporation Low energy collimated ion milling of semiconductor structures
US9279849B2 (en) 2013-12-09 2016-03-08 International Business Machines Corporation Atom probe tomography sample preparation for three-dimensional (3D) semiconductor devices
CN106124549A (en) * 2016-07-06 2016-11-16 天津工业大学 A kind of method characterizing fiber radially different depth chemical constitution
US9534299B2 (en) 2011-11-10 2017-01-03 Techinsights Inc. Method and system for ion beam delayering of a sample and control thereof
US10338002B1 (en) * 2016-02-01 2019-07-02 Kla-Tencor Corporation Methods and systems for selecting recipe for defect inspection
US20220005669A1 (en) * 2018-11-21 2022-01-06 Techinsights Inc. Ion beam delayering system and method, topographically enhanced delayered sample produced thereby, and imaging methods and systems related thereto

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7008803B2 (en) * 2002-10-24 2006-03-07 International Business Machines Corporation Method of reworking structures incorporating low-k dielectric materials
US6900137B2 (en) * 2003-03-28 2005-05-31 International Business Machines Corporation Dry etch process to edit copper lines
US20080003926A1 (en) * 2004-09-29 2008-01-03 Fujifilm Corporation Method of Grinding Multilayer Body and Method of Manufacturing Solid State Image Pickup Device
US7208325B2 (en) * 2005-01-18 2007-04-24 Applied Materials, Inc. Refreshing wafers having low-k dielectric materials
US8189292B2 (en) * 2008-12-24 2012-05-29 Hitachi Global Storage Technologies Netherlands B.V. Method for manufacturing a magnetic write head having a write pole with a trailing edge taper using a Rieable hard mask
US20100270262A1 (en) * 2009-04-22 2010-10-28 Applied Materials, Inc. Etching low-k dielectric or removing resist with a filtered ionized gas
JP5737922B2 (en) * 2010-12-14 2015-06-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Manufacturing method of semiconductor device
US9064811B2 (en) * 2013-05-28 2015-06-23 Fei Company Precursor for planar deprocessing of semiconductor devices using a focused ion beam
US10003014B2 (en) * 2014-06-20 2018-06-19 International Business Machines Corporation Method of forming an on-pitch self-aligned hard mask for contact to a tunnel junction using ion beam etching
US10707166B2 (en) 2016-10-04 2020-07-07 International Business Machines Corporation Advanced metal interconnects
US10431464B2 (en) 2016-10-17 2019-10-01 International Business Machines Corporation Liner planarization-free process flow for fabricating metallic interconnect structures
US10242872B2 (en) 2017-03-21 2019-03-26 International Business Machines Corporation Rework of patterned dielectric and metal hardmask films
JP6968194B2 (en) 2017-04-04 2021-11-17 テスカン ブルノ エスアールオーTESCAN BRNO s.r.o. A method of etching one or more layers of a mixture of metals and dielectrics in a semiconductor device.
US10546719B2 (en) 2017-06-02 2020-01-28 Fei Company Face-on, gas-assisted etching for plan-view lamellae preparation
US10522398B2 (en) 2017-08-31 2019-12-31 International Business Machines Corporation Modulating metal interconnect surface topography
CN107731746B (en) * 2017-11-16 2020-03-13 长江存储科技有限责任公司 Semiconductor characteristic analysis method for preventing tungsten plug corrosion
US10672653B2 (en) 2017-12-18 2020-06-02 International Business Machines Corporation Metallic interconnect structures with wrap around capping layers
US10658235B2 (en) 2018-06-21 2020-05-19 International Business Machines Corporation Rework for metal interconnects using etch and thermal anneal
US11664238B1 (en) * 2019-08-30 2023-05-30 National Technology & Engineering Solutions Of Sandia, Llc Plasma-based method for delayering of circuits
US11171048B2 (en) * 2020-03-12 2021-11-09 Fei Company Adaptive endpoint detection for automated delayering of semiconductor samples

Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4457803A (en) * 1981-12-18 1984-07-03 Tokyo Shibaura Denki Kabushiki Kaisha Processing method using a focused ion beam
US4569592A (en) * 1981-12-11 1986-02-11 Hitachi, Ltd. Plasma monitor
US4609809A (en) * 1983-03-16 1986-09-02 Hitachi, Ltd. Method and apparatus for correcting delicate wiring of IC device
US4639301A (en) * 1985-04-24 1987-01-27 Micrion Limited Partnership Focused ion beam processing
US4682566A (en) * 1979-04-06 1987-07-28 Applied Materials, Inc. Evacuated equipment
US4733091A (en) * 1984-09-19 1988-03-22 Applied Materials, Inc. Systems and methods for ion implantation of semiconductor wafers
US4734158A (en) * 1987-03-16 1988-03-29 Hughes Aircraft Company Molecular beam etching system and method
US4776925A (en) * 1987-04-30 1988-10-11 The Trustees Of Columbia University In The City Of New York Method of forming dielectric thin films on silicon by low energy ion beam bombardment
US4874947A (en) * 1988-02-26 1989-10-17 Micrion Corporation Focused ion beam imaging and process control
US4938992A (en) * 1988-01-07 1990-07-03 Varian Associates, Inc. Methods for thermal transfer with a semiconductor
US5504340A (en) * 1993-03-10 1996-04-02 Hitachi, Ltd. Process method and apparatus using focused ion beam generating means
US5825035A (en) * 1993-03-10 1998-10-20 Hitachi, Ltd. Processing method and apparatus using focused ion beam generating means
US5916424A (en) * 1996-04-19 1999-06-29 Micrion Corporation Thin film magnetic recording heads and systems and methods for manufacturing the same
US5948217A (en) * 1996-12-20 1999-09-07 Intel Corporation Method and apparatus for endpointing while milling an integrated circuit
US6136685A (en) * 1997-06-03 2000-10-24 Applied Materials, Inc. High deposition rate recipe for low dielectric constant films
US6180976B1 (en) * 1999-02-02 2001-01-30 Conexant Systems, Inc. Thin-film capacitors and methods for forming the same
US6214738B1 (en) * 1998-12-25 2001-04-10 Canon Kabushiki Kaisha Method for producing narrow pores and structure having the narrow pores, and narrow pores and structure produced by the method
US6281025B1 (en) * 1999-09-30 2001-08-28 Advanced Micro Devices, Inc. Substrate removal as a function of SIMS analysis
US6288357B1 (en) * 2000-02-10 2001-09-11 Speedfam-Ipec Corporation Ion milling planarization of semiconductor workpieces
US6366346B1 (en) * 1998-11-19 2002-04-02 Applied Materials, Inc. Method and apparatus for optical detection of effluent composition
US6549279B2 (en) * 2001-04-09 2003-04-15 Speedfam-Ipec Corporation Method and apparatus for optical endpoint calibration in CMP
US6565720B1 (en) * 2000-05-31 2003-05-20 Advanced Micro Devices, Inc. Substrate removal as a function of sputtered ions
US6630395B1 (en) * 2002-10-24 2003-10-07 International Business Machines Corporation Methods for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials
US6746961B2 (en) * 2001-06-19 2004-06-08 Lam Research Corporation Plasma etching of dielectric layer with etch profile control
US7008803B2 (en) * 2002-10-24 2006-03-07 International Business Machines Corporation Method of reworking structures incorporating low-k dielectric materials

Patent Citations (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682566A (en) * 1979-04-06 1987-07-28 Applied Materials, Inc. Evacuated equipment
US4569592A (en) * 1981-12-11 1986-02-11 Hitachi, Ltd. Plasma monitor
US4457803A (en) * 1981-12-18 1984-07-03 Tokyo Shibaura Denki Kabushiki Kaisha Processing method using a focused ion beam
US4609809B1 (en) * 1983-03-16 1993-01-26 Hitachi Ltd
US4609809A (en) * 1983-03-16 1986-09-02 Hitachi, Ltd. Method and apparatus for correcting delicate wiring of IC device
US4733091A (en) * 1984-09-19 1988-03-22 Applied Materials, Inc. Systems and methods for ion implantation of semiconductor wafers
US4639301A (en) * 1985-04-24 1987-01-27 Micrion Limited Partnership Focused ion beam processing
US4639301B1 (en) * 1985-04-24 1989-06-27 Micrion Limited Partnership Focused ion beam processing
US4639301B2 (en) * 1985-04-24 1999-05-04 Micrion Corp Focused ion beam processing
US4734158A (en) * 1987-03-16 1988-03-29 Hughes Aircraft Company Molecular beam etching system and method
US4776925A (en) * 1987-04-30 1988-10-11 The Trustees Of Columbia University In The City Of New York Method of forming dielectric thin films on silicon by low energy ion beam bombardment
US4938992A (en) * 1988-01-07 1990-07-03 Varian Associates, Inc. Methods for thermal transfer with a semiconductor
US4874947A (en) * 1988-02-26 1989-10-17 Micrion Corporation Focused ion beam imaging and process control
US5504340A (en) * 1993-03-10 1996-04-02 Hitachi, Ltd. Process method and apparatus using focused ion beam generating means
US5825035A (en) * 1993-03-10 1998-10-20 Hitachi, Ltd. Processing method and apparatus using focused ion beam generating means
US5916424A (en) * 1996-04-19 1999-06-29 Micrion Corporation Thin film magnetic recording heads and systems and methods for manufacturing the same
US5948217A (en) * 1996-12-20 1999-09-07 Intel Corporation Method and apparatus for endpointing while milling an integrated circuit
US6136685A (en) * 1997-06-03 2000-10-24 Applied Materials, Inc. High deposition rate recipe for low dielectric constant films
US6366346B1 (en) * 1998-11-19 2002-04-02 Applied Materials, Inc. Method and apparatus for optical detection of effluent composition
US6214738B1 (en) * 1998-12-25 2001-04-10 Canon Kabushiki Kaisha Method for producing narrow pores and structure having the narrow pores, and narrow pores and structure produced by the method
US6180976B1 (en) * 1999-02-02 2001-01-30 Conexant Systems, Inc. Thin-film capacitors and methods for forming the same
US6281025B1 (en) * 1999-09-30 2001-08-28 Advanced Micro Devices, Inc. Substrate removal as a function of SIMS analysis
US6288357B1 (en) * 2000-02-10 2001-09-11 Speedfam-Ipec Corporation Ion milling planarization of semiconductor workpieces
US6565720B1 (en) * 2000-05-31 2003-05-20 Advanced Micro Devices, Inc. Substrate removal as a function of sputtered ions
US6549279B2 (en) * 2001-04-09 2003-04-15 Speedfam-Ipec Corporation Method and apparatus for optical endpoint calibration in CMP
US6746961B2 (en) * 2001-06-19 2004-06-08 Lam Research Corporation Plasma etching of dielectric layer with etch profile control
US6630395B1 (en) * 2002-10-24 2003-10-07 International Business Machines Corporation Methods for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials
US7008803B2 (en) * 2002-10-24 2006-03-07 International Business Machines Corporation Method of reworking structures incorporating low-k dielectric materials

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7560692B2 (en) * 2006-12-28 2009-07-14 International Business Machines Corporation Method of TEM sample preparation for electron holography for semiconductor devices
US20080156987A1 (en) * 2006-12-28 2008-07-03 International Business Machines Corporation Method of tem sample preparation for electron holography for semiconductor devices
US20170089813A1 (en) * 2011-11-10 2017-03-30 Techinsights Inc. Method and system for ion beam delayering of a sample and control thereof
US11214874B2 (en) 2011-11-10 2022-01-04 Techinsights Inc. Method and system for ion beam delayering of a sample and control thereof
US10689763B2 (en) * 2011-11-10 2020-06-23 Techinsights Inc. Method and system for ion beam delayering of a sample and control thereof
US10550480B2 (en) 2011-11-10 2020-02-04 Techinsights Inc. Method and system for ion beam delayering of a sample and control thereof
US9534299B2 (en) 2011-11-10 2017-01-03 Techinsights Inc. Method and system for ion beam delayering of a sample and control thereof
CN106435595A (en) * 2011-11-10 2017-02-22 泰科英赛科技有限公司 System and method for de-engineering a sample to reverse engineer a sample
US20160035633A1 (en) * 2013-03-27 2016-02-04 International Business Machines Corporation Low energy collimated ion milling of semiconductor structures
US9170273B2 (en) * 2013-12-09 2015-10-27 Globalfoundries U.S. 2 Llc High frequency capacitance-voltage nanoprobing characterization
US9279849B2 (en) 2013-12-09 2016-03-08 International Business Machines Corporation Atom probe tomography sample preparation for three-dimensional (3D) semiconductor devices
US20150160261A1 (en) * 2013-12-09 2015-06-11 International Business Machines Corporation High frequency capacitance-voltage nanoprobing characterization
US10338002B1 (en) * 2016-02-01 2019-07-02 Kla-Tencor Corporation Methods and systems for selecting recipe for defect inspection
CN106124549A (en) * 2016-07-06 2016-11-16 天津工业大学 A kind of method characterizing fiber radially different depth chemical constitution
US20220005669A1 (en) * 2018-11-21 2022-01-06 Techinsights Inc. Ion beam delayering system and method, topographically enhanced delayered sample produced thereby, and imaging methods and systems related thereto

Also Published As

Publication number Publication date
US7008803B2 (en) 2006-03-07
US20040082176A1 (en) 2004-04-29

Similar Documents

Publication Publication Date Title
US7008803B2 (en) Method of reworking structures incorporating low-k dielectric materials
CN100595891C (en) Damage-free ashing process and system for post low-k etch
US7595005B2 (en) Method and apparatus for ashing a substrate using carbon dioxide
US6150272A (en) Method for making metal plug contacts and metal lines in an insulating layer by chemical/mechanical polishing that reduces polishing-induced damage
US6350694B1 (en) Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials
CN100399542C (en) Interconnect structure and method of forming the same
US7750479B2 (en) Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair
US20060102197A1 (en) Post-etch treatment to remove residues
JPH0845914A (en) Method of removing resist form semiconductor wafer with substrate and resist removing device
US20070105247A1 (en) Method And Apparatus For Detecting The Endpoint Of A Chemical-Mechanical Polishing Operation
US6037278A (en) Method of manufacturing semiconductor devices having multi-level wiring structure
US7220677B2 (en) WAT process to avoid wiring defects
US7172962B2 (en) Method of manufacturing a semiconductor device
US6629879B1 (en) Method of controlling barrier metal polishing processes based upon X-ray fluorescence measurements
US6179691B1 (en) Method for endpoint detection for copper CMP
US6465345B1 (en) Prevention of inter-channel current leakage in semiconductors
US20050136681A1 (en) Method and apparatus for removing photoresist from a substrate
US10566231B2 (en) Interconnect formation with chamferless via, and related interconnect
US6809032B1 (en) Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques
US20040245636A1 (en) Full removal of dual damascene metal level
US7815815B2 (en) Method and apparatus for processing the peripheral and edge portions of a wafer after performance of a surface treatment thereon
US6784107B1 (en) Method for planarizing a copper interconnect structure
JPH1070097A (en) Method of planarization of semiconductor substrate
US6780783B2 (en) Method of wet etching low dielectric constant materials
US20230402427A1 (en) Heterogenous bonding layers for direct semiconductor bonding

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KANE, TERENCE L.;ENG, CHUNG-PING;ENGEL, BRETT H.;AND OTHERS;REEL/FRAME:016896/0065;SIGNING DATES FROM 20021010 TO 20021011

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION