US20060006507A1 - Silicon building block architecture with flex tape - Google Patents

Silicon building block architecture with flex tape Download PDF

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US20060006507A1
US20060006507A1 US11/228,662 US22866205A US2006006507A1 US 20060006507 A1 US20060006507 A1 US 20060006507A1 US 22866205 A US22866205 A US 22866205A US 2006006507 A1 US2006006507 A1 US 2006006507A1
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integrated circuit
power
flex tape
flexible
signal
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US11/228,662
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Dong Zhong
Yuan-Liang Li
Jiangqi He
Jung Kang
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Definitions

  • the present invention relates generally to the field of integrated circuit packaging. Specifically, this invention relates to the efficient power and signal delivery associated with integrated circuit packaging.
  • FIG. 1 illustrates one cross sectional view of an integrated circuit packaging scheme using flex tape for signal ingress/egress and power delivery, in accordance with one embodiment.
  • FIG. 2 illustrates a different cross sectional view of the integrated circuit packaging shown in FIG. 1 .
  • FIG. 3 illustrates a top view of an integrated circuit utilizing flex tape for both power and signal ingress/egress.
  • FIG. 4 illustrate power delivery via flex tape, in accordance with another embodiment.
  • FIG. 5 illustrates power delivery from above through flex tape material, in accordance with one embodiment.
  • FIG. 6 illustrates a more detailed of the flex tape providing power in FIG. 5 .
  • FIGS. 7A and 7B illustrate cross sectional views of integrated circuits, including power delivery to the integrated circuits, in accordance with multiple embodiments.
  • FIG. 8 illustrates a power providing flex tape in accordance with another embodiment.
  • FIG. 9 illustrates flex tape enabled signal ingress/egress in a Silicon Building Block (SiBB) design.
  • SiBB Silicon Building Block
  • FIG. 10 illustrates an architecture for a flex tape for signal delivery, in accordance with one embodiment.
  • FIG. 11 illustrates a flex tape signaling design in accordance with another embodiment.
  • FIG. 12 illustrates a flex tape signaling design in accordance with yet another embodiment.
  • FIG. 13 illustrates a flex tape signaling design that additionally provides power, in accordance with one embodiment.
  • FIG. 14 illustrates a flex tape architecture in accordance with another embodiment.
  • FIG. 15 illustrates a coaxial design for signals in flex tape, in accordance with one embodiment.
  • FIG. 16 illustrates a coplanar waveguide design for signal traces in a flex tape, in accordance with one embodiment.
  • FIG. 17 illustrates a grounded coplanar waveguide design for signal traces in a flex tape, in accordance with one embodiment.
  • flex tape as used herein is meant to include any flexible substrate material supporting conductors or conductor materials.
  • die and “integrated circuit” as used herein are interchangeable, and are meant to include semiconductor comprising an electronic circuit design.
  • power layer and “ground layer” are meant to imply layers of conductors or conductor materials utilized to provide a reference voltage signal. While generally the term power layer is meant to imply a higher reference level than a ground layer, this is not a requirement. The actual voltage reference level is technology dependant.
  • metal line trace, signal trace, wire, conductor, signal path and signaling medium are all related. The related terms listed above, are generally interchangeable, and appear in order from specific to general. In this field, metal lines are sometimes referred to as traces, wires, lines, interconnect or simply metal. Metal lines, generally aluminum (Al), copper (Cu) or an alloy of Al and Cu, are conductors that provide signal paths for coupling or interconnecting, electrical circuitry. Conductors other than metal are available in microelectronic devices.
  • doped polysilicon doped single-crystal silicon (often referred to simply as diffusion, regardless of whether such doping is achieved by thermal diffusion or ion implantation), titanium (Ti), molybdenum (Mo), and refractory metal suicides are examples of other conductors
  • FIGS. 1-3 illustrate an integrated circuit packaging scheme using flex tape for signal ingress/egress and power delivery, in accordance with one embodiment.
  • integrated circuit 110 has a number of input/output bumps 120 located at the periphery that are used to provide signal ingress/egress to/from integrated circuit 110 through first flex tape 130 .
  • Signal ingress/egress may be facilitated e.g. by optical technologies such as optical waveguides or electromechanical technologies. In alternate embodiments, signal ingress/egress may be facilitated via other signaling techniques.
  • FIG. 2 illustrates a cross sectional view of the integrated circuit packaging shown in FIG. 1 . This cross section view is shown with respect to cut line AB of FIG. 1 . Periphery integrated circuit bumps 140 are utilized to provide power to the integrated circuit 110 through second flex tape 150 .
  • FIG. 3 illustrates a top view of an integrated circuit utilizing flex tape for both power and signal ingress/egress.
  • the view shown in FIG. 3 illustrates the flexible input/output signal routing substrate, or simply signal flex tape, 130 and the flexible power delivery substrate, or simply power flex tape, 150 of FIGS. 1 and 2 , respectively.
  • Integrated circuit 110 is shown with four flex tapes 130 and 150 connected to peripheral signals bumps 120 and peripheral power bumps 140 for the integrated circuit 110 .
  • Two signal flex tapes 130 provide signal ingress/egress to the integrated circuit 110 .
  • Two power flex tapes 150 are used to provide power delivery to the integrated circuit 110 .
  • all four flex tapes are used to provide signal ingress and egress to/from and power to the integrated circuit.
  • peripheral die bumps are used for signal ingress/egress. Die bumps away from the periphery, e.g. internal die bumps, of the die are used for power delivery to the die.
  • FIG. 4 illustrate power delivery via flex tape, in accordance with another embodiment. As shown, power delivery is provided via multiple paths in this embodiment.
  • Rigid substrate material 430 provides power to integrated circuit 410 from the motherboard 460 through vias 450 to internal die bumps 420 .
  • flex tape material 440 provides power to integrated circuit 410 through periphery die bumps 425 .
  • FIG. 5 illustrates power delivery from above through flex tape material, in accordance with one embodiment.
  • power delivery to the integrated circuit 510 of FIG. 5 is performed from above.
  • power is delivered from a power source from above via a connector 530 .
  • the power is then routed through a board 520 to the board's edge where the board is connected to connectors 540 .
  • the power is delivered through the connectors 540 to flex tape 550 .
  • the power is delivered by the flex tape to the integrated circuit 510 via die bumps 560 .
  • the integrated circuit 510 is mounted below the board 520 .
  • stiffeners 570 that are connected to flex tape 550 .
  • these stiffeners 570 are used to provide rigidity to the flex tape 550 .
  • the rigidity facilities handling of the package.
  • the stiffeners 570 provide mount points for the package to be mounted to the motherboard 580 .
  • such a design advantageously allows spacing between the flex tape and the motherboard for placement of landside capacitors 590 , to be discussed in more detail below.
  • FIG. 6 illustrates a more detailed view of the flex tape providing power in FIG. 5 .
  • flex tape 550 used to provide power to an integrated circuit is a “two layer” flex tape.
  • the power is provided via a connector to a board 520 .
  • This board provides power to the flex tape 550 through connector 540 .
  • the first conductive layer 552 provides a first reference voltage for the integrated circuit, e.g. V CC .
  • the second conductive layer 554 provides a second reference voltage for the integrated circuit, e.g. V SS .
  • FIGS. 7A and 7B illustrate cross sectional views of integrated circuits, including power delivery to the integrated circuits, in accordance with multiple embodiments.
  • FIG. 7A illustrates an example of a cross section as shown by line AB in the embodiment of FIG. 5 .
  • FIG. 7B illustrates a cross section of an embodiment of a three layer flex tape design, described in more detail below.
  • signal-carrying flex tape 705 is illustrated as extending out from both sides of the integrated circuit 720 .
  • the flex tape has two trace layers, one for carrying signal 707 and one for a signal return path 709 .
  • the flex tape has three traces; one trace 709 for carrying signals and two for signal return paths 707 717 .
  • micro vias 712 are utilized to provide access through the flex tape dielectric material.
  • Peripheral bumps 715 are used to provide signal ingress/egress to/from the integrated circuit 720 .
  • Interior bumps 735 on the integrated circuit 720 are utilized to provide power to the integrated circuit 720 .
  • a board 730 is utilized to provide power to the integrated circuit 720 via flex tape.
  • the integrated circuit 720 is mounted under the power providing board 730 .
  • conductive trace layer 750 is utilized to provide V SS to the integrated circuit 720 . Additionally, conductive trace layer 765 is utilized to provide V CC to integrated circuit 720 . In the illustrated embodiment of FIG. 7B , an additional layer is utilized to provide to provide power paths to the integrated circuit 720 . Illustrated in FIGS. 7A and 7B are micro vias 760 utilized to provide an access path through the substrate to interior bumps 735 utilized to carry power to integrated circuit 720 . Heatsink 740 provides a traditional focus on carrying away excess heat, but also provides a power conduit, such as a voltage regulator module (not shown) to board 730 . Landside capacitors 775 are utilized to reduce first and second voltage droop.
  • a rigid substrate, socket and interconnects or power planes in the motherboard were utilized in the packaging of an IC.
  • the packaging of the IC would need to be larger than otherwise required in order to support the land side capacitors.
  • the use of a board and flex tape design for power delivery provides room for the design to have land side capacitors without requiring an increase in the overall packaging size.
  • FIG. 8 illustrates a power providing flex tape in accordance with another embodiment.
  • an additional reference layer is advantageously provided.
  • the flex tape will have certain parasitic inductance and/or resistances associated with it. As a result of these factors, depending on the power deliver requirements, a two-layer power deliver flex tape may not be sufficient.
  • a three-layer power deliver flex tape comprising a third reference layer, may be used to provide power to an integrated circuit.
  • an inner reference layer 810 and an outer reference layer 820 are power providing reference layers.
  • a middle reference layer 830 is utilized as a ground reference layer. Between layers of reference signal layers are layers of dielectric materials 835 .
  • dielectrics When separating flex tapes for power and ground from flex tapes for signaling, dielectrics may be optimized for the particular usage. As discussed in further detail below, when high speed signaling is to be accommodated on signal traces in flex tape, it is desirable to have a low dielectric constant, low loss dielectric material.
  • low dielectric constant material refers to materials having a lower dielectric constant than silicon dioxide.
  • the dielectric material may be optimized for the power delivery.
  • high dielectric constant materials may be used between power and ground traces for improved power delivery. Examples of high dielectric constant materials include titanium dioxide with a dielectric constant of 110 .
  • FIG. 9 illustrates flex tape enabled signal ingress/egress in a Silicon Building Block (SiBB) design.
  • an integrated circuit 910 utilizes flex tape 920 for the ingress/egress of signals to the integrated circuit 910 .
  • power is delivered to the integrated circuit from the bottom via a motherboard 950 .
  • Rigid substrate 940 provides power delivery pathways 945 for the delivery of power to the integrated circuit 910 .
  • the substrate 940 may contain a relatively simplified power routing design.
  • substrate 940 may be made up of a low cost substrate material such as plastic. This simplified, inexpensive power routing design is possible because of silicon interposer 930 .
  • Silicon interposer 930 provides the ability to move detailed power delivery routing issues from substrate 940 to the silicon interposer 930 .
  • Power delivery substrates are designed to take into account inductance, resistance and capacitance effects in routing power from a power source to power bumps. This allows for maximum power transfer with minimum loss.
  • today's substrates can cost up to as much as that of the integrated circuit designs.
  • a manufacturer of integrated circuits could utilize internal expertise in silicon to create a silicon interposer that performs these critical power deliver design tasks, the resulting substrate cost can be reduced dramatically.
  • a manufacturer of an integrated circuit may have particularly strong skills in silicon processing.
  • the manufacturer that may have access to older generation silicon manufacturing equipment that, while outdated by the standards of today's leading edge integrated circuit processing, is available for other uses. This equipment and expertise can be utilized to create a silicon interposer at greatly reduced costs as compared to a substrate.
  • This equipment and expertise can be utilized to create a silicon interposer at greatly reduced costs as compared to a substrate.
  • FIG. 10 illustrates an architecture for flex tape for signal delivery, in accordance with one embodiment.
  • differential signaling is used to provide for high-speed operation of signal ingress and egress to/from integrated circuits.
  • Flex tape 1000 contains traces 1010 for differential signal routing.
  • a ground layer 1020 is introduced into the flex tape.
  • Differential signaling especially in low voltage applications which are possible due to differential signaling noise immunity, provides a number of advantages over single-ended signaling. Such advantages, in addition to noise immunity, include reduced electromagnetic interference, improvements in switching speeds and reduction in power consumption.
  • An example of differential signaling is Low Voltage Differential Signaling, which uses a 400 mV differential signal at 1.2V.
  • the ground layer 1020 provides for improved coupling to further improve performance of the differential signals.
  • dielectric materials should be used which possess low-loss and low-k, k being the average dielectric constant of the material.
  • a low-k material would be a material with a dielectric constant less then 3.
  • a low-loss material would have a loss tangent of less than 0.01. Examples of such materials are polyimides.
  • FIG. 11 illustrates a flex tape signaling design in accordance with another embodiment.
  • this embodiment of flex tape illustrates a second reference layer 1124 .
  • the addition of this second reference layer 1124 provides additional shielding. This added shielding provides for enhanced noise immunity.
  • FIG. 12 illustrates a flex tape signaling design in accordance with yet another embodiment.
  • This design utilizes traces 1210 for differential signals and two references layers 1222 1224 .
  • this design electrically couples (e.g. stitches) the ground layers 1222 1224 together at intervals.
  • ground layers 1222 1224 are stitched together utilizing stitching vias 1250 .
  • the number of stitching vias 1250 present in a design can vary.
  • the ground layers 1222 1224 are stitched together after every two sets of differential signaling pairs 1210 .
  • the use of stitching ground layers results in, among other things, better electromagnetic interference shielding.
  • FIG. 13 illustrates a flex tape signaling design that additionally provides power, in accordance with one embodiment. Traces for carrying differential signals 1310 are illustrated. As previously discussed, these traces provide high-speed ingress and egress to/from an integrated circuit. Ground layers 1320 provide shielding and coupling to allow improved operational speed of signals utilizing these traces. Additionally, in this embodiment, power layer 1330 is provided. Power layer 1330 provides power to an integrated circuit. Referring again briefly to FIG. 3 , recall that in the embodiment shown there, four flex tapes are used to provide signals and power to the design. As described in relationship to FIG. 3 , two flex tapes provides signal ingress/egress and two flex tapes provide power.
  • each flex tape contains a design as shown in FIG. 13 .
  • each of the four flex tapes can provide signal ingress/egress. This allows for a potential of up to twice as many signal I/Os to be routing using the flex tapes in designs with very high I/O signal count.
  • the flex tape design of FIG. 13 provides addition sources for power delivery to an integrated circuit. Utilizing the flex tape embodiment of FIG. 13 , all four flex tapes can also be used to provide power to an integrated circuit.
  • FIG. 14 illustrates a flex tape architecture in accordance with another embodiment.
  • traces for carrying differential signals 1412 1414 are used in the flex tape design. These traces are located between two ground layers 1420 to provide for better reference and electromagnetic interference shielding. Instead of the traces for two differential signals being arranged horizontally between the two ground layers 1420 as in the previous embodiments, the two traces 1412 1414 are arranged vertically. This vertical orientation allows for greater coupling effect between two differential signals routed on the two traces, further reducing the signals' susceptibility to noise.
  • FIG. 15 illustrates a coaxial design for signals in flex tape 1500 , in accordance with one embodiment.
  • rigid substrates have not allowed for the design of signals in a coaxial pattern.
  • propagating signals using a coaxial conductive set is practical.
  • a conductive core 1540 provides propagation path for a signal. Outside the conductive core 1540 is a dielectric layer 1530 . Outside the dielectric layer 1530 is a signal return path, via a reference layer 1520 .
  • the signal core 1530 and reference layer 1520 are positioned inside a flexible substrate 1510 .
  • Propagating signals using coaxial cable flex tapes reduces insertion loss and return loss associated with current I/O designs, while enhancing impedance control.
  • the conductive core comprises two wires and insulation, forming a twisted pair.
  • differential signaling is used in the propagation of the signal inside a coaxial design. This further improves noise immunity.
  • FIG. 16 illustrates a coplanar waveguide design 1600 for signal traces in a flex tape, in accordance with one embodiment.
  • single ended signals traces 1630 - 1632 are placed between reference traces 1640 - 1644 , e.g. ground. Both signal traces 1630 - 1632 and ground traces 1640 - 1644 are in flexible substrate material 1620 .
  • Two references surrounding a signal trace defining a set of coplanar waveguide signal traces.
  • adjacent sets of coplanar waveguide signal traces share a common reference signal trace.
  • one set of coplanar waveguide signal traces is made up of two references traces 1640 1642 and a signal trace 1630 .
  • An adjacent set of coplanar waveguide signal traces is made up of two references traces 1642 1644 and a signal trace 1632 . These two sets share a reference trace 1642 .
  • coplanar waveguide design reduces insertion and return loss associated with current I/O designs.
  • coplanar waveguide designs significantly reduce the crosstalk between signals.
  • FIG. 17 illustrates a grounded coplanar waveguide design 1700 for signal traces in a flex tape, in accordance with one embodiment.
  • ground layers 1710 1715 are used. Ground layers 1710 1715 are used to improve electromagnetic shielding of signals. In the embodiment illustrated, an upper ground layer 1710 and a lower ground layer 1715 are shown.

Abstract

An apparatus is constituted with an integrated circuit and a flex tape coupled to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal-traces. In another embodiment, the apparatus also includes a silicon interposer coupled to the flex tape and a substrate coupled to the silicon interposer.

Description

    RELATED APPLICATION
  • The present application is a divisional of U.S. patent application Ser. No. 10/455,908, filed Jun. 4, 2003, and entitled “SILICON BUILDING BLOCK ARCHITECTURE WITH FLEX TAPE,” which is hereby incorporated by reference in its entirety.
  • FIELD OF THE INVENTION
  • The present invention relates generally to the field of integrated circuit packaging. Specifically, this invention relates to the efficient power and signal delivery associated with integrated circuit packaging.
  • BACKGROUND OF THE INVENTION
  • Advances in the technology surrounding today's integrated circuits designs, such as microprocessors, continue at an astounding rate. As a result of these advances, integrated circuits are more dense and faster than ever. Moreover, integrated circuits have input/output (I/O) which are operating at higher frequencies than ever. In addition, integrated circuits are consuming more power than their predecessors. These factors are bringing about new challenges for packaging engineers.
  • On the issue of power consumption, today's microprocessors often consume up to 120 watts of power or more. With these microprocessors operating at a 1.2 volt level; 120 watts of power consumption means delivering significant amount of current, up to 100 amps, to these devices. A consequence of this is a requirement to dissipate a great amount of heat. As design advances continue, designs are predicted to approach 200 watts of power consumption in the near future. Successfully delivery of such power to today's and future integrated circuits has become, and will continue to be, a significant challenge.
  • The factors causing the increase in power consumption are numerous. One such factor is the operating speed of today's designs. Today, core speeds of microprocessors have surpassed 2 GHz. Similarly, bus speeds have increased as well; today's bus speeds have surpassed 400 MHz. As operating frequency increases for a given size integrated circuit, power consumption is also increased. This increase is due to, among other things, parasitic resistance of the motherboard, socket pins and electronic packaging. Unfortunately, the cost to reduce parasitic resistance on motherboards, socket pins and electronic packaging can be extensive. Thus, delivering increased power to today's designs without incurring a significant increase in cost is one challenge facing packaging engineers.
  • An additional issue facing today's packaging engineers with respect to integrated circuits is coupling associated with higher I/O signal switching speeds and the higher power being delivered to the integrated circuits. In addition to having more power and I/O signals to be delivered/facilitated than previous generations of designs, the desire is to have even smaller packaging of these integrated circuit designs. This is pushing the pins containing the higher speed I/O signals and pins providing increased power delivery closer together in the packaging. This, in turn, is creating further issues between the power delivered to an integrated circuit and the I/O signals entering and leaving the integrated circuit.
  • Thus, significant challenges face today's packaging engineers with respect to signal I/O and power delivery to today's integrated circuits.
  • BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 illustrates one cross sectional view of an integrated circuit packaging scheme using flex tape for signal ingress/egress and power delivery, in accordance with one embodiment.
  • FIG. 2 illustrates a different cross sectional view of the integrated circuit packaging shown in FIG. 1.
  • FIG. 3 illustrates a top view of an integrated circuit utilizing flex tape for both power and signal ingress/egress.
  • FIG. 4 illustrate power delivery via flex tape, in accordance with another embodiment.
  • FIG. 5 illustrates power delivery from above through flex tape material, in accordance with one embodiment.
  • FIG. 6 illustrates a more detailed of the flex tape providing power in FIG. 5.
  • FIGS. 7A and 7B illustrate cross sectional views of integrated circuits, including power delivery to the integrated circuits, in accordance with multiple embodiments.
  • FIG. 8 illustrates a power providing flex tape in accordance with another embodiment.
  • FIG. 9 illustrates flex tape enabled signal ingress/egress in a Silicon Building Block (SiBB) design.
  • FIG. 10 illustrates an architecture for a flex tape for signal delivery, in accordance with one embodiment.
  • FIG. 11 illustrates a flex tape signaling design in accordance with another embodiment.
  • FIG. 12 illustrates a flex tape signaling design in accordance with yet another embodiment.
  • FIG. 13 illustrates a flex tape signaling design that additionally provides power, in accordance with one embodiment.
  • FIG. 14 illustrates a flex tape architecture in accordance with another embodiment.
  • FIG. 15 illustrates a coaxial design for signals in flex tape, in accordance with one embodiment.
  • FIG. 16 illustrates a coplanar waveguide design for signal traces in a flex tape, in accordance with one embodiment.
  • FIG. 17 illustrates a grounded coplanar waveguide design for signal traces in a flex tape, in accordance with one embodiment.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In the following description, various aspects of the invention will be described. However, it will be apparent to those skilled in the art that the invention may be practiced with only some or all aspects of the invention. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the invention. However, it will also be apparent to one skilled in the art that the invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the invention.
  • The term “flex tape” as used herein is meant to include any flexible substrate material supporting conductors or conductor materials.
  • The terms “die” and “integrated circuit” as used herein are interchangeable, and are meant to include semiconductor comprising an electronic circuit design.
  • The terms “power layer” and “ground layer” are meant to imply layers of conductors or conductor materials utilized to provide a reference voltage signal. While generally the term power layer is meant to imply a higher reference level than a ground layer, this is not a requirement. The actual voltage reference level is technology dependant.
  • The terms metal line, trace, signal trace, wire, conductor, signal path and signaling medium are all related. The related terms listed above, are generally interchangeable, and appear in order from specific to general. In this field, metal lines are sometimes referred to as traces, wires, lines, interconnect or simply metal. Metal lines, generally aluminum (Al), copper (Cu) or an alloy of Al and Cu, are conductors that provide signal paths for coupling or interconnecting, electrical circuitry. Conductors other than metal are available in microelectronic devices. Materials such as doped polysilicon, doped single-crystal silicon (often referred to simply as diffusion, regardless of whether such doping is achieved by thermal diffusion or ion implantation), titanium (Ti), molybdenum (Mo), and refractory metal suicides are examples of other conductors
  • FIGS. 1-3 illustrate an integrated circuit packaging scheme using flex tape for signal ingress/egress and power delivery, in accordance with one embodiment. As shown in FIG. 1, a cross sectional view of integrated circuit 110, for the embodiment, integrated circuit 110 has a number of input/output bumps 120 located at the periphery that are used to provide signal ingress/egress to/from integrated circuit 110 through first flex tape 130. Signal ingress/egress may be facilitated e.g. by optical technologies such as optical waveguides or electromechanical technologies. In alternate embodiments, signal ingress/egress may be facilitated via other signaling techniques.
  • FIG. 2 illustrates a cross sectional view of the integrated circuit packaging shown in FIG. 1. This cross section view is shown with respect to cut line AB of FIG. 1. Periphery integrated circuit bumps 140 are utilized to provide power to the integrated circuit 110 through second flex tape 150.
  • FIG. 3 illustrates a top view of an integrated circuit utilizing flex tape for both power and signal ingress/egress. The view shown in FIG. 3 illustrates the flexible input/output signal routing substrate, or simply signal flex tape, 130 and the flexible power delivery substrate, or simply power flex tape, 150 of FIGS. 1 and 2, respectively. Integrated circuit 110 is shown with four flex tapes 130 and 150 connected to peripheral signals bumps 120 and peripheral power bumps 140 for the integrated circuit 110. Two signal flex tapes 130 provide signal ingress/egress to the integrated circuit 110. Two power flex tapes 150 are used to provide power delivery to the integrated circuit 110.
  • In another embodiment, all four flex tapes are used to provide signal ingress and egress to/from and power to the integrated circuit. In this embodiment, peripheral die bumps are used for signal ingress/egress. Die bumps away from the periphery, e.g. internal die bumps, of the die are used for power delivery to the die.
  • FIG. 4 illustrate power delivery via flex tape, in accordance with another embodiment. As shown, power delivery is provided via multiple paths in this embodiment. Rigid substrate material 430 provides power to integrated circuit 410 from the motherboard 460 through vias 450 to internal die bumps 420. In addition, flex tape material 440 provides power to integrated circuit 410 through periphery die bumps 425.
  • FIG. 5 illustrates power delivery from above through flex tape material, in accordance with one embodiment. Unlike traditional models for delivery of power to an integrated circuit mounted on a motherboard, power delivery to the integrated circuit 510 of FIG. 5 is performed from above. In this case, power is delivered from a power source from above via a connector 530. The power is then routed through a board 520 to the board's edge where the board is connected to connectors 540. The power is delivered through the connectors 540 to flex tape 550. The power is delivered by the flex tape to the integrated circuit 510 via die bumps 560. In this embodiment, the integrated circuit 510 is mounted below the board 520. Also shown are stiffeners 570 that are connected to flex tape 550. In the embodiment shown, these stiffeners 570 are used to provide rigidity to the flex tape 550. The rigidity facilities handling of the package. In addition, the stiffeners 570 provide mount points for the package to be mounted to the motherboard 580. Finally, note that such a design advantageously allows spacing between the flex tape and the motherboard for placement of landside capacitors 590, to be discussed in more detail below.
  • FIG. 6 illustrates a more detailed view of the flex tape providing power in FIG. 5. In this embodiment, flex tape 550 used to provide power to an integrated circuit is a “two layer” flex tape. As previously discussed, the power is provided via a connector to a board 520. This board provides power to the flex tape 550 through connector 540. In this flex tape architecture, there are two conductive layers 552 556 and a dielectric layer 554. The first conductive layer 552 provides a first reference voltage for the integrated circuit, e.g. VCC. The second conductive layer 554 provides a second reference voltage for the integrated circuit, e.g. VSS.
  • FIGS. 7A and 7B illustrate cross sectional views of integrated circuits, including power delivery to the integrated circuits, in accordance with multiple embodiments. FIG. 7A illustrates an example of a cross section as shown by line AB in the embodiment of FIG. 5. FIG. 7B illustrates a cross section of an embodiment of a three layer flex tape design, described in more detail below. In these embodiments, signal-carrying flex tape 705 is illustrated as extending out from both sides of the integrated circuit 720. In the embodiment illustrated in FIG. 7A, the flex tape has two trace layers, one for carrying signal 707 and one for a signal return path 709. In the embodiment illustrated in FIG. 7B, the flex tape has three traces; one trace 709 for carrying signals and two for signal return paths 707 717.
  • In the illustrated embodiments, micro vias 712 are utilized to provide access through the flex tape dielectric material. Peripheral bumps 715 are used to provide signal ingress/egress to/from the integrated circuit 720. Interior bumps 735 on the integrated circuit 720 are utilized to provide power to the integrated circuit 720. In these embodiments, as previously discussed with respect to FIG. 5, a board 730 is utilized to provide power to the integrated circuit 720 via flex tape. The integrated circuit 720 is mounted under the power providing board 730.
  • In the cross sectional view illustrated in FIG. 7A, conductive trace layer 750 is utilized to provide VSS to the integrated circuit 720. Additionally, conductive trace layer 765 is utilized to provide VCC to integrated circuit 720. In the illustrated embodiment of FIG. 7B, an additional layer is utilized to provide to provide power paths to the integrated circuit 720. Illustrated in FIGS. 7A and 7B are micro vias 760 utilized to provide an access path through the substrate to interior bumps 735 utilized to carry power to integrated circuit 720. Heatsink 740 provides a traditional focus on carrying away excess heat, but also provides a power conduit, such as a voltage regulator module (not shown) to board 730. Landside capacitors 775 are utilized to reduce first and second voltage droop.
  • In prior art implementations, a rigid substrate, socket and interconnects or power planes in the motherboard were utilized in the packaging of an IC. To enable the use of land side capacitors in such a prior art packaging, the packaging of the IC would need to be larger than otherwise required in order to support the land side capacitors. As illustrated in FIG. 5, the use of a board and flex tape design for power delivery provides room for the design to have land side capacitors without requiring an increase in the overall packaging size.
  • FIG. 8 illustrates a power providing flex tape in accordance with another embodiment. As illustrated, instead of two reference layers in a two-layer substrate, an additional reference layer is advantageously provided. As will be appreciated, the flex tape will have certain parasitic inductance and/or resistances associated with it. As a result of these factors, depending on the power deliver requirements, a two-layer power deliver flex tape may not be sufficient. In such as case, a three-layer power deliver flex tape, comprising a third reference layer, may be used to provide power to an integrated circuit. For example, as illustrated in FIG. 8, an inner reference layer 810 and an outer reference layer 820 are power providing reference layers. A middle reference layer 830 is utilized as a ground reference layer. Between layers of reference signal layers are layers of dielectric materials 835. By having an additional reference layer to provide power to the integrated circuit, effects of parasitics can be minimized.
  • When separating flex tapes for power and ground from flex tapes for signaling, dielectrics may be optimized for the particular usage. As discussed in further detail below, when high speed signaling is to be accommodated on signal traces in flex tape, it is desirable to have a low dielectric constant, low loss dielectric material. The expression, low dielectric constant material, refers to materials having a lower dielectric constant than silicon dioxide. However, when power is to be supplied by a flex tape that will not also have signal traces, the dielectric material may be optimized for the power delivery. Thus, in this power delivery flex tape, high dielectric constant materials may be used between power and ground traces for improved power delivery. Examples of high dielectric constant materials include titanium dioxide with a dielectric constant of 110.
  • FIG. 9 illustrates flex tape enabled signal ingress/egress in a Silicon Building Block (SiBB) design. In this embodiment, an integrated circuit 910 utilizes flex tape 920 for the ingress/egress of signals to the integrated circuit 910. In this embodiment, power is delivered to the integrated circuit from the bottom via a motherboard 950. Rigid substrate 940 provides power delivery pathways 945 for the delivery of power to the integrated circuit 910. In this embodiment, the substrate 940 may contain a relatively simplified power routing design. Thus, substrate 940 may be made up of a low cost substrate material such as plastic. This simplified, inexpensive power routing design is possible because of silicon interposer 930. Silicon interposer 930 provides the ability to move detailed power delivery routing issues from substrate 940 to the silicon interposer 930.
  • Power delivery substrates are designed to take into account inductance, resistance and capacitance effects in routing power from a power source to power bumps. This allows for maximum power transfer with minimum loss. The detailed aspects of creating and manufacturing a well-designed substrate for today's designs, drive the cost up dramatically. Thus, today's substrates can cost up to as much as that of the integrated circuit designs.
  • If a manufacturer of integrated circuits could utilize internal expertise in silicon to create a silicon interposer that performs these critical power deliver design tasks, the resulting substrate cost can be reduced dramatically. For example, a manufacturer of an integrated circuit may have particularly strong skills in silicon processing. In addition, the manufacturer that may have access to older generation silicon manufacturing equipment that, while outdated by the standards of today's leading edge integrated circuit processing, is available for other uses. This equipment and expertise can be utilized to create a silicon interposer at greatly reduced costs as compared to a substrate. Thus, by using an interposer design for power delivery, combined with flex tape enable I/O signaling, significant reductions in the manufacturing costs can be obtained.
  • FIG. 10 illustrates an architecture for flex tape for signal delivery, in accordance with one embodiment. In this embodiment, differential signaling is used to provide for high-speed operation of signal ingress and egress to/from integrated circuits. Flex tape 1000 contains traces 1010 for differential signal routing. In the embodiment shown in FIG. 10, a ground layer 1020 is introduced into the flex tape. Differential signaling, especially in low voltage applications which are possible due to differential signaling noise immunity, provides a number of advantages over single-ended signaling. Such advantages, in addition to noise immunity, include reduced electromagnetic interference, improvements in switching speeds and reduction in power consumption. An example of differential signaling is Low Voltage Differential Signaling, which uses a 400 mV differential signal at 1.2V. The ground layer 1020 provides for improved coupling to further improve performance of the differential signals.
  • Differential signaling is utilized when high speed signaling is required. To further facilitate high speed signaling, dielectric materials should be used which possess low-loss and low-k, k being the average dielectric constant of the material. A low-k material would be a material with a dielectric constant less then 3. A low-loss material would have a loss tangent of less than 0.01. Examples of such materials are polyimides.
  • FIG. 11 illustrates a flex tape signaling design in accordance with another embodiment. In addition to traces 1110 designed for differential pair signaling and a reference, e.g. ground, layer 1122, this embodiment of flex tape illustrates a second reference layer 1124. The addition of this second reference layer 1124 provides additional shielding. This added shielding provides for enhanced noise immunity.
  • FIG. 12 illustrates a flex tape signaling design in accordance with yet another embodiment. This design utilizes traces 1210 for differential signals and two references layers 1222 1224. In addition, this design electrically couples (e.g. stitches) the ground layers 1222 1224 together at intervals. In one embodiment, ground layers 1222 1224 are stitched together utilizing stitching vias 1250. The number of stitching vias 1250 present in a design can vary. In one embodiment, the ground layers 1222 1224 are stitched together after every two sets of differential signaling pairs 1210. The use of stitching ground layers results in, among other things, better electromagnetic interference shielding.
  • FIG. 13 illustrates a flex tape signaling design that additionally provides power, in accordance with one embodiment. Traces for carrying differential signals 1310 are illustrated. As previously discussed, these traces provide high-speed ingress and egress to/from an integrated circuit. Ground layers 1320 provide shielding and coupling to allow improved operational speed of signals utilizing these traces. Additionally, in this embodiment, power layer 1330 is provided. Power layer 1330 provides power to an integrated circuit. Referring again briefly to FIG. 3, recall that in the embodiment shown there, four flex tapes are used to provide signals and power to the design. As described in relationship to FIG. 3, two flex tapes provides signal ingress/egress and two flex tapes provide power. In another usage model for four flex tapes, each flex tape contains a design as shown in FIG. 13. By using the flex tape design of FIG. 13, each of the four flex tapes can provide signal ingress/egress. This allows for a potential of up to twice as many signal I/Os to be routing using the flex tapes in designs with very high I/O signal count. In addition, the flex tape design of FIG. 13 provides addition sources for power delivery to an integrated circuit. Utilizing the flex tape embodiment of FIG. 13, all four flex tapes can also be used to provide power to an integrated circuit.
  • FIG. 14 illustrates a flex tape architecture in accordance with another embodiment. In this embodiment, as illustrated before, traces for carrying differential signals 1412 1414 are used in the flex tape design. These traces are located between two ground layers 1420 to provide for better reference and electromagnetic interference shielding. Instead of the traces for two differential signals being arranged horizontally between the two ground layers 1420 as in the previous embodiments, the two traces 1412 1414 are arranged vertically. This vertical orientation allows for greater coupling effect between two differential signals routed on the two traces, further reducing the signals' susceptibility to noise.
  • FIG. 15 illustrates a coaxial design for signals in flex tape 1500, in accordance with one embodiment. Traditionally rigid substrates have not allowed for the design of signals in a coaxial pattern. However with the use of a substrate comprised of flexible materials, propagating signals using a coaxial conductive set is practical. Thus, in the flex tape embodiment show in FIG. 15, a conductive core 1540 provides propagation path for a signal. Outside the conductive core 1540 is a dielectric layer 1530. Outside the dielectric layer 1530 is a signal return path, via a reference layer 1520. The signal core 1530 and reference layer 1520 are positioned inside a flexible substrate 1510. Propagating signals using coaxial cable flex tapes reduces insertion loss and return loss associated with current I/O designs, while enhancing impedance control. In another embodiment, the conductive core comprises two wires and insulation, forming a twisted pair. In this embodiment, differential signaling is used in the propagation of the signal inside a coaxial design. This further improves noise immunity.
  • FIG. 16 illustrates a coplanar waveguide design 1600 for signal traces in a flex tape, in accordance with one embodiment. In the illustrated coplanar wave guide structure, single ended signals traces 1630-1632 are placed between reference traces 1640-1644, e.g. ground. Both signal traces 1630-1632 and ground traces 1640-1644 are in flexible substrate material 1620. Two references surrounding a signal trace defining a set of coplanar waveguide signal traces. In the embodiment shown, adjacent sets of coplanar waveguide signal traces share a common reference signal trace. For example, one set of coplanar waveguide signal traces is made up of two references traces 1640 1642 and a signal trace 1630. An adjacent set of coplanar waveguide signal traces is made up of two references traces 1642 1644 and a signal trace 1632. These two sets share a reference trace 1642.
  • The coplanar waveguide design, and grounded coplanar waveguide design described below, reduces insertion and return loss associated with current I/O designs. In addition, coplanar waveguide designs significantly reduce the crosstalk between signals.
  • FIG. 17 illustrates a grounded coplanar waveguide design 1700 for signal traces in a flex tape, in accordance with one embodiment. In addition to single ended signals traces 1730 being placed between grounds traces 1740 as with the coplanar waveguide design of FIG. 16, in this embodiment ground layers 1710 1715 are used. Ground layers 1710 1715 are used to improve electromagnetic shielding of signals. In the embodiment illustrated, an upper ground layer 1710 and a lower ground layer 1715 are shown.
  • Thus a novel architecture for delivery of power to an integrated circuit is disclosed.

Claims (20)

1. An apparatus comprising:
an integrated circuit;
a board coupled to said integrated circuit; and
a flexible power delivery substrate electrically coupled to said board and said integrated circuit.
2. The apparatus of claim 1 wherein said board comprises one or more power conduits.
3. The apparatus of claim 1 wherein said integrated circuit is mounted to said board.
4. The apparatus of claim 1 wherein said integrated circuit is mounted to a bottom side of said board.
5. The apparatus of claim 1 further comprising land side capacitors coupled to said flexible power delivery substrate.
6. The apparatus of claim 1 wherein said flexible power delivery substrate comprises a three-layer flex tape.
7. The apparatus of claim 6 wherein said three-layer flex tape comprises a first, second and third conductive layer and a first and second dielectric layer, said first dielectric layer between said first and said second conductive layers, said second dielectric layer between said second and said third conductive layers.
8. The apparatus of claim 1 further comprising one or more stiffeners coupled to said flexible power delivery substrate.
9. The apparatus of claim 8 further comprising a motherboard coupled to said one or more stiffeners.
10. The apparatus of claim 1 wherein said flexible power delivery substrate comprises a dielectric material and wherein said dielectric material comprises a dielectric constant greater than 100.
11. The apparatus of claim 1 further comprising a flexible I/O (input/output) signal routing substrate coupled to said integrated circuit.
12. The apparatus of claim 11 wherein connections between said integrated circuit and said flexible I/O signal routing substrate occur on periphery bumps of said integrated circuit.
13. The apparatus of claim 11 wherein said flexible I/O signal routing substrate comprise a plurality of signal traces and wherein two signal traces comprise a differential signal pair.
14. The apparatus of claim 11 wherein said flexible I/O signal routing substrate comprises an optical transmission material.
15. The apparatus of claim 11 wherein said flexible I/O signal routing substrate comprises an electromagnetic transmission material.
16. The apparatus of claim 11 wherein said flexible I/O signal routing substrate comprises a polyimide.
17. The apparatus of claim 11 wherein said flexible I/O signal routing substrate comprises a dielectric material, wherein said dielectric material comprises a loss tangent less than 0.01 including a dielectric constant less than 3.
18. An apparatus comprising:
an integrated circuit;
a board coupled to said integrated circuit, said integrated circuit mounted to said board;
a flexible power delivery substrate electrically coupled to said board and said integrated circuit; and
a motherboard coupled to said flexible power delivery substrate.
19. The apparatus of claim 18 wherein said flexible power delivery substrate comprises a three-layer flex tape.
20. The apparatus of claim 18 further comprising land side capacitors coupled to said flexible power delivery substrate.
US11/228,662 2003-06-04 2005-09-15 Silicon building block architecture with flex tape Abandoned US20060006507A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6995465B2 (en) * 2003-06-04 2006-02-07 Intel Corporation Silicon building block architecture with flex tape
US7705445B2 (en) * 2005-02-11 2010-04-27 Rambus Inc. Semiconductor package with low and high-speed signal paths

Citations (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278724A (en) * 1992-07-06 1994-01-11 International Business Machines Corporation Electronic package and method of making same
US5805422A (en) * 1994-09-21 1998-09-08 Nec Corporation Semiconductor package with flexible board and method of fabricating the same
US5854534A (en) * 1992-08-05 1998-12-29 Fujitsu Limited Controlled impedence interposer substrate
US5872700A (en) * 1996-07-11 1999-02-16 Nokia Mobile Phones Limited Multi-chip module package with insulating tape having electrical leads and solder bumps
US5885710A (en) * 1997-03-26 1999-03-23 Ericsson, Inc. Flexible strip transmission line
US5926369A (en) * 1998-01-22 1999-07-20 International Business Machines Corporation Vertically integrated multi-chip circuit package with heat-sink support
US5933712A (en) * 1997-03-19 1999-08-03 The Regents Of The University Of California Attachment method for stacked integrated circuit (IC) chips
US5973928A (en) * 1998-08-18 1999-10-26 International Business Machines Corporation Multi-layer ceramic substrate decoupling
US5982256A (en) * 1997-04-22 1999-11-09 Kyocera Corporation Wiring board equipped with a line for transmitting a high frequency signal
US5995370A (en) * 1997-09-01 1999-11-30 Sharp Kabushiki Kaisha Heat-sinking arrangement for circuit elements
US6239485B1 (en) * 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
US20020044423A1 (en) * 1999-05-14 2002-04-18 Primavera Anthony A. Method and apparatus for mounting and packaging electronic components
US20020114143A1 (en) * 2000-12-28 2002-08-22 Morrison Gary P. Chip-scale packages stacked on folded interconnector for vertical assembly on substrates
US20020164838A1 (en) * 2001-05-02 2002-11-07 Moon Ow Chee Flexible ball grid array chip scale packages and methods of fabrication
US20030109078A1 (en) * 1996-12-03 2003-06-12 Yoshikazu Takahashi Semiconductor device, method for manufacturing the same, and method for mounting the same
US6600222B1 (en) * 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6613855B1 (en) * 1997-04-09 2003-09-02 Sanyo Chemical Industries, Ltd. Polymerizable resin, and cured resins, insulators, components of electrical appliances, and electrical appliances made by using the same
US6703705B2 (en) * 2000-11-28 2004-03-09 Nec Corporation Semiconductor device and method for packaging same
US6770822B2 (en) * 2002-02-22 2004-08-03 Bridgewave Communications, Inc. High frequency device packages and methods
US6784375B2 (en) * 1999-07-30 2004-08-31 Denso Corporation Interconnection structure for interconnecting printed circuit boards
US6791403B1 (en) * 2003-03-19 2004-09-14 Raytheon Company Miniature RF stripline linear phase filters
US6870257B2 (en) * 2003-06-04 2005-03-22 Intel Corporation Power delivery through a flex tape in decoupled I/O-power hybrid substrate
US6869825B2 (en) * 2002-12-31 2005-03-22 Intel Corporation Folded BGA package design with shortened communication paths and more electrical routing flexibility
US6885107B2 (en) * 2002-08-29 2005-04-26 Micron Technology, Inc. Flip-chip image sensor packages and methods of fabrication
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US6977441B2 (en) * 1999-08-19 2005-12-20 Seiko Epson Corporation Interconnect substrate and method of manufacture thereof, electronic component and method of manufacturing thereof, circuit board and electronic instrument
US6995465B2 (en) * 2003-06-04 2006-02-07 Intel Corporation Silicon building block architecture with flex tape
US6998704B2 (en) * 2002-08-30 2006-02-14 Nec Corporation Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus
US7321167B2 (en) * 2003-06-04 2008-01-22 Intel Corporation Flex tape architecture for integrated circuit signal ingress/egress

Patent Citations (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278724A (en) * 1992-07-06 1994-01-11 International Business Machines Corporation Electronic package and method of making same
US5854534A (en) * 1992-08-05 1998-12-29 Fujitsu Limited Controlled impedence interposer substrate
US5805422A (en) * 1994-09-21 1998-09-08 Nec Corporation Semiconductor package with flexible board and method of fabricating the same
US5872700A (en) * 1996-07-11 1999-02-16 Nokia Mobile Phones Limited Multi-chip module package with insulating tape having electrical leads and solder bumps
US20030109078A1 (en) * 1996-12-03 2003-06-12 Yoshikazu Takahashi Semiconductor device, method for manufacturing the same, and method for mounting the same
US5933712A (en) * 1997-03-19 1999-08-03 The Regents Of The University Of California Attachment method for stacked integrated circuit (IC) chips
US5885710A (en) * 1997-03-26 1999-03-23 Ericsson, Inc. Flexible strip transmission line
US6613855B1 (en) * 1997-04-09 2003-09-02 Sanyo Chemical Industries, Ltd. Polymerizable resin, and cured resins, insulators, components of electrical appliances, and electrical appliances made by using the same
US5982256A (en) * 1997-04-22 1999-11-09 Kyocera Corporation Wiring board equipped with a line for transmitting a high frequency signal
US5995370A (en) * 1997-09-01 1999-11-30 Sharp Kabushiki Kaisha Heat-sinking arrangement for circuit elements
US5926369A (en) * 1998-01-22 1999-07-20 International Business Machines Corporation Vertically integrated multi-chip circuit package with heat-sink support
US5973928A (en) * 1998-08-18 1999-10-26 International Business Machines Corporation Multi-layer ceramic substrate decoupling
US6239485B1 (en) * 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
US20020044423A1 (en) * 1999-05-14 2002-04-18 Primavera Anthony A. Method and apparatus for mounting and packaging electronic components
US6784375B2 (en) * 1999-07-30 2004-08-31 Denso Corporation Interconnection structure for interconnecting printed circuit boards
US6977441B2 (en) * 1999-08-19 2005-12-20 Seiko Epson Corporation Interconnect substrate and method of manufacture thereof, electronic component and method of manufacturing thereof, circuit board and electronic instrument
US6703705B2 (en) * 2000-11-28 2004-03-09 Nec Corporation Semiconductor device and method for packaging same
US20020114143A1 (en) * 2000-12-28 2002-08-22 Morrison Gary P. Chip-scale packages stacked on folded interconnector for vertical assembly on substrates
US20020164838A1 (en) * 2001-05-02 2002-11-07 Moon Ow Chee Flexible ball grid array chip scale packages and methods of fabrication
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US6770822B2 (en) * 2002-02-22 2004-08-03 Bridgewave Communications, Inc. High frequency device packages and methods
US6600222B1 (en) * 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6885107B2 (en) * 2002-08-29 2005-04-26 Micron Technology, Inc. Flip-chip image sensor packages and methods of fabrication
US6998704B2 (en) * 2002-08-30 2006-02-14 Nec Corporation Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus
US6869825B2 (en) * 2002-12-31 2005-03-22 Intel Corporation Folded BGA package design with shortened communication paths and more electrical routing flexibility
US6791403B1 (en) * 2003-03-19 2004-09-14 Raytheon Company Miniature RF stripline linear phase filters
US6870257B2 (en) * 2003-06-04 2005-03-22 Intel Corporation Power delivery through a flex tape in decoupled I/O-power hybrid substrate
US6995465B2 (en) * 2003-06-04 2006-02-07 Intel Corporation Silicon building block architecture with flex tape
US7321167B2 (en) * 2003-06-04 2008-01-22 Intel Corporation Flex tape architecture for integrated circuit signal ingress/egress

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Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION