US20060108635A1 - Trenched MOSFETS with part of the device formed on a (110) crystal plane - Google Patents

Trenched MOSFETS with part of the device formed on a (110) crystal plane Download PDF

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US20060108635A1
US20060108635A1 US10/996,561 US99656104A US2006108635A1 US 20060108635 A1 US20060108635 A1 US 20060108635A1 US 99656104 A US99656104 A US 99656104A US 2006108635 A1 US2006108635 A1 US 2006108635A1
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crystal orientation
trench
sidewalls
along
mosfet power
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Anup Bhalla
Sik Lui
Sung-Shan Tai
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Alpha and Omega Semiconductor Ltd
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Alpha and Omega Semiconductor Ltd
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Priority to US10/996,561 priority Critical patent/US20060108635A1/en
Assigned to ALPHA OMEGA SEMICONDUCTOR LIMITED reassignment ALPHA OMEGA SEMICONDUCTOR LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BHALLA, ANUP, LUI, SIK K., TAI, SUNG-SHAN
Priority to TW094136885A priority patent/TW200629424A/en
Priority to PCT/US2005/042743 priority patent/WO2006058210A1/en
Priority to US11/634,031 priority patent/US20110042724A1/en
Publication of US20060108635A1 publication Critical patent/US20060108635A1/en
Priority to US11/894,240 priority patent/US8564049B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates generally to the semiconductor power devices. More particularly, this invention relates to a novel and improved manufacture method and device configuration for a metal-oxide semiconductor field effect transistor (MOSFET) trenched power device manufactured with part of trench oriented on a ( 110 ) crystal plane of a silicon wafer.
  • MOSFET metal-oxide semiconductor field effect transistor
  • the MOS devices are formed on the silicon wafer along a crystal orientation of a ( 100 ) plane because the oxide layer grown on a ( 100 ) plane has the lowest fixed charge and interface state density.
  • the trench walls of the N-channel and P-channel of the trenched MOSFETs are typically oriented along the ( 100 ) plane as well.
  • the channel formed along the ( 100 ) orientation has the benefit for achieving higher channel mobility.
  • the oxide layer grown along the ( 110 ) plane has greater thickness and higher interface state density.
  • a thicker oxide layer often leads to a higher threshold voltage and lower transconductance.
  • measured data also provide some evidence that thicker oxide layer also causes a degradation of channel mobility.
  • Hasegawa discloses a CMOS silicon-on-insulation structure fabricated by first forming an insulating SiO2 layer on a silicon substrate having a ( 110 ) plane. Openings are then formed in the SiO2 layer to expose a part of the substrate, and a polycrystalline or an amorphous silicon layer is deposited on the SiO2 layer and in the openings. The deposited silicon layer is divided into islands so that a first island includes one of the openings and a second island does not include any openings.
  • a laser beam is then irradiated onto the islands so as to melt the islands, and when the laser light irradiation is discontinued, the melted islands recrystallize so that the first island forms a ( 110 ) plane and the second island forms a ( 100 ) plane.
  • a p-channel MOSFET is fabricated on the first island, and an n-channel MOSFET is fabricated on the second island.
  • the thus paired CMOS operates at high speeds, because the p-channel MOSFET using positive holes as the carrier is fast in a ( 110 ) crystal, and the n-channel MOSFET using electrons as the carrier is fast in a ( 100 ) crystal.
  • Hasegawa disclose the benefits of building a p-channel MOSFET in a ( 110 ) crystal plane, however the configurations and method as disclosed would be too complicate and costly with limited merits for practical application to build a commercial MOSFET product.
  • a semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a ( 110 ) direction.
  • the method disclosed by Noble et al. provides for forming an integrated circuit including an array of MOSFETs and another method includes forming an integrated circuit including a number of lateral transistors.
  • the disclosure also includes structures as well as systems incorporating such structures all formed according to the methods provided in this application.
  • Noble's disclosures are however for a lateral device.
  • a vertical trench MOS device would require different considerations.
  • FIG. 1 shows a typical trench power MOSFET device that has its MOS channel vertically along the sidewall of a trench 10 .
  • the trench sidewall is covered by the gate dielectric 20 , and is filled with the gate electrode material 30 .
  • mobile carriers e.g., electrons for n-channel and holes for p-channel.
  • Table 1 shows the measured data that summarizes the characteristics of two identical P-channel MOSFETs next to each other on the same wafer, with the channel formed on ( 100 ) and ( 110 ) interfaces respectively on a ( 100 ) wafer.
  • An ( 110 ) orientation on the trench sidewall where the channel is formed is achieved by simply rotating the FETs by 45 degrees as can be seen from FIG. 2 .
  • the results from two wafers are shown. The only difference in process between the two wafers is the duration of gate oxidation.
  • the trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate.
  • Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.
  • forming the trenches with a stripe configuration, and choosing a different orientation of the seed crystal can produce an orientation of the trench with both sidewalls and bottom surface align along a ( 110 ) crystal orientation of the semiconductor substrate.
  • this invention discloses a trenched MOSFET power transistor that includes a gate disposed in a trench formed in a semiconductor substrate.
  • the trench further includes sidewalls and a trench bottom surface all formed along a ( 110 ) crystal orientation of the semiconductor substrate.
  • the MOSFET power transistor is a P-channel MOSFET power transistor.
  • this invention further discloses a trenched MOSFET power transistor comprising a gate disposed in a trench formed in a semiconductor substrate.
  • the trench further includes sidewalls formed along a first crystal orientation of the semiconductor substrate and a trench bottom surface formed along a second crystal orientation of the semiconductor substrate different from the first crystal orientation.
  • the trench further includes an oxide layer covering the sidewalls having a substantially the same thickness as an oxide layer covering the bottom surface of the trench.
  • FIG. 1 is a cross sectional view of a MOSFET device manufactured according to a process of this invention
  • FIG. 2 shows two identical MOSFETs next to each other on the same wafer, with the channel formed on ( 100 ) and ( 110 ) interfaces on the vertical sidewall respectively on a ( 100 ) wafer.
  • FIGS. 3A and 3B are perspective views for showing the crystal orientations of a silicon ingot and the configuration of a trench;
  • FIG. 4A to 4 C are cross sectional views for showing the process to form the trench aligned along different crystal orientations of a semiconductor substrate
  • FIG. 5 is a perspective view for showing the termination tip of a trench to minimize the ( 100 ) plane effect
  • FIGS. 6A to 6 C are perspective views for showing manufacturing processes using SOG to thicken the oxide at the termination of a trench
  • FIGS. 7A and 7B are perspective views for showing an annealing process to produce trench oxide layer covering ( 110 ) and ( 100 ) planes of uniform thickness;
  • FIGS. 8A to 8 C show the cross sectional view of another embodiment using ( 100 ) wafer as starting material, following the steps described in FIGS. 4A-4C ;
  • FIG. 9 is a perspective view of a P-channel DMOS with channel along ( 110 ) plane.
  • FIG. 10 is a perspective view of a wafer and the trench for a N-channel trenched MOSFET device with the bottom of the trench formed on a ( 110 ) plane and the sidewalls on the ( 100 ) plane.
  • FIGS. 3A and 3B show the orientations of the substrate and trench according to the current invention.
  • the silicon ingot 125 is grown in the ( 110 ) plane.
  • the silicon ingot 125 provides a configuration that four sidewalls are situated with four sidewall surfaces forming a corner with a corner angle of 90 degrees, thus these sidewall surfaces are perpendicular to each other. Two of these sidewalls are along a ( 100 ) crystal orientation and two are along a ( 110 ) crystal orientation.
  • two sidewalls 150 and bottom 155 of the trench 148 are formed along a ( 110 ) crystal orientation while the termination end surface 160 of the trench 148 is formed along a ( 100 ) crystal orientation.
  • the wafer 325 is formed by rotating a normal ( 100 ) wafer as shown in FIG. 2 by 45° thus forming two interface planes on a ( 110 ) plane while the top and bottom planes are still on the ( 100 ) plane.
  • the bottom 355 of the trench is still oriented along a ( 100 ) plane. Due to these different orientations, the gate oxide layer along the sidewalls formed along the ( 110 ) will be thicker than the gate oxide layer formed on the bottom of the trench along the ( 100 ) plane during thermal oxidation process.
  • the thin oxide bottom or end surface of the trench sets the minimum oxide thickness usable. This then forces the use of a thicker oxide along the sidewall compared to a device with all trench sides along the ( 100 ), and causes a higher threshold voltage for a given channel doping profile.
  • stripe structure design with round termination or round bottom is incorporated with dielectric layer thickening techniques to provide improve P-channel trench MOSFET device.
  • one embodiment uses ( 110 ) wafer 125 as substrate.
  • An oxide layer 135 is formed on the top ( 110 ) surface by thermal oxidation.
  • a trench mask 145 is used to expose the silicon dioxide in the area for forming the trenches as shown in FIG. 4C below.
  • the trench mask may have a round or oval shape where the trench ends. As shown in FIG. 5 , this produces a trench with round termination therefore the section lying along the ( 100 ) plane during trench dry etching process is minimized.
  • FIG. 4B after the exposed oxide is removed by etching, the photoresist 145 is stripped off and the remaining oxide layer 135 forms the hard mask for forming the trenches where the oxide layer 135 is removed.
  • the trenches 148 are then formed along the ( 110 ) direction on the wafer by dry etching process.
  • the trench MOSFET it is possible for the trench MOSFET to have the trench sidewalls 150 and the channel, and the trench bottom 155 along a ( 110 ) interface, making the gate oxide thickness uniform both along the sidewall and at the trench bottom. Therefore, the on resistance of the device may be reduced.
  • the gate oxide may be thinner at the trench termination area 160 thus limiting gate maximum rating of the gate oxide.
  • the thickness of oxide layer around ( 100 ) plane is enhanced to provide a gate oxide layer with uniform thickness or even thicker at the trench bottom or at the trench termination.
  • Numerous oxide thickening techniques may be used to achieve the above design goal.
  • FIGS. 6A to 6 C shows another P-channel MOSFET device 200 that has a configuration with the trench sidewalls formed along the ( 110 ) plane while using a mask to form thicker oxide in the designated areas thus minimizing the effects of uneven thickness of gate oxide layer.
  • oxide 210 is filled with oxide 210 using techniques such as SOG (spin on glass) or oxide deposition as shown in FIG. 6A .
  • SOG spin on glass
  • oxide deposition oxide Alternatively, an oxide layer may thermally be grown over the entire Silicon surface.
  • a mask 220 is used to generate a protection area at the trench termination as that shown in FIG. 6B .
  • the oxide is then etched back with the oxide in the terminal area intact as that shown in FIG. 6C .
  • a sacrificial oxide layer may be thermally grown and then removed by wet etch to remove the defects on silicon surface on the bottom and the sides of the trench caused by the harsh etching process during trench formation and SOG etch back.
  • a high quality gate oxide is then thermally grown (not shown).
  • FIGS. 7A to 7 B show another embodiment, using a high temperature gate anneal to flow the oxide, so its thickness loses its orientation dependence.
  • the gate oxide layer 260 is thinner at the trench termination tip portion of ( 100 ) plan.
  • silicon oxide goes into viscous flow and losses its orientation dependence to yield a film with uniform thickness.
  • FIG. 7B shows the result after 1200° C. of annealing for 5 minutes.
  • FIGS. 8A to 8 C show another embodiment using ( 100 ) wafer 325 as starting material. Following the steps described in FIGS. 4A-4C , a trench 348 with both side walls 350 and termination end faces (not shown) on ( 110 ) plane is obtained. The trench bottom 355 is in ( 100 ) plane. An additional ion reactive etching process is performed to round the bottom 355 of the trench. To overcome the technical difficulties caused by a non-uniform thickness of the gate oxide layer when part of the device is formed along different crystal orientations, the thickness of oxide layer around ( 100 ) trench bottom is enhanced to provide a gate oxide layer with uniform thickness or even thicker at the trench bottom or at the trench termination. Referring to FIG.
  • a layer of oxide is deposited to fill the bottom of trench.
  • polysilicon may be deposited and then oxidized, or SOG may be used to fill the trench.
  • the oxide is then etched back. In one embodiment, the oxide is etched with a mask. In another embodiment, the oxide is etched backed without using a mask. The etch back process goes on until the thickness of the bottom oxide 310 reaches a predetermined thickness ( FIG. 8C ).
  • a sacrificial oxide layer may be thermally grown and then removed by wet etch to remove the defects on silicon surface on the sides of the trench caused by the harsh etching process during trench formation and oxide etch back.
  • a high quality gate oxide is then thermally grown. As shown in FIG. 8D , this yields a layer of gate oxide 320 lining within the trench 348 where the oxide thickness at the bottom portion 355 has been increased so that the overall thickness is substantially the same.
  • MOSFET devices 400 After the gate dielectric layer is formed in the trench, standard trench MOSFET processes are carried out to complete the fabrication of a MOSFET device 400 as that shown in FIG. 9 .
  • the processes for the formation of the gate 410 , the body 420 , the source 430 , BPSG deposition 440 , and contact with the substrate 405 functioning as a drain are well know in the art, to form the device as shown in FIG. 9 .
  • This invention discloses a trenched MOSFET device 400 formed on a silicon substrate with sidewalls of the trench formed along a ( 110 ) crystal plane. The sidewalls and the bottom surface are covered with an dielectric layer 415 having substantially a uniform thickness on the sidewalls and the bottom surface.
  • the trench and gate is formed before the formation of body or source. In another embodiment, the trench and gate is formed after the formation of body or source.
  • FIG. 10 are perspective views for forming an N-channel trenched MOSFET device with a part of the device on a ( 110 ) plane.
  • the wafer 510 is a ( 110 ) wafer.
  • a stripe design is implemented wherein a trenched N-channel MOSFET 500 is formed with the trenches 520 perpendicular to the ( 110 ) direction. This orientation of the trench results in a configuration where the sidewalls 525 of the trench 520 are formed on the ( 100 ) plane while the bottom of the trench 530 is formed on a ( 110 ) plane. This process naturally produces a thicker gate oxide on the bottom of the trench.
  • the thicker oxide at the bottom has several advantages that the thick gate oxide at the bottom reduces the gate-drain capacitance, leading to a faster switching MOSFET. Furthermore, the thicker gate oxide at the bottom of the trench reduces the electric field at the trench bottom, increasing the breakdown voltage. This allows the designer to increase the epitaxial layer doping, thereby lowering the on-resistance of the MOSFET. For a stripe configuration as shown, the trench termination will also lie on a 110 plane, and since the oxide is thicker here, there is no penalty in gate voltage rating.
  • this invention discloses a N-channel MOSFET device having a trench wherein a sidewall of the trench is oriented along a different crystal orientation than a bottom of the sidewall.
  • the bottom of the trench is oriented along a ( 110 ) crystal plane.
  • the sidewall is oriented along a ( 100 ) crystal plane.
  • the trench and gate is formed before the formation of body or source.
  • the trench and gate is formed after the formation of body or source.

Abstract

This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming part of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates generally to the semiconductor power devices. More particularly, this invention relates to a novel and improved manufacture method and device configuration for a metal-oxide semiconductor field effect transistor (MOSFET) trenched power device manufactured with part of trench oriented on a (110) crystal plane of a silicon wafer.
  • 2. Description of the Prior Art
  • Even though the techniques to provide improved carrier mobility for a P-channel MOSFET, i.e., metal oxide silicon field effect transistors, by forming the transistor on a (110) crystal plane is known, the difficulties of high interface state density is still a limitation for practical implementation of such configurations. Specifically, Sze disclosed in “Physics of Semiconductor Devices” (Wiley-Interscience, 1969, pp. 16, pp. 473) and B. Goebel, D. Schumann, E. Bertagnolli disclosed in IEEE Trans. Electronics Devices, Vol. 48, No. 5, May 2001, pp. 897-906 that there is a thicker oxidation and higher interface state density along a (110) crystal plane. The thicker oxidation thus results in a thick gate oxide layer and lead to an adversely affected higher threshold voltage.
  • Historically, the MOS devices are formed on the silicon wafer along a crystal orientation of a (100) plane because the oxide layer grown on a (100) plane has the lowest fixed charge and interface state density. For these reasons, the trench walls of the N-channel and P-channel of the trenched MOSFETs are typically oriented along the (100) plane as well. Specifically, for a N-channel device, the channel formed along the (100) orientation has the benefit for achieving higher channel mobility. In contrast, the oxide layer grown along the (110) plane has greater thickness and higher interface state density. A thicker oxide layer often leads to a higher threshold voltage and lower transconductance. Furthermore, measured data also provide some evidence that thicker oxide layer also causes a degradation of channel mobility. Due to these concerns, forming the MOSFET power devices using a (100) crystal orientation has become a common rule in the conventional design methods. However, there are potential benefits of forming the power MOSFET devices or at least part of the transistors on the (110) plane. These potential benefits are often ignored due to the common practice as typically carried out by those of ordinary skill in the art without further exploration. Furthermore, even when there are several U.S. patents and patent applications that explored the techniques of building the MOS devices on a semiconductor substrate having a (110) crystal orientation, these disclosures are still limited by several technique difficulties due to different practical configuration and manufacture constraints due to the oxide layer thickness variations along different crystal orientations as will be discussed below.
  • In U.S. Pat. No. 4,933,298, entitled “Method of making high speed semiconductor device having a silicon-on-insulator structure”, Hasegawa discloses a CMOS silicon-on-insulation structure fabricated by first forming an insulating SiO2 layer on a silicon substrate having a (110) plane. Openings are then formed in the SiO2 layer to expose a part of the substrate, and a polycrystalline or an amorphous silicon layer is deposited on the SiO2 layer and in the openings. The deposited silicon layer is divided into islands so that a first island includes one of the openings and a second island does not include any openings. A laser beam is then irradiated onto the islands so as to melt the islands, and when the laser light irradiation is discontinued, the melted islands recrystallize so that the first island forms a (110) plane and the second island forms a (100) plane. A p-channel MOSFET is fabricated on the first island, and an n-channel MOSFET is fabricated on the second island. The thus paired CMOS operates at high speeds, because the p-channel MOSFET using positive holes as the carrier is fast in a (110) crystal, and the n-channel MOSFET using electrons as the carrier is fast in a (100) crystal. Hasegawa disclose the benefits of building a p-channel MOSFET in a (110) crystal plane, however the configurations and method as disclosed would be too complicate and costly with limited merits for practical application to build a commercial MOSFET product.
  • In another U.S. Pat. No. 6,245,615 entitled “Method and apparatus on (110) surfaces of silicon structures with conduction in the (110) direction” Noble et al. disclosed methods and structures that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the (110) direction for the purposed of achieving improvements in hole carrier mobility. The structure's channel is oriented in a (110) plane such that the electrical current flow is in the (110) direction. A method of forming an integrated circuit includes forming a trench in a silicon wafer with the trench wall oriented to have a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a (110) direction. The method disclosed by Noble et al. provides for forming an integrated circuit including an array of MOSFETs and another method includes forming an integrated circuit including a number of lateral transistors. The disclosure also includes structures as well as systems incorporating such structures all formed according to the methods provided in this application. Noble's disclosures are however for a lateral device. A vertical trench MOS device would require different considerations.
  • FIG. 1 shows a typical trench power MOSFET device that has its MOS channel vertically along the sidewall of a trench 10. The trench sidewall is covered by the gate dielectric 20, and is filled with the gate electrode material 30. Current flows from the source contact 40 to the drain contact 50, vertically down along the channel when the gate voltage is sufficient to connect the source and drain regions by an inversion layer of mobile carriers, e.g., electrons for n-channel and holes for p-channel. Many such cells operated in parallel form a power MOSFET.
  • Table 1 shows the measured data that summarizes the characteristics of two identical P-channel MOSFETs next to each other on the same wafer, with the channel formed on (100) and (110) interfaces respectively on a (100) wafer. An (110) orientation on the trench sidewall where the channel is formed is achieved by simply rotating the FETs by 45 degrees as can be seen from FIG. 2. The results from two wafers are shown. The only difference in process between the two wafers is the duration of gate oxidation.
    Estimated
    Crystal Oxide Rds1 Rds2 Rds3
    Orientation thickness Vth Vgs = 10 V Vgs = 4.5 V Vgs = 2.5 V Qg
    100 250 Å 0.99 V 0.37 Ohm 0.37 Ohm 0.37 Ohm 1.02 nC
    110 330 Å 1.33 V 0.31 Ohm 0.31 Ohm 0.31 Ohm 0.82 nC
  • Estimated
    Crystal Oxide Rds1 Rds2
    Orientation thickness Vth Vgs = 10 V Vgs = 4.5 V Qg
    100 450 Å 1.7 V 0.37 Ohm 0.83 Ohm
    110 600 Å 2.6 V 0.31 Ohm 0.78 Ohm

    It is clear from those measured data that there is a significant increase in threshold voltage, i.e., Vth, caused by the thicker oxide for (110) oriented device. However, there is a marked improvement in on-resistance, especially at higher gate bias, showing that there must have been a large improvement in the hole-channel mobility.
  • Therefore, a need still exists in the art of MOSFET device design and manufacture to provide new design method and device configuration in forming the MOSFET channel along the (110) plane to achieve device performances.
    • SUMMARY OF THE PRESENT INVENTION
  • It is therefore an object of the present invention to provide a new design and manufacturing methods and device configuration for the power MOSFET devices to take advantages of building the devices on planes of different crystal orientations such that the limitations of the conventional methods can be overcome.
  • Specifically, it is an object of the present invention to provide improved MOSFET devices manufactured with a trenched gate by forming part of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth. In a special preferred embodiment, forming the trenches with a stripe configuration, and choosing a different orientation of the seed crystal can produce an orientation of the trench with both sidewalls and bottom surface align along a (110) crystal orientation of the semiconductor substrate.
  • Briefly in a preferred embodiment this invention discloses a trenched MOSFET power transistor that includes a gate disposed in a trench formed in a semiconductor substrate. The trench further includes sidewalls and a trench bottom surface all formed along a (110) crystal orientation of the semiconductor substrate. In a preferred embodiment, the MOSFET power transistor is a P-channel MOSFET power transistor. In a different preferred embodiment, this invention further discloses a trenched MOSFET power transistor comprising a gate disposed in a trench formed in a semiconductor substrate. The trench further includes sidewalls formed along a first crystal orientation of the semiconductor substrate and a trench bottom surface formed along a second crystal orientation of the semiconductor substrate different from the first crystal orientation. The trench further includes an oxide layer covering the sidewalls having a substantially the same thickness as an oxide layer covering the bottom surface of the trench.
  • These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross sectional view of a MOSFET device manufactured according to a process of this invention;
  • FIG. 2 shows two identical MOSFETs next to each other on the same wafer, with the channel formed on (100) and (110) interfaces on the vertical sidewall respectively on a (100) wafer.
  • FIGS. 3A and 3B are perspective views for showing the crystal orientations of a silicon ingot and the configuration of a trench;
  • FIG. 4A to 4C are cross sectional views for showing the process to form the trench aligned along different crystal orientations of a semiconductor substrate;
  • FIG. 5 is a perspective view for showing the termination tip of a trench to minimize the (100) plane effect;
  • FIGS. 6A to 6C are perspective views for showing manufacturing processes using SOG to thicken the oxide at the termination of a trench;
  • FIGS. 7A and 7B are perspective views for showing an annealing process to produce trench oxide layer covering (110) and (100) planes of uniform thickness;
  • FIGS. 8A to 8C show the cross sectional view of another embodiment using (100) wafer as starting material, following the steps described in FIGS. 4A-4C;
  • FIG. 9 is a perspective view of a P-channel DMOS with channel along (110) plane; and
  • FIG. 10 is a perspective view of a wafer and the trench for a N-channel trenched MOSFET device with the bottom of the trench formed on a (110) plane and the sidewalls on the (100) plane.
    • DETAILED DESCRIPTION OF THE METHOD
  • For P-channel implementations, FIGS. 3A and 3B show the orientations of the substrate and trench according to the current invention. In FIG. 3A, the silicon ingot 125 is grown in the (110) plane. The silicon ingot 125 provides a configuration that four sidewalls are situated with four sidewall surfaces forming a corner with a corner angle of 90 degrees, thus these sidewall surfaces are perpendicular to each other. Two of these sidewalls are along a (100) crystal orientation and two are along a (110) crystal orientation. Referring to FIG. 3A, two sidewalls 150 and bottom 155 of the trench 148 are formed along a (110) crystal orientation while the termination end surface 160 of the trench 148 is formed along a (100) crystal orientation. In FIG. 3B, the wafer 325 is formed by rotating a normal (100) wafer as shown in FIG. 2 by 45° thus forming two interface planes on a (110) plane while the top and bottom planes are still on the (100) plane. As can be observed from FIG. 3B, when a trench 348 is formed with the sidewalls 350 along the (110) plane, the bottom 355 of the trench is still oriented along a (100) plane. Due to these different orientations, the gate oxide layer along the sidewalls formed along the (110) will be thicker than the gate oxide layer formed on the bottom of the trench along the (100) plane during thermal oxidation process. In order to fabricate a device capable of an operating voltage at a given gate voltage, the thin oxide bottom or end surface of the trench sets the minimum oxide thickness usable. This then forces the use of a thicker oxide along the sidewall compared to a device with all trench sides along the (100), and causes a higher threshold voltage for a given channel doping profile. To minimize the effect of (100) surface, stripe structure design with round termination or round bottom is incorporated with dielectric layer thickening techniques to provide improve P-channel trench MOSFET device.
  • Referring to FIG. 4A, one embodiment uses (110) wafer 125 as substrate. An oxide layer 135 is formed on the top (110) surface by thermal oxidation. A trench mask 145 is used to expose the silicon dioxide in the area for forming the trenches as shown in FIG. 4C below. In one embodiment, the trench mask may have a round or oval shape where the trench ends. As shown in FIG. 5, this produces a trench with round termination therefore the section lying along the (100) plane during trench dry etching process is minimized. Referring to FIG. 4B, after the exposed oxide is removed by etching, the photoresist 145 is stripped off and the remaining oxide layer 135 forms the hard mask for forming the trenches where the oxide layer 135 is removed. Referring now to FIG. 4C, the trenches 148 are then formed along the (110) direction on the wafer by dry etching process. Thus, by using a stripe design, it is possible for the trench MOSFET to have the trench sidewalls 150 and the channel, and the trench bottom 155 along a (110) interface, making the gate oxide thickness uniform both along the sidewall and at the trench bottom. Therefore, the on resistance of the device may be reduced. However, as that shown in FIG. 5, in the area 160 where the trench terminates, some part of the tip will be in the (100) plane. The gate oxide may be thinner at the trench termination area 160 thus limiting gate maximum rating of the gate oxide.
  • In order to overcome the technical difficulties caused by a non-uniform thickness of the gate dielectric layer when part of the device is formed along different crystal orientations, the thickness of oxide layer around (100) plane is enhanced to provide a gate oxide layer with uniform thickness or even thicker at the trench bottom or at the trench termination. Numerous oxide thickening techniques may be used to achieve the above design goal. Several measures are disclosed in this invention.
  • FIGS. 6A to 6C shows another P-channel MOSFET device 200 that has a configuration with the trench sidewalls formed along the (110) plane while using a mask to form thicker oxide in the designated areas thus minimizing the effects of uneven thickness of gate oxide layer. After the trench is formed, it is filled with oxide 210 using techniques such as SOG (spin on glass) or oxide deposition as shown in FIG. 6A. Alternatively, an oxide layer may thermally be grown over the entire Silicon surface. A mask 220 is used to generate a protection area at the trench termination as that shown in FIG. 6B. The oxide is then etched back with the oxide in the terminal area intact as that shown in FIG. 6C. A sacrificial oxide layer may be thermally grown and then removed by wet etch to remove the defects on silicon surface on the bottom and the sides of the trench caused by the harsh etching process during trench formation and SOG etch back. A high quality gate oxide is then thermally grown (not shown).
  • FIGS. 7A to 7B show another embodiment, using a high temperature gate anneal to flow the oxide, so its thickness loses its orientation dependence. As seen in FIG. 7A, when following the regular process, the gate oxide layer 260 is thinner at the trench termination tip portion of (100) plan. After annealing at a temperature higher than 950° C., silicon oxide goes into viscous flow and losses its orientation dependence to yield a film with uniform thickness. FIG. 7B shows the result after 1200° C. of annealing for 5 minutes.
  • FIGS. 8A to 8C show another embodiment using (100) wafer 325 as starting material. Following the steps described in FIGS. 4A-4C, a trench 348 with both side walls 350 and termination end faces (not shown) on (110) plane is obtained. The trench bottom 355 is in (100) plane. An additional ion reactive etching process is performed to round the bottom 355 of the trench. To overcome the technical difficulties caused by a non-uniform thickness of the gate oxide layer when part of the device is formed along different crystal orientations, the thickness of oxide layer around (100) trench bottom is enhanced to provide a gate oxide layer with uniform thickness or even thicker at the trench bottom or at the trench termination. Referring to FIG. 8B, a layer of oxide is deposited to fill the bottom of trench. Alternatively, polysilicon may be deposited and then oxidized, or SOG may be used to fill the trench. The oxide is then etched back. In one embodiment, the oxide is etched with a mask. In another embodiment, the oxide is etched backed without using a mask. The etch back process goes on until the thickness of the bottom oxide 310 reaches a predetermined thickness (FIG. 8C). A sacrificial oxide layer may be thermally grown and then removed by wet etch to remove the defects on silicon surface on the sides of the trench caused by the harsh etching process during trench formation and oxide etch back. A high quality gate oxide is then thermally grown. As shown in FIG. 8D, this yields a layer of gate oxide 320 lining within the trench 348 where the oxide thickness at the bottom portion 355 has been increased so that the overall thickness is substantially the same.
  • Other techniques and any of combinations of these techniques including those mentioned above can be used to increase the thickness of thin dielectric layer portion in the trench when part of the device is formed along different crystal orientations. This will improve the device rating without deteriorating the performance.
  • After the gate dielectric layer is formed in the trench, standard trench MOSFET processes are carried out to complete the fabrication of a MOSFET device 400 as that shown in FIG. 9. The processes for the formation of the gate 410, the body 420, the source 430, BPSG deposition 440, and contact with the substrate 405 functioning as a drain are well know in the art, to form the device as shown in FIG. 9. This invention discloses a trenched MOSFET device 400 formed on a silicon substrate with sidewalls of the trench formed along a (110) crystal plane. The sidewalls and the bottom surface are covered with an dielectric layer 415 having substantially a uniform thickness on the sidewalls and the bottom surface. In one embodiment, the trench and gate is formed before the formation of body or source. In another embodiment, the trench and gate is formed after the formation of body or source.
  • Referring to FIG. 10 are perspective views for forming an N-channel trenched MOSFET device with a part of the device on a (110) plane. The wafer 510 is a (110) wafer. A stripe design is implemented wherein a trenched N-channel MOSFET 500 is formed with the trenches 520 perpendicular to the (110) direction. This orientation of the trench results in a configuration where the sidewalls 525 of the trench 520 are formed on the (100) plane while the bottom of the trench 530 is formed on a (110) plane. This process naturally produces a thicker gate oxide on the bottom of the trench. The thicker oxide at the bottom has several advantages that the thick gate oxide at the bottom reduces the gate-drain capacitance, leading to a faster switching MOSFET. Furthermore, the thicker gate oxide at the bottom of the trench reduces the electric field at the trench bottom, increasing the breakdown voltage. This allows the designer to increase the epitaxial layer doping, thereby lowering the on-resistance of the MOSFET. For a stripe configuration as shown, the trench termination will also lie on a 110 plane, and since the oxide is thicker here, there is no penalty in gate voltage rating.
  • Thus this invention discloses a N-channel MOSFET device having a trench wherein a sidewall of the trench is oriented along a different crystal orientation than a bottom of the sidewall. In a preferred embodiment, the bottom of the trench is oriented along a (110) crystal plane. In another preferred embodiment, the sidewall is oriented along a (100) crystal plane. In yet another embodiment, the trench and gate is formed before the formation of body or source. In yet another embodiment, the trench and gate is formed after the formation of body or source.
  • Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.

Claims (42)

1. A trenched semiconductor power device comprising a gate disposed in a trench formed in a semiconductor substrate wherein:
said trench further comprising sidewalls formed along a first crystal orientation of said semiconductor substrate for enhancing a carrier mobility in a channel disposed near said sidewalls in an active cell region of said substrate and said trench further comprising a trench bottom surface formed along a second crystal orientation different from said first crystal orientation of said semiconductor substrate and said trench further comprising a gate oxide layer covering said sidewalls and said bottom surface having a substantially same gate oxide thickness.
2. The trenched semiconductor power device of claim 1 wherein:
said semiconductor power device is a P-channel MOSFET power device and said sidewalls formed along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device having a reduced on-resistance.
3. The trenched semiconductor power device of claim 1 wherein:
said sidewalls of said trench formed along a (110) crystal orientation and said bottom surface of said trench having a round-shaped surface and formed along a (100) crystal orientation of said semiconductor substrate wherein said round-shaped bottom surface is covered with a gate oxide layer substantially of same thickness as a gate oxide layer covering said sidewalls.
4. The trenched semiconductor power device of claim 2 wherein:
said sidewalls and said bottom surface of said trench are covered with an annealed gate oxide layer having substantially a same gate oxide layer thickness.
5. A trenched MOSFET power transistor comprising a gate disposed in a trench formed in a semiconductor substrate wherein:
said trench further comprising sidewalls formed along a first crystal orientation of said semiconductor substrate for enhancing a carrier mobility in a channel disposed near said sidewalls in an active cell region of said substrate and a trench bottom surface formed along a second crystal orientation of said semiconductor substrate different from said first crystal orientation; and
said trench further comprising an dielectric layer having different thickness formation rates on said sidewalls and said trench bottom covering said sidewalls having a substantially a same thickness as an dielectric layer covering said bottom surface of said trench.
6. The trenched MOSFET power transistor of claim 5 wherein:
said sidewalls are formed along a (110) crystal orientation and said bottom surface is formed along a (100) crystal orientation wherein said dielectric layer having a higher thickness formation rate on said sidewalls than on said bottom surface.
7. The trenched MOSFET power transistor of claim 5 wherein:
said MOSFET power transistor is a P-channel MOSFET power transistor and said sidewalls are formed along a (110) crystal orientation and said bottom surface is formed along a (100) crystal orientation.
8. The trenched MOSFET power transistor of claim 5 wherein:
at least one of sidewalls is formed along a (100) crystal orientation having a round sidewall surface and said bottom surface is formed along a (110) crystal orientation wherein said dielectric layer having a lower thickness formation rate on said sidewalls than on said bottom surface.
9. An N-channel trenched MOSFET power transistor includes a trenched gate disposed in a trench wherein:
sidewalls of said trench are formed along a (100) crystal orientation and a trench bottom surface is formed along a (110) crystal orientation whereby said trench bottom surface having a thicker layer surface for reducing a gate-to-drain capacitance.
10. The trenched MOSFET power transistor of claim 5 wherein:
said dielectric layer is an oxide layer having substantially a same thickness covering said sidewalls and said bottom surface of said trench wherein said oxide layer having a higher thickness formation rate on said sidewalls than on said bottom surface.
11. A trenched MOSFET power transistor comprising a gate disposed in a trench formed in a semiconductor substrate wherein:
said trench disposed in an active cell area further comprising two sidewalls formed along a first crystal orientation and two other sidewalls formed along a second crystal orientation of said semiconductor substrate and a trench bottom surface formed along said second crystal orientation different from said first crystal orientation of said semiconductor substrate; and
said trench further comprising a dielectric layer covering said sidewalls having a substantially same thickness as an dielectric layer covering said bottom surface of said trench.
12. The trenched MOSFET power transistor of claim 11 wherein:
said MOSFET power transistor is a P-channel MOSFET power transistor having an enhanced P-type carrier mobility along sidewalls of (110) crystal orientation whereby said P-channel MOSFET power transistor having a reduced on-resistance.
13. The trenched MOSFET power transistor of claim 11 wherein:
said dielectric layer is an oxide layer having substantially a same thickness covering said sidewalls and said bottom surface of said trench wherein two of said sidewalls formed along said second crystal orientation having a round sidewall surface in order to form said oxide layer to have said substantially a same thickness covering said two sidewalls formed along said first crystal orientation.
14. A trenched MOSFET power transistor comprising a gate disposed in a trench formed in an active cell area of a semiconductor substrate wherein:
said trench constituting an elongated stripe further comprising sidewalls along an elongated direction formed along a first crystal orientation of said semiconductor substrate for improving a device performance of said MOSFET power transistor and a trench termination end surface at terminal ends of said elongated stripe along a second crystal orientation of said semiconductor substrate different from said first crystal orientation.
15. The trenched MOSFET power transistor of claim 14 wherein
said termination end surface having a curved surface whereby said termination end surface only having a small tip portion formed along said second crystal orientation of said semiconductor substrate different from said first crystal orientation whereby device performance improvements along said sidewalls formed in said first crystal orientation along said elongated direction may be increased and device performance differences arising from said second crystal orientation on said small tip portion are reduced.
16. The trenched MOSFET power transistor of claim 14 wherein:
said sidewall are formed along a (110) crystal orientation and said termination end surface is formed along a (100) crystal orientation for increasing a device performance improvement because of sidewalls formed along said (110) crystal orientation and device performance differences arising from said end surface formed along said (100) crystal orientation may are reduced.
17. The trenched MOSFET power transistor of claim 14 wherein:
said MOSFET power transistor is a P-channel MOSFET power transistor and said sidewalls formed along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device having a reduced on-resistance.
18. The trenched MOSFET power transistor of claim 14 wherein:
said MOSFET power transistor is a N-channel MOSFET power transistor and said sidewalls along said elongated direction are formed along a (100) crystal orientation and said termination end surface is formed along a (110) crystal orientation.
19. The trenched MOSFET power transistor of claim 14 wherein:
said MOSFET power transistor is a N-channel MOSFET power transistor and said trench having a bottom surface formed along a (110) crystal orientation to form a thick oxide layer thereon to reduce a gate-to-drain capacitance.
20. A trenched MOSFET power transistor comprising a gate disposed in a trench formed in an active cell area of a semiconductor substrate wherein:
said trench constituting an elongated stripe further comprising sidewalls along an elongated direction of said elongated stripe formed along a first crystal orientation of said semiconductor substrate for improving a device performance of said MOSFET power transistor and a trench termination end surface at terminal ends of said elongated stripe having a significantly less areas than said sidewalls along said elongated direction formed along a second crystal orientation of said semiconductor substrate different from said first crystal orientation; and
said trench further comprising an dielectric layer covering said sidewalls and said termination end surface wherein said dielectric layer having different formation growth rates along said first crystal orientation and said second crystal orientation.
21. The trenched MOSFET power transistor of claim 20 wherein:
said sidewall are formed along a (110) crystal orientation and said termination end surface is formed along a (100) crystal orientation for increasing a device performance improvement because of sidewalls formed along said (110) crystal orientation and device performance differences arising from said end surface formed along said (100) crystal orientation may are reduced.
22. The trenched MOSFET power transistor of claim 20 wherein:
said MOSFET power transistor is a P-channel MOSFET power transistor and said sidewalls formed along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device having a reduced on-resistance.
23. The trenched MOSFET power transistor of claim 20 wherein:
said MOSFET power transistor is a N-channel MOSFET power transistor and said sidewall along said elongated direction are formed along a (100) crystal orientation and said termination end surface is formed along a (110) crystal orientation.
24. The trenched MOSFET power transistor of claim 20 wherein:
said MOSFET power transistor is a N-channel MOSFET power transistor and said trench having a bottom surface formed along a (110) crystal orientation to form a thick oxide layer thereon to reduce a gate-to-drain capacitance.
25. The trenched MOSFET power transistor of claim 20 wherein:
said dielectric layer is an oxide layer having a substantially a same thickness covering said sidewalls and said termination end surface of said trench wherein termination end surface formed along said second crystal orientation having a round sidewall surface in order to form said oxide layer to have said substantially a same thickness covering said termination end surface formed along said first crystal orientation.
26. A method for manufacturing a trenched MOSFET power transistor by forming a trench in a semiconductor substrate and then forming a gate in said trench wherein:
said step of forming said trench further comprising a step of forming said trench with sidewalls along a first crystal orientation of said semiconductor substrate for enhancing a carrier mobility in a channel disposed near said sidewalls in an active cell region of said substrate and forming a trench bottom surface along a second crystal orientation different from said first crystal orientation of said semiconductor substrate; and
forming a gate oxide layer covering said sidewalls and said bottom surface having a substantially same gate oxide thickness.
27. The method of claim 26 further comprising a step of:
manufacturing said MOSFET power transistor as a P-channel MOSFET power transistor with said sidewalls surface along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device a a reduced on-resistance.
28. A method for manufacturing a trenched MOSFET power transistor by forming a trench in a semiconductor substrate and then forming a gate in said trench wherein:
said step of forming said trench further comprising a step of forming said trench with sidewalls along a first crystal orientation of said semiconductor substrate for enhancing a carrier mobility in a channel disposed near said sidewalls in an active cell region of said substrate and a trench bottom surface along a second crystal orientation of said semiconductor substrate different from said first crystal orientation; and
covering said sidewalls and said bottom surface with an dielectric layer having different formation rates on said side wall and said trench bottom having substantially a same thickness on said sidewalls and said bottom surface.
29. The method of claim 28 further comprising a step of:
forming at least one of said sidewall along a (110) crystal orientation and said bottom surface along a (100) crystal orientation having a round bottom surface wherein said dielectric layer having a lower thickness formation rate on said bottom surface than said sidewall surface.
30. The method of claim 28 further comprising a step of:
manufacturing said MOSFET power transistor as a P-channel MOSFET power transistor and forming said sidewalls surface along a (110) crystal orientation and said bottom surface along a (100) crystal orientation.
31. The method of claim 28 further comprising a step of:
forming at least one of said sidewalls along a (100) crystal orientation having a round sidewall surface and said bottom surface along a (110) crystal orientation with said dielectric layer having a lower thickness formation rate on said sidewalls than on said bottom surface.
32. A method for manufacturing an N-channel MOSFET power device having a trench comprising:
forming sidewalls of said trench along a (100) crystal orientation and a trench bottom surface along a (110) crystal orientation whereby said trench bottom surface having a thicker layer surface for reducing a gate-to-drain capacitance.
33. A method for manufacturing a trenched MOSFET power transistor by forming a trench in an active cell area of a semiconductor substrate and then forming a gate in said trench wherein:
said step of forming said trench further comprising a step of forming said trench as an elongated stripe with sidewalls along an elongated direction along a first crystal orientation of said semiconductor substrate for improving a device performance of said MOSFET power transistor and a trench termination end surface at terminal ends of said elongated stripe having a curved surface whereby said termination end surface only having a small tip portion formed along a second crystal orientation of said semiconductor substrate different from said first crystal orientation whereby device performance improvements along said sidewalls formed in said first crystal orientation along said elongated direction may be increased and device performance differences arising from said second crystal orientation on said small tip portion are reduced.
34. The method of claim 33 further comprising a step of:
forming said sidewall along a (110) crystal orientation and said termination end surface along a (100) crystal orientation for increasing a device performance improvement because of sidewalls formed along said (110) crystal orientation and device performance differences arising from said end surface formed along said (100) crystal orientation may are reduced.
35. The method of claim 33 further comprising a step of:
manufacturing said MOSFET power transistor as a P-channel MOSFET power transistor and forming said sidewalls along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device having a reduced on-resistance.
36. The method of claim 33 further comprising a step of:
forming said MOSFET power device as an N-channel device and forming said sidewall along said elongated direction along a (100) crystal orientation and said termination end surface along a (110) crystal orientation.
37. The method of claim 33 further comprising a step of:
manufacturing said MOSFET power transistor as a N-channel MOSFET power transistor and forming said trench bottom surface along a (110) crystal orientation for increasing a oxide layer thickness thereon to reduce a gate-to-drain capacitance.
38. A method for manufacturing a trenched MOSFET power transistor by forming a trench in an active cell area of a semiconductor substrate and then forming a gate in said trench wherein:
said step of forming said trench further comprising a step of forming said trench as an elongated stripe with sidewalls along an elongated direction of said stripe along a first crystal orientation of said semiconductor substrate for improving a device performance of said MOSFET power transistor and a trench termination end surface at terminal ends of said elongated stripe having a significantly less areas than said sidewalls along said elongated direction along a second crystal orientation of said semiconductor substrate different from said first crystal orientation; and
forming an dielectric layer covering said sidewalls and said termination end surface wherein said dielectric layer having different formation growth rates along said first crystal orientation and said second crystal orientation.
39. The method of claim 38 further comprising a step of:
forming said sidewall along a (110) crystal orientation and said termination end surface along a (100) crystal orientation for increasing a device performance improvement because of sidewalls formed along said (110) crystal orientation and device performance differences arising from said end surface formed along said (100) crystal orientation may are reduced.
40. The method of claim 38 further comprising a step of:
manufacturing said MOSFET power transistor as a P-channel MOSFET power transistor and forming said sidewalls along a (110) crystal orientation of said semiconductor substrate for enhancing a P-type carrier mobility whereby said P-channel MOSFET power device having a reduced on-resistance.
41. The method of claim 38 further comprising a step of:
forming said MOSFET power transistor as an N-channel MOSFET power transistor and forming said sidewall along said elongated direction along a (100) crystal orientation and said termination end surface along a (110) crystal orientation.
42. The method of claim 38 further comprising a step of:
manufacturing said MOSFET power transistor as a N-channel MOSFET power transistor and forming said trench with a bottom surface formed along a (110) crystal orientation to form a thick oxide layer thereon to reduce a gate-to-drain capacitance.
US10/996,561 2004-11-23 2004-11-23 Trenched MOSFETS with part of the device formed on a (110) crystal plane Abandoned US20060108635A1 (en)

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PCT/US2005/042743 WO2006058210A1 (en) 2004-11-23 2005-11-23 Improved trenched mosfets with part of the device formed on a (110) crystal plane
US11/634,031 US20110042724A1 (en) 2004-11-23 2005-11-23 Trenched mosfets with part of the device formed on a (110) crystal plane
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US10084037B2 (en) 2007-10-05 2018-09-25 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US20100059797A1 (en) * 2008-09-09 2010-03-11 Tat Ngai (110)-oriented p-channel trench mosfet having high-k gate dielectric
US8039877B2 (en) 2008-09-09 2011-10-18 Fairchild Semiconductor Corporation (110)-oriented p-channel trench MOSFET having high-K gate dielectric
US20110053326A1 (en) * 2009-08-27 2011-03-03 Vishay-Siliconix Super junction trench power mosfet device fabrication
US9425306B2 (en) 2009-08-27 2016-08-23 Vishay-Siliconix Super junction trench power MOSFET devices
US9443974B2 (en) 2009-08-27 2016-09-13 Vishay-Siliconix Super junction trench power MOSFET device fabrication
US9431530B2 (en) 2009-10-20 2016-08-30 Vishay-Siliconix Super-high density trench MOSFET
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US8415718B2 (en) * 2009-10-30 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming epi film in substrate trench
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US10720361B2 (en) 2011-11-22 2020-07-21 Taiwan Semiconductor Manufacturing Company Methods and apparatus for MOS capacitors in replacement gate process
US10354920B2 (en) 2011-11-22 2019-07-16 Taiwan Semiconductor Manufacturing Company Methods and apparatus for MOS capacitors in replacement gate process
US10229988B2 (en) 2012-05-30 2019-03-12 Vishay-Siliconix Adaptive charge balanced edge termination
US10283587B2 (en) 2014-06-23 2019-05-07 Vishay-Siliconix Modulated super junction power MOSFET devices
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US10527654B2 (en) 2014-08-19 2020-01-07 Vishay SIliconix, LLC Vertical sense devices in vertical trench MOSFET
US10234486B2 (en) 2014-08-19 2019-03-19 Vishay/Siliconix Vertical sense devices in vertical trench MOSFET
US10444262B2 (en) 2014-08-19 2019-10-15 Vishay-Siliconix Vertical sense devices in vertical trench MOSFET
US10340377B2 (en) 2014-08-19 2019-07-02 Vishay-Siliconix Edge termination for super-junction MOSFETs
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
US10256236B2 (en) 2016-10-14 2019-04-09 Alpha And Omega Semiconductor Incorporated Forming switch circuit with controllable phase node ringing
US10103140B2 (en) 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
CN106910774A (en) * 2017-03-06 2017-06-30 北京世纪金光半导体有限公司 Silicon carbide power MOSFET element of arc chord angle U-shaped slot grid structure and preparation method thereof

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US20080211070A1 (en) 2008-09-04

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