US20060115932A1 - Method for fabricating semiconductor components with conductive vias - Google Patents
Method for fabricating semiconductor components with conductive vias Download PDFInfo
- Publication number
- US20060115932A1 US20060115932A1 US11/332,929 US33292906A US2006115932A1 US 20060115932 A1 US20060115932 A1 US 20060115932A1 US 33292906 A US33292906 A US 33292906A US 2006115932 A1 US2006115932 A1 US 2006115932A1
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- Prior art keywords
- substrate
- forming
- conductive member
- contact
- opening
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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Abstract
A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.
Description
- This application is a division of Ser. No. 10/998,269 filed Nov. 26, 2004, which is a division of Ser. No. 10/316,349 filed Dec. 11, 2002, U.S. Pat. No. 6,903,442, which is a division of Ser. No. 10/035,355 filed Jan. 4, 2002, U.S. Pat. No. 6,620,731, which is a continuation-in-part of Ser. No. 09/961,646 filed Sep. 25, 2001, U.S. Pat. No. 6,833,613, which is a division of Ser. No. 09/385,606 filed Aug. 30, 1999, U.S. Pat. No. 6,294,387, which is a division of Ser. No. 08/993,965 filed Dec. 18, 1997, U.S. Pat. No. 6,107,109.
- This invention relates generally to semiconductor manufacture, and specifically to a method for fabricating semiconductor components and interconnects with contacts on opposing sides.
- Semiconductor components include external contacts that allow electrical connections to be made from the outside to the integrated circuits contained on the components. A semiconductor die, for example, includes patterns of bond pads formed on the face of the die. Semiconductor packages, such as chip scale packages, also include external contacts. One type of semiconductor package includes solder balls arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA).
- Typically, a component includes only one set of external contacts on either the face side (circuit side) or the back side of the component. However, it is sometimes necessary for a component to have external contacts on both sides. For example, for stacking a semiconductor package to another identical package, external contacts can be formed on the face of the package and on the back side as well. U.S. Pat. No. 6,271,056 to Farnworth et al. discloses this type of stackable package.
- Interconnects configured to make electrical connections with semiconductor components also include external contacts. A wafer probe card is one type of interconnect adapted to make electrical connections between external contacts on a wafer under test, and test circuitry associated with a wafer handler. Another type of interconnect is adapted to electrically engage unpackaged dice, or chip scale packages, packaged within a test carrier. U.S. Pat. No. 5,541,525 to Wood et al. discloses this type of interconnect and test carrier.
- In each of these examples, the interconnect includes external contacts for electrically engaging the external contacts on the semiconductor component. With a conventional needle probe card the external contacts comprise probe needles. With an interconnect used with a test carrier as described above, the interconnect contacts can comprise projections formed on a silicon substrate and covered with a conductive layer.
- As with semiconductor components, the external contacts for an interconnect are often formed on both sides of the interconnect. For example, a probe card can include contacts on its face for electrically engaging the component, and contacts on its back side for electrically engaging spring loaded pins (e.g., “POGO PINS”) in electrical communication with test circuitry. U.S. Pat. No. 6,060,891 to Hembree et al. discloses this type of interconnect.
- The present invention is directed to a method for fabricating semiconductor components and interconnects with contacts on opposing sides.
- In accordance with the present invention, a method for fabricating semiconductor components and interconnects is provided. Also provided are improved components and interconnects fabricated using the method, and improved electronic assemblies and test systems incorporating the components and the interconnects.
- Initially a substrate having a face side, an opposing back side and a plurality of substrate contacts on the face side. For fabricating semiconductor components, such as packages, the substrate can comprise a semiconductor die containing integrated circuits. The substrate contacts can comprise bond pads in electrical communication with the integrated circuits. For fabricating interconnects the substrate can comprise a semiconductor, a ceramic or a plastic. In addition, the substrate contacts can be dummies or omitted entirely.
- The method also includes the step of forming vias through the substrate using a laser beam directed through the substrate contacts. The method also includes the steps of forming conductive members in the vias, and then forming external contacts on the face side and the back side of the substrate in electrical communication with the conductive members. The external contacts can also include a non-oxidizing layer which facilitates making permanent or temporary electrical connections with the external contacts. The external contacts on the face side and the back side can have matching patterns that allows identical components to be stacked to one another. Alternately the external contacts on the face side and the back side can be offset or redistributed with respect to one another.
- A semiconductor component, such as a die, a package or a wafer, fabricated using the method, includes the substrate and the external contacts on the face side and the back side. The external contacts on the face side can be bonded to external contacts on the back side of an identical component to make a stacked assembly. An interconnect fabricated using the method includes the external contacts on the face side which can be configured to electrically engage a semiconductor component. The interconnect also includes external contacts on the back side which can be configured to electrically engage electrical connectors associated with test circuitry.
- In an alternate embodiment of the method, the vias are initially formed as counter bores, and the conductive members are formed in the vias. The substrate is then thinned from the back side using a thinning process, such as chemical mechanical planarization (CMP) or etching, to expose the conductive members.
- An electronic assembly includes multiple stacked components fabricated using the method. Another electronic assembly includes an interconnect fabricated using the method having semiconductor components attached to opposing sides. A test system for testing singulated components, such as dice and packages, includes a die level interconnect mounted to a test carrier configured to temporarily package the components. A test system for testing wafers, or other substrates containing multiple components, includes a wafer level interconnect mounted to a test apparatus such as a wafer prober.
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FIGS. 1A-1G are schematic cross sectional views illustrating a method for fabricating semiconductor components and interconnects on a substrate in accordance with the invention; -
FIG. 2A is a top view taken alongline 2A-2A ofFIG. 1B illustrating a substrate contact on the substrate; -
FIG. 2B is a top view taken alongline 2B-2B ofFIG. 1D illustrating the substrate contact following an etching step but prior to a laser drilling step; -
FIG. 2C is a top view taken alongline 2C-2C ofFIG. 1D illustrating the substrate contact following the laser drilling step; -
FIGS. 3A-3F are schematic cross sectional views illustrating an alternate embodiment method for fabricating semiconductor components and interconnects; -
FIG. 4A is a schematic side elevation view illustrating an electronic assembly fabricated using stackable components fabricated using the method; -
FIG. 4B is a plan view taken alongline 4B-4B ofFIG. 4A ; -
FIG. 5A is a schematic cross sectional view illustrating an electronic assembly that includes an interconnect fabricated using the method; -
FIG. 5B is a cross sectional view taken alongsection line 5B-5B ofFIG. 5A ; -
FIG. 6 is a schematic cross sectional view illustrating a test system that includes an interconnect fabricated using the method; -
FIGS. 7A and 7B are schematic perspective views illustrating a test system that includes a die level interconnect fabricated using the method; -
FIG. 7C is an enlarged cross sectional view taken alongsection line 7C-7C ofFIG. 7B ; -
FIG. 8 is a schematic view illustrating a test system that includes a wafer level interconnect fabricated using the method; -
FIG. 9 is a schematic side elevation view illustrating an electronic assembly fabricated using stackable components fabricated using the method; -
FIG. 10A is a schematic side elevation view illustrating an electronic assembly fabricated using stackable components fabricated using the method; and -
FIG. 10B is a plan view taken alongline 10B-10B ofFIG. 10A . - As used herein, the term “semiconductor component” means an electronic component that includes a semiconductor die. Exemplary semiconductor components include bare semiconductor dice, chip scale packages, ceramic or plastic semiconductor packages, BGA devices, semiconductor wafers, and panels and leadframes containing multiple dice or chip scale packages.
- An “interconnect” means an electronic component configured to make electrical connections with a semiconductor component. A die level interconnect can be configured to electrically engage singulated components such as a die or a package. A wafer level interconnect can be configured to electrically engage a substrate, such as a wafer, a panel, or a leadframe, containing multiple components.
- Referring to
FIGS. 1A-1G , a method for fabricating semiconductor components and interconnects in accordance with the invention is illustrated. Initially as shown inFIG. 1A , asubstrate 10 is provided. Preferably, thesubstrate 10 comprises a wafer of material on which multiple components or interconnects will be fabricated using semiconductor circuit fabrication techniques, and then singulated by cutting the wafer. - If the semiconductor component being fabricated is a package, such as a chip scale package, the
substrate 10 can comprise a semiconductor die containing a plurality of integrated circuits. The die in turn can be contained on a wafer which includes a plurality of dice which are then singulated into individual packages. Depending on the application, the die can be configured as a memory device, as a vertical cavity surface emitting laser device (VCSEL), or in any other conventional configuration. - If the semiconductor component being fabricated is an interconnect, the substrate can comprise a semiconductor material such as monocrystalline silicon, germanium, silicon-on-glass, or silicon-on-sapphire. These materials have a TCE (thermal coefficient of expansion) that matches, or is close to, the TCE of the mating semiconductor component which the interconnect engages. Alternately, the
substrate 10 can comprise a ceramic material, such as mullite, or a plastic material, such as a glass filled resin (e.g., FR-4). - The
substrate 10 includes a face side 14 (“first side” in the claims) and an opposing back side 16 (“second side” in the claims). Theface side 14 and theback side 16 are the major planar surfaces of thesubstrate 10, and are generally parallel to one another. A representative thickness of thesubstrate 10 can be from about 12 mils to 38 mils. A peripheral size and shape of thesubstrate 10 can be selected as required. For example, semiconductor dice have generally rectangular or square peripheral shapes. - As shown in
FIG. 1A , thesubstrate 10 can includesubstrate contacts 18, and a frontside insulating layer 20. Thesubstrate contacts 18 are formed of a highly conductive metal such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals. If thesubstrate 10 is a semiconductor die, thesubstrate contacts 18 can be the device bond pads, or alternately redistribution layer pads, in electrical communication with the integrated circuits contained on the die. - If an interconnect is being fabricated, the
substrate contacts 18 can be dummy contacts, or can be omitted entirely. As shown inFIG. 2A , thesubstrate contacts 18 have a generally square peripheral shape. However, other shapes such as rectangular, circular or oval can also be employed. A size of thesubstrate contacts 18 can also be selected as required (e.g., 10-100 μm on a side). - The front
side insulating layer 20 can comprise an electrically insulating material deposited to a desired thickness using a suitable deposition process (e.g., CVD, sputtering, spin-on). Exemplary materials include glass materials such as BPSG, oxide materials, such as SiO2, or polymer materials, such as polyimide. If thesubstrate 10 is a die, the frontside insulating layer 20 can be the outer passivation layer for the die. A thickness for the frontside insulating layer 20 will be dependent on the material. For example oxide materials can be deposited to thicknesses of 500 Å or less, and polymer materials can be deposited to thicknesses of several mils or more. - As shown in
FIG. 1B , a backside insulating layer 22 is blanket deposited on theback side 16 of thesubstrate 10. The purpose of the backside insulating layer 22 is to provide electrical insulation for theback side 16. The backside insulating layer 22 can be formed of the same materials as previously described for the frontside insulating layer 22 using a suitable deposition process (e.g., CVD, sputtering, spin-on). - As shown in
FIG. 1C , a front sideprotective mask 24 is formed on the frontside insulating layer 20, and a back sideprotective mask 26 is formed on the backside insulating layer 22. Preferably theprotective masks protective masks protective mask 24 is aligned with a mask and exposed using UV light. - As shown in
FIG. 1D , the front sideprotective mask 24 is developed to formopenings 28 aligned with thesubstrate contacts 18. Thesubstrate contacts 18 are then etched such that theopenings 28 also extend through thesubstrate contacts 18 to thesubstrate 10. Depending on the material for the substrate contacts 18 a wet etchant can be used to etch thesubstrate contacts 18. For example, forsubstrate contacts 18 made of aluminum, one suitable wet etchant is H3PO4. -
FIG. 2B illustrates themask 24 and thesubstrate contacts 18 following the etching step but prior to a laser drilling step. As shown inFIG. 2B , theopenings 28 in themask 24 and in thesubstrate contacts 18 are generally circular, and are smaller in diameter than the width of thesubstrate contacts 18. Thesubstrate contacts 18 thus have metal around their peripheries but no metal in the center. In the illustrative embodiment theopenings 28 have a diameter that is about half the width of thesubstrate contacts 18. In addition, theopenings 28 surround a portion of thesubstrate 10, such that thesubstrate contacts 18 and theopenings 28 form targets, or bullseyes, for a subsequent laser drilling step in which a laser beam 33 (FIG. 1D ) is directed at theopenings 28 and through thesubstrate 10. The laser beam 33 (FIG. 1D ) initially pierces thesubstrate 10 on the portions of thesubstrate 10 surrounded by theopenings 28. - As shown in
FIG. 1D , the laser drilling step forms laseredopenings 29 through thesubstrate 10, through the backside insulating layer 22 and through the back sideprotective mask 26.FIG. 2C illustrates themask 24 and thesubstrate contacts 18 following the laser drilling step. As shown inFIG. 2C , the laseredopenings 29 do not touch the metal of thesubstrate contacts 18, as they are located in the middle of theopenings 28 in thesubstrate contacts 18. In the illustrative embodiment, the laseredopenings 29 have diameters that are about half the diameters of theopenings 28. The laser beam 33 (FIG. 1D ) thus initially contacts and pierces thesubstrate 10 without having to contact and pierce the metal that forms thesubstrate contacts 18. This eliminates shorting between the completed external contacts 38 (FIG. 1G ) and thesubstrate 10 because any conducting or semiconducting material redeposited by penetration of thelaser beam 33 will not contact theexternal contacts 38. - Following the laser drilling step, a cleaning step can be performed in which the lasered
openings 29 are cleaned using a suitable wet or dry etchant. One suitable wet etchant for cleaning the laseredopenings 29 with thesubstrate 10 comprising silicon is tetramethylammoniumhydroxide (TMAH). - As shown in
FIG. 1E , the cleaning step forms vias 30 which extend through thesubstrate 10, through the backside insulating layer 22, and through the back sideprotective mask 26. In the illustrative embodiment the vias have diameters that are about twice the inside diameters of the laseredopenings 29, and about equal to the inside diameters of theopenings 28. By way of example, the diameters of the vias 30 can be from 10 μm to 2 mils or greater. - A suitable laser system for performing the laser drilling step is manufactured by Electro Scientific, Inc., of Portland, Oreg. and is designated a Model No. 2700. A representative laser fluence for forming the vias 30 through a silicon substrate having a thickness of about 28 mils, is from 2 to 10 watts/per opening at a pulse duration of 20-25 ns, and at a repetition rate of up to several thousand per second. The wavelength of the laser beam can be a standard UV wavelength (e.g., 455 nm).
- As shown in
FIG. 1E , thevias 30 are preferably generally perpendicular to theface side 14, and to theback side 16 of thesubstrate 10. In addition, thevias 30 are located along alongitudinal axis 31 which preferably extends through the centers of theopenings 28 in the front sideprotective mask 24 and thesubstrate contacts 18. Theopenings 28 and thesubstrate contacts 18 thus provide targets for aligning the laser beam. In addition, theopenings 28 help to compensate for misalignment of the laser beam because theopenings 28 will subsequently determine the peripheral shape of the external contacts 38 (FIG. 1G ). Further, during the laser drilling step theprotective masks face side 14 and theback side 16 of thesubstrate 10. - As also shown in
FIG. 1E , following formation of thevias 30, insulatinglayers 32 can be formed on the inside surfaces of thevias 30. The insulating layers 32 electrically insulate the vias 30 from the rest of thesubstrate 10, and are required if thesubstrate 10 comprises a semiconductor material. The insulating layers 32 can be a grown or deposited material. - With the
substrate 10 comprising silicon, the insulatinglayers 32 can be an oxide, such as SiO2, formed by a growth process by exposure of thesubstrate 10 to an O2 atmosphere at an elevated temperature (e.g., 950° C). In this case the insulatinglayers 32 do not completely close thevias 30, but form only on the sidewalls of thevias 30. Alternately, the insulatinglayers 32 can comprise a deposited electrically insulating material, such as an oxide or a nitride, deposited using a deposition process such as CVD. - The insulating layers 32 can also comprise a polymer material deposited using a suitable deposition process such as screen printing. In this case, if the insulating material completely fills the
vias 30, a subsequent laser drilling step, substantially as previously described, may be required to re-open thevias 30. If thesubstrate 10 comprises an electrically insulating material, such as ceramic, or a glass filled resin, such as FR-4, the insulatinglayers 32 are not required. - Following formation of the insulating
layers 32, conductive members 34 (FIG. 1G ) can be formed within thevias 30. Theconductive members 34 can be plugs that completely fill thevias 30, or alternately, can be layers that cover just the inside surfaces or sidewalls of thevias 30. Theconductive members 34 can comprise a highly conductive metal, such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals. The above metals can be deposited within theopenings 28 using a deposition process, such as electroless deposition, CVD, or electrolytic deposition. Alternately a solder metal can be screen printed in thevias 30 and drawn into thevias 30 with capillary action. A solder metal can also be drawn into thevias 30 using a vacuum system and a hot solder wave. - Rather than being a metal, the
conductive members 34 can comprise a conductive polymer, such as a metal filled silicone, or an isotropic epoxy. Suitable conductive polymers are sold by A.I. Technology, Trenton, N.J.; Sheldahl, Northfield, Minn.; and 3M, St. Paul, Minn. A conductive polymer can be deposited within thevias 30, as a viscous material, and then cured as required. A suitable deposition process, such as screen printing, or stenciling, can be used to deposit the conductive polymer into thevias 30. - In the embodiment illustrated in
FIGS. 1A-1G , theconductive members 34 are formed by an electroless deposition process. To perform the electroless deposition process, a seeding step is performed in which thesubstrate 10, with theprotective masks conductive members 34 the seed solution can comprise a copper sulfate solution available from Shipley. The seed solution adheres to all exposed surfaces including on theprotective masks openings 28. - As shown in
FIG. 1F , following the seeding step, a stripping step is performed in which theprotective masks masks vias 30. - Next, as shown in
FIG. 1G , an electroless deposition step is performed in which a metal is electrolessly deposited into thevias 30 to form theconductive members 34. The electroless deposition step can be performed by dipping thesubstrate 10 in a suitable electroless deposition solution. For example, for depositing copperconductive members 34, the electroless deposition solution can comprise a nickel hypophosphate solution available from Shipley or Packaging Technology of Nauen, Germany. - As shown in
FIG. 1G , the electroless deposition step forms theconductive members 34 with generally concave terminal portions 36 (dish shaped buttons) on the insulatinglayers terminal portions 36 facilitate making electrical connections with bumped contacts, such as solder balls or bumps. Theconductive members 34 are also in electrical communication with thesubstrate contacts 18. In addition, theconductive members 34 at least partially fill thevias 30, and physically contact thesubstrate contacts 18. - As also shown in
FIG. 1G , following formation of theconductive members 34, non-oxidizing metal layers 42 are formed on the concaveterminal portions 36 of theconductive members 34. The non-oxidizing metal layers 42 can be formed using a suitable deposition process such as electroless deposition or CVD. With electroless deposition, a mask is not required, as thesubstrate 10 is dipped into a suitable solution and deposition onto theterminal portions 36 occurs as previously described. With CVD, a mask (not shown) can be formed on the insulatinglayers terminal portions 36 of theconductive members 34. The non-oxidizing metal can then be deposited through the openings to a desired thickness. - Suitable metals for the non-oxidizing metal layers 42 include gold, platinum, and palladium. A representative thickness for the non-oxidizing metal layers 42 can be from 600 Å to 3000 Å or more. In addition, the non-oxidizing metal layers 42 have a concave shape substantially similar to that of the concave
terminal portions 36. Following the depositing of the non-oxidizing metal layers 42 thesubstrate 10 can be singulated into individual components or interconnects if required using a suitable process such as sawing, shearing, punching or etching. - As shown in
FIG. 1G , the faceside insulating layer 20 on theface side 14 of thesubstrate 10 includes face side external contacts 38 (“first external contacts” in the claims). The backside insulating layer 22 on theback side 16 of thesubstrate 10 includes back side external contacts 40 (“second external contacts” in the claims). - The size and spacing of the face side
external contacts 38 matches the size and the spacing of the back sideexternal contacts 40, such that each face sideexternal contact 38 has a mating back sideexternal contact 40 located along a common longitudinal axis 31 (FIG. 1E ). Stated differently, the face sideexternal contacts 38 and the back sideexternal contacts 40 have matching patterns such as a dense grid array. As will be further explained, alternately the back sideexternal contacts 40 can be “offset” or “redistributed” with respect to the face sideexternal contacts 38. - The
conductive members 34 establish electrical communication between the matingexternal contacts substrate 10. In addition, theconductive members 34 establish electrical communication between matingexternal contacts substrate contacts 18. If thesubstrate 10 includes integrated circuits in electrical communication with thesubstrate contacts 18, theexternal contacts FIGS. 3A-3F , an alternate embodiment method for fabricating semiconductor components and interconnects is illustrated. Initially, as shown inFIG. 3A , asubstrate 10A is provided having a front side 14A, aback side 16A,substrate contacts 18A and a frontside insulating layer 20A as previously described. - As shown in
FIG. 3B , a front sideprotective mask 24A is formed on the front side 14A of thesubstrate 10A. Themask 24A is then used to etchopenings 28A in thesubstrate contacts 18A as previously described. In addition, laseredopenings 29A are formed in thesubstrate 10A by directing alaser beam 33A through thesubstrate 10A as previously described. However, in this case the laser drilling step is performed such that thelaser openings 29A are counter bores that do not extend completely through thesubstrate 10A. For forming thelaser openings 29A, parameters of the laser system, such as beam power, power distribution, pulse length and pulse duration of thelaser beam 33, can be adjusted such that the substrate is not pierced. - Next, as shown in
FIG. 3C , a cleaning step is performed in which the laseredopenings 29A are cleaned and enlarged as previously described to formvias 30A. Again thevias 30A are counter bores that do not extend completely through thesubstrate 10A. As also shown inFIG. 3C , insulatinglayers 32A are formed in thevias 30A as previously described. - Next, as shown in
FIG. 3D ,conductive members 34A are formed in thevias 30A. Theconductive members 34A can comprise a metal or a conductive polymer deposited as previously described using a deposition process such as CVD or screen printing. However, in this case themask 24A is retained, and theconductive members 34A are also formed in theopenings 28A and have surfaces generally planar to a surface of themask 24A. - Next, as shown in
FIG. 3E , themask 24A is stripped as previously described. In addition, a thinning step is performed in which thesubstrate 10A is thinned from theback side 16A to form a thinnedsubstrate 10A-T. In addition, the thinning step is controlled to planarize and expose theconductive members 34A on a thinned backside 16A-T of the thinnedsubstrate 10A-T. One process for performing the thinning step is chemical mechanical planarization (CMP). One suitable CMP apparatus for performing the thinning step is a Model 372 manufactured by Westech. The thinning step can also be performed by etching theback side 16A of thesubstrate 10A using a suitable etchant. - Next, as shown in
FIG. 3F ,non-oxidizing layers 42A are formed on theconductive members 34A, as previously described. However, unless thesubstrate 10 comprises an electrically insulating material such as ceramic or plastic, thenon-oxidizing layers 42A on the thinned backside 16A-T must only contact theconductive members 34A and insulatinglayers 32A. The completed front sideexternal contacts 38A and back sideexternal contacts 40A function substantially as previously described. - Referring to
FIGS. 4A and 4B , anelectronic assembly 52 constructed using stackable components 54-1, 54-2 fabricated in accordance with the method of the invention are illustrated. In this embodiment, the stackable components 54-1, 54-2 are in the form of singulated packages having a chip scale configuration. However, it is to be understood that the stackable components 54-1, 54-2 can also comprise stackable semiconductor dice, stackable semiconductor wafers or stackable panels. In addition, although only two components 54-1, 54-2 form theassembly 52, it is to be understood that any number of stackable components can be utilized. - In addition to the stackable components 54-1, 54-2, the
electronic assembly 52 includes a supportingsubstrate 56, such as a printed circuit board or multi chip module substrate, having a plurality ofmetal electrodes 58. The stackable components 54-1, 54-2 are stacked to one another with the back sideexternal contacts 40 on the lowermost component 54-1 bonded to theelectrodes 58 on the supportingsubstrate 56. In addition, the front sideexternal contacts 38 on the lowermost component 54-1 are bonded to the back sideexternal contacts 40 on the uppermost component 54-2. Theexternal contacts external contacts external contacts FIG. 1G ) on theexternal contacts - Referring to
FIGS. 5A and 5B , anelectronic assembly 60 constructed using aninterconnect 66 fabricated in accordance with the invention is illustrated. In this embodiment, theelectronic assembly 60 is in the form of a multi chip module. Theinterconnect 66 includes front sideexternal contacts 38 and back sideexternal contacts 40 as previously described. In addition, theinterconnect 66 includesconductors 68 in electrical communication with thecontacts edge contacts 70 in electrical communication with theconductors 68. - The
electronic assembly 60 also includes a semiconductor package 62-1 having bumpedcontacts 64, such as solder bumps or balls, bonded to the front sideexternal contacts 38 on theinterconnect 66. In addition, theelectronic assembly 60 includes a semiconductor package 62-2 having bumpedcontacts 64 bonded to the back sideexternal contacts 40 on theinterconnect 66. Again, a reflow process or a soldering process can be used to bond the bumpedcontacts 64 to theexternal contacts - Referring to
FIG. 6 , atest assembly 72 constructed using aninterconnect 74 fabricated in accordance with the invention is illustrated. Thetest assembly 72 includestest circuitry 84 configured to generate and apply test signals to a device undertest 76. By way of example, the device undertest 76 can comprise a die, a package, a wafer or a panel having bumpedcontacts 78. Thetest circuitry 84 is in electrical communication with the back sideexternal contacts 40 on theinterconnect 74. The front sideexternal contacts 38 establish temporary electrical connections with thedevice contacts 78. - Referring to
FIGS. 7A-7C , a dielevel test system 80 constructed with aninterconnect 86 fabricated in accordance with the invention is illustrated. Thetest system 80 is configured to temporarily package and testmultiple semiconductor components 88 such as dice, packages, or BGA devices having bumpedcontacts 90. - The
test system 80 includes theinterconnect 86 which is configured to electrically engage the bumpedcontacts 90 on thecomponents 88. Thetest system 80 also includes analignment member 92 configured to align thecomponents 88 on theinterconnect 86, and aforce applying mechanism 94 withelastomeric members 98 configured to bias thecomponents 88 and theinterconnect 86 together. - The
interconnect 86 includes the front sideexternal contacts 38 formed as previously described, and configured to make temporary electrical connections with the bumpedcontacts 90 on thecomponents 88. In addition, theinterconnect 86 includes the back sideexternal contacts 40 formed as previously described but withterminal contacts 96, such as solder balls attached thereto. Theterminal contacts 96 are configured for mating electrical engagement with atest apparatus 82, such as a test socket or burn-in board in electrical communication withtest circuitry 84. Thetest circuitry 84 is configured to apply test signals to the integrated circuits contained on thecomponents 88 and to analyze the resultant signals. - As shown in
FIG. 7B , theforce applying mechanism 94 attaches to thealignment member 92 and theinterconnect 86, and biases thecomponents 88 and theinterconnect 86 together. As shown inFIG. 7C , thealignment member 92 includes taperedalignment openings 100 configured to align thecomponents 88 on theinterconnect 86. - Referring to
FIG. 8 , a waferlevel test system 102 suitable for testing a wafersized semiconductor component 104 with bumpedcontacts 106 is illustrated. By way of example, thesemiconductor component 104 can comprise a semiconductor wafer containing bare dice, a wafer or panel containing chip scale packages, a printed circuit board containing semiconductor dice, or an electronic assembly, such as a field emission display containing semiconductor dice. - The wafer
level test system 102 includes aninterconnect 108 constructed as previously described, and mounted to atesting apparatus 110. Thetesting apparatus 110 includes, or is in electrical communication withtest circuitry 84. Thetesting apparatus 110 also includes awafer chuck 116 configured to support and move thecomponent 104 in x, y and z directions as required. Thetesting apparatus 110 can comprise a conventional wafer probe handler, or probe tester, modified for use with theinterconnect 108. Wafer probe handlers and associated test equipment are commercially available from Electroglass, Advantest, Teradyne, Megatest, Hewlett-Packard and others. In thissystem 102, theinterconnect 108 takes the place of a conventional probe card. - The
interconnect 108 includes the previously described front sideexternal contacts 38 configured to establish temporary electrical connections with the bumpedcontacts 106 on thecomponent 108. In addition, theinterconnect 108 includes the previously described back sideexternal contacts 40 configured to electrically engage spring loaded electrical connectors 114 (e.g., “POGO PINS” manufactured by Pogo Instruments, Inc., Kansas City, Kans.) in electrical communication with the testing circuitry 112. - Referring to
FIG. 9 , anelectronic assembly 118 constructed usingstackable components 54B-1, 54B-2, 54B-3, 54B-4 fabricated in accordance with the method of the invention are illustrated. In this embodiment, thestackable components 54B-1, 54B-2, 54B-3, 54B-4 are in the form of singulated packages having a chip scale configuration substantially similar to the previously described stackable component 54. However, as before stackable semiconductor dice, stackable semiconductor wafers or stackable panels can be employed. In addition, although fourcomponents 54B-1, 54B-2, 54B-3, 120-4 form theassembly 118, it is to be understood that any number of stackable components can be utilized. - Each
stackable component 54B-1, 54B-2, 54B-3, 54B-4 includes face sideexternal contacts 38B and back sideexternal contacts 40B having matching patterns. Eachstackable component 54B-1, 54B-2, 54B-3, 54B-4 also includesconductive members 34B formed using a laser machining process as previously described. In addition, the back sideexternal contacts 40B include bumpedcontacts 120 such as solder balls or bumps attached thereto using a suitable process such as ball bumping, bump deposition or reflow bonding. The bumpedcontacts 120 and face sideexternal contacts 40B onadjacent components 54B-1, 54B-2, 54B-3, 54B-4 are bonded to one another using a suitable bonding process such as reflow bonding. - Referring to
FIGS. 10A and 10B , anelectronic assembly 122 constructed usingstackable components 54C-1, 54C-2, 54C-3, 54C-4 fabricated in accordance with the method of the invention are illustrated. In this embodiment, thestackable components 54C-1, 54C-2, 54C-3, 54C-4 are in the form of singulated packages having a chip scale configuration substantially similar to the previously described stackable component 54. However, as before stackable semiconductor dice, stackable semiconductor wafers or stackable panels can be employed. - Each
stackable component 54C-1, 54C-2, 54C-3 includes face sideexternal contacts 38C and back sideexternal contacts 40C having matching patterns. Eachstackable component 54C-1, 54C-2, 54C-3 also includesconductive members 34C formed using a laser machining process as previously described. In addition, the back sideexternal contacts 40C include bumpedcontacts 124 such as solder balls or bumps attached thereto using a suitable process such as ball bumping, bump deposition or reflow bonding. The bumpedcontacts 122 and face sideexternal contacts 40C onadjacent components 54C-1, 54C-2, 54C-3 are bonded to one another using a suitable bonding process such as reflow bonding. - Although
stackable components 54C-1, 54C-2, 54C-3 have identical configurations, thestackable component 54C-4 has a different configuration. Specifically, the back sideexternal contacts 40C forstackable component 54C-4 are “offset” or “redistributed” with respect to the face sideexternal contacts 38C. As shown inFIG. 10B ,redistribution conductors 126 on the back side of thestackable component 54C-4 are in electrical communication with theconductive members 34C and with the back sideexternal contacts 40C. This arrangement allows the back sideexternal contacts 40C to have a different pattern than the face sideexternal contacts 38C. For example, a pitch P1 of the back sideexternal contacts 38C can be greater than a pitch P2 of the face sideexternal contacts 38C. This arrangement can be used to facilitate bonding of thestackable component 54C-4 and thus theassembly 122 to a supporting substrate, such as a printed circuit board. - Thus the invention provides a method for fabricating semiconductor components and interconnect for semiconductor components. The invention also provides improved electronic assemblies and test systems constructed using components and interconnects fabricated in accordance with the invention.
- Although the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.
Claims (40)
1. A method for fabricating a semiconductor component comprising:
providing a substrate comprising a first side, a substrate contact on the first side, and an opposing second side;
forming an opening through the substrate contact;
forming a via at least partially aligned with the opening through the substrate to the second side; and
forming a conductive member in the opening and the via in electrical contact with the substrate contact.
2. The method of claim 1 wherein the forming the conductive member step comprises electroless deposition or electrolytic deposition of a metal into the opening and the via.
3. The method of claim 1 wherein the forming the conductive member step comprises depositing a conductive polymer into the opening and the via.
4. The method of claim 1 wherein the forming the opening step comprises etching the substrate contact.
5. The method of claim 1 wherein the forming the via step comprises laser machining the substrate.
6. The method of claim 1 wherein the forming the via step comprises etching.
7. The method of claim 1 further comprising forming an insulating layer on a surface of the via prior to the forming the conductive member step.
8. The method of claim 1 wherein the conductive member fills the via.
9. The method of claim 1 wherein the conductive member comprises a layer on a sidewall of the via.
10. The method of claim 1 wherein the substrate comprises a semiconductor die and the substrate contact comprises a pad in electrical communication with at least one integrated circuit on the substrate.
11. The method of claim 1 wherein the substrate comprises a semiconductor die and the substrate contact comprises a bond pad or a redistribution pad in electrical communication with at least one integrated circuit on the die.
12. The method of claim 1 wherein the conductive member comprises a metal, a solder or a conductive polymer.
13. The method of claim 1 further comprising forming a non oxidizing metal layer on a terminal portion of the conductive member.
14. The method of claim 1 further comprising forming a first external contact on the first side in electrical communication with the conductive member and a second external contact on the second side in electrical communication with the conductive member.
15. The method of claim 1 wherein the forming the conductive member step forms generally concave terminal portions on the conductive member.
16. A method for fabricating a semiconductor component comprising:
providing a semiconductor substrate comprising a first side, a substrate contact on the first side in electrical communication with an integrated circuit on the substrate, and an opposing second side;
forming an opening through the substrate contact;
forming a via at least partially aligned with the opening through the substrate to the second side;
forming an insulating layer on a surface of the via; and
forming a conductive material in the opening and the via in electrical contact with the substrate contact.
17. The method of claim 16 wherein the forming the conductive material step comprises electroless deposition, CVD or electrolytic deposition.
18. The method of claim 16 wherein the forming the insulating layer step comprises depositing an oxide, a nitride or a polymer material on the surface.
19. The method of claim 16 further comprising forming a first external contact on the first side in electrical communication with the conductive member and a second external contact on the second side in electrical communication with the conductive member.
20. The method of claim 16 wherein the substrate contact comprises a bond pad or a redistribution pad.
21. The method of claim 16 wherein the substrate comprises a plurality of substrate contacts and the forming the opening step forms a plurality of openings, the forming the vias step forms a plurality of vias, the forming the insulating layer step forms a plurality of insulating layers, and the forming the conductive member step forms a plurality of conductive members.
22. The method of claim 16 wherein the conductive member fills the via.
23. The method of claim 16 wherein the conductive member comprises a layer on a sidewall of the via.
24. The method of claim 16 wherein the conductive member comprises a metal, a solder or a conductive polymer.
25. The method of claim 16 further comprising forming a non oxidizing metal layer on a terminal portion of the conductive member.
26. The method of claim 16 further comprising forming a first external contact on the first side in electrical communication with the conductive member and a second external contact on the second side in electrical communication with the conductive member.
27. The method of claim 16 wherein the forming the opening step comprises etching the substrate contact.
28. The method of claim 16 wherein the forming the via step comprises laser machining the substrate.
29. The method of claim 16 wherein the forming the via step comprises etching.
30. A method for fabricating a semiconductor component comprising:
providing a substrate comprising a first side, a substrate contact on the first side, and an opposing second side;
forming an opening through the substrate contact;
forming a via part way through the substrate at least partially aligned with the opening;
forming a conductive member in the opening and the via in electrical contact with the substrate contact; and
thinning the substrate from the second side to expose the conductive member.
31. The method of claim 30 wherein the forming the conductive member step comprises a method selected from the group consisting of electroless deposition, CVD, electrolytic deposition, screen printing, and stenciling.
32. The method of claim 30 wherein the thinning the substrate step comprises a method selected from the group consisting of planarization, chemical mechanical planarization and etching.
33. The method of claim 30 wherein the substrate comprises a semiconductor die and the substrate contact comprises a pad in electrical communication with at least one integrated circuit on the substrate.
34. The method of claim 30 wherein the forming the opening step comprises etching.
35. The method of claim 30 wherein the forming the via step comprises laser machining and etching.
36. The method of claim 30 wherein the substrate comprises a semiconductor die and the substrate contact comprises a bond pad or a redistribution pad.
37. The method of claim 30 further comprising forming a first external contact on the first side in electrical communication with the conductive member.
38. The method of claim 37 further comprising forming a first non oxidizing layer on the first external contact.
39. The method of claim 30 further comprising forming a second external contact on the second side in electrical communication with the conductive member.
40. The method of claim 39 further comprising forming a second non oxidizing layer on the second external contact.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US08/993,965 US6107109A (en) | 1997-12-18 | 1997-12-18 | Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate |
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US09/961,646 US6833613B1 (en) | 1997-12-18 | 2001-09-25 | Stacked semiconductor package having laser machined contacts |
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US11/332,929 US20060115932A1 (en) | 1997-12-18 | 2006-01-17 | Method for fabricating semiconductor components with conductive vias |
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US11/332,929 Abandoned US20060115932A1 (en) | 1997-12-18 | 2006-01-17 | Method for fabricating semiconductor components with conductive vias |
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US10/998,269 Abandoned US20050101037A1 (en) | 1997-12-18 | 2004-11-26 | Test system with interconnect having conductive members and contacts on opposing sides |
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Also Published As
Publication number | Publication date |
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US20030080408A1 (en) | 2003-05-01 |
US6903443B2 (en) | 2005-06-07 |
US6620731B1 (en) | 2003-09-16 |
US20050101037A1 (en) | 2005-05-12 |
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