US20060131716A1 - Stacking system and method - Google Patents
Stacking system and method Download PDFInfo
- Publication number
- US20060131716A1 US20060131716A1 US11/317,425 US31742505A US2006131716A1 US 20060131716 A1 US20060131716 A1 US 20060131716A1 US 31742505 A US31742505 A US 31742505A US 2006131716 A1 US2006131716 A1 US 2006131716A1
- Authority
- US
- United States
- Prior art keywords
- csp
- contacts
- flex
- circuit module
- density circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06579—TAB carriers; beam leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/05—Flexible printed circuits [FPCs]
- H05K2201/056—Folded around rigid support or component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
- H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
Definitions
- the present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages.
- a variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits.
- the predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration.
- IC integrated circuit
- the enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation.
- Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
- Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages have recently gained market share.
- CSP chip scale packaging
- CSP CSP leads or contacts do not typically extend beyond the outline perimeter of the package.
- the absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
- CSP has enabled reductions in size and weight parameters for many applications.
- micro ball grid array ( ⁇ BGA) for flash and SRAM and wirebond on tape or rigid laminate CSPs for SRAM or EEPROM have been employed in a variety of applications.
- CSP is a broad category including a variety of packages from near chip scale to die-sized packages such as the die sized ball grid array (DSBGA) recently described in proposed JEDEC standard 95-1 for DSBGA.
- DSBGA die sized ball grid array
- CSP technologies that aggregate integrated circuits in CSP technology have recently been developed. For example, Sharp, Hitachi, Mitsubishi and Intel recently undertook support of what are called the S-CSP specifications for flash and SRAM applications.
- the assignee of the present invention has developed previous systems for aggregating ⁇ BGA packages in space saving topologies.
- the assignee of the present invention has systems for stacking BGA packages on a DIMM in a RAMBUS environment.
- U.S. Pat. No. 6,262,895 B1 to Forthun (the “Forthun patent”) purports to disclose a technique for stacking chip scale packaged ICs.
- the Forthun patent discloses a “package” that exhibits a flex circuit wrapped partially about a CSP.
- the flex circuit is said to have pad arrays on upper and lower surfaces of the flex.
- the flex circuit of the Forthun “package” has a pad array on its upper surface and a pad array centrally located upon its lower surface. On the lower surface of the flex there are third and fourth arrays on opposite sides from the central lower surface pad array.
- a CSP contacts the pad array located on the upper surface of the flex circuit. As described in the Forthun patent, the contacts on the lower surface of the CSP are pushed through “slits” in the upper surface pads and advanced through the flex to protrude from the pads of the lower surface array and, therefore, the bottom surface of the package. Thus, the contacts of the CSP serve as the contacts for the package.
- the sides of the flex are partially wrapped about the CSP to adjacently place the third and fourth pad arrays above the upper major surface of the CSP to create from the combination of the third and fourth pad arrays, a fifth pad array for connection to another such package.
- a stacked module of CSPs created with the described packages will exhibit a flex circuit wrapped about each CSP in the module.
- CSPs have various deficiencies including complex structural arrangements and thermal or high frequency performance issues.
- the reliability of chip scale packaging is closely scrutinized.
- CSP devices often exhibit temperature cycle performance issues.
- CSPs are generally directly mounted on a PWB or other platform offset from the PWB by only the height of the ball or bump array emergent from the lower surface of the CSP. Consequently, stresses arising from temperature gradients over time are concentrated in the short lever arm of a low-height ball array.
- the issues associated with temp cycle performance in single CSPs will likely arise in those prior art CSP stacking solutions where the stack is offset from the PWB or application platform by only the height of the lower CSP ball grid array.
- Thermal performance is also a characteristic of importance in CSP stacks. To increase dissipation of heat generated by constituent CSPs, the thermal gradient between the lower CSP and upper CSP in a CSP stack or module should be minimized. Prior art solutions to CSP stacking do not, however, address thermal gradient minimization in disclosed constructions.
- the present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area.
- CSPs chip scale-packaged integrated circuits
- the present invention can be used to advantage with CSP packages of a variety of sizes and configurations ranging from typical BGAs with footprints somewhat larger than the contained die to smaller packages such as, for example, die-sized packages such as DSBGA.
- the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die.
- two CSPs are stacked, with one CSP disposed above the other.
- the two CSPs are connected with a pair of flex circuits.
- Each of the pair of flex circuits is partially wrapped about a respective opposite lateral edge of the lower CSP of the module.
- the flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB).
- PWB printed wiring board
- the present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.
- FIG. 1 is an elevation view of module 10 devised in accordance with a preferred embodiment of the present invention.
- FIG. 2 is an elevation view of module 10 devised in accordance with a preferred embodiment of the present invention.
- FIG. 3 depicts, in enlarged view, the area marked “A” in FIG. 2 .
- FIG. 4 is an enlarged detail of an exemplar connection in a preferred embodiment of the present invention.
- FIG. 5 is an enlarged depiction of an exemplar area around a lower flex contact in a preferred embodiment of the present invention.
- FIG. 6 depicts a first outer surface layer of a flex circuit employed in a preferred embodiment of the present invention.
- FIG. 7 depicts a first outer surface layer of a flex circuit employed in a preferred embodiment of the present invention.
- FIG. 8 depicts a first conductive layer of a flex circuit employed in a preferred embodiment of the present invention.
- FIG. 9 illustrates a first conductive layer of a flex circuit employed in a preferred embodiment of the present invention.
- FIG. 10 depicts an intermediate layer of a flex circuit employed in a preferred embodiment of the present invention.
- FIG. 11 depicts an intermediate layer of a right side flex circuit employed in a preferred embodiment of the present invention.
- FIG. 12 depicts a second conductive layer of a flex circuit of a preferred embodiment of the present invention.
- FIG. 13 depicts a second conductive layer of a flex circuit of a preferred embodiment of the present invention.
- FIG. 14 depicts a second outer layer of a flex circuit employed in a preferred embodiment of the present invention.
- FIG. 15 reflects a second outer layer of a flex circuit employed in a preferred embodiment of the present invention.
- FIG. 16 depicts an alternative preferred embodiment of the present invention.
- FIG. 17 illustrates a JEDEC pinout for DDR-II FBGA packages.
- FIG. 18 illustrates the pinout of a module 10 in an alternative preferred embodiment of the invention.
- FIG. 19 illustrates the pinout of a module 10 in an alternative embodiment of the invention.
- FIG. 20 depicts the pinout of an exemplar CSP employed in a preferred embodiment of the invention.
- FIG. 21 depicts a second conductive layer of a flex circuit employed in an alternative preferred embodiment of the present invention.
- FIG. 22 depicts a second conductive layer of a flex circuit employed in an alternative preferred embodiment of the present invention.
- FIG. 1 is an elevation view of module 10 devised in accordance with a preferred embodiment of the present invention.
- Module 10 is comprised of upper CSP 12 and lower CSP 14 .
- Each of CSPs 12 and 14 have an upper surface 16 and a lower surface 18 and opposite lateral sides 20 and 22 .
- CSPs chip scale packaged integrated circuits
- FIGS. 1 and 2 are depicted with CSPs of a particular profile known to those in the art, but it should be understood that the figures are exemplary only.
- CSPs such as, for example, ball-grid-array (“BGA”), micro-ball-grid array (“ ⁇ BGA”), and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, or balls that extend from lower surface 18 of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Shown in FIG. 1 are CSP contacts 24 along lower surfaces 18 of CSPs 12 and 14 . CSP contacts 24 provide connection to the integrated circuit within the respective packages. Collectively, CSP contacts 24 comprise CSP array 26 shown as to lower CSP 14 in the depicted particular package configuration as CSP arrays 26 1 and 26 2 which collectively comprise CSP array 26 .
- BGA ball-grid-array
- ⁇ BGA micro-ball-grid array
- FBGA fine-pitch ball grid array
- flex circuits (“flex”, “flex circuits” or “flexible circuit structures”) 30 and 32 are shown partially wrapped about lower CSP 14 with flex 30 partially wrapped over lateral side 20 of lower CSP 14 and flex 32 partially wrapped about lateral side 22 of lower CSP 14 .
- Lateral sides 20 and 22 may be in the character of sides or may, if the CSP is especially thin, be in the character of an edge. Any flexible or conformable substrate with a multiple internal layer connectivity capability may be used as a flex circuit in the invention.
- the entire flex circuit may be flexible or, as those of skill in the art will recognize, a PCB structure made flexible in certain areas to allow conformability around lower CSP 14 and rigid in other areas for planarity along CSP surfaces may be employed as an alternative flex circuit in the present invention.
- structures known as rigid-flex may be employed.
- Portions of flex circuits 30 and 32 are fixed to upper surface 16 of lower CSP 14 by adhesive 34 which is shown as a tape adhesive, but may be a liquid adhesive or may be placed in discrete locations across the package.
- adhesive 34 is thermally conductive. Adhesives that include a flux are used to advantage in assembly of module 10 .
- Layer 34 may also be a thermally conductive medium to encourage heat flow between the CSPs of module 10 .
- Flex circuits 30 and 32 are multi-layer flexible circuit structures that have at least two conductive layers.
- the conductive layers are metal such as alloy 110.
- the use of plural conductive layers provides advantages as will be seen and the creation of a distributed capacitance across module 10 intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize.
- Module 10 of FIG. 1 has module contacts 36 collectively identified as module array 38 .
- FIG. 2 shows a module 10 devised in accordance with a preferred embodiment of the invention.
- FIG. 2 illustrates use of a conformal media 40 provided in a preferred embodiment to assist in creating conformality of structural areas of module 10 .
- Planarity of the module is improved by conformal media 40 .
- conformal media 40 is thermally conductive.
- thermal spreaders or a thermal medium may be placed as shown by reference 41 .
- Identified in FIG. 2 are upper flex contacts 42 and lower flex contacts 44 that are at one of the conductive layers of flex circuits 30 and 32 .
- Upper flex contacts 42 and lower flex contacts 44 are conductive material and, preferably, are solid metal.
- Lower flex contacts 44 are collectively lower flex contact array 46 .
- Upper flex contacts 42 are collectively upper flex contact array 48 . Only some of upper flex contacts 42 and lower flex contacts 44 are identified in FIG. 2 to preserve clarity of the view. It should be understood that each of flex circuits 30 and 32 have both upper flex contacts 42 and lower flex contacts 44 . Lower flex contacts 44 are employed with lower CSP 14 and upper flex contacts 42 are employed with upper CSP 12 .
- FIG. 2 has an area marked “A” that is subsequently shown in enlarged depiction in FIG. 3 .
- FIG. 3 depicts in enlarged view, the area marked “A” in FIG. 2 .
- FIG. 3 illustrates the connection between example CSP contact 24 and module contact 36 through lower flex contact 44 to illustrate the solid metal path from lower CSP 14 to module contact 36 and, therefore, to an application PWB to which module is connectable. As those of skill in the art will understand, heat transference from module 10 is thereby encouraged.
- CSP contact 24 and module contact 36 together offset module 10 from an application platform such as a PWB.
- the combined heights of CSP contact 24 and module contact 36 provide a moment arm longer than the height of a single CSP contact 24 alone. This provides a longer moment arm through which temperature-gradient-over-time stresses (such as typified by temp cycle), can be distributed.
- Flex 30 is shown in FIG. 3 to be comprised of multiple layers. Flex 30 has a first outer surface 50 and a second outer surface 52 . Flex circuit 30 has at least two conductive layers interior to first and second outer surfaces 50 and 52 . There may be more than two conductive layers in flex 30 and flex 32 . In the depicted preferred embodiment, first conductive layer 54 and second conductive layer 58 are interior to first and second outer surfaces 50 and 52 . Intermediate layer 56 lies between first conductive layer 54 and second conductive layer 58 . There may be more than one intermediate layer, but one intermediate layer of polyimide is preferred.
- lower flex contact 44 is preferably comprised from metal at the level of second conductive layer 58 interior to second outer surface 52 .
- Lower flex contact 44 is solid metal in a preferred embodiment and is comprised of metal alloy such as alloy 110. This results in a solid metal pathway from lower CSP 14 to an application board thereby providing a significant thermal pathway for dissipation of heat generated in module 10 .
- FIG. 4 is an enlarged detail of an exemplar connection between example CSP contact 24 and example module contact 36 through lower flex contact 44 to illustrate the solid metal path from lower CSP 14 to module contact 36 and, therefore, to an application PWB to which module 10 is connectable.
- lower flex contact 44 is at second conductive layer 58 that is interior to first and second outer surface layers 50 and 52 respectively, of flex circuit 30 .
- FIG. 5 is an enlarged depiction of an exemplar area around a lower flex contact 44 in a preferred embodiment.
- Windows 60 and 62 are opened in first and second outer surface layers 50 and 52 respectively, to provide access to particular lower flex contacts 44 residing at the level of second conductive layer 58 in the flex.
- the upper flex contacts 42 are contacted by CSP contacts 24 of upper CSP 12 .
- Lower flex contacts 44 and upper flex contacts 42 are particular areas of conductive material (preferably metal such as alloy 110) at the level of second conductive layer 58 in the flex.
- Upper flex contacts 42 and lower flex contacts 44 are demarked in second conductive layer 58 and, as will be shown in subsequent Figs., may be connected to or isolated from the conductive plane of second conductive layer 58 .
- Demarking a lower flex contact 44 from second conductive layer 58 is represented in FIG. 5 by demarcation gap 63 shown at second conductive layer 58 .
- demarcation gaps do not extend completely around the flex contact as shown, for example, by lower flex contacts 44 C in later FIG. 12 .
- CSP contacts 24 of lower CSP 14 pass through a window 60 opened through first outer surface layer 50 , first conductive layer 54 , and intermediate layer 56 , to contact an appropriate lower flex contact 44 .
- Window 62 is opened through second outer surface layer 52 through which module contacts 36 pass to contact the appropriate lower flex contact 44 .
- Respective ones of CSP contacts 24 of upper CSP 12 and lower CSP 14 are connected at the second conductive layer 58 level in flex circuits 30 and 32 to interconnect appropriate signal and voltage contacts of the two CSPs.
- Respective CSP contacts 24 of upper CSP 12 and lower CSP 14 that convey ground (VSS) signals are connected at the first conductive layer 54 level in flex circuits 30 and 32 by vias that pass through intermediate layer 56 to connect the levels as will subsequently be described in further detail.
- CSPs 12 and 14 are connected. Consequently, when flex circuits 30 and 32 are in place about lower CSP 14 , respective CSP contacts 24 of each of upper and lower CSPs 12 and 14 are in contact with upper and lower flex contacts 42 and 44 , respectively. Selected ones of upper flex contacts 42 and lower flex contacts 44 are connected. Consequently, by being in contact with lower flex contacts 44 , module contacts 36 are in contact with both upper and lower CSPs 12 and 14 .
- module contacts 36 pass through windows 62 opened in second outer layer 52 to contact lower CSP contacts 44 .
- module 10 will exhibit a module contact array 38 that has a greater number of contacts than do the constituent CSPs of module 10 .
- some of module contacts 36 may contact lower flex contacts 44 that do not contact one of the CSP contacts 24 of lower CSP 14 but are connected to CSP contacts 24 of upper CSP 12 . This allows module 10 to express a wider datapath than that expressed by the constituent CSPs 12 or 14 .
- a module contact 36 may also be in contact with a lower flex contact 44 to provide a location through which different levels of CSPs in the module may be enabled when no unused CSP contacts are available or convenient for that purpose.
- first conductive layer 54 is employed as a ground plane, while second conductive layer 58 provides the functions of being a signal conduction layer and a voltage conduction layer.
- first and second conductive layers may be reversed with attendant changes in windowing and use of commensurate interconnections.
- first and second conductive layers 54 and 58 there is at least one intermediate layer 56 that, in a preferred embodiment, is a polyimide. Placement of such an intermediate layer between ground-conductive first conductive layer 54 and signal/voltage conductive second conductive layer 58 provides, in the combination, a distributed capacitance that assists in mitigation of ground bounce phenomena to improve high frequency performance of module 10 .
- FIG. 6 depicts first outer surface layer 50 of flex 30 (i.e., left side of FIG. 1 ). The view is from above the flex looking down into flex 30 from the perspective of first conductive layer 54 . Throughout the Figs., the location reference “B” is to orient views of layers of flex 30 to those of flex 32 as well as across layers. Windows 60 are opened through first outer surface layer 50 , first conductive layer 54 , and intermediate layer 56 . CSP contacts 24 of lower CSP 14 pass through windows 60 of first outer surface layer 50 , first conductive layer 54 , and intermediate layer 56 to reach the level of second conductive layer 58 of flex 30 .
- selected CSP contacts 24 of lower CSP 14 make contact with selected lower flex contacts 44 .
- Lower flex contacts 44 provide several types of connection in a preferred embodiment as will be explained with reference to later FIG. 12 .
- a portion of flex 30 will be wrapped about lateral side 20 of lower CSP 14 to place edge 62 above upper surface 16 of lower CSP 14 .
- FIG. 7 depicts first outer surface layer 50 of flex 32 (i.e., right side of FIG. 1 ).
- the view is from above the flex looking down into flex 32 from the perspective of first conductive layer 54 .
- the location reference “B” relatively orients the views of FIGS. 6 and 7 .
- the views of FIGS. 6 and 7 may be understood together with the reference marks “B” of each view being placed nearer each other than to any other corner of the other view of the pair of views of the same layer.
- windows 60 are opened through first outer surface layer 50 , first conductive layer 54 and intermediate layer 56 .
- CSP contacts 24 of lower CSP 14 pass through windows 60 of first outer surface layer 50 , first conductive layer 54 , and intermediate layer 56 to reach the level of second conductive layer 58 of flex 30 .
- selected CSP contacts 24 of lower CSP 14 make contact with lower flex contacts 44 .
- Lower flex contacts 44 provide several types of connection in a preferred embodiment as will be explained with reference to later FIG. 12 .
- FIG. 8 depicts first conductive layer 54 of flex 30 .
- Windows 60 continue the opened orifice in flex 30 through which CSP contacts 24 of lower CSP 14 pass to reach second conductive layer 58 and, therefore, selected lower flex contacts 44 at the level of second conductive layer 58 .
- first conductive layer 54 becomes, on the part of flex 30 disposed above upper surface 16 of lower CSP 14 , the lower-most conductive layer of flex 30 from the perspective of upper CSP 12 .
- those CSP contacts 24 of upper CSP 12 that provide ground (VSS) connections are connected to the first conductive layer 54 .
- First conductive layer 54 lies beneath, however, second conductive layer 58 in that part of flex 30 that is wrapped above lower CSP 14 . Consequently, some means must be provided for connection of the upper flex contact 42 to which ground-conveying CSP contacts 24 of upper CSP 12 are connected and first conductive layer 54 .
- those upper flex contacts 42 that are in contact with ground-conveying CSP contacts 24 of upper CSP 12 have vias that route through intermediate layer 56 to reach first conductive layer 54 .
- the sites where those vias meet first conductive layer 54 are identified in FIG. 8 as vias 66 .
- These vias may be “on-pad” or coincident with the flex contact 42 to which they are connected.
- vias 66 in FIG. 8 are one via.
- vias in the figures are shown larger in diameter than in manufactured embodiments.
- connection between conductive layers provided by vias may be provided any of several well-known techniques such as plated holes or solid lines or wires and need not literally be vias.
- Off-pad vias 74 are disposed on first conductive layer 54 at locations near, but not coincident with selected ones of windows 60 . Unlike vias 66 that connect selected ones of upper flex contacts 42 to first conductive layer 54 , off-pad vias 74 connect selected ones of lower flex contacts 44 to first conductive layer 54 . In the vicinity of upper flex contacts 42 , second conductive layer 58 is between the CSP connected to module 10 by the upper flex contacts 42 (i.e., upper CSP 12 ) and first conductive layer 54 .
- first conductive layer 54 is between the CSP connected to module 10 by the lower flex contacts 44 (i.e., lower CSP 14 ) and second conductive layer 58 . Consequently, vias between ground-conveying lower flex contacts 44 and first conductive layer 54 are offset from the selected lower flex contacts 44 by off-pad vias 74 shown in offset locations.
- FIG. 9 illustrates first conductive layer 54 of flex 32 .
- the location reference marks “B” are employed to relatively orient FIGS. 8 and 9 .
- Windows 60 , vias 66 and off-pad vias 74 are identified in FIG. 9 .
- Enable via 70 is connected off-pad to a selected lower flex contact 44 that corresponds, in this preferred embodiment, to an unused CSP contact 24 of lower CSP 14 (i.e., a N/C).
- a module contact 36 at that site conveys an enable signal (C/S) for upper CSP 12 through the selected lower flex contact 44 (which is at the level of second conductive layer 58 ) to off-pad enable via 70 that conveys the enable signal to first conductive layer 54 and thereby to enable trace 72 .
- Enable trace 72 further conveys the enable signal to enable via 68 which extends through intermediate layer 56 to selected upper flex contact 42 at the level of second conductive layer 58 where contact is made with the C/S pin of upper CSP 12 .
- upper and lower CSPs 12 and 14 may be independently enabled.
- FIG. 10 depicts intermediate layer 56 of flex 30 .
- Windows 60 are shown opened in intermediate surface 56 .
- CSP contacts 24 of lower CSP 14 pass through windows 60 in intermediate layer 58 to reach lower flex contacts 44 at the level of second conductive layer 58 .
- windows 60 narrow in diameter from their manifestation in first outer layer 50 .
- Vias 66 , off-pad vias 74 , and enable vias 68 and 70 pass through intermediate layer 56 connecting selected conductive areas at the level of first and second conductive layers 54 and 58 , respectively.
- FIG. 11 depicts intermediate layer 56 of flex 32 showing windows 60 , vias 66 , off-pad vias 74 , and enable vias 68 and 70 passing through intermediate layer 56 .
- FIG. 12 depicts second conductive layer 58 of flex 30 of a preferred embodiment of the present invention. Depicted are various types of upper flex contacts 42 , various types of lower flex contacts 44 , signal traces 76 , and VDD plane 78 as well as previously described vias 66 and off-pad vias 74 . Throughout FIGS. 12 and 13 , only exemplars of particular features are identified to preserve clarity of the view. Flex contacts 44 A are connected to corresponding selected upper flex contacts 42 A with signal traces 76 . To enhance the clarity of the view, only exemplar individual flex contacts 44 A and 42 A are literally identified in FIG. 12 .
- signal traces 76 exhibit path routes determined to provide substantially equal signal lengths between corresponding flex contacts 42 A and 44 A. As shown, traces 76 are separated from the larger surface area of second conductive layer 58 that is identified as VDD plane 78 . VDD plane 78 may be in one or more delineated sections but, preferably is one section. Lower flex contacts 44 C provide connection to VDD plane 78 . In a preferred embodiment, upper flex contacts 42 C and lower flex contacts 44 C connect upper CSP 12 and lower CSP 14 , respectively, to VDD plane 78 . Lower flex contacts 44 that are connected to first conductive layer 54 by off-pad vias 74 are identified as lower flex contacts 44 B. To enhance the clarity of the view, only exemplar individual lower flex contacts 44 B are literally identified in FIG. 12 . Upper flex contacts 42 that are connected to first conductive layer 54 by vias 66 are identified as upper flex contacts 42 B.
- FIG. 13 depicts second conductive layer 58 of right side flex 32 of a preferred embodiment of the present invention. Depicted are various types of upper flex contacts 42 , various types of lower flex contacts 44 , signal traces 76 , and VDD plane 78 as well as previously described vias 66 , off-pad vias 74 , and enable vias 70 and 68 .
- FIG. 13 illustrates upper flex contacts 42 A connected by traces 76 to lower flex contacts 44 A.
- VDD plane 78 provides a voltage plane at the level of second conductive layer 58 .
- Lower flex contacts 44 C and upper flex contacts 42 C connect lower CSP 14 and upper CSP 12 , respectively, to VDD plane 78 .
- Lower flex contact 44 D is shown with enable via 70 described earlier.
- Corresponding upper flex contact 42 D is connected to lower flex contact 44 D through enable vias 70 and 68 that are connected to each other through earlier described enable trace 72 at the first conductive layer 54 level of flex 32 .
- FIG. 14 depicts second outer layer 52 of flex 30 .
- Windows 62 are identified. Those of skill will recognize that module contacts 36 pass through windows 62 to contact appropriate lower flex contacts 44 .
- flex 30 is partially wrapped about lateral side 20 of lower CSP 14 , a portion of second outer layer 52 becomes the upper-most layer of flex 30 from the perspective of upper CSP 12 .
- CSP contacts 24 of upper CSP 12 pass through windows 64 to reach second conductive layer 58 and make contact with appropriate ones of upper flex contacts 42 located at that level.
- FIG. 15 reflects second outer layer 52 of flex 32 and exhibits windows 64 and 62 .
- Module contacts 36 pass through windows 62 to contact appropriate lower flex contacts 44 .
- CSP contacts 24 of upper CSP 12 pass through windows 64 to reach second conductive layer 58 and make contact with appropriate ones of upper flex contacts 42 located at that level.
- FIG. 16 depicts an alternative preferred embodiment of the present invention showing module 10 .
- module contacts 36 E supply a part of the datapath of module 10 and may provide a facility for differential enablement of the constituent CSPs.
- a module contact 36 E not employed in wide datapath provision may provide a contact point to supply an enable signal to differentially enable upper CSP 12 or lower CSP 14 .
- a wide datapath module 10 the data paths of the constituent upper CSP 12 and lower CSP 14 are combined to provide a module 10 that expresses a module datapath that is twice the width of the datapaths of the constituent CSPs in a two-high module 10 .
- the preferred method of combination is concatenation, but other combinations may be employed to combine the datapaths of CSPs 12 and 14 on the array of module contacts 36 and 36 E.
- FIGS. 17, 18 , and 19 are provided to illustrate using added module contacts 36 E in alternative embodiments of the present invention to provide wider datapaths for module 10 than are present in constituent CSPs 12 and 14 .
- FIG. 17 illustrates a JEDEC pinout for DDR-II FBGA packages.
- FIG. 18 illustrates the pinout provided by module contacts 36 and 36 E of a module 10 expressing an 8-bit wide datapath.
- Module 10 is devised in accordance with the present invention and is, in the exemplar embodiment, comprised of an upper CSP 12 and lower CSP 14 that are DDR-II-compliant in timing, but each of which are only 4 bits wide in datapath. As will be recognized, the module 10 mapped in FIG.
- FIG. 18 expresses an 8-bit wide datapath.
- FIG. 18 depicts DQ pins differentiated in source between upper CSP 12 (“top”) and lower CSP 14 (“bot”) to aggregate to 8-bits.
- FIG. 19 illustrates the pinout provided by module contacts 36 and 36 E of module 10 expressing a 16-bit wide datapath.
- Module 10 is devised in accordance with the present invention and is, in this exemplar embodiment, comprised of an upper CSP 12 and lower CSP 14 that are DDR-II-compliant in timing, but each of which are only 8-bits wide in datapath.
- the wide datapath embodiment may be employed with any of a variety of CSPs available in the field and such CSPs need not be DDR compliant.
- FIG. 20 illustrates a typical pinout of a memory circuit provided as a CSP and useable in the present invention. Individual array positions are identified by the JEDEC convention of numbered columns and alphabetic rows. The central area (e.g., A3-A6; B3-B6; etc.) is unpopulated. CSP contacts 24 are present at the locations that are identified by alpha-numeric identifiers such as, for example, A3, shown as an example CSP contact 24 .
- FIG. 21 depicts second metal layer 58 of flex 30 in an alternative embodiment of the invention in which module 10 expresses a datapath wider than that expressed by either of the constituent CSPs 12 and 14 .
- Lower flex contacts 44 E are not contacted by CSP contacts 24 of lower CSP 14 , but are contacted by module contacts 36 E to provide, with selected module contacts 36 , a datapath for module 10 that is 2n-bits in width where the datapaths of CSPs 12 and 14 have a width of n-bits.
- lower flex contacts 44 E are connected to upper flex contacts 42 E.
- windows 62 pass through second outer layer 52 .
- module contacts 36 and 36 E pass through windows 62 in second outer layer 52 of flex circuit 30 , to contact appropriate lower flex contacts 44 .
- FIG. 22 illustrates second metal layer 58 of flex 32 in an alternative embodiment of the invention in which module 10 expresses a datapath wider than that expressed by either of the constituent CSPs 12 and 14 .
- Lower flex contacts 44 E are not contacted by CSP contacts 24 of lower CSP 14 , but are contacted by module contacts 36 E to provide, with selected module contacts 36 , a datapath for module 10 that is 2n-bits in width where the datapaths of CSPs 12 and 14 have a width of n-bits.
- lower flex contacts 44 E are connected to upper flex contacts 42 E.
- windows 62 pass through second outer layer 52 .
- module contacts 36 pass through windows 62 in second outer layer 52 of flex circuit 32 , to contact appropriate lower flex contacts 44 .
- module contacts 36 E contact flex contacts 44 E and 44 EE.
- lower flex contacts 44 E are, in the depicted embodiment, eight (8) in number and that there is another lower flex contacts identified by reference 44 EE shown on FIG. 21 .
- Lower flex contact 44 EE is contacted by one of the module contacts 36 E to provide differential enablement between upper and lower CSPs.
- lower flex contacts 44 E are connected to corresponding upper flex contacts 42 E.
- CSP contacts 24 of upper CSP 12 that convey data are in contact with upper flex contacts 42 E.
- module 10 expresses a 16-bit datapath and CSP 12 and CSP 14 each express an 8-bit datapath.
Abstract
The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.
Description
- This application is a continuation of U.S. application Ser. No. 10/400,309 filed Mar. 27, 2003, which is a continuation of U.S. application Ser. No. 10/005,581, filed Oct. 26, 2001, now issued as U.S. Pat. No. 6,576,992, each of which is hereby incorporated by reference for all purposes.
- The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages.
- A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits.
- The predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
- Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages have recently gained market share.
- One family of alternative packages is identified generally by the term “chip scale packaging” or CSP. CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package.
- The goal of CSP is to occupy as little area as possible and, preferably, approximately the area of the encapsulated IC. Therefore, CSP leads or contacts do not typically extend beyond the outline perimeter of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
- CSP has enabled reductions in size and weight parameters for many applications. For example, micro ball grid array (μBGA) for flash and SRAM and wirebond on tape or rigid laminate CSPs for SRAM or EEPROM have been employed in a variety of applications. CSP is a broad category including a variety of packages from near chip scale to die-sized packages such as the die sized ball grid array (DSBGA) recently described in proposed JEDEC standard 95-1 for DSBGA. To meet the continuing demands for cost and form factor reduction with increasing memory capacities, CSP technologies that aggregate integrated circuits in CSP technology have recently been developed. For example, Sharp, Hitachi, Mitsubishi and Intel recently undertook support of what are called the S-CSP specifications for flash and SRAM applications. Those S-CSP specifications describe, however, stacking multiple die within a single chip scale package and do not provide a technology for stacking chip scale packages. Stacking integrated circuits within a single package requires specialized technology that includes reformulation of package internals and significant expense with possible supply chain vulnerabilities.
- There are several known techniques for stacking packages articulated in chip scale technology. The assignee of the present invention has developed previous systems for aggregating μBGA packages in space saving topologies. The assignee of the present invention has systems for stacking BGA packages on a DIMM in a RAMBUS environment.
- In U.S. Pat. No. 6,205,654 B1 owned by the assignee of the present invention, a system for stacking ball grid array packages that employs lead carriers to extend connectable points out from the packages is described. Other known techniques add structures to a stack of BGA-packaged ICs. Still others aggregate CSPs on a DIMM with angular placement of the packages. Such techniques provide alternatives, but require topologies of added cost and complexity.
- U.S. Pat. No. 6,262,895 B1 to Forthun (the “Forthun patent”) purports to disclose a technique for stacking chip scale packaged ICs. The Forthun patent discloses a “package” that exhibits a flex circuit wrapped partially about a CSP. The flex circuit is said to have pad arrays on upper and lower surfaces of the flex.
- The flex circuit of the Forthun “package” has a pad array on its upper surface and a pad array centrally located upon its lower surface. On the lower surface of the flex there are third and fourth arrays on opposite sides from the central lower surface pad array. To create the package of Forthun, a CSP contacts the pad array located on the upper surface of the flex circuit. As described in the Forthun patent, the contacts on the lower surface of the CSP are pushed through “slits” in the upper surface pads and advanced through the flex to protrude from the pads of the lower surface array and, therefore, the bottom surface of the package. Thus, the contacts of the CSP serve as the contacts for the package. The sides of the flex are partially wrapped about the CSP to adjacently place the third and fourth pad arrays above the upper major surface of the CSP to create from the combination of the third and fourth pad arrays, a fifth pad array for connection to another such package. Thus, as described in the Forthun disclosure, a stacked module of CSPs created with the described packages will exhibit a flex circuit wrapped about each CSP in the module.
- The previous known methods for stacking CSPs apparently have various deficiencies including complex structural arrangements and thermal or high frequency performance issues. Typically, the reliability of chip scale packaging is closely scrutinized. During such reliability evaluations, CSP devices often exhibit temperature cycle performance issues. CSPs are generally directly mounted on a PWB or other platform offset from the PWB by only the height of the ball or bump array emergent from the lower surface of the CSP. Consequently, stresses arising from temperature gradients over time are concentrated in the short lever arm of a low-height ball array. The issues associated with temp cycle performance in single CSPs will likely arise in those prior art CSP stacking solutions where the stack is offset from the PWB or application platform by only the height of the lower CSP ball grid array.
- Thermal performance is also a characteristic of importance in CSP stacks. To increase dissipation of heat generated by constituent CSPs, the thermal gradient between the lower CSP and upper CSP in a CSP stack or module should be minimized. Prior art solutions to CSP stacking do not, however, address thermal gradient minimization in disclosed constructions.
- What is needed, therefore, is a technique and system for stacking integrated circuits packaged in chip scale technology packaging that provides a thermally efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows production at reasonable cost with readily understood and managed materials and methods.
- The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP packages of a variety of sizes and configurations ranging from typical BGAs with footprints somewhat larger than the contained die to smaller packages such as, for example, die-sized packages such as DSBGA. Although the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die.
- In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with a pair of flex circuits. Each of the pair of flex circuits is partially wrapped about a respective opposite lateral edge of the lower CSP of the module. The flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB).
- The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.
-
FIG. 1 is an elevation view ofmodule 10 devised in accordance with a preferred embodiment of the present invention. -
FIG. 2 is an elevation view ofmodule 10 devised in accordance with a preferred embodiment of the present invention. -
FIG. 3 depicts, in enlarged view, the area marked “A” inFIG. 2 . -
FIG. 4 is an enlarged detail of an exemplar connection in a preferred embodiment of the present invention. -
FIG. 5 is an enlarged depiction of an exemplar area around a lower flex contact in a preferred embodiment of the present invention. -
FIG. 6 depicts a first outer surface layer of a flex circuit employed in a preferred embodiment of the present invention. -
FIG. 7 depicts a first outer surface layer of a flex circuit employed in a preferred embodiment of the present invention. -
FIG. 8 depicts a first conductive layer of a flex circuit employed in a preferred embodiment of the present invention. -
FIG. 9 illustrates a first conductive layer of a flex circuit employed in a preferred embodiment of the present invention. -
FIG. 10 depicts an intermediate layer of a flex circuit employed in a preferred embodiment of the present invention. -
FIG. 11 depicts an intermediate layer of a right side flex circuit employed in a preferred embodiment of the present invention. -
FIG. 12 depicts a second conductive layer of a flex circuit of a preferred embodiment of the present invention. -
FIG. 13 depicts a second conductive layer of a flex circuit of a preferred embodiment of the present invention. -
FIG. 14 depicts a second outer layer of a flex circuit employed in a preferred embodiment of the present invention. -
FIG. 15 reflects a second outer layer of a flex circuit employed in a preferred embodiment of the present invention. -
FIG. 16 depicts an alternative preferred embodiment of the present invention. -
FIG. 17 illustrates a JEDEC pinout for DDR-II FBGA packages. -
FIG. 18 illustrates the pinout of amodule 10 in an alternative preferred embodiment of the invention. -
FIG. 19 illustrates the pinout of amodule 10 in an alternative embodiment of the invention. -
FIG. 20 depicts the pinout of an exemplar CSP employed in a preferred embodiment of the invention. -
FIG. 21 depicts a second conductive layer of a flex circuit employed in an alternative preferred embodiment of the present invention. -
FIG. 22 depicts a second conductive layer of a flex circuit employed in an alternative preferred embodiment of the present invention. -
FIG. 1 is an elevation view ofmodule 10 devised in accordance with a preferred embodiment of the present invention.Module 10 is comprised ofupper CSP 12 andlower CSP 14. Each ofCSPs upper surface 16 and alower surface 18 and oppositelateral sides - The invention is used with CSP packages of a variety of types and configurations such as, for example, those that are die-sized, as well those that are near chip-scale as well as the variety of ball grid array packages known in the art. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the elevation views of
FIGS. 1 and 2 are depicted with CSPs of a particular profile known to those in the art, but it should be understood that the figures are exemplary only. Later figures show embodiments of the invention that employ CSPs of other configurations as an example of one other of the many alternative CSP configurations with which the invention may be employed. The invention may be employed to advantage in the wide range of CSP configurations available in the art where an array of connective elements is emergent from at least one major surface. The invention is advantageously employed with CSPs that contain memory circuits but may be employed to advantage with logic and computing circuits where added capacity without commensurate PWB or other board surface area consumption is desired. - Typical CSPs, such as, for example, ball-grid-array (“BGA”), micro-ball-grid array (“μBGA”), and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, or balls that extend from
lower surface 18 of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Shown inFIG. 1 areCSP contacts 24 alonglower surfaces 18 ofCSPs CSP contacts 24 provide connection to the integrated circuit within the respective packages. Collectively,CSP contacts 24 compriseCSP array 26 shown as to lowerCSP 14 in the depicted particular package configuration asCSP arrays CSP array 26. - In
FIG. 1 , flex circuits (“flex”, “flex circuits” or “flexible circuit structures”) 30 and 32 are shown partially wrapped aboutlower CSP 14 withflex 30 partially wrapped overlateral side 20 oflower CSP 14 and flex 32 partially wrapped aboutlateral side 22 oflower CSP 14.Lateral sides lower CSP 14 and rigid in other areas for planarity along CSP surfaces may be employed as an alternative flex circuit in the present invention. For example, structures known as rigid-flex may be employed. - Portions of
flex circuits upper surface 16 oflower CSP 14 by adhesive 34 which is shown as a tape adhesive, but may be a liquid adhesive or may be placed in discrete locations across the package. Preferably, adhesive 34 is thermally conductive. Adhesives that include a flux are used to advantage in assembly ofmodule 10.Layer 34 may also be a thermally conductive medium to encourage heat flow between the CSPs ofmodule 10. -
Flex circuits module 10 intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize.Module 10 ofFIG. 1 hasmodule contacts 36 collectively identified asmodule array 38. -
FIG. 2 shows amodule 10 devised in accordance with a preferred embodiment of the invention.FIG. 2 illustrates use of aconformal media 40 provided in a preferred embodiment to assist in creating conformality of structural areas ofmodule 10. Planarity of the module is improved byconformal media 40. Preferably,conformal media 40 is thermally conductive. In alternative embodiments, thermal spreaders or a thermal medium may be placed as shown byreference 41. Identified inFIG. 2 areupper flex contacts 42 andlower flex contacts 44 that are at one of the conductive layers offlex circuits Upper flex contacts 42 andlower flex contacts 44 are conductive material and, preferably, are solid metal.Lower flex contacts 44 are collectively lowerflex contact array 46.Upper flex contacts 42 are collectively upperflex contact array 48. Only some ofupper flex contacts 42 andlower flex contacts 44 are identified inFIG. 2 to preserve clarity of the view. It should be understood that each offlex circuits upper flex contacts 42 andlower flex contacts 44.Lower flex contacts 44 are employed withlower CSP 14 andupper flex contacts 42 are employed withupper CSP 12.FIG. 2 has an area marked “A” that is subsequently shown in enlarged depiction inFIG. 3 . -
FIG. 3 depicts in enlarged view, the area marked “A” inFIG. 2 .FIG. 3 illustrates the connection betweenexample CSP contact 24 andmodule contact 36 throughlower flex contact 44 to illustrate the solid metal path fromlower CSP 14 tomodule contact 36 and, therefore, to an application PWB to which module is connectable. As those of skill in the art will understand, heat transference frommodule 10 is thereby encouraged. - With continuing reference to
FIG. 3 ,CSP contact 24 andmodule contact 36 together offsetmodule 10 from an application platform such as a PWB. The combined heights ofCSP contact 24 andmodule contact 36 provide a moment arm longer than the height of asingle CSP contact 24 alone. This provides a longer moment arm through which temperature-gradient-over-time stresses (such as typified by temp cycle), can be distributed. -
Flex 30 is shown inFIG. 3 to be comprised of multiple layers.Flex 30 has a firstouter surface 50 and a secondouter surface 52.Flex circuit 30 has at least two conductive layers interior to first and secondouter surfaces flex 30 andflex 32. In the depicted preferred embodiment, firstconductive layer 54 and secondconductive layer 58 are interior to first and secondouter surfaces Intermediate layer 56 lies between firstconductive layer 54 and secondconductive layer 58. There may be more than one intermediate layer, but one intermediate layer of polyimide is preferred. - As depicted in
FIG. 3 and seen in more detail in later figures,lower flex contact 44 is preferably comprised from metal at the level of secondconductive layer 58 interior to secondouter surface 52.Lower flex contact 44 is solid metal in a preferred embodiment and is comprised of metal alloy such as alloy 110. This results in a solid metal pathway fromlower CSP 14 to an application board thereby providing a significant thermal pathway for dissipation of heat generated inmodule 10. -
FIG. 4 is an enlarged detail of an exemplar connection betweenexample CSP contact 24 andexample module contact 36 throughlower flex contact 44 to illustrate the solid metal path fromlower CSP 14 tomodule contact 36 and, therefore, to an application PWB to whichmodule 10 is connectable. As shown inFIG. 4 ,lower flex contact 44 is at secondconductive layer 58 that is interior to first and second outer surface layers 50 and 52 respectively, offlex circuit 30. -
FIG. 5 is an enlarged depiction of an exemplar area around alower flex contact 44 in a preferred embodiment.Windows lower flex contacts 44 residing at the level of secondconductive layer 58 in the flex. Theupper flex contacts 42 are contacted byCSP contacts 24 ofupper CSP 12.Lower flex contacts 44 andupper flex contacts 42 are particular areas of conductive material (preferably metal such as alloy 110) at the level of secondconductive layer 58 in the flex.Upper flex contacts 42 andlower flex contacts 44 are demarked in secondconductive layer 58 and, as will be shown in subsequent Figs., may be connected to or isolated from the conductive plane of secondconductive layer 58. Demarking alower flex contact 44 from secondconductive layer 58 is represented inFIG. 5 bydemarcation gap 63 shown at secondconductive layer 58. Where an upper orlower flex contact conductive layer 58, demarcation gaps do not extend completely around the flex contact as shown, for example, bylower flex contacts 44C in laterFIG. 12 .CSP contacts 24 oflower CSP 14 pass through awindow 60 opened through firstouter surface layer 50, firstconductive layer 54, andintermediate layer 56, to contact an appropriatelower flex contact 44.Window 62 is opened through secondouter surface layer 52 through whichmodule contacts 36 pass to contact the appropriatelower flex contact 44. - Respective ones of
CSP contacts 24 ofupper CSP 12 andlower CSP 14 are connected at the secondconductive layer 58 level inflex circuits Respective CSP contacts 24 ofupper CSP 12 andlower CSP 14 that convey ground (VSS) signals are connected at the firstconductive layer 54 level inflex circuits intermediate layer 56 to connect the levels as will subsequently be described in further detail. Thereby,CSPs flex circuits lower CSP 14,respective CSP contacts 24 of each of upper andlower CSPs lower flex contacts upper flex contacts 42 andlower flex contacts 44 are connected. Consequently, by being in contact withlower flex contacts 44,module contacts 36 are in contact with both upper andlower CSPs - In a preferred embodiment,
module contacts 36 pass throughwindows 62 opened in secondouter layer 52 to contactlower CSP contacts 44. In some embodiments, as will be later shown,module 10 will exhibit amodule contact array 38 that has a greater number of contacts than do the constituent CSPs ofmodule 10. In such embodiments, some ofmodule contacts 36 may contactlower flex contacts 44 that do not contact one of theCSP contacts 24 oflower CSP 14 but are connected toCSP contacts 24 ofupper CSP 12. This allowsmodule 10 to express a wider datapath than that expressed by theconstituent CSPs module contact 36 may also be in contact with alower flex contact 44 to provide a location through which different levels of CSPs in the module may be enabled when no unused CSP contacts are available or convenient for that purpose. - In a preferred embodiment, first
conductive layer 54 is employed as a ground plane, while secondconductive layer 58 provides the functions of being a signal conduction layer and a voltage conduction layer. Those of skill will note that roles of the first and second conductive layers may be reversed with attendant changes in windowing and use of commensurate interconnections. - As those of skill will recognize, interconnection of respective
voltage CSP contacts 24 of upper andlower CSPs module 10. Such flattening of the thermal gradient curve acrossmodule 10 is further encouraged by connection of commonground CSP contacts 24 of upper andlower CSPs conductive layer 54. Those of skill will notice that between first and secondconductive layers intermediate layer 56 that, in a preferred embodiment, is a polyimide. Placement of such an intermediate layer between ground-conductive firstconductive layer 54 and signal/voltage conductive secondconductive layer 58 provides, in the combination, a distributed capacitance that assists in mitigation of ground bounce phenomena to improve high frequency performance ofmodule 10. - In a preferred embodiment,
FIG. 6 depicts firstouter surface layer 50 of flex 30 (i.e., left side ofFIG. 1 ). The view is from above the flex looking down intoflex 30 from the perspective of firstconductive layer 54. Throughout the Figs., the location reference “B” is to orient views of layers offlex 30 to those offlex 32 as well as across layers.Windows 60 are opened through firstouter surface layer 50, firstconductive layer 54, andintermediate layer 56.CSP contacts 24 oflower CSP 14 pass throughwindows 60 of firstouter surface layer 50, firstconductive layer 54, andintermediate layer 56 to reach the level of secondconductive layer 58 offlex 30. At secondconductive layer 58, selectedCSP contacts 24 oflower CSP 14 make contact with selectedlower flex contacts 44.Lower flex contacts 44 provide several types of connection in a preferred embodiment as will be explained with reference to laterFIG. 12 . Whenmodule 10 is assembled, a portion offlex 30 will be wrapped aboutlateral side 20 oflower CSP 14 to placeedge 62 aboveupper surface 16 oflower CSP 14. - In a preferred embodiment,
FIG. 7 depicts firstouter surface layer 50 of flex 32 (i.e., right side ofFIG. 1 ). The view is from above the flex looking down intoflex 32 from the perspective of firstconductive layer 54. The location reference “B” relatively orients the views ofFIGS. 6 and 7 . The views ofFIGS. 6 and 7 may be understood together with the reference marks “B” of each view being placed nearer each other than to any other corner of the other view of the pair of views of the same layer. As shown inFIG. 7 ,windows 60 are opened through firstouter surface layer 50, firstconductive layer 54 andintermediate layer 56.CSP contacts 24 oflower CSP 14 pass throughwindows 60 of firstouter surface layer 50, firstconductive layer 54, andintermediate layer 56 to reach the level of secondconductive layer 58 offlex 30. At secondconductive layer 58, selectedCSP contacts 24 oflower CSP 14 make contact withlower flex contacts 44.Lower flex contacts 44 provide several types of connection in a preferred embodiment as will be explained with reference to laterFIG. 12 . Whenmodule 10 is assembled, a portion offlex 32 will be wrapped aboutlateral side 22 oflower CSP 14 to placeedge 64 aboveupper surface 16 oflower CSP 14. -
FIG. 8 depicts firstconductive layer 54 offlex 30.Windows 60 continue the opened orifice inflex 30 through whichCSP contacts 24 oflower CSP 14 pass to reach secondconductive layer 58 and, therefore, selectedlower flex contacts 44 at the level of secondconductive layer 58. - Those of skill will recognize that as
flex 30 is partially wrapped aboutlateral side 20 oflower CSP 14, firstconductive layer 54 becomes, on the part offlex 30 disposed aboveupper surface 16 oflower CSP 14, the lower-most conductive layer offlex 30 from the perspective ofupper CSP 12. In the depicted embodiment, thoseCSP contacts 24 ofupper CSP 12 that provide ground (VSS) connections are connected to the firstconductive layer 54. Firstconductive layer 54 lies beneath, however, secondconductive layer 58 in that part offlex 30 that is wrapped abovelower CSP 14. Consequently, some means must be provided for connection of theupper flex contact 42 to which ground-conveyingCSP contacts 24 ofupper CSP 12 are connected and firstconductive layer 54. Consequently, in the depicted preferred embodiment, thoseupper flex contacts 42 that are in contact with ground-conveyingCSP contacts 24 ofupper CSP 12 have vias that route throughintermediate layer 56 to reach firstconductive layer 54. The sites where those vias meet firstconductive layer 54 are identified inFIG. 8 asvias 66. These vias may be “on-pad” or coincident with theflex contact 42 to which they are connected. Those of skill will note a match between the vias 66 identified inFIG. 8 and vias 66 identified in the later view of secondconductive layer 58 of the depicted preferred embodiment. In a preferred embodiment, vias 66 in coincident locations from Fig. to Fig. are one via. For clarity of the view, depicted vias in the figures are shown larger in diameter than in manufactured embodiments. As those of skill will recognize, the connection between conductive layers provided by vias (on or off pad) may be provided any of several well-known techniques such as plated holes or solid lines or wires and need not literally be vias. - Also shown in
FIG. 8 are off-pad vias 74. Off-pad vias 74 are disposed on firstconductive layer 54 at locations near, but not coincident with selected ones ofwindows 60. Unlikevias 66 that connect selected ones ofupper flex contacts 42 to firstconductive layer 54, off-pad vias 74 connect selected ones oflower flex contacts 44 to firstconductive layer 54. In the vicinity ofupper flex contacts 42, secondconductive layer 58 is between the CSP connected tomodule 10 by the upper flex contacts 42 (i.e., upper CSP 12) and firstconductive layer 54. Consequently, vias between ground-conveyingupper flex contacts 42 and firstconductive layer 54 may be directly attached to the selectedupper flex contacts 42 through which ground signals are conveyed. In contrast, in the vicinity oflower flex contacts 44, firstconductive layer 54 is between the CSP connected tomodule 10 by the lower flex contacts 44 (i.e., lower CSP 14) and secondconductive layer 58. Consequently, vias between ground-conveyinglower flex contacts 44 and firstconductive layer 54 are offset from the selectedlower flex contacts 44 by off-pad vias 74 shown in offset locations. -
FIG. 9 illustrates firstconductive layer 54 offlex 32. The location reference marks “B” are employed to relatively orientFIGS. 8 and 9 .Windows 60, vias 66 and off-pad vias 74 are identified inFIG. 9 . Also shown inFIG. 9 , are enablevias trace 72. Enable via 70 is connected off-pad to a selectedlower flex contact 44 that corresponds, in this preferred embodiment, to anunused CSP contact 24 of lower CSP 14 (i.e., a N/C). Amodule contact 36 at that site conveys an enable signal (C/S) forupper CSP 12 through the selected lower flex contact 44 (which is at the level of second conductive layer 58) to off-pad enable via 70 that conveys the enable signal to firstconductive layer 54 and thereby to enabletrace 72. Enabletrace 72 further conveys the enable signal to enable via 68 which extends throughintermediate layer 56 to selectedupper flex contact 42 at the level of secondconductive layer 58 where contact is made with the C/S pin ofupper CSP 12. Thus, upper andlower CSPs -
FIG. 10 depictsintermediate layer 56 offlex 30.Windows 60 are shown opened inintermediate surface 56.CSP contacts 24 oflower CSP 14 pass throughwindows 60 inintermediate layer 58 to reachlower flex contacts 44 at the level of secondconductive layer 58. Those of skill will notice that, in the depicted preferred embodiment,windows 60 narrow in diameter from their manifestation in firstouter layer 50.Vias 66, off-pad vias 74, and enablevias intermediate layer 56 connecting selected conductive areas at the level of first and secondconductive layers FIG. 11 depictsintermediate layer 56 offlex 32 showingwindows 60, vias 66, off-pad vias 74, and enablevias intermediate layer 56. -
FIG. 12 depicts secondconductive layer 58 offlex 30 of a preferred embodiment of the present invention. Depicted are various types ofupper flex contacts 42, various types oflower flex contacts 44, signal traces 76, andVDD plane 78 as well as previously describedvias 66 and off-pad vias 74. ThroughoutFIGS. 12 and 13 , only exemplars of particular features are identified to preserve clarity of the view.Flex contacts 44A are connected to corresponding selectedupper flex contacts 42A with signal traces 76. To enhance the clarity of the view, only exemplarindividual flex contacts FIG. 12 . As shown, in this preferred embodiment, signal traces 76 exhibit path routes determined to provide substantially equal signal lengths betweencorresponding flex contacts conductive layer 58 that is identified asVDD plane 78.VDD plane 78 may be in one or more delineated sections but, preferably is one section.Lower flex contacts 44C provide connection toVDD plane 78. In a preferred embodiment,upper flex contacts 42C andlower flex contacts 44C connectupper CSP 12 andlower CSP 14, respectively, toVDD plane 78.Lower flex contacts 44 that are connected to firstconductive layer 54 by off-pad vias 74 are identified aslower flex contacts 44B. To enhance the clarity of the view, only exemplar individuallower flex contacts 44B are literally identified inFIG. 12 .Upper flex contacts 42 that are connected to firstconductive layer 54 byvias 66 are identified asupper flex contacts 42B. -
FIG. 13 depicts secondconductive layer 58 ofright side flex 32 of a preferred embodiment of the present invention. Depicted are various types ofupper flex contacts 42, various types oflower flex contacts 44, signal traces 76, andVDD plane 78 as well as previously describedvias 66, off-pad vias 74, and enablevias FIG. 13 illustratesupper flex contacts 42A connected bytraces 76 tolower flex contacts 44A.VDD plane 78 provides a voltage plane at the level of secondconductive layer 58.Lower flex contacts 44C andupper flex contacts 42C connectlower CSP 14 andupper CSP 12, respectively, toVDD plane 78.Lower flex contact 44D is shown with enable via 70 described earlier. Correspondingupper flex contact 42D is connected tolower flex contact 44D through enablevias trace 72 at the firstconductive layer 54 level offlex 32. -
FIG. 14 depicts secondouter layer 52 offlex 30.Windows 62 are identified. Those of skill will recognize thatmodule contacts 36 pass throughwindows 62 to contact appropriatelower flex contacts 44. Whenflex 30 is partially wrapped aboutlateral side 20 oflower CSP 14, a portion of secondouter layer 52 becomes the upper-most layer offlex 30 from the perspective ofupper CSP 12.CSP contacts 24 ofupper CSP 12 pass throughwindows 64 to reach secondconductive layer 58 and make contact with appropriate ones ofupper flex contacts 42 located at that level.FIG. 15 reflects secondouter layer 52 offlex 32 andexhibits windows Module contacts 36 pass throughwindows 62 to contact appropriatelower flex contacts 44.CSP contacts 24 ofupper CSP 12 pass throughwindows 64 to reach secondconductive layer 58 and make contact with appropriate ones ofupper flex contacts 42 located at that level. -
FIG. 16 depicts an alternative preferred embodiment of the presentinvention showing module 10. Those of skill will recognize that the embodiment depicted inFIG. 16 differs from that inFIG. 2 by the presence ofmodule contacts 36E.Module contacts 36E supply a part of the datapath ofmodule 10 and may provide a facility for differential enablement of the constituent CSPs. Amodule contact 36E not employed in wide datapath provision may provide a contact point to supply an enable signal to differentially enableupper CSP 12 orlower CSP 14. - In a
wide datapath module 10, the data paths of the constituentupper CSP 12 andlower CSP 14 are combined to provide amodule 10 that expresses a module datapath that is twice the width of the datapaths of the constituent CSPs in a two-high module 10. The preferred method of combination is concatenation, but other combinations may be employed to combine the datapaths ofCSPs module contacts - As an example,
FIGS. 17, 18 , and 19 are provided to illustrate using addedmodule contacts 36E in alternative embodiments of the present invention to provide wider datapaths formodule 10 than are present inconstituent CSPs FIG. 17 illustrates a JEDEC pinout for DDR-II FBGA packages.FIG. 18 illustrates the pinout provided bymodule contacts module 10 expressing an 8-bit wide datapath.Module 10 is devised in accordance with the present invention and is, in the exemplar embodiment, comprised of anupper CSP 12 andlower CSP 14 that are DDR-II-compliant in timing, but each of which are only 4 bits wide in datapath. As will be recognized, themodule 10 mapped inFIG. 18 expresses an 8-bit wide datapath. For example,FIG. 18 depicts DQ pins differentiated in source between upper CSP 12 (“top”) and lower CSP 14 (“bot”) to aggregate to 8-bits.FIG. 19 illustrates the pinout provided bymodule contacts module 10 expressing a 16-bit wide datapath.Module 10 is devised in accordance with the present invention and is, in this exemplar embodiment, comprised of anupper CSP 12 andlower CSP 14 that are DDR-II-compliant in timing, but each of which are only 8-bits wide in datapath. Those of skill in the art will recognize that the wide datapath embodiment may be employed with any of a variety of CSPs available in the field and such CSPs need not be DDR compliant. -
FIG. 20 illustrates a typical pinout of a memory circuit provided as a CSP and useable in the present invention. Individual array positions are identified by the JEDEC convention of numbered columns and alphabetic rows. The central area (e.g., A3-A6; B3-B6; etc.) is unpopulated.CSP contacts 24 are present at the locations that are identified by alpha-numeric identifiers such as, for example, A3, shown as anexample CSP contact 24.FIG. 21 depictssecond metal layer 58 offlex 30 in an alternative embodiment of the invention in whichmodule 10 expresses a datapath wider than that expressed by either of theconstituent CSPs Lower flex contacts 44E are not contacted byCSP contacts 24 oflower CSP 14, but are contacted bymodule contacts 36E to provide, with selectedmodule contacts 36, a datapath formodule 10 that is 2n-bits in width where the datapaths ofCSPs FIG. 21 ,lower flex contacts 44E are connected toupper flex contacts 42E. As shown in earlierFIG. 14 ,windows 62 pass through secondouter layer 52. In the alternative preferred embodiment for which secondconductive layer 58 is shown inFIG. 21 ,module contacts windows 62 in secondouter layer 52 offlex circuit 30, to contact appropriatelower flex contacts 44. -
FIG. 22 illustratessecond metal layer 58 offlex 32 in an alternative embodiment of the invention in whichmodule 10 expresses a datapath wider than that expressed by either of theconstituent CSPs Lower flex contacts 44E are not contacted byCSP contacts 24 oflower CSP 14, but are contacted bymodule contacts 36E to provide, with selectedmodule contacts 36, a datapath formodule 10 that is 2n-bits in width where the datapaths ofCSPs FIG. 22 ,lower flex contacts 44E are connected toupper flex contacts 42E. As shown in earlierFIG. 14 ,windows 62 pass through secondouter layer 52. In the alternative preferred embodiment for which secondconductive layer 58 is shown inFIG. 22 ,module contacts 36 pass throughwindows 62 in secondouter layer 52 offlex circuit 32, to contact appropriatelower flex contacts 44. - In particular, in the embodiment depicted in
FIGS. 21 and 22 ,module contacts 36Econtact flex contacts 44E and 44EE. Those of skill will recognize thatlower flex contacts 44E are, in the depicted embodiment, eight (8) in number and that there is another lower flex contacts identified by reference 44EE shown onFIG. 21 . Lower flex contact 44EE is contacted by one of themodule contacts 36E to provide differential enablement between upper and lower CSPs. Those of skill will recognize thatlower flex contacts 44E are connected to correspondingupper flex contacts 42E.CSP contacts 24 ofupper CSP 12 that convey data are in contact withupper flex contacts 42E. Consequently, the datapaths of bothupper CSP 12 andlower CSP 14 are combined to provide a wide datapath onmodule 10. With the depicted connections ofFIGS. 21 and 22 ,lower flex contacts 44E offlex circuits module contacts 36E, the datapath ofupper CSP 12, while otherlower flex contacts 44 convey the datapath oflower CSP 14 tomodule contacts 36 to providemodule 10 with a module datapath that is the combination of the datapath ofupper CSP 12 andlower CSP 14. In the depicted particular embodiment ofFIGS. 21 and 22 ,module 10 expresses a 16-bit datapath andCSP 12 andCSP 14 each express an 8-bit datapath. - Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.
Claims (40)
1. A high-density circuit module comprising:
a first CSP having a major surface and a first plurality of CSP contacts along the major surface;
a second CSP having a major surface and a second plurality of CSP contacts along the major surface, the first CSP and the second CSP being disposed in a stacked configuration;
a flex circuit comprising
a first conductive layer having first conductive areas, each electrically connected to a selected one of the first plurality of CSP contacts, and second conductive areas, each electrically connected to a selected one of the second plurality of CSP contacts
a second conductive layer having third conductive areas, each electrically connected to a selected one of the first plurality of CSP contacts, and fourth conductive areas, each electrically connected to a selected one of the second plurality of CSP contacts, and
an intermediate layer between the first conductive layer and the second conductive layer; and
module contacts, at least one of which is electrically connected to one of the first conductive areas, and at least one of which is electrically connected to one of the third conductive areas.
2. The high-density circuit module of claim 1 in which at least one of the module contacts is electrically connected to one of the fourth conductive areas.
3. The high-density circuit module of claim 1 in which the first conductive layer comprises a ground plane.
4. The high-density circuit module of claim 1 in which a first selected one of the first plurality of CSP contacts is electrically connected through the first conductive layer to at least one of the second plurality of CSP contacts, and in which a second selected one of the first plurality of CSP contacts is connected through the second conductive layer to at least one of the second plurality of CSP contacts.
5. The high-density circuit module of claim 1 in which the first conductive layer, the intermediate layer, and the second conductive layer are configured to provide distributed capacitance.
6. The high-density circuit module of claim 1 in which the second conductive layer comprises electrical paths each connecting a selected one of the CSP contacts of the first plurality of CSP contacts to a selected one of the CSP contacts of the second plurality of CSP contacts.
7. The high-density circuit module of claim 6 in which selected ones of the plurality of the electrical paths have substantially equal signal lengths.
8. The high-density circuit module of claim 6 in which the second conductive layer further comprises a voltage plane.
9. The high-density circuit module of claim 1 in which thermally conductive material is disposed between the first CSP and the second CSP.
10. The high-density circuit module of claim 9 in which the thermally conductive material is a thermally conductive adhesive.
11. A high-density circuit module comprising:
a first CSP stacked with a second CSP, the first CSP having an outline perimeter and a major surface with a first plurality of CSP contacts, and the second CSP having a major surface with a second plurality of CSP contacts; and
a flex circuit having a first conductive layer, a second conductive layer, a first portion having a first plurality of flex contacts connected to selected ones of the first plurality of CSP contacts, a second portion having a second plurality of flex contacts connected to selected ones of the second plurality of CSP contacts, and a third portion having a bend disposed outside the outline perimeter of the first CSP and adjacent to the stack formed by the first CSP and the second CSP.
12. The high-density circuit module of claim 11 further comprising module contacts disposed along the first portion or the second portion of the flex circuit.
13. The high-density circuit module of claim 11 in which the first conductive layer comprises a ground plane.
14. The high-density circuit module of claim 11 in which a first selected one of the first plurality of CSP contacts is electrically connected through the first conductive layer to at least one of the second plurality of CSP contacts, and in which a second selected one of the first plurality of CSP contacts is connected through the second conductive layer to at least one of the second plurality of CSP contacts.
15. The high-density circuit module of claim 11 in which the second conductive layer comprises electrical paths each connecting a selected one of the CSP contacts of the first plurality of CSP contacts to a selected one of the CSP contacts of the second plurality of CSP contacts.
16. The high-density circuit module of claim 15 in which the second conductive layer further comprises a voltage plane and selected ones of the electrical paths comprise traces.
17. The high-density circuit module of claim 15 in which selected ones of the electrical paths have substantially equal signal lengths.
18. The high-density circuit module of claim 17 in which the second conductive layer further comprises a voltage plane and selected ones of the electrical paths comprise traces.
19. The high-density circuit module of claim 11 in which thermally conductive material is disposed between the first CSP and the second CSP.
20. The high-density circuit module of claim 19 in which the thermally conductive material is a thermally conductive adhesive.
21. A high-density circuit module component comprising:
a CSP having a first major surface, a second major surface, an outline perimeter, and CSP contacts along at least the first major surface or the second major surface;
a flex circuit having a plurality of conductive layers, a first generally planar portion proximal to at least a portion of the first major surface of the CSP, a second generally planar portion proximal to at least a portion of the second major surface of the CSP, and a bend outside the outline perimeter of the CSP;
flex contacts disposed along the second generally planar portion of the flex circuit; and
module contacts disposed along the first generally planar portion of the flex circuit.
22. The high-density circuit module component of claim 21 in which the flex contacts are connectable with CSP contacts of another CSP.
23. The high-density circuit module component of claim 21 in which one of the conductive layers comprises a ground plane.
24. The high-density circuit module component of claim 23 in which one of the flex contacts is connected to the ground plane by a via.
25. The high-density circuit module component of claim 24 in which the via is on-pad.
26. The high-density circuit module component of claim 24 in which the via is off-pad.
27. The high-density circuit module component of claim 21 in which the flex circuit comprises plural primary traces each connecting a selected one of the CSP contacts to a selected one of the flex contacts.
28. The high-density circuit module component of claim 27 in which selected ones of the primary traces have substantially equal signal lengths.
29. The high-density circuit module component of claim 27 in which the flex circuit further comprises at least one secondary trace connecting a selected one of the module contacts only to one or more of the CSP contacts.
30. The high-density circuit module component of claim 27 in which the flex circuit further comprises at least one secondary trace connecting a selected one of the module contacts only to one or more of the flex contacts.
31. The high-density circuit module component of claim 30 in which the flex circuit further comprises at least one tertiary trace connecting a selected one of the module contacts only to one or more of the CSP contacts.
32. A high-density circuit module comprising:
a stack comprising a first CSP having a major surface along which a first plurality of CSP contacts is disposed and a second CSP having a major surface along which a second plurality of CSP contacts is disposed;
a flex circuit having a plurality of conductive layers, a first generally planar portion disposed adjacent to at least a portion of the major surface of the first CSP, a second generally planar portion disposed adjacent to at least a portion of the major surface of the second CSP, and a folded portion disposed adjacent to the stack;
sets of flex contacts, respectively comprising a first plurality of flex contacts, a second plurality of flex contacts, and a third plurality of flex contacts;
a plurality of module contacts;
conductive connections between ones of the first plurality of CSP contacts and ones of the first plurality of flex contacts;
conductive connections between ones of the second plurality of CSP contacts and ones of the second plurality of flex contacts; and
conductive connections between ones of the plurality of module contacts and ones of the third plurality of flex contacts.
33. The high-density circuit module of claim 32 in which a first of the conductive levels comprises a ground plane.
34. The high-density circuit module of claim 33 in which a second of the conductive levels has plural electrical paths, each between a selected one of the contacts of the first plurality of CSP contacts and a selected one of the contacts of the second plurality of CSP contacts.
35. The high-density circuit module of claim 34 in which the second conductive layer comprises a voltage plane, and the electrical paths comprise traces.
36. The high-density circuit module of claim 34 in which selected ones of the electrical paths have substantially equal signal lengths.
37. The high-density circuit module of claim 36 in which the second conductive layer comprises a voltage plane, and the electrical paths comprise traces.
38. The high-density circuit module of claim 32 in which a first selected one of the first plurality of CSP contacts is electrically connected through a first one of the conductive layers to at least one of the second plurality of CSP contacts, and in which a second selected one of the first plurality of CSP contacts is connected through a second one of the conductive layers to at least one of the second plurality of CSP contacts.
39. The high-density circuit module of claim 32 in which thermally conductive material is disposed between the first CSP and the second CSP.
40. The high-density circuit module of claim 39 in which the thermally conductive material is a thermally conductive adhesive.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/317,425 US20060131716A1 (en) | 2001-10-26 | 2005-12-22 | Stacking system and method |
US11/403,081 US20060255446A1 (en) | 2001-10-26 | 2006-04-12 | Stacked modules and method |
US11/873,355 US20080120831A1 (en) | 2001-10-26 | 2007-10-16 | Stacked Modules and Method |
US11/873,351 US7719098B2 (en) | 2001-10-26 | 2007-10-16 | Stacked modules and method |
US11/874,795 US20080088032A1 (en) | 2001-10-26 | 2007-10-18 | Stacked Modules and Method |
US11/874,775 US20080090329A1 (en) | 2001-10-26 | 2007-10-18 | Stacked Modules and Method |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/005,581 US6576992B1 (en) | 2001-10-26 | 2001-10-26 | Chip scale stacking system and method |
US10/400,309 US20030137048A1 (en) | 2001-10-26 | 2003-03-27 | Stacking system and method |
US11/317,425 US20060131716A1 (en) | 2001-10-26 | 2005-12-22 | Stacking system and method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/400,309 Continuation US20030137048A1 (en) | 2001-10-26 | 2003-03-27 | Stacking system and method |
Related Child Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/403,081 Continuation-In-Part US20060255446A1 (en) | 2001-10-26 | 2006-04-12 | Stacked modules and method |
US11/873,351 Continuation-In-Part US7719098B2 (en) | 2001-10-26 | 2007-10-16 | Stacked modules and method |
US11/874,795 Continuation-In-Part US20080088032A1 (en) | 2001-10-26 | 2007-10-18 | Stacked Modules and Method |
US11/874,775 Continuation-In-Part US20080090329A1 (en) | 2001-10-26 | 2007-10-18 | Stacked Modules and Method |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060131716A1 true US20060131716A1 (en) | 2006-06-22 |
Family
ID=21716598
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/005,581 Expired - Lifetime US6576992B1 (en) | 2001-10-26 | 2001-10-26 | Chip scale stacking system and method |
US10/400,309 Abandoned US20030137048A1 (en) | 2001-10-26 | 2003-03-27 | Stacking system and method |
US11/316,505 Abandoned US20060091521A1 (en) | 2001-10-26 | 2005-12-21 | Stacking system and method |
US11/317,425 Abandoned US20060131716A1 (en) | 2001-10-26 | 2005-12-22 | Stacking system and method |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/005,581 Expired - Lifetime US6576992B1 (en) | 2001-10-26 | 2001-10-26 | Chip scale stacking system and method |
US10/400,309 Abandoned US20030137048A1 (en) | 2001-10-26 | 2003-03-27 | Stacking system and method |
US11/316,505 Abandoned US20060091521A1 (en) | 2001-10-26 | 2005-12-21 | Stacking system and method |
Country Status (5)
Country | Link |
---|---|
US (4) | US6576992B1 (en) |
CN (2) | CN100594608C (en) |
GB (1) | GB2395367B (en) |
HK (1) | HK1077460A1 (en) |
WO (1) | WO2003037053A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080048316A1 (en) * | 2006-08-25 | 2008-02-28 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
US8588017B2 (en) | 2010-10-20 | 2013-11-19 | Samsung Electronics Co., Ltd. | Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same |
CN111093316A (en) * | 2018-10-24 | 2020-05-01 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and manufacturing method thereof |
Families Citing this family (80)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6627984B2 (en) * | 2001-07-24 | 2003-09-30 | Dense-Pac Microsystems, Inc. | Chip stack with differing chip package types |
DE10138278C1 (en) * | 2001-08-10 | 2003-04-03 | Infineon Technologies Ag | Electronic component with electronic components stacked on top of one another and method for producing the same |
US6759745B2 (en) * | 2001-09-13 | 2004-07-06 | Texas Instruments Incorporated | Semiconductor device and manufacturing method thereof |
US7371609B2 (en) * | 2001-10-26 | 2008-05-13 | Staktek Group L.P. | Stacked module systems and methods |
US7026708B2 (en) * | 2001-10-26 | 2006-04-11 | Staktek Group L.P. | Low profile chip scale stacking system and method |
US20060255446A1 (en) | 2001-10-26 | 2006-11-16 | Staktek Group, L.P. | Stacked modules and method |
US7656678B2 (en) | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
US6914324B2 (en) * | 2001-10-26 | 2005-07-05 | Staktek Group L.P. | Memory expansion and chip scale stacking system and method |
US7081373B2 (en) * | 2001-12-14 | 2006-07-25 | Staktek Group, L.P. | CSP chip stack with flex circuit |
SG121707A1 (en) * | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
SG107595A1 (en) | 2002-06-18 | 2004-12-29 | Micron Technology Inc | Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assembles and packages including such semiconductor devices or packages and associated methods |
SG111069A1 (en) * | 2002-06-18 | 2005-05-30 | Micron Technology Inc | Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods |
KR100442880B1 (en) * | 2002-07-24 | 2004-08-02 | 삼성전자주식회사 | Stacked semiconductor module and manufacturing method thereof |
US20050167817A1 (en) * | 2002-08-05 | 2005-08-04 | Tessera, Inc. | Microelectronic adaptors, assemblies and methods |
KR20040022063A (en) * | 2002-09-06 | 2004-03-11 | 주식회사 유니세미콘 | A stack semiconductor package and it's manufacture method |
JP3867785B2 (en) * | 2002-10-15 | 2007-01-10 | セイコーエプソン株式会社 | Optical module |
KR20040078807A (en) * | 2003-03-05 | 2004-09-13 | 삼성전자주식회사 | Ball Grid Array Stack Package |
US6924551B2 (en) * | 2003-05-28 | 2005-08-02 | Intel Corporation | Through silicon via, folded flex microelectronic package |
US6940158B2 (en) * | 2003-05-30 | 2005-09-06 | Tessera, Inc. | Assemblies having stacked semiconductor chips and methods of making same |
US20040245615A1 (en) * | 2003-06-03 | 2004-12-09 | Staktek Group, L.P. | Point to point memory expansion system and method |
KR100592786B1 (en) * | 2003-08-22 | 2006-06-26 | 삼성전자주식회사 | Stack package made of area array type packages, and manufacturing method thereof |
SG120123A1 (en) * | 2003-09-30 | 2006-03-28 | Micron Technology Inc | Castellated chip-scale packages and methods for fabricating the same |
US20050150813A1 (en) * | 2003-10-29 | 2005-07-14 | Tessera, Inc. | Foldover packages and manufacturing and test methods therefor |
US7126829B1 (en) | 2004-02-09 | 2006-10-24 | Pericom Semiconductor Corp. | Adapter board for stacking Ball-Grid-Array (BGA) chips |
US7254036B2 (en) * | 2004-04-09 | 2007-08-07 | Netlist, Inc. | High density memory module using stacked printed circuit boards |
WO2006016198A1 (en) * | 2004-08-02 | 2006-02-16 | Infineon Technologies Ag | Electronic component with stacked semiconductor chips and heat dissipating means |
US7511968B2 (en) * | 2004-09-03 | 2009-03-31 | Entorian Technologies, Lp | Buffered thin module system and method |
US20060050492A1 (en) * | 2004-09-03 | 2006-03-09 | Staktek Group, L.P. | Thin module system and method |
US7324352B2 (en) * | 2004-09-03 | 2008-01-29 | Staktek Group L.P. | High capacity thin module system and method |
US7443023B2 (en) * | 2004-09-03 | 2008-10-28 | Entorian Technologies, Lp | High capacity thin module system |
US7616452B2 (en) * | 2004-09-03 | 2009-11-10 | Entorian Technologies, Lp | Flex circuit constructions for high capacity circuit module systems and methods |
US20060053345A1 (en) * | 2004-09-03 | 2006-03-09 | Staktek Group L.P. | Thin module system and method |
US7423885B2 (en) | 2004-09-03 | 2008-09-09 | Entorian Technologies, Lp | Die module system |
US7760513B2 (en) | 2004-09-03 | 2010-07-20 | Entorian Technologies Lp | Modified core for circuit module system and method |
US7542297B2 (en) * | 2004-09-03 | 2009-06-02 | Entorian Technologies, Lp | Optimized mounting area circuit module system and method |
US7579687B2 (en) * | 2004-09-03 | 2009-08-25 | Entorian Technologies, Lp | Circuit module turbulence enhancement systems and methods |
JP2006172586A (en) * | 2004-12-15 | 2006-06-29 | Hitachi Global Storage Technologies Netherlands Bv | Magnetic disk device |
US20060175694A1 (en) * | 2005-02-07 | 2006-08-10 | Hsin Chung H | Stacked structure of integrated circuits and method for manufacturing the same |
US7291907B2 (en) * | 2005-02-28 | 2007-11-06 | Infineon Technologies, Ag | Chip stack employing a flex circuit |
US20100020515A1 (en) * | 2005-03-08 | 2010-01-28 | Smart Modular Technologies, Inc. | Method and system for manufacturing micro solid state drive devices |
US7196427B2 (en) * | 2005-04-18 | 2007-03-27 | Freescale Semiconductor, Inc. | Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element |
US7098073B1 (en) | 2005-04-18 | 2006-08-29 | Freescale Semiconductor, Inc. | Method for stacking an integrated circuit on another integrated circuit |
US20060255459A1 (en) * | 2005-05-11 | 2006-11-16 | Simon Muff | Stacked semiconductor memory device |
US7033861B1 (en) * | 2005-05-18 | 2006-04-25 | Staktek Group L.P. | Stacked module systems and method |
US7785928B2 (en) | 2005-07-09 | 2010-08-31 | Gautham Viswanadam | Integrated circuit device and method of manufacturing thereof |
US7442050B1 (en) | 2005-08-29 | 2008-10-28 | Netlist, Inc. | Circuit card with flexible connection for memory module with heat spreader |
US20070096333A1 (en) * | 2005-10-31 | 2007-05-03 | Amir Motamedi | Optimal stacked die organization |
US7576995B2 (en) * | 2005-11-04 | 2009-08-18 | Entorian Technologies, Lp | Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area |
DE102005059189B3 (en) * | 2005-12-12 | 2007-03-08 | Infineon Technologies Ag | Arrangement of semiconductor memory devices for module, has conductive tracks connecting contacts of flexible substrate and stacked semiconductor devices |
US7508069B2 (en) * | 2006-01-11 | 2009-03-24 | Entorian Technologies, Lp | Managed memory component |
US20070164416A1 (en) * | 2006-01-17 | 2007-07-19 | James Douglas Wehrly | Managed memory component |
US7619893B1 (en) | 2006-02-17 | 2009-11-17 | Netlist, Inc. | Heat spreader for electronic modules |
SG135066A1 (en) | 2006-02-20 | 2007-09-28 | Micron Technology Inc | Semiconductor device assemblies including face-to-face semiconductor dice, systems including such assemblies, and methods for fabricating such assemblies |
US7888185B2 (en) * | 2006-08-17 | 2011-02-15 | Micron Technology, Inc. | Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device |
US7425758B2 (en) * | 2006-08-28 | 2008-09-16 | Micron Technology, Inc. | Metal core foldover package structures |
US7417310B2 (en) | 2006-11-02 | 2008-08-26 | Entorian Technologies, Lp | Circuit module having force resistant construction |
KR100829614B1 (en) * | 2006-12-29 | 2008-05-14 | 삼성전자주식회사 | Stacked semiconductor package and method of manufacturing the same |
US7508070B2 (en) * | 2007-01-13 | 2009-03-24 | Cheng-Lien Chiang | Two dimensional stacking using interposers |
CN101755335B (en) | 2007-07-19 | 2012-07-11 | 日本电气株式会社 | Device having electronic component mounted therein and method for manufacturing such device |
WO2009038169A1 (en) | 2007-09-19 | 2009-03-26 | Nec Corporation | Semiconductor device and its fabrication method |
JP5115269B2 (en) * | 2008-03-26 | 2013-01-09 | 日本電気株式会社 | Semiconductor device mounting structure and electronic device using the mounting structure |
US8018723B1 (en) | 2008-04-30 | 2011-09-13 | Netlist, Inc. | Heat dissipation for electronic modules |
GB2459751A (en) * | 2008-05-06 | 2009-11-11 | Ibm | Self contained memory subsystem |
US20110156240A1 (en) * | 2009-12-31 | 2011-06-30 | Stmicroelectronics Asia Pacific Pte. Ltd. | Reliable large die fan-out wafer level package and method of manufacture |
US8884422B2 (en) | 2009-12-31 | 2014-11-11 | Stmicroelectronics Pte Ltd. | Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture |
US8502394B2 (en) * | 2009-12-31 | 2013-08-06 | Stmicroelectronics Pte Ltd. | Multi-stacked semiconductor dice scale package structure and method of manufacturing same |
US8466997B2 (en) * | 2009-12-31 | 2013-06-18 | Stmicroelectronics Pte Ltd. | Fan-out wafer level package for an optical sensor and method of manufacture thereof |
US8436255B2 (en) * | 2009-12-31 | 2013-05-07 | Stmicroelectronics Pte Ltd. | Fan-out wafer level package with polymeric layer for high reliability |
US9013037B2 (en) | 2011-09-14 | 2015-04-21 | Stmicroelectronics Pte Ltd. | Semiconductor package with improved pillar bump process and structure |
US8779601B2 (en) | 2011-11-02 | 2014-07-15 | Stmicroelectronics Pte Ltd | Embedded wafer level package for 3D and package-on-package applications, and method of manufacture |
US8916481B2 (en) | 2011-11-02 | 2014-12-23 | Stmicroelectronics Pte Ltd. | Embedded wafer level package for 3D and package-on-package applications, and method of manufacture |
USD758372S1 (en) * | 2013-03-13 | 2016-06-07 | Nagrastar Llc | Smart card interface |
US9888283B2 (en) | 2013-03-13 | 2018-02-06 | Nagrastar Llc | Systems and methods for performing transport I/O |
CN103523739A (en) * | 2013-11-05 | 2014-01-22 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure of three-dimensional flexible substrate of environment MEMS sensor and manufacturing method |
US9648754B1 (en) | 2013-11-12 | 2017-05-09 | Smart Modular Technologies, Inc. | Integrated circuit device system with elevated stacked configuration and method of manufacture thereof |
US9603252B1 (en) * | 2013-11-12 | 2017-03-21 | Smart Modular Technologies, Inc. | Integrated circuit device system with elevated configuration and method of manufacture thereof |
CN103715184A (en) * | 2013-12-24 | 2014-04-09 | 华进半导体封装先导技术研发中心有限公司 | Three-dimensional multi-chip storage system packaging structure based on flexible base board and manufacturing method thereof |
USD864968S1 (en) | 2015-04-30 | 2019-10-29 | Echostar Technologies L.L.C. | Smart card interface |
US11721657B2 (en) * | 2019-06-14 | 2023-08-08 | Stmicroelectronics Pte Ltd | Wafer level chip scale package having varying thicknesses |
CN113352069B (en) * | 2021-06-17 | 2022-06-28 | 江苏创源电子有限公司 | Workpiece feeding mechanism and workpiece assembling equipment |
Citations (98)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3372310A (en) * | 1965-04-30 | 1968-03-05 | Radiation Inc | Universal modular packages for integrated circuits |
US3718842A (en) * | 1972-04-21 | 1973-02-27 | Texas Instruments Inc | Liquid crystal display mounting structure |
US4079511A (en) * | 1976-07-30 | 1978-03-21 | Amp Incorporated | Method for packaging hermetically sealed integrated circuit chips on lead frames |
US4429349A (en) * | 1980-09-30 | 1984-01-31 | Burroughs Corporation | Coil connector |
US4437235A (en) * | 1980-12-29 | 1984-03-20 | Honeywell Information Systems Inc. | Integrated circuit package |
US4567543A (en) * | 1983-02-15 | 1986-01-28 | Motorola, Inc. | Double-sided flexible electronic circuit module |
US4645944A (en) * | 1983-09-05 | 1987-02-24 | Matsushita Electric Industrial Co., Ltd. | MOS register for selecting among various data inputs |
US4722691A (en) * | 1986-02-03 | 1988-02-02 | General Motors Corporation | Header assembly for a printed circuit board |
US4724611A (en) * | 1985-08-23 | 1988-02-16 | Nec Corporation | Method for producing semiconductor module |
US4727513A (en) * | 1983-09-02 | 1988-02-23 | Wang Laboratories, Inc. | Signal in-line memory module |
US4891789A (en) * | 1988-03-03 | 1990-01-02 | Bull Hn Information Systems, Inc. | Surface mounted multilayer memory printed circuit board |
US4903169A (en) * | 1986-04-03 | 1990-02-20 | Matsushita Electric Industrial Co., Ltd. | Shielded high frequency apparatus having partitioned shield case, and method of manufacture thereof |
US4911643A (en) * | 1988-10-11 | 1990-03-27 | Beta Phase, Inc. | High density and high signal integrity connector |
US4982265A (en) * | 1987-06-24 | 1991-01-01 | Hitachi, Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
US4983533A (en) * | 1987-10-28 | 1991-01-08 | Irvine Sensors Corporation | High-density electronic modules - process and product |
US4985703A (en) * | 1988-02-03 | 1991-01-15 | Nec Corporation | Analog multiplexer |
US4992849A (en) * | 1989-02-15 | 1991-02-12 | Micron Technology, Inc. | Directly bonded board multiple integrated circuit module |
US4992850A (en) * | 1989-02-15 | 1991-02-12 | Micron Technology, Inc. | Directly bonded simm module |
US5081067A (en) * | 1989-02-10 | 1992-01-14 | Fujitsu Limited | Ceramic package type semiconductor device and method of assembling the same |
US5099393A (en) * | 1991-03-25 | 1992-03-24 | International Business Machines Corporation | Electronic package for high density applications |
US5188926A (en) * | 1991-12-09 | 1993-02-23 | Eastman Kodak Company | Photographic elements having carbonamide coupler solvents and addenda to reduce sensitizing dye stain |
US5191404A (en) * | 1989-12-20 | 1993-03-02 | Digital Equipment Corporation | High density memory array packaging |
US5198888A (en) * | 1987-12-28 | 1993-03-30 | Hitachi, Ltd. | Semiconductor stacked device |
US5198985A (en) * | 1989-11-28 | 1993-03-30 | Goldstar Co., Ltd. | Apparatus for removing erroneously inserted parts in automatic insertion machine |
US5276418A (en) * | 1988-11-16 | 1994-01-04 | Motorola, Inc. | Flexible substrate electronic assembly |
US5279029A (en) * | 1990-08-01 | 1994-01-18 | Staktek Corporation | Ultra high density integrated circuit packages method |
US5281852A (en) * | 1991-12-10 | 1994-01-25 | Normington Peter J C | Semiconductor device including stacked die |
US5289346A (en) * | 1991-02-26 | 1994-02-22 | Microelectronics And Computer Technology Corporation | Peripheral to area adapter with protective bumper for an integrated circuit chip |
US5289062A (en) * | 1991-03-18 | 1994-02-22 | Quality Semiconductor, Inc. | Fast transmission gate switch |
US5384690A (en) * | 1993-07-27 | 1995-01-24 | International Business Machines Corporation | Flex laminate package for a parallel processor |
US5386341A (en) * | 1993-11-01 | 1995-01-31 | Motorola, Inc. | Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape |
US5394010A (en) * | 1991-03-13 | 1995-02-28 | Kabushiki Kaisha Toshiba | Semiconductor assembly having laminated semiconductor devices |
US5394303A (en) * | 1992-09-11 | 1995-02-28 | Kabushiki Kaisha Toshiba | Semiconductor device |
US5394300A (en) * | 1992-09-04 | 1995-02-28 | Mitsubishi Denki Kabushiki Kaisha | Thin multilayered IC memory card |
US5396573A (en) * | 1993-08-03 | 1995-03-07 | International Business Machines Corporation | Pluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal |
US5397916A (en) * | 1991-12-10 | 1995-03-14 | Normington; Peter J. C. | Semiconductor device including stacked die |
US5400003A (en) * | 1992-08-19 | 1995-03-21 | Micron Technology, Inc. | Inherently impedance matched integrated circuit module |
US5484959A (en) * | 1992-12-11 | 1996-01-16 | Staktek Corporation | High density lead-on-package fabrication method and apparatus |
US5491612A (en) * | 1995-02-21 | 1996-02-13 | Fairchild Space And Defense Corporation | Three-dimensional modular assembly of integrated circuits |
US5493476A (en) * | 1994-03-07 | 1996-02-20 | Staktek Corporation | Bus communication system for stacked high density integrated circuit packages with bifurcated distal lead ends |
US5592364A (en) * | 1995-01-24 | 1997-01-07 | Staktek Corporation | High density integrated circuit module with complex electrical interconnect rails |
US5594275A (en) * | 1993-11-18 | 1997-01-14 | Samsung Electronics Co., Ltd. | J-leaded semiconductor package having a plurality of stacked ball grid array packages |
US5600178A (en) * | 1993-10-08 | 1997-02-04 | Texas Instruments Incorporated | Semiconductor package having interdigitated leads |
US5708297A (en) * | 1992-09-16 | 1998-01-13 | Clayton; James E. | Thin multichip module |
US5714802A (en) * | 1991-06-18 | 1998-02-03 | Micron Technology, Inc. | High-density electronic module |
US5717556A (en) * | 1995-04-26 | 1998-02-10 | Nec Corporation | Printed-wiring board having plural parallel-connected interconnections |
US5869353A (en) * | 1997-11-17 | 1999-02-09 | Dense-Pac Microsystems, Inc. | Modular panel stacking process |
US5872051A (en) * | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
US6013948A (en) * | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
US6014316A (en) * | 1997-06-13 | 2000-01-11 | Irvine Sensors Corporation | IC stack utilizing BGA contacts |
US6021048A (en) * | 1998-02-17 | 2000-02-01 | Smith; Gary W. | High speed memory module |
US6025642A (en) * | 1995-08-17 | 2000-02-15 | Staktek Corporation | Ultra high density integrated circuit packages |
US6028352A (en) * | 1997-06-13 | 2000-02-22 | Irvine Sensors Corporation | IC stack utilizing secondary leadframes |
US6028365A (en) * | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
US6172874B1 (en) * | 1998-04-06 | 2001-01-09 | Silicon Graphics, Inc. | System for stacking of integrated circuit packages |
US6178093B1 (en) * | 1996-06-28 | 2001-01-23 | International Business Machines Corporation | Information handling system with circuit assembly having holes filled with filler material |
US6180881B1 (en) * | 1998-05-05 | 2001-01-30 | Harlan Ruben Isaak | Chip stack and method of making same |
US6186106B1 (en) * | 1997-12-29 | 2001-02-13 | Visteon Global Technologies, Inc. | Apparatus for routing electrical signals in an engine |
US6187652B1 (en) * | 1998-09-14 | 2001-02-13 | Fujitsu Limited | Method of fabrication of multiple-layer high density substrate |
US20020001216A1 (en) * | 1996-02-26 | 2002-01-03 | Toshio Sugano | Semiconductor device and process for manufacturing the same |
US6336262B1 (en) * | 1996-10-31 | 2002-01-08 | International Business Machines Corporation | Process of forming a capacitor with multi-level interconnection technology |
US20020006032A1 (en) * | 2000-05-23 | 2002-01-17 | Chris Karabatsos | Low-profile registered DIMM |
US6343020B1 (en) * | 1998-12-28 | 2002-01-29 | Foxconn Precision Components Co., Ltd. | Memory module |
US6347394B1 (en) * | 1998-11-04 | 2002-02-12 | Micron Technology, Inc. | Buffering circuit embedded in an integrated circuit device module used for buffering clocks and other input signals |
US6349050B1 (en) * | 2000-10-10 | 2002-02-19 | Rambus, Inc. | Methods and systems for reducing heat flux in memory systems |
US6351029B1 (en) * | 1999-05-05 | 2002-02-26 | Harlan R. Isaak | Stackable flex circuit chip package and method of making same |
US20030002262A1 (en) * | 2001-07-02 | 2003-01-02 | Martin Benisek | Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor memories |
US6504104B2 (en) * | 1997-12-10 | 2003-01-07 | Siemens Aktiengesellschaft | Flexible wiring for the transformation of a substrate with edge contacts into a ball grid array |
US6509639B1 (en) * | 2001-07-27 | 2003-01-21 | Charles W. C. Lin | Three-dimensional stacked semiconductor package |
US20030016710A1 (en) * | 2001-07-19 | 2003-01-23 | Satoshi Komoto | Semiconductor laser device including light receiving element for receiving monitoring laser beam |
US20030020153A1 (en) * | 2001-07-24 | 2003-01-30 | Ted Bruce | Chip stack with differing chip package types |
US6514793B2 (en) * | 1999-05-05 | 2003-02-04 | Dpac Technologies Corp. | Stackable flex circuit IC package and method of making same |
US20030026155A1 (en) * | 2001-08-01 | 2003-02-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory module and register buffer device for use in the same |
US6521530B2 (en) * | 1998-11-13 | 2003-02-18 | Fujitsu Limited | Composite interposer and method for producing a composite interposer |
US6522018B1 (en) * | 2000-05-16 | 2003-02-18 | Micron Technology, Inc. | Ball grid array chip packages having improved testing and stacking characteristics |
US20030035328A1 (en) * | 2001-08-08 | 2003-02-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device shiftable to test mode in module as well as semiconductor memory module using the same |
US20040000708A1 (en) * | 2001-10-26 | 2004-01-01 | Staktek Group, L.P. | Memory expansion and chip scale stacking system and method |
US6673651B2 (en) * | 1999-07-01 | 2004-01-06 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device including semiconductor elements mounted on base plate |
US20040004281A1 (en) * | 2002-07-03 | 2004-01-08 | Jin-Chuan Bai | Semiconductor package with heat sink |
US6677670B2 (en) * | 2000-04-25 | 2004-01-13 | Seiko Epson Corporation | Semiconductor device |
US20040012991A1 (en) * | 2002-07-18 | 2004-01-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory module |
US6683377B1 (en) * | 2000-05-30 | 2004-01-27 | Amkor Technology, Inc. | Multi-stacked memory package |
US20040021211A1 (en) * | 2002-08-05 | 2004-02-05 | Tessera, Inc. | Microelectronic adaptors, assemblies and methods |
US6690584B2 (en) * | 2000-08-14 | 2004-02-10 | Fujitsu Limited | Information-processing device having a crossbar-board connected to back panels on different sides |
US6689634B1 (en) * | 1999-09-22 | 2004-02-10 | Texas Instruments Incorporated | Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability |
US20040031972A1 (en) * | 2001-10-09 | 2004-02-19 | Tessera, Inc. | Stacked packages |
US6838761B2 (en) * | 2002-09-17 | 2005-01-04 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US6839266B1 (en) * | 1999-09-14 | 2005-01-04 | Rambus Inc. | Memory module with offset data lines and bit line swizzle configuration |
US6841855B2 (en) * | 2003-04-28 | 2005-01-11 | Intel Corporation | Electronic package having a flexible substrate with ends connected to one another |
US6841868B2 (en) * | 1996-10-08 | 2005-01-11 | Micron Technology, Inc. | Memory modules including capacity for additional memory |
US20050018495A1 (en) * | 2004-01-29 | 2005-01-27 | Netlist, Inc. | Arrangement of integrated circuits in a memory module |
US6849949B1 (en) * | 1999-09-27 | 2005-02-01 | Samsung Electronics Co., Ltd. | Thin stacked package |
US20050035440A1 (en) * | 2001-08-22 | 2005-02-17 | Tessera, Inc. | Stacked chip assembly with stiffening layer |
US6858910B2 (en) * | 2000-01-26 | 2005-02-22 | Texas Instruments Incorporated | Method of fabricating a molded package for micromechanical devices |
US20050040508A1 (en) * | 2003-08-22 | 2005-02-24 | Jong-Joo Lee | Area array type package stack and manufacturing method thereof |
US6984885B1 (en) * | 2000-02-10 | 2006-01-10 | Renesas Technology Corp. | Semiconductor device having densely stacked semiconductor chips |
US6998704B2 (en) * | 2002-08-30 | 2006-02-14 | Nec Corporation | Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus |
US7180167B2 (en) * | 2001-10-26 | 2007-02-20 | Staktek Group L. P. | Low profile stacking system and method |
Family Cites Families (119)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US150107A (en) * | 1874-04-21 | Improvement in machines for twisting auger-bits | ||
US3294988A (en) * | 1964-09-24 | 1966-12-27 | Hewlett Packard Co | Transducers |
US3436604A (en) | 1966-04-25 | 1969-04-01 | Texas Instruments Inc | Complex integrated circuit array and method for fabricating same |
US3654394A (en) * | 1969-07-08 | 1972-04-04 | Gordon Eng Co | Field effect transistor switch, particularly for multiplexing |
US3772776A (en) | 1969-12-03 | 1973-11-20 | Thomas & Betts Corp | Method of interconnecting memory plane boards |
US3727064A (en) | 1971-03-17 | 1973-04-10 | Monsanto Co | Opto-isolator devices and method for the fabrication thereof |
US3746934A (en) | 1971-05-06 | 1973-07-17 | Siemens Ag | Stack arrangement of semiconductor chips |
US4103318A (en) | 1977-05-06 | 1978-07-25 | Ford Motor Company | Electronic multichip module |
SU834957A1 (en) | 1979-03-12 | 1981-05-30 | Предприятие П/Я А-7438 | Device for feeding printed circuit boards |
US4288841A (en) | 1979-09-20 | 1981-09-08 | Bell Telephone Laboratories, Incorporated | Double cavity semiconductor chip carrier |
JPS5731166A (en) | 1980-07-31 | 1982-02-19 | Fujitsu Ltd | Semiconductor device |
US4398235A (en) | 1980-09-11 | 1983-08-09 | General Motors Corporation | Vertical integrated circuit package integration |
US4513368A (en) * | 1981-05-22 | 1985-04-23 | Data General Corporation | Digital data processing system having object-based logical memory addressing and self-structuring modular memory |
US4406508A (en) | 1981-07-02 | 1983-09-27 | Thomas & Betts Corporation | Dual-in-line package assembly |
JPS5896756A (en) | 1981-12-04 | 1983-06-08 | Toshiba Corp | Mounting method of multichip package |
JPS58112348A (en) | 1981-12-25 | 1983-07-04 | Fujitsu Ltd | Semiconductor device |
JPS59172253A (en) | 1983-03-18 | 1984-09-28 | Mitsubishi Electric Corp | Semiconductor device |
KR890004820B1 (en) | 1984-03-28 | 1989-11-27 | 인터내셔널 비지네스 머신즈 코포레이션 | Stacked double density memory module using industry standard memory chips |
US4587596A (en) * | 1984-04-09 | 1986-05-06 | Amp Incorporated | High density mother/daughter circuit board connector |
JPS60254762A (en) | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | Package for semiconductor element |
EP0213205B1 (en) | 1984-12-28 | 1992-12-09 | Micro Co., Ltd. | Method of stacking printed circuit boards |
DE3675321D1 (en) | 1985-08-16 | 1990-12-06 | Dai Ichi Seiko Co Ltd | SEMICONDUCTOR ARRANGEMENT WITH PACK OF PIN PLUG TYPE. |
US4895703A (en) * | 1985-09-17 | 1990-01-23 | Calgon Corporation | Trihydroxybenzene boiler corrosion inhibitor compositions and method |
US4696525A (en) | 1985-12-13 | 1987-09-29 | Amp Incorporated | Socket for stacking integrated circuit packages |
JPS62230027A (en) | 1986-03-31 | 1987-10-08 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS63153849A (en) | 1986-12-17 | 1988-06-27 | Nec Corp | Semiconductor device |
US4821007A (en) | 1987-02-06 | 1989-04-11 | Tektronix, Inc. | Strip line circuit component and method of manufacture |
US4862249A (en) | 1987-04-17 | 1989-08-29 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
US4771366A (en) | 1987-07-06 | 1988-09-13 | International Business Machines Corporation | Ceramic card assembly having enhanced power distribution and cooling |
IT1214254B (en) | 1987-09-23 | 1990-01-10 | Sgs Microelettonica S P A | SEMICONDUCTOR DEVICE IN PLASTIC OR CERAMIC CONTAINER WITH "CHIPS" FIXED ON BOTH SIDES OF THE CENTRAL ISLAND OF THE "FRAME". |
US5016138A (en) | 1987-10-27 | 1991-05-14 | Woodman John K | Three dimensional integrated circuit package |
US4833568A (en) | 1988-01-29 | 1989-05-23 | Berhold G Mark | Three-dimensional circuit component assembly and method corresponding thereto |
US4956694A (en) | 1988-11-04 | 1990-09-11 | Dense-Pac Microsystems, Inc. | Integrated circuit chip stacking |
US4953060A (en) | 1989-05-05 | 1990-08-28 | Ncr Corporation | Stackable integrated circuit chip package with improved heat removal |
US5104820A (en) | 1989-07-07 | 1992-04-14 | Irvine Sensors Corporation | Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting |
US5012323A (en) | 1989-11-20 | 1991-04-30 | Micron Technology, Inc. | Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe |
JPH03227541A (en) | 1990-02-01 | 1991-10-08 | Hitachi Ltd | Semiconductor device |
US5041015A (en) | 1990-03-30 | 1991-08-20 | Cal Flex, Inc. | Electrical jumper assembly |
JP2816239B2 (en) | 1990-06-15 | 1998-10-27 | 株式会社日立製作所 | Resin-sealed semiconductor device |
US5499160A (en) | 1990-08-01 | 1996-03-12 | Staktek Corporation | High density integrated circuit module with snap-on rail assemblies |
US5446620A (en) | 1990-08-01 | 1995-08-29 | Staktek Corporation | Ultra high density integrated circuit packages |
US5475920A (en) | 1990-08-01 | 1995-12-19 | Burns; Carmen D. | Method of assembling ultra high density integrated circuit packages |
US5377077A (en) | 1990-08-01 | 1994-12-27 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
US5117282A (en) * | 1990-10-29 | 1992-05-26 | Harris Corporation | Stacked configuration for integrated circuit devices |
JPH04209562A (en) | 1990-12-06 | 1992-07-30 | Fujitsu Ltd | Module structure of semiconductor package |
US5138430A (en) | 1991-06-06 | 1992-08-11 | International Business Machines Corporation | High performance versatile thermally enhanced IC chip mounting |
JPH0513666A (en) | 1991-06-29 | 1993-01-22 | Sony Corp | Complex semiconductor device |
US5214307A (en) * | 1991-07-08 | 1993-05-25 | Micron Technology, Inc. | Lead frame for semiconductor devices having improved adhesive bond line control |
US5311401A (en) | 1991-07-09 | 1994-05-10 | Hughes Aircraft Company | Stacked chip assembly and manufacturing method therefor |
JP3014176B2 (en) | 1991-07-10 | 2000-02-28 | 新光電気工業株式会社 | Lead frame and semiconductor device |
US5252857A (en) * | 1991-08-05 | 1993-10-12 | International Business Machines Corporation | Stacked DCA memory chips |
US5448450A (en) | 1991-08-15 | 1995-09-05 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
US5198965A (en) * | 1991-12-18 | 1993-03-30 | International Business Machines Corporation | Free form packaging of specific functions within a computer system |
US5241454A (en) | 1992-01-22 | 1993-08-31 | International Business Machines Corporation | Mutlilayered flexible circuit package |
US5262927A (en) | 1992-02-07 | 1993-11-16 | Lsi Logic Corporation | Partially-molded, PCB chip carrier package |
US5222014A (en) | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5259770A (en) | 1992-03-19 | 1993-11-09 | Amp Incorporated | Impedance controlled elastomeric connector |
US5438224A (en) * | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
US5247423A (en) | 1992-05-26 | 1993-09-21 | Motorola, Inc. | Stacking three dimensional leadless multi-chip module and method for making the same |
US5702985A (en) | 1992-06-26 | 1997-12-30 | Staktek Corporation | Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method |
US5729894A (en) * | 1992-07-21 | 1998-03-24 | Lsi Logic Corporation | Method of assembling ball bump grid array semiconductor packages |
US5402006A (en) | 1992-11-10 | 1995-03-28 | Texas Instruments Incorporated | Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound |
US5313097A (en) | 1992-11-16 | 1994-05-17 | International Business Machines, Corp. | High density memory module |
US5375041A (en) | 1992-12-02 | 1994-12-20 | Intel Corporation | Ra-tab array bump tab tape based I.C. package |
US5347428A (en) | 1992-12-03 | 1994-09-13 | Irvine Sensors Corporation | Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip |
US6205654B1 (en) | 1992-12-11 | 2001-03-27 | Staktek Group L.P. | Method of manufacturing a surface mount package |
US5801437A (en) | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
US5644161A (en) | 1993-03-29 | 1997-07-01 | Staktek Corporation | Ultra-high density warp-resistant memory module |
US5541812A (en) | 1995-05-22 | 1996-07-30 | Burns; Carmen D. | Bus communication system for stacked high density integrated circuit packages having an intermediate lead frame |
US5523619A (en) | 1993-11-03 | 1996-06-04 | International Business Machines Corporation | High density memory structure |
US5477082A (en) * | 1994-01-11 | 1995-12-19 | Exponential Technology, Inc. | Bi-planar multi-chip module |
US5502333A (en) * | 1994-03-30 | 1996-03-26 | International Business Machines Corporation | Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit |
JPH07312469A (en) * | 1994-05-16 | 1995-11-28 | Nippon Mektron Ltd | Structure of bent part of multilayer flexible circuit board |
US5514907A (en) | 1995-03-21 | 1996-05-07 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
US5612570A (en) | 1995-04-13 | 1997-03-18 | Dense-Pac Microsystems, Inc. | Chip stack and method of making same |
DE19516272A1 (en) | 1995-05-08 | 1996-11-14 | Hermann Leguin | Primary element scanner for determining deflection of scanning pin or similar |
US5637920A (en) * | 1995-10-04 | 1997-06-10 | Lsi Logic Corporation | High contact density ball grid array package for flip-chips |
KR0184076B1 (en) * | 1995-11-28 | 1999-03-20 | 김광호 | Three-dimensional stacked package |
US5646446A (en) | 1995-12-22 | 1997-07-08 | Fairchild Space And Defense Corporation | Three-dimensional flexible assembly of integrated circuits |
JPH09260568A (en) | 1996-03-27 | 1997-10-03 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
US5789815A (en) * | 1996-04-23 | 1998-08-04 | Motorola, Inc. | Three dimensional semiconductor package having flexible appendages |
US5778522A (en) * | 1996-05-20 | 1998-07-14 | Staktek Corporation | Method of manufacturing a high density integrated circuit module with complex electrical interconnect rails having electrical interconnect strain relief |
DE19626126C2 (en) | 1996-06-28 | 1998-04-16 | Fraunhofer Ges Forschung | Method for forming a spatial chip arrangement and spatial chip arrangement |
US6247228B1 (en) * | 1996-08-12 | 2001-06-19 | Tessera, Inc. | Electrical connection with inwardly deformable contacts |
JP3695893B2 (en) * | 1996-12-03 | 2005-09-14 | 沖電気工業株式会社 | Semiconductor device, manufacturing method and mounting method thereof |
US6225688B1 (en) | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
JP3455040B2 (en) * | 1996-12-16 | 2003-10-06 | 株式会社日立製作所 | Source clock synchronous memory system and memory unit |
JPH10270506A (en) * | 1997-03-21 | 1998-10-09 | Mitsubishi Electric Corp | Semiconductor device |
JP3011233B2 (en) * | 1997-05-02 | 2000-02-21 | 日本電気株式会社 | Semiconductor package and its semiconductor mounting structure |
US6208521B1 (en) | 1997-05-19 | 2001-03-27 | Nitto Denko Corporation | Film carrier and laminate type mounting structure using same |
US5917709A (en) * | 1997-06-16 | 1999-06-29 | Eastman Kodak Company | Multiple circuit board assembly having an interconnect mechanism that includes a flex connector |
US6040624A (en) * | 1997-10-02 | 2000-03-21 | Motorola, Inc. | Semiconductor device package and method |
US6097087A (en) * | 1997-10-31 | 2000-08-01 | Micron Technology, Inc. | Semiconductor package including flex circuit, interconnects and dense array external contacts |
US6205521B1 (en) * | 1997-11-03 | 2001-03-20 | Compaq Computer Corporation | Inclusion map for accelerated cache flush |
DE19758197C2 (en) * | 1997-12-30 | 2002-11-07 | Infineon Technologies Ag | Stack arrangement for two semiconductor memory chips and printed circuit board, which is equipped with a plurality of such stack arrangements |
US5926369A (en) | 1998-01-22 | 1999-07-20 | International Business Machines Corporation | Vertically integrated multi-chip circuit package with heat-sink support |
US6329709B1 (en) * | 1998-05-11 | 2001-12-11 | Micron Technology, Inc. | Interconnections for a semiconductor device |
US6300679B1 (en) * | 1998-06-01 | 2001-10-09 | Semiconductor Components Industries, Llc | Flexible substrate for packaging a semiconductor component |
JP3186700B2 (en) * | 1998-06-24 | 2001-07-11 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
DE19833713C1 (en) | 1998-07-27 | 2000-05-04 | Siemens Ag | Laminate or stacked package arrangement based on at least two integrated circuits |
US6153929A (en) * | 1998-08-21 | 2000-11-28 | Micron Technology, Inc. | Low profile multi-IC package connector |
KR100514558B1 (en) * | 1998-09-09 | 2005-09-13 | 세이코 엡슨 가부시키가이샤 | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
US6222737B1 (en) * | 1999-04-23 | 2001-04-24 | Dense-Pac Microsystems, Inc. | Universal package and method of forming the same |
JP2000353767A (en) * | 1999-05-14 | 2000-12-19 | Universal Instr Corp | Board for mounting electronic component, package, mounting method, and method for housing integrated circuit chip in package |
US6376769B1 (en) * | 1999-05-18 | 2002-04-23 | Amerasia International Technology, Inc. | High-density electronic package, and method for making same |
JP2001053243A (en) * | 1999-08-06 | 2001-02-23 | Hitachi Ltd | Semiconductor memory device and memory module |
US6675469B1 (en) * | 1999-08-11 | 2004-01-13 | Tessera, Inc. | Vapor phase connection techniques |
KR100459971B1 (en) * | 1999-10-01 | 2004-12-04 | 세이코 엡슨 가부시키가이샤 | Semiconductor device, method and device for producing the same, circuit board, and electronic equipment |
US6441476B1 (en) * | 2000-10-18 | 2002-08-27 | Seiko Epson Corporation | Flexible tape carrier with external terminals formed on interposers |
US6262895B1 (en) | 2000-01-13 | 2001-07-17 | John A. Forthun | Stackable chip package with flex carrier |
US6528870B2 (en) * | 2000-01-28 | 2003-03-04 | Kabushiki Kaisha Toshiba | Semiconductor device having a plurality of stacked wiring boards |
TW579555B (en) * | 2000-03-13 | 2004-03-11 | Ibm | Semiconductor chip package and packaging of integrated circuit chip in electronic apparatus |
US6560117B2 (en) * | 2000-06-28 | 2003-05-06 | Micron Technology, Inc. | Packaged microelectronic die assemblies and methods of manufacture |
US6552910B1 (en) * | 2000-06-28 | 2003-04-22 | Micron Technology, Inc. | Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture |
JP3390412B2 (en) * | 2000-08-07 | 2003-03-24 | 株式会社キャットアイ | head lamp |
US6884653B2 (en) * | 2001-03-21 | 2005-04-26 | Micron Technology, Inc. | Folded interposer |
US6707684B1 (en) * | 2001-04-02 | 2004-03-16 | Advanced Micro Devices, Inc. | Method and apparatus for direct connection between two integrated circuits via a connector |
US6927471B2 (en) * | 2001-09-07 | 2005-08-09 | Peter C. Salmon | Electronic system modules and method of fabrication |
KR20030029743A (en) * | 2001-10-10 | 2003-04-16 | 삼성전자주식회사 | Stack package using flexible double wiring substrate |
-
2001
- 2001-10-26 US US10/005,581 patent/US6576992B1/en not_active Expired - Lifetime
-
2002
- 2002-10-25 CN CN200810009614A patent/CN100594608C/en not_active Expired - Lifetime
- 2002-10-25 WO PCT/US2002/034340 patent/WO2003037053A1/en not_active Application Discontinuation
- 2002-10-25 GB GB0406140A patent/GB2395367B/en not_active Expired - Fee Related
- 2002-10-25 CN CNB028261879A patent/CN100449747C/en not_active Expired - Lifetime
-
2003
- 2003-03-27 US US10/400,309 patent/US20030137048A1/en not_active Abandoned
-
2005
- 2005-10-22 HK HK05109243.1A patent/HK1077460A1/en not_active IP Right Cessation
- 2005-12-21 US US11/316,505 patent/US20060091521A1/en not_active Abandoned
- 2005-12-22 US US11/317,425 patent/US20060131716A1/en not_active Abandoned
Patent Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3372310A (en) * | 1965-04-30 | 1968-03-05 | Radiation Inc | Universal modular packages for integrated circuits |
US3718842A (en) * | 1972-04-21 | 1973-02-27 | Texas Instruments Inc | Liquid crystal display mounting structure |
US4079511A (en) * | 1976-07-30 | 1978-03-21 | Amp Incorporated | Method for packaging hermetically sealed integrated circuit chips on lead frames |
US4429349A (en) * | 1980-09-30 | 1984-01-31 | Burroughs Corporation | Coil connector |
US4437235A (en) * | 1980-12-29 | 1984-03-20 | Honeywell Information Systems Inc. | Integrated circuit package |
US4567543A (en) * | 1983-02-15 | 1986-01-28 | Motorola, Inc. | Double-sided flexible electronic circuit module |
US4727513A (en) * | 1983-09-02 | 1988-02-23 | Wang Laboratories, Inc. | Signal in-line memory module |
US4645944A (en) * | 1983-09-05 | 1987-02-24 | Matsushita Electric Industrial Co., Ltd. | MOS register for selecting among various data inputs |
US4724611A (en) * | 1985-08-23 | 1988-02-16 | Nec Corporation | Method for producing semiconductor module |
US4722691A (en) * | 1986-02-03 | 1988-02-02 | General Motors Corporation | Header assembly for a printed circuit board |
US4903169A (en) * | 1986-04-03 | 1990-02-20 | Matsushita Electric Industrial Co., Ltd. | Shielded high frequency apparatus having partitioned shield case, and method of manufacture thereof |
US4982265A (en) * | 1987-06-24 | 1991-01-01 | Hitachi, Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
US4983533A (en) * | 1987-10-28 | 1991-01-08 | Irvine Sensors Corporation | High-density electronic modules - process and product |
US5198888A (en) * | 1987-12-28 | 1993-03-30 | Hitachi, Ltd. | Semiconductor stacked device |
US4985703A (en) * | 1988-02-03 | 1991-01-15 | Nec Corporation | Analog multiplexer |
US4891789A (en) * | 1988-03-03 | 1990-01-02 | Bull Hn Information Systems, Inc. | Surface mounted multilayer memory printed circuit board |
US4911643A (en) * | 1988-10-11 | 1990-03-27 | Beta Phase, Inc. | High density and high signal integrity connector |
US5276418A (en) * | 1988-11-16 | 1994-01-04 | Motorola, Inc. | Flexible substrate electronic assembly |
US5081067A (en) * | 1989-02-10 | 1992-01-14 | Fujitsu Limited | Ceramic package type semiconductor device and method of assembling the same |
US4992850A (en) * | 1989-02-15 | 1991-02-12 | Micron Technology, Inc. | Directly bonded simm module |
US4992849A (en) * | 1989-02-15 | 1991-02-12 | Micron Technology, Inc. | Directly bonded board multiple integrated circuit module |
US5198985A (en) * | 1989-11-28 | 1993-03-30 | Goldstar Co., Ltd. | Apparatus for removing erroneously inserted parts in automatic insertion machine |
US5191404A (en) * | 1989-12-20 | 1993-03-02 | Digital Equipment Corporation | High density memory array packaging |
US5279029A (en) * | 1990-08-01 | 1994-01-18 | Staktek Corporation | Ultra high density integrated circuit packages method |
US5289346A (en) * | 1991-02-26 | 1994-02-22 | Microelectronics And Computer Technology Corporation | Peripheral to area adapter with protective bumper for an integrated circuit chip |
US5394010A (en) * | 1991-03-13 | 1995-02-28 | Kabushiki Kaisha Toshiba | Semiconductor assembly having laminated semiconductor devices |
US5289062A (en) * | 1991-03-18 | 1994-02-22 | Quality Semiconductor, Inc. | Fast transmission gate switch |
US5099393A (en) * | 1991-03-25 | 1992-03-24 | International Business Machines Corporation | Electronic package for high density applications |
US5714802A (en) * | 1991-06-18 | 1998-02-03 | Micron Technology, Inc. | High-density electronic module |
US5188926A (en) * | 1991-12-09 | 1993-02-23 | Eastman Kodak Company | Photographic elements having carbonamide coupler solvents and addenda to reduce sensitizing dye stain |
US5281852A (en) * | 1991-12-10 | 1994-01-25 | Normington Peter J C | Semiconductor device including stacked die |
US5397916A (en) * | 1991-12-10 | 1995-03-14 | Normington; Peter J. C. | Semiconductor device including stacked die |
US5400003A (en) * | 1992-08-19 | 1995-03-21 | Micron Technology, Inc. | Inherently impedance matched integrated circuit module |
US5394300A (en) * | 1992-09-04 | 1995-02-28 | Mitsubishi Denki Kabushiki Kaisha | Thin multilayered IC memory card |
US5394303A (en) * | 1992-09-11 | 1995-02-28 | Kabushiki Kaisha Toshiba | Semiconductor device |
US5708297A (en) * | 1992-09-16 | 1998-01-13 | Clayton; James E. | Thin multichip module |
US5484959A (en) * | 1992-12-11 | 1996-01-16 | Staktek Corporation | High density lead-on-package fabrication method and apparatus |
US5384690A (en) * | 1993-07-27 | 1995-01-24 | International Business Machines Corporation | Flex laminate package for a parallel processor |
US5396573A (en) * | 1993-08-03 | 1995-03-07 | International Business Machines Corporation | Pluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal |
US5600178A (en) * | 1993-10-08 | 1997-02-04 | Texas Instruments Incorporated | Semiconductor package having interdigitated leads |
US5386341A (en) * | 1993-11-01 | 1995-01-31 | Motorola, Inc. | Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape |
US5594275A (en) * | 1993-11-18 | 1997-01-14 | Samsung Electronics Co., Ltd. | J-leaded semiconductor package having a plurality of stacked ball grid array packages |
US5493476A (en) * | 1994-03-07 | 1996-02-20 | Staktek Corporation | Bus communication system for stacked high density integrated circuit packages with bifurcated distal lead ends |
US5592364A (en) * | 1995-01-24 | 1997-01-07 | Staktek Corporation | High density integrated circuit module with complex electrical interconnect rails |
US5491612A (en) * | 1995-02-21 | 1996-02-13 | Fairchild Space And Defense Corporation | Three-dimensional modular assembly of integrated circuits |
US5717556A (en) * | 1995-04-26 | 1998-02-10 | Nec Corporation | Printed-wiring board having plural parallel-connected interconnections |
US5872051A (en) * | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
US6025642A (en) * | 1995-08-17 | 2000-02-15 | Staktek Corporation | Ultra high density integrated circuit packages |
US6013948A (en) * | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
US20020001216A1 (en) * | 1996-02-26 | 2002-01-03 | Toshio Sugano | Semiconductor device and process for manufacturing the same |
US6178093B1 (en) * | 1996-06-28 | 2001-01-23 | International Business Machines Corporation | Information handling system with circuit assembly having holes filled with filler material |
US6841868B2 (en) * | 1996-10-08 | 2005-01-11 | Micron Technology, Inc. | Memory modules including capacity for additional memory |
US6336262B1 (en) * | 1996-10-31 | 2002-01-08 | International Business Machines Corporation | Process of forming a capacitor with multi-level interconnection technology |
US6014316A (en) * | 1997-06-13 | 2000-01-11 | Irvine Sensors Corporation | IC stack utilizing BGA contacts |
US6028352A (en) * | 1997-06-13 | 2000-02-22 | Irvine Sensors Corporation | IC stack utilizing secondary leadframes |
US5869353A (en) * | 1997-11-17 | 1999-02-09 | Dense-Pac Microsystems, Inc. | Modular panel stacking process |
US6504104B2 (en) * | 1997-12-10 | 2003-01-07 | Siemens Aktiengesellschaft | Flexible wiring for the transformation of a substrate with edge contacts into a ball grid array |
US6186106B1 (en) * | 1997-12-29 | 2001-02-13 | Visteon Global Technologies, Inc. | Apparatus for routing electrical signals in an engine |
US6021048A (en) * | 1998-02-17 | 2000-02-01 | Smith; Gary W. | High speed memory module |
US6028365A (en) * | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
US6172874B1 (en) * | 1998-04-06 | 2001-01-09 | Silicon Graphics, Inc. | System for stacking of integrated circuit packages |
US6180881B1 (en) * | 1998-05-05 | 2001-01-30 | Harlan Ruben Isaak | Chip stack and method of making same |
US6187652B1 (en) * | 1998-09-14 | 2001-02-13 | Fujitsu Limited | Method of fabrication of multiple-layer high density substrate |
US6347394B1 (en) * | 1998-11-04 | 2002-02-12 | Micron Technology, Inc. | Buffering circuit embedded in an integrated circuit device module used for buffering clocks and other input signals |
US6521530B2 (en) * | 1998-11-13 | 2003-02-18 | Fujitsu Limited | Composite interposer and method for producing a composite interposer |
US6343020B1 (en) * | 1998-12-28 | 2002-01-29 | Foxconn Precision Components Co., Ltd. | Memory module |
US6351029B1 (en) * | 1999-05-05 | 2002-02-26 | Harlan R. Isaak | Stackable flex circuit chip package and method of making same |
US6514793B2 (en) * | 1999-05-05 | 2003-02-04 | Dpac Technologies Corp. | Stackable flex circuit IC package and method of making same |
US6673651B2 (en) * | 1999-07-01 | 2004-01-06 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device including semiconductor elements mounted on base plate |
US6839266B1 (en) * | 1999-09-14 | 2005-01-04 | Rambus Inc. | Memory module with offset data lines and bit line swizzle configuration |
US6689634B1 (en) * | 1999-09-22 | 2004-02-10 | Texas Instruments Incorporated | Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability |
US6849949B1 (en) * | 1999-09-27 | 2005-02-01 | Samsung Electronics Co., Ltd. | Thin stacked package |
US6858910B2 (en) * | 2000-01-26 | 2005-02-22 | Texas Instruments Incorporated | Method of fabricating a molded package for micromechanical devices |
US6984885B1 (en) * | 2000-02-10 | 2006-01-10 | Renesas Technology Corp. | Semiconductor device having densely stacked semiconductor chips |
US6677670B2 (en) * | 2000-04-25 | 2004-01-13 | Seiko Epson Corporation | Semiconductor device |
US6522018B1 (en) * | 2000-05-16 | 2003-02-18 | Micron Technology, Inc. | Ball grid array chip packages having improved testing and stacking characteristics |
US20020006032A1 (en) * | 2000-05-23 | 2002-01-17 | Chris Karabatsos | Low-profile registered DIMM |
US6683377B1 (en) * | 2000-05-30 | 2004-01-27 | Amkor Technology, Inc. | Multi-stacked memory package |
US6690584B2 (en) * | 2000-08-14 | 2004-02-10 | Fujitsu Limited | Information-processing device having a crossbar-board connected to back panels on different sides |
US6349050B1 (en) * | 2000-10-10 | 2002-02-19 | Rambus, Inc. | Methods and systems for reducing heat flux in memory systems |
US6850414B2 (en) * | 2001-07-02 | 2005-02-01 | Infineon Technologies Ag | Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor memories |
US20030002262A1 (en) * | 2001-07-02 | 2003-01-02 | Martin Benisek | Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor memories |
US20030016710A1 (en) * | 2001-07-19 | 2003-01-23 | Satoshi Komoto | Semiconductor laser device including light receiving element for receiving monitoring laser beam |
US20030020153A1 (en) * | 2001-07-24 | 2003-01-30 | Ted Bruce | Chip stack with differing chip package types |
US6509639B1 (en) * | 2001-07-27 | 2003-01-21 | Charles W. C. Lin | Three-dimensional stacked semiconductor package |
US20030026155A1 (en) * | 2001-08-01 | 2003-02-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory module and register buffer device for use in the same |
US20030035328A1 (en) * | 2001-08-08 | 2003-02-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device shiftable to test mode in module as well as semiconductor memory module using the same |
US20050035440A1 (en) * | 2001-08-22 | 2005-02-17 | Tessera, Inc. | Stacked chip assembly with stiffening layer |
US20040031972A1 (en) * | 2001-10-09 | 2004-02-19 | Tessera, Inc. | Stacked packages |
US20040000708A1 (en) * | 2001-10-26 | 2004-01-01 | Staktek Group, L.P. | Memory expansion and chip scale stacking system and method |
US7180167B2 (en) * | 2001-10-26 | 2007-02-20 | Staktek Group L. P. | Low profile stacking system and method |
US20040004281A1 (en) * | 2002-07-03 | 2004-01-08 | Jin-Chuan Bai | Semiconductor package with heat sink |
US20040012991A1 (en) * | 2002-07-18 | 2004-01-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory module |
US20040021211A1 (en) * | 2002-08-05 | 2004-02-05 | Tessera, Inc. | Microelectronic adaptors, assemblies and methods |
US6998704B2 (en) * | 2002-08-30 | 2006-02-14 | Nec Corporation | Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus |
US6838761B2 (en) * | 2002-09-17 | 2005-01-04 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US6841855B2 (en) * | 2003-04-28 | 2005-01-11 | Intel Corporation | Electronic package having a flexible substrate with ends connected to one another |
US20050040508A1 (en) * | 2003-08-22 | 2005-02-24 | Jong-Joo Lee | Area array type package stack and manufacturing method thereof |
US20050018495A1 (en) * | 2004-01-29 | 2005-01-27 | Netlist, Inc. | Arrangement of integrated circuits in a memory module |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080048316A1 (en) * | 2006-08-25 | 2008-02-28 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
US7868440B2 (en) * | 2006-08-25 | 2011-01-11 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
US20110104857A1 (en) * | 2006-08-25 | 2011-05-05 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
US8354301B2 (en) | 2006-08-25 | 2013-01-15 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
US8987885B2 (en) | 2006-08-25 | 2015-03-24 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
US8588017B2 (en) | 2010-10-20 | 2013-11-19 | Samsung Electronics Co., Ltd. | Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same |
CN111093316A (en) * | 2018-10-24 | 2020-05-01 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
GB2395367B (en) | 2005-05-25 |
CN1608400A (en) | 2005-04-20 |
WO2003037053A1 (en) | 2003-05-01 |
US6576992B1 (en) | 2003-06-10 |
GB2395367A (en) | 2004-05-19 |
CN101271886A (en) | 2008-09-24 |
CN100594608C (en) | 2010-03-17 |
US20060091521A1 (en) | 2006-05-04 |
GB0406140D0 (en) | 2004-04-21 |
US20030137048A1 (en) | 2003-07-24 |
CN100449747C (en) | 2009-01-07 |
HK1077460A1 (en) | 2006-02-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6576992B1 (en) | Chip scale stacking system and method | |
US7495334B2 (en) | Stacking system and method | |
US7335975B2 (en) | Integrated circuit stacking system and method | |
US7524703B2 (en) | Integrated circuit stacking system and method | |
US7053478B2 (en) | Pitch change and chip scale stacking system | |
US20080067662A1 (en) | Modularized Die Stacking System and Method | |
US7719098B2 (en) | Stacked modules and method | |
US20080079132A1 (en) | Inverted CSP Stacking System and Method | |
US7542304B2 (en) | Memory expansion and integrated circuit stacking system and method | |
US7202555B2 (en) | Pitch change and chip scale stacking system and method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ENTORIAN TECHNOLOGIES, L.P. (FORMERLY STAKTEK GROU Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CADY, JAMES W.;WILDER, JAMES;ROPER, DAVID L.;AND OTHERS;REEL/FRAME:021464/0745;SIGNING DATES FROM 20011025 TO 20011026 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |