US20060240600A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- US20060240600A1 US20060240600A1 US11/474,332 US47433206A US2006240600A1 US 20060240600 A1 US20060240600 A1 US 20060240600A1 US 47433206 A US47433206 A US 47433206A US 2006240600 A1 US2006240600 A1 US 2006240600A1
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- die
- semiconductor device
- lead frame
- manufacturing
- leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a semiconductor device and a manufacturing method of the same. More particularly, the present invention relates to a technique effectively applicable to the increase of the number of pins used in a resin-encapsulated semiconductor device.
- a QFN Quad Flat Non-leaded package
- a resin package in which a semiconductor die mounted on a lead frame is encapsulated in a plastic package made of molding resin.
- tip portions of a plurality of leads electrically connected to a semiconductor die via bonding wires are exposed from a rear surface (lower surface) of a peripheral part of a plastic package, by which terminals are formed.
- bonding wires are connected to the surfaces opposite to the surfaces on which the terminals are exposed. More specifically, bonding wires are connected to the terminal surfaces inside the plastic package, by which the terminals and the semiconductor die are electrically connected to each other.
- the QFN is mounted on a wiring board by soldering these terminals to electrodes (footprint) on the wiring board. This structure of the QFN enables to obtain the advantage that the size of the mounting area can be reduced in comparison to a QFP (Quad Flat Package) in which the leads transversely extending from the side surfaces of a package (plastic package) constitute the terminals.
- QFP Quad Flat Package
- the interval between the terminals is equal to the interval between the tip portions of the leads at which the bonding wires are connected.
- a predetermined size of the terminal is necessary to ensure the reliability of the mounting, it is impossible to reduce the size too much.
- the length between the semiconductor die and the position at which the bonding wire is connected becomes greater.
- An object of the present invention is to provide a technique capable of achieving the increase of the number of pins in a QFN.
- Another object of the present invention is to provide a technique to obtain a QFN which is adapted to deal with a reduction in die size.
- a semiconductor device includes: a semiconductor die; a die pad on which the semiconductor die is mounted; a plurality of leads arranged around the semiconductor die; a plurality of wires for electrically connecting the semiconductor die and the leads; and a plastic package for encapsulating the semiconductor die, the die pad, the plurality of leads, and the plurality of wires, wherein the plurality of leads are formed so that intervals between lead tips on one side near the semiconductor die are narrower than those between leads tips on the other side opposite to the one side, and a terminal protruded from a rear surface of the plastic package to the outside is selectively provided to each of the plurality of leads.
- a method of manufacturing a semiconductor device according to the present invention includes the steps of:
- FIG. 1 is a plan view of an outward appearance (main surface side) of a semiconductor device according to an embodiment of the present invention
- FIG. 2 is a plan view of an outward appearance (rear surface side) of a semiconductor device according to an embodiment of the present invention
- FIG. 3 is a plan view of an internal structure (main surface side) of a semiconductor device according to an embodiment of the present invention.
- FIG. 4 is a plan view of an internal structure (rear surface side) of a semiconductor device according to an embodiment of the present invention.
- FIG. 5 is a sectional view of a semiconductor device according to an embodiment of the present invention.
- FIG. 6 is a plan view showing the entire lead frame used in the manufacture of a semiconductor device according to an embodiment of the present invention.
- FIG. 7 is a sectional view of the principal part of the lead frame shown in FIG. 6 for illustrating the manufacturing method of the same;
- FIG. 8 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention
- FIG. 9 is a sectional view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention.
- FIG. 10 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention.
- FIG. 11 is a sectional view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention
- FIG. 12 is a sectional view of the principal part of a lead frame and a molding die for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention
- FIG. 13 is a sectional view of the principal part of a lead frame and a molding die for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention
- FIG. 14 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention
- FIG. 15 is a sectional view of the principal part of a lead frame and a molding die for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention
- FIG. 16 is a plan view showing the positions where the lead frame contacts to an upper die of the molding die used in the manufacture of a semiconductor device according to an embodiment of the present invention
- FIG. 17 is a plan view schematically showing the flowing directions of resin injected in cavities and the positions of gates of the molding die used in the manufacture of a semiconductor device according to an embodiment of the present invention.
- FIG. 18 is a plan view (main surface side) showing the entire lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention
- FIG. 19 is a sectional view of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention.
- FIG. 20 is a plan view (rear surface side) showing the entire lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention
- FIG. 21 is a plan view of the principal part of a lead frame used in the manufacture of a semiconductor device according to another embodiment of the present invention.
- FIG. 22 is a sectional view of the principal part of a lead frame used in the manufacture of a semiconductor device according to another embodiment of the present invention.
- FIG. 23 is a sectional view of the principal part of a lead frame for illustrating the manufacturing method of a lead frame used in the manufacture of a semiconductor device according to another embodiment of the present invention.
- FIG. 24 is a sectional view for illustrating the manufacturing method of a semiconductor device by the use of the lead frame shown in FIGS. 21 and 22 ;
- FIG. 25 is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 26A is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 26B is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 26C is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 26D is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 26E is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 27A is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 27B is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 28A is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 28B is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 29 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 30 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 31 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 32 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 33 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 34 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 35 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 36 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 37 is a plan view of an internal structure (main surface side) of a semiconductor device according to another embodiment of the present invention.
- FIG. 38 is an explanatory diagram for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 39 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 40 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 41 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 42A is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 42B is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 42C is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 42D is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 42E is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 43 is a sectional view for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 44 is a sectional view of a semiconductor device according to another embodiment of the present invention.
- FIG. 45 is a sectional view of a semiconductor device according to another embodiment of the present invention.
- FIG. 46 is a sectional view of a semiconductor device according to another embodiment of the present invention.
- FIG. 47 is a sectional view of a semiconductor device according to another embodiment of the present invention.
- FIG. 48 is a sectional view of a semiconductor device according to another embodiment of the present invention.
- FIG. 49 is a sectional view of a semiconductor device according to another embodiment of the present invention.
- FIG. 50A is a sectional view of a semiconductor device according to another embodiment of the present invention.
- FIG. 50B is a sectional view of a semiconductor device according to another embodiment of the present invention.
- FIG. 51 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 52 is a plan view of an outward appearance (rear surface side) of a semiconductor device according to another embodiment of the present invention.
- FIG. 53 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 54 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 55 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 56 is a plan view of the principal part of a lead frame used in the manufacture of a semiconductor device according to another embodiment of the present invention.
- FIG. 57 is a sectional view of a semiconductor device according to another embodiment of the present invention.
- FIG. 58 is a plan view of an internal structure (rear surface side) of a semiconductor device according to another embodiment of the present invention.
- FIG. 59 is a sectional view of the principal part of a molding die for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 60A is a partially enlarged sectional view of a plastic package separated from a molding die
- FIG. 60B is a partially enlarged sectional view of a plastic package separated from a molding die.
- FIG. 61 is a sectional view for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention.
- FIG. 1 is a plan view showing an outward appearance (main surface side) of a QFN according to this embodiment
- FIG. 2 is a plan view showing an outward appearance (rear surface side) of the QFN
- FIG. 3 is a plan view showing an internal structure (main surface side) of the QFN
- FIG. 4 is a plan view showing an internal structure (rear surface side) of the QFN
- FIG. 5 is a sectional view of the QFN.
- the QFN 1 is a surface mounting type package in which one semiconductor die 2 is encapsulated in a plastic package 3 , and has dimensions of, for example, length 12 mm, width 12 mm, and thickness 1.0 mm.
- the semiconductor die 2 is mounted on a metal die pad 4 and is arranged at the center of the plastic package 3 .
- the semiconductor die 2 has a size of 4 mm on a side.
- the die pad 4 has a diameter smaller than that of the semiconductor die 2 (so called small tab structure) so as to enable the mounting of various types of semiconductor dies 2 with a size of 4 to 7 mm on a side. In this embodiment, the diameter of the die pad 4 is 3 mm.
- the die pad 4 is supported by four die pad supports 5 b extending to the four corners of the plastic package 3 .
- the die pad supports 5 b are formed integrally with the die pad 4 .
- a plurality of (for example, 116 ) leads 5 made of the same metal as the die pad 4 and the die pad supports 5 b are arranged around the die pad 4 so as to surround the same.
- Lead tip 5 a of the lead 5 (on the side near the semiconductor die 2 ) is electrically connected to a bonding pad 7 on the main surface of the semiconductor die 2 via a gold wire 6
- lead tip 5 c of the lead 5 (near the package edge) is ended at a side surface of the plastic package 3 .
- Each of the lead tips 5 a near the semiconductor die is extended to a position close to the die pad 4 so as to reduce the length between the semiconductor die 2 and the leads 5 , and the interval (P 3 ) between the tip portions of the leads 5 is narrow (0.18 mm to 0.2 mm). Therefore, the interval between adjoining lead tips 5 a near the semiconductor die is smaller than the interval between adjoining lead tips 5 c near the package edge.
- the leads 5 formed in the above-described shape make it possible to reduce the length of the gold wires 6 that connect the lead tips 5 a near the semiconductor die and the bonding pads 7 (in this embodiment, 3 mm or shorter).
- a plurality of (for example, 116 ) external connection terminals 8 are provided on a rear surface (substrate mounting surface) of the QFN 1 .
- These terminals 8 are arranged in two lines along each of the sides of the plastic package 3 in a zigzag pattern, and each of the tip portions of the terminals 8 is exposed from the rear surface of the plastic package 3 and protruded to the outside.
- the diameter (d) of the terminal 8 is 0.3 mm.
- the interval (P 1 ) between the adjoining terminals 8 in the same line is 0.65 mm, and the interval (P 2 ) between the interstitial terminals in different lines is 0.325 mm.
- the terminal 8 in this embodiment is formed integrally with the lead 5 , and the thickness of the terminal 8 is about 125 to 150 ⁇ m.
- the thickness of the part of the lead 5 other than the terminal 8 more specifically, the thickness of the lead tip 5 a near the semiconductor die and that of the lead tip 5 c near the package edge are about 65 to 75 ⁇ m.
- a solder layer 9 is deposited by an electroplating method or a printing method.
- the QFN 1 in this embodiment is mounted by soldering the terminals 8 to electrodes (footprint) on a wiring board.
- the lead frame LF 1 is a metal sheet made of Cu, Cu alloy, or Fe—Ni alloy, in which above-described patterns such as die pads 4 , leads 5 , die pad supports 5 b, and the like are successively formed laterally and longitudinally. More specifically, the lead frame LF 1 has a structure in which a plurality of (for example, 24 ) semiconductor dies are successively mounted.
- the lead frame LF 1 is manufactured in the following manner. That is, a metal sheet 10 made of Cu, Cu alloy, or Fe—Ni alloy with a thickness of about 125 to 150 ⁇ m as shown in FIG. 7 is prepared, and one surface of the parts on the metal sheet 10 where the die pad 4 , the leads 5 , and the die pad supports 5 b are formed is coated with a photoresist film 11 . Also, both surfaces of the parts on the metal sheet 10 where the external connection terminals 8 are formed are coated with the photoresist film 11 .
- the metal sheet 10 in this state is etched by the use of etching solution, and the thickness of the metal sheet 10 whose one surface is coated with the photoresist film 11 is reduced to about a half (65 to 75 ⁇ m) (half etching).
- the etching performed in this manner the parts of the metal sheet 10 not coated with the photoresist film 11 on both faces are completely removed, and the die pad 4 , the leads 5 , and the die pad supports 5 b each having a thickness of about 65 to 75 ⁇ m are formed on the parts of the metal sheet 10 whose one surface is coated with the photoresist film 11 .
- the photoresist film 11 is removed, and then, the surfaces of the lead tips 5 a near the semiconductor die are plated with silver. By doing so, the lead frame LF 1 shown in FIG. 6 is completed.
- the palladium (Pd) plating to the entire surface of the lead frame LF 1 is also available. Since a thickness of a plated layer by the palladium plating is thinner in comparison to that by the silver plating, it is possible to improve the bondability between the leads 5 and the gold wires 6 .
- the plating on the entire surface of the lead frame LF 1 forms a plated layer also on the surface of the terminals 8 . Therefore, it is possible to reduce the number of the plating processes.
- the half etching is performed after coating, with the photoresist film 11 , one surface of the parts of the metal sheet 10 to be a base material of the lead frame LF 1 , and the thickness of the lead 5 is reduced to about half of the thickness of the metal sheet 10 .
- the leads 5 in which intervals between the lead tips 5 a on one side are extremely narrow in this embodiment, 0.18 to 0.2 mm interval
- the manufacturing process of the QFN 1 using the lead frame LF 1 described above proceeds in the following manner.
- the semiconductor die 2 is mounted on the die pad 4 , with a device forming surface of the semiconductor die 2 facing upward, and the semiconductor die 2 and the die pad 4 are adhered to each other by the use of adhesives such as gold paste and epoxy adhesive.
- the QFN 1 in this embodiment has a structure in which the die pad 4 is located at a position higher than those of the leads 5 by partially bending the die pad supports 5 b (tab-lifted structure). Accordingly, as shown in FIG. 9 , a protrusion 32 is formed on the jig 30 A at a position corresponding to the die pad 4 , which makes it possible to stably support the lead frame LF 1 . Therefore, it is possible to prevent the occurrence of defects such as deformation of the lead frame LF 1 and misalignment between the die pad 4 and the semiconductor die 2 when mounting the semiconductor die 2 on the die pad 4 .
- the bonding pads 7 on the semiconductor die 2 and the lead tips 5 a in one side of the leads 5 are connected by the gold wires 6 by the use of a well-known ball bonding apparatus.
- the stable support of the lead frame LF 1 can be achieved by forming the grooves 31 in a jig 30 B that supports the lead frame LF 1 at positions corresponding to the terminals 8 and forming the protrusion 32 on the jig 30 B at a position corresponding to the die pad 4 . Therefore, the misalignment between the gold wires 6 and the leads 5 and the misalignment between the gold wires 6 and the boding pads 7 can be prevented.
- FIG. 12 is a sectional view showing a part of the molding die 40 (area in which one QFN is formed).
- a thin resin film 41 is first laid on a surface of a lower die 40 B, and the lead frame LF 1 is placed on the resin film 41 .
- the surface of the lead frame LF 1 on which the protrusions of the terminals 8 are formed is faced downward, and then, the lead frame LF 1 is placed to contact the terminals 8 and the resin film 41 .
- the resin film 41 and the lead frame LF 1 are pressed by the upper die 40 A and the lower die 40 B.
- the terminals 8 on the lower surface of the leads 5 are pressed to the resin film 41 by the pressing force of the molding die 40 (upper die 40 A and lower die 40 B), and the tip portions of the terminals 8 are pushed into the resin film 41 .
- molten resin is injected into a space (cavity) between the upper die 40 A and the lower die 40 B to cast the molding resin, thereby forming the plastic package 3 .
- the upper die 40 A and the lower die 40 B are separated from each other, and the tip portions of the terminals 8 pushed into the resin film 41 protrude to the outside from the rear surface of the plastic package 3 .
- the width (W 1 ) of the lead 5 on which the terminal 8 is formed near the lead tip 5 a is made larger than the width (W 2 ) of the lead 5 on which the terminal 8 is formed apart form the lead tip 5 a (W 2 ⁇ W 1 ).
- the forces of the terminals 8 to press the resin film 41 become almost equal to each other in all of the leads 5 . Therefore, the lengths of the terminals 8 pushed into the resin film 41 , in other words, the heights of the tip portions of the terminals 8 protruded to the outside from the rear surface of the plastic package 3 become almost equal to each other in all of the leads 5 .
- the thickness of the lead 5 is reduced to about the half of the normal lead frame 5 . Therefore, the force of the molding die 40 (upper die 40 A and lower die 40 B) to press the lead frame LF 1 is weaker than that in the case where a normal lead frame is used. Accordingly, the force of the terminal 8 to press the resin film 41 is weaker, and thus, the height of the terminal 8 protruded to the outside of the plastic package 3 is reduced.
- the half etching is not performed to the part of the lead frame LF 1 that contacts to the upper die 40 A (enclosed by a circle in FIG. 15 ) so as to keep the thickness of the part equal to that of the terminal 8 .
- FIG. 16 is a plan view in which the positions where the upper die 40 A of the molding die 40 and the lead frame LF 1 are contacted are marked with diagonal lines.
- FIG. 17 is a plan view schematically showing the positions of gates of the molding die 40 and showing the directions of the resin flow injected into cavities.
- the upper die 40 A of the molding die 40 contacts only to the outer frame of the lead frame LF 1 and the connection parts between the leads 5 , and other areas are effectively used as cavities in which the resin is injected.
- a plurality of gates G 1 to G 16 are provided on one side of the molding die 40 , and, for example, the resin is injected through the gates G 1 and G 2 into the longitudinally arranged three cavities C 1 to C 3 on the left side of FIG. 17 .
- the resin is injected through the gates G 3 and G 4 into the three cavities C 4 to C 6 adjoining the cavities C 1 to C 3 .
- dummy cavities DC 1 to DC 8 and air vents 42 are provided on the side opposite to the gates G 1 to G 16 .
- the air in the cavities C 1 to C 3 is flown to the dummy cavity DC 1 , which makes it possible to prevent the void created in the resin in the cavity C 3 .
- FIG. 18 is a plan view of the lead frame LF 1 separated from the molding die 40 after forming the plastic packages 3 by injecting the resin into the cavities C 1 to C 18 to cast the molding resin.
- FIG. 19 is a sectional view taken along the line X-X′ in FIG. 18 .
- FIG. 20 is a plan view of the rear surface of the lead frame LF 1 .
- a solder layer ( 9 ) is formed on the surface of the terminal 8 exposed in the rear surface of the lead frame LF 1 , and then, marks such as product names and the like are printed on the surface of the plastic package 3 . Thereafter, the lead frame LF 1 and the some parts of the molding resin are cut along the dicing lines L shown in FIG. 18 . In this manner, 24 pieces of QFN 1 according to this embodiment shown in FIGS. 1 to 5 are completed.
- the thickness of the solder layer 9 formed on the surface of the terminal 8 is increased to about 50 ⁇ m.
- Such a thick solder layer 9 is formed by, for example, printing a solder paste on a surface of the terminal 8 by the use of a metal mask.
- the lead tip 5 a near the semiconductor die is extended to a position close to the die pad 4 . Therefore, it is possible to reduce the length between the lead tip 5 a near the semiconductor die and the semiconductor die 2 , and it is also possible to reduce the length of the gold wire 6 used to connect the lead tip 5 a and the semiconductor die 2 . Also, even if the terminals 8 are arranged in a zigzag pattern, the lengths of the lead tips 5 a near the semiconductor die are almost equal to each other. Therefore, the edge portions of the lead tips 5 a are substantially arranged in a row along with each of the sides of the semiconductor die 2 . Accordingly, the lengths of the gold wires 6 for connecting the lead tips 5 a near the semiconductor die and the semiconductor die 2 can be made almost equal to each other, and the gold wires 6 can have the loop forms almost equal to each other.
- the lead tip 5 a near the semiconductor die is extended to a position close to the die pad 4 , the length between the terminal 8 and the lead tip 5 a is increased. Therefore, since moisture getting into the plastic package 3 through the terminal 8 exposed to the outside of the plastic package 3 cannot easily reach the semiconductor die 2 , corrosion of the bonding pad 7 due to the moisture can be prevented. As a result, the reliability of the QFN 1 is improved.
- the lead tip 5 a near the semiconductor die is extended to a position close to the die pad 4 , even if the semiconductor die 2 is shrunk, the increase in length of the gold wires 6 is extremely small (for example, even if the semiconductor die 2 is shrunk from 4 mm square to 3 mm square, the increase in length of the gold wires 6 is about 0.7 mm on average). Therefore, it is possible to prevent the deterioration of the workability in the wire bonding process caused from the shrinkage of the semiconductor die 2 .
- the QFN manufactured by the use of the LF 1 having the small tab structure has been described in the first embodiment.
- the die support 33 is made of an insulating film.
- the lead frame LF 2 used in the second embodiment can be manufactured in the manner similar to that of the lead frame LF 1 in the first embodiment. More specifically, a metal sheet 10 with a thickness of about 125 to 150 ⁇ m as shown in FIG. 23 is prepared, and one surface of the parts of the metal sheet 10 where the leads 5 are formed is coated with the photoresist film 11 . Also, both surfaces of the parts of the metal sheet 10 , where the external connection terminals 8 are formed, are coated with the photoresist film 11 .
- the metal sheet 10 is subjected to the half etching in the same manner as described in the first embodiment, thereby forming the leads 5 with a thickness of about 65 to 75 ⁇ m and the terminals 8 with a thickness of about 125 to 150 ⁇ m simultaneously. Thereafter, the surfaces of the lead tips 5 a near the semiconductor die are plated with silver, and finally, an insulating film 33 is adhered to an upper surface of the lead tips 5 a.
- a conductive material such as a thin metal sheet can be used to constitute the chip support 33 .
- an insulation adhesive is preferably used to adhere the conductive material to the leads 5 in order to prevent the short circuit between the leads 5 .
- the thickness of the lead 5 can be reduced to about the half of the thickness of the metal sheet 10 by performing the half etching after coating one surface of the parts on the metal sheet 10 with the photoresist film 11 . Therefore, the leads 5 in which intervals between the lead tips 5 a near the semiconductor die are extremely narrow (for example, 0.18 to 0.2 mm interval) can be processed with high accuracy. In addition, by coating both surfaces of the parts on the metal sheet 10 with the photoresist film 11 , it is possible to form the protrusions of the terminals 8 simultaneously with the formation of the leads 5 .
- the lead frame LF 2 described above is different from the lead frame LF 1 used in the first embodiment in that the die pad supports 5 b for supporting the die pad 4 are unnecessary. Therefore, it is possible to give more margin for the interval between the lead tips 5 a near the semiconductor die.
- the leads 5 are supported by the chip support 33 , the length between the lead tip 5 a near the semiconductor die and the semiconductor die 2 is reduced. Therefore, it is possible to further reduce the length of the gold wires 6 .
- the chip support 33 can be supported more surely than the case where the die pad 4 is supported by the four die pad supports 5 b. Therefore, it is possible to inhibit the displacement of the chip support 33 and to prevent the short circuit between the gold wires 6 in the molding process where molten resin is injected in the molding die.
- the method of manufacturing the QFN 1 by the use of the lead frame LF 2 is almost the same as that described in the first embodiment.
- the external connection terminal 8 is constituted of the lead frame material. However, it is also possible to form the terminal in the following manner.
- a metal sheet 10 with a thickness of about 75 ⁇ m as shown in FIG. 25 is prepared, and both surfaces of the parts on the metal sheet 10 , where the die pad 4 , the leads 5 , and the die pad supports 5 b are formed, are coated with the photoresist film 11 .
- the metal sheet 10 in this state is etched to form the die pad 4 , the leads 5 , and the die supports 5 b.
- the photoresist film 11 is removed, and the surfaces of the lead tips 5 a near the semiconductor die are plated with silver. In this manner, a lead frame LF 3 is fabricated.
- This lead frame LF 3 has the same configuration as that of the lead frame LF 1 in the first embodiment except that the lead frame LF 3 does not have the external connection terminals 8 .
- the die support 33 it is possible to use the die support 33 to form the die pad of the lead frame LF 3 similar to that of the lead frame LF 2 in the second embodiment.
- dummy terminals 12 which are not used as actual terminals are formed on some parts of the lead frame LF 3 .
- the dummy terminals 12 are formed in the following manner. First, a screen-printing mask 15 is laminated on the rear surface of the lead frame LF 3 , and polyimide 12 a is printed on some parts where external connection terminals are to be formed in the later process. Thereafter, the polyimide 12 a is baked ( FIGS. 26B to 26 D).
- the dummy terminal 12 is designed to have approximately the same size as that of the actual terminal formed in the later process. Note that the case where the dummy terminal 12 is formed by printing the polyimide 12 a on the surface of the lead 5 has been described here. However, the dummy terminal 12 is not limited to this, and any materials and forming methods of the dummy terminal are available as long as it can be removed from the surface of the lead 5 in the later process.
- the semiconductor die 2 is mounted on the die pad 4 in accordance with the method described in the first embodiment, and the bonding pads 7 and the leads 5 are connected by the gold wires 6 ( FIG. 26E ).
- the semiconductor die 2 is encapsulated in the formed molding resin, thereby forming the plastic package 3 in accordance with the method described in the first embodiment.
- the tip portions of the dummy terminals 12 formed on one surface of the leads 5 are protruded to the outside from the rear surface of the plastic package 3 .
- the dummy terminals 12 are removed from the surface of the leads 5 .
- the dummy terminals 12 are formed of polyimide
- the dummy terminals 12 can be removed by dissolving it by the use of organic solution such as hydrazine.
- holes 35 are formed in the rear surface of the plastic package 3 , and parts of the surface of the leads 5 are exposed.
- a screen-printing mask 16 is laminated on the rear surface of the plastic package 3 .
- solder paste 13 a is supplied to the inside of the holes 35 as shown in FIG. 28B .
- solder paste 13 a is melted in a heating furnace. By doing so, solder bumps 13 are formed as shown in FIG. 29 .
- the solder bumps 13 are electrically connected to the leads 5 exposed in the holes 35 , and the tip portions of the solder bumps 13 protrude to the outside from the rear surface of the plastic package 3 .
- solder bumps 13 are formed by printing the solder paste 13 a on the surface of the lead 5 has been described here. However, it is also possible to form the solder bumps 13 by supplying solder balls formed in a spherical shape into the holes 35 and then performing the reflow of the solder balls.
- the process of forming the solder bumps 13 by removing the dummy terminals 12 is usually performed immediately after the completion of casting the molding resin. Thereafter, the lead frame LF 3 is cut to obtain the pieces of the QFN 1 . However, it is also possible to remove the dummy terminals 12 and form the solder bumps 13 after cutting the lead frame LF 3 into pieces of the QFN 1 .
- the terminals In the above-described manufacturing method according to this embodiment, it is possible to form the terminals with a material suitable for the application of the QFN 1 and the types of the mounting substrates in contrast to the method in which the terminals ( 8 ) are formed by the half etching of the lead frame (LF 1 ).
- the external connection terminals can also be formed in the following manner. That is, as shown in FIG. 30 , a thin metal sheet 20 with a thickness of about 75 ⁇ m is prepared, and the metal sheet 20 is etched in the same manner as that of the third embodiment, thereby fabricating a lead frame LF 4 having the die pad 4 , the leads 5 and the die pad supports 5 b (not shown in FIG. 30 ). Thereafter, a middle portion of each lead 5 is press-molded so as to have a sawtooth shape in cross section. When it is intended to adopt the structure in which a part of the die pad support 5 b is bent upward (tab-lifted structure), the bending of the die pad support 5 b and the formation of the lead 5 are preferably performed simultaneously. Note that it is also possible to form the die pad 4 , the leads 5 , and the die pad supports 5 b can be formed by the half etching or the press-molding of the thick metal sheet 10 like that used in the first embodiment.
- the semiconductor die 2 is mounted on the die pad 4 of the lead frame LF 4 , and the bonding pads 7 and the lead tips 5 a near the semiconductor die are connected by the gold wires 6 . Thereafter, the semiconductor die 2 is encapsulated in the molding resin, thereby forming the plastic package 3 . Consequently, convex portions of the leads 5 having a sawtooth shape are exposed on the rear surface of the plastic package 3 .
- the lower end portion of the leads 5 exposed on the rear surface of the plastic package 3 is polished with a device such as a grinder to cut the middle portions of the leads 5 , thereby dividing one lead 5 into several leads 5 and 5 .
- a terminal 36 is formed in each of the leads 5 and 5 obtained by dividing one lead 5 .
- the terminal 36 can be formed by the use of the printing of the conductive paste, the solder ball supply method, and the plating method.
- the process for forming the terminals 36 is usually performed immediately after the completion of the plastic package 3 by casting the molding resin. Thereafter, the lead frame LF 4 is cut to obtain the pieces of the QFN 1 .
- the solder terminals 36 after cutting the lead frame LF 4 into pieces of the QFN 1 .
- the method of forming a terminal when using the method of forming a terminal according to this embodiment, it is possible to form a plurality of lead tips by cutting the lead 5 in the following manner. That is, a wide lead 5 as shown in FIG. 34 provided with lead tips 5 a at alternate positions apart from the semiconductor die 2 and near the semiconductor die 2 is formed, and the gold wires are bonded to the lead tips 5 a of the lead 5 . Thereafter, the middle portion of the lead 5 is polished and cut as shown in FIG. 35 . According to this method, the intervals between the adjoining lead tips 5 a can be substantially eliminated. Therefore, it is possible to greatly increase the number of terminals in the QFN 1 .
- FIG. 36 is a plan view of a part of a lead frame LF 5 used in the manufacture of the QFN.
- FIG. 37 is a plan view of an internal structure (main surface side) of the QFN manufactured by the use of the lead frame LF 5 .
- the lead frame LF 5 in this embodiment has a structure in which lengths of a plurality of tips of the leads 5 (lead tips 5 a ) surrounding the die pad 4 are alternately changed. Also, in the case of using this lead frame LF 5 , a semiconductor die 2 on which two lines of the bonding pads 7 are arranged along each of the sides of the main surface thereof in a zigzag pattern is used as the semiconductor die 2 to be mounted on the die pad 4 .
- the bonding pad 7 in a line closer to the edge of the semiconductor die 2 is connected to the lead 5 having longer tip portion by the shorter gold wire 6 having a lower loop
- the bonding pad 7 in an inner line of the semiconductor die 2 is connected to the lead 5 having shorter tip portion by the longer gold wire 6 having a higher loop as shown in FIG. 38 .
- the above-described lead frame LF 5 can be used even in the case where the semiconductor chip 2 on which the bonding pads 7 are arranged in a line is mounted.
- the shape of the die pad 4 on which the semiconductor die 2 is mounted is not limited to a circular shape, and it is possible to use the die pad 4 having a structure in which the width of the die pad 4 is larger than that of the die pad supports 5 b (so-called cross tab structure) like in a lead frame LF 6 shown in FIG. 40 and a lead frame LF 7 shown in FIG. 41 . In this case, as shown in FIG.
- adhesive 14 is applied to several parts on the die pad 4 and the semiconductor die 2 is adhered thereon, by which the displacement in the rotating direction of the semiconductor die 2 can be effectively prevented.
- the relative location accuracy between the die pad 4 and the semiconductor die 2 is improved.
- the width of the die pad 4 substantially functioning as a part of the die pad support 5 b is large, the advantage of the improvement in the strength of the die pad support 5 b can be obtained. Note that it is needless to say that the die pad 4 of the cross tab structure can mount several types of semiconductor dies 2 with different sizes.
- the terminals of the QFN can be formed in the following manner. First, as shown in FIG. 42A , the lead frame LF 3 , for example, fabricated in the same manner as described in the third embodiment shown in FIG. 25 is prepared. Subsequently, as shown in FIGS. 42B to 42 D, a screen-printing mask 17 is laminated on a rear surface of the lead frame LF 3 , and copper paste 18 is printed on the parts where the terminals are to be formed. Then, the copper paste 18 a are baked. In this manner, copper terminals 18 are formed.
- the semiconductor die 2 is mounted on the die pad 4 in accordance with the method described in the first embodiment, and the bonding pads 7 and the leads 5 are connected by the gold wires 6 .
- the semiconductor die 2 is encapsulated in the formed molding resin, thereby forming the plastic package 3 in accordance with the method described in the first embodiment. Consequently, tip portions of the copper terminals 18 formed on one surface of the leads 5 are protruded to the outside from the rear surface of the plastic package 3 .
- plating of tin and gold may be performed on the surface of the copper terminals 18 by the use of the electroless plating method if necessary.
- FIG. 44 shows an example of the QFN 1 in which the lead tips 5 a of the leads 5 (near the semiconductor die 2 ) are bent upward.
- the difference in height between the lead tips 5 a of the leads 5 and the main surface of the semiconductor die 2 is reduced, and the loop height of the gold wires 6 that connect the leads 5 and the bonding pads 7 can be lowered. Therefore, it is possible to reduce the thickness of the plastic package 3 in proportion to the reduction.
- FIG. 45 shows an example of the QFN 1 in which the lead tips 5 a of the leads 5 are bent upward so that the height of the die pad 4 is made equal to those of the lead tips 5 a of the leads 5 , and the semiconductor die 2 is mounted on the lower surface of the die pad 4 by using the face down bonding.
- the thickness of the resin between the upper surfaces of the lead tips 5 a of the leads 5 and the die pad 4 and that of the plastic package 3 can be made extremely thin. Therefore, an ultra-thin type QFN having the plastic package 3 with a thickness of 0.5 mm can be realized.
- the above-described method in which the lead tips 5 a of the leads 5 are bent upward can be applied to the case where the lead frame LF 2 in which the die support 33 made from an insulating film is adhered to the lead tips 5 a of the leads 5 is used.
- the die support 33 and the semiconductor die 2 are adhered via an adhesive 19 formed on, for example, one surface of the die support 33 . Also in this case, it is possible to reduce the thickness of the plastic package 3 because of the reasons described above.
- FIGS. 48 and 49 show an example in which the die support is constituted by the use of a heat spreader 23 made of a material with high heat conductivity such as Cu and Al. Since the heat spreader 23 also functions as the die support, it is possible to realize the QFN having good heat radiation characteristics. In addition, in the case where the die support is constituted by the use of the heat spreader 23 , it is possible to expose one surface of the heat spreader 23 on the surface of the plastic package 3 as shown in FIG. 50 . By doing so, the heat radiation characteristics of the QFN can be further improved.
- this embodiment is applied to the QFN having the terminals 8 formed by the half etching of the lead frame.
- the application is not limited to this, and this embodiment can be applied to the various QFN having the terminals formed in accordance with the various methods described above.
- FIG. 51 is a plan view of a part of a lead frame LF 8 used in the manufacture of the QFN.
- FIG. 52 is a plan of an outward appearance (rear surface side) of the QFN manufactured by the use of the lead frame LF 8 .
- the interval between the terminals 8 becomes extremely narrow. Therefore, if it is intended to make the width of the terminal 8 larger than that of the lead 5 like in the lead frame LF 1 used in the first embodiment, the process of the lead frame becomes extremely difficult.
- the width of the terminals 8 is 0.15 to 0.18 mm, and the interval P 1 between the adjoining terminals 8 in the same line is 0.5 mm, and the interval P 2 between the interstitial terminals in different lines is 0.25 mm.
- the width of the terminal 8 becomes narrower, the size of the contact area between the terminal 8 and the mounting substrate is reduced, and thus, the connection reliability is deteriorated. Therefore, as compensation means thereof, it is desirable that the length of the terminal 8 is increased to prevent the reduction in size of the contact area. In addition, since the width of the lead 5 becomes narrower, the strength of the lead 5 is also reduced. Therefore, it is desirable that the die support 33 is adhered to the tip of the lead 5 and supports the lead 5 for the prevention of the deformation of the lead 5 .
- the die support 33 can be provided in the middle portion of the lead 5 as shown in FIG. 53 .
- FIGS. 54 and 55 the structure of the lead frame LF 8 in which the width of the terminal 8 and that of the lead 5 are made equal to each other can be of course applied to a lead frame not having the die support 33 .
- the lead frame LF 1 before dicing may be warped or deformed due to the difference in the thermal expansion coefficient between the lead frame LF 1 and the molding resin.
- the QFN 1 with high heat radiation characteristics by forming the die pad 4 exposed on the rear surface of the plastic package 3 as shown in FIG. 57 .
- the thin die pad 4 , the thin leads 5 and the thin die pad supports 5 b are formed by the half etching of the thick metal sheet 10 in the first embodiment.
- the strength of the die pad supports 5 b becomes insufficient in some cases when a relatively large semiconductor die 2 is mounted on the thin die pad supports 5 b.
- the connection reliability between the QFN 1 and the wiring board and the heat radiation characteristics of the QFN 1 can be improved by soldering the exposed portion to the wiring board.
- the molding method in which the resin film 41 is interposed between the molding die 40 (upper die 40 A and lower die 40 B) is used to form the plastic package 3 .
- a part of the terminal 8 or the entire of the terminal 8 is covered with the resin in some cases as shown in FIGS. 60A and 60B when the plastic package 3 is separated from the molding die 40 . Therefore, it is required to remove the resin burr on the surface of the terminal 8 by the use of a burr removal means 37 such as a grinder as shown in FIG. 61 , and then, the metal layer is formed on the surface of the terminal 8 by the above-described printing method and the electroplating method.
- a semiconductor device comprising: a semiconductor die; a die pad on which the semiconductor die is mounted; a plurality of leads arranged around the semiconductor die; a plurality of wires for electrically connecting the semiconductor die and the leads; and a plastic package for encapsulating the semiconductor die, the die pad, the plurality of leads, and the plurality of wires,
- the plurality of leads are formed so that intervals between the lead tips on one side near the semiconductor die are narrower than those between the lead tips on the other side opposite to the one side, and
- a terminal protruded from a rear surface of the plastic package to the outside is selectively provided to each of the plurality of leads.
- terminal is constituted of a part of the lead protruded from the rear surface of the plastic package to the outside.
- the terminal is made of a conductive material which is different from that of the lead.
- terminals are arranged in two lines along each side of the plastic package in a zigzag pattern.
- leads on which the terminals are arranged closer to the one side have a width larger than that of leads on which the terminals are arranged closer to the other side.
- die pad is supported by a plurality of die pad supports.
- a semiconductor device comprising: a semiconductor die; a die pad support having a film shape on which the semiconductor die is mounted; a plurality of leads arranged around the semiconductor die; a plurality of wires for electrically connecting the semiconductor die and the leads; and a plastic package for encapsulating the semiconductor die, the die pad support, the plurality of leads, and the plurality of wires,
- the plurality of leads are formed so that intervals between the lead tips on one side near the semiconductor die are narrower than those between the lead tips on the other side opposite to the one side, and
- a terminal protruded from a rear surface of the plastic package to the outside is electrically connected to each of the plurality of leads.
- die pad support is supported by the plurality of leads.
- a method of manufacturing a semiconductor device which comprises: a semiconductor die; a die pad on which the semiconductor die is mounted; a plurality of leads arranged around the semiconductor die; a plurality of wires for electrically connecting the semiconductor die and the leads; and a plastic package for encapsulating the semiconductor die, the die pad, the plurality of leads, and the plurality of wires,
- step (a) includes the step of coating a part of a metal sheet with a photoresist film, and performing etching of parts of the metal sheet not coated with the photoresist film, thereby forming the plurality of leads, the die pad, and the terminals.
- the plurality of leads are formed so that intervals between the lead tips on one side near the die pad are narrower than those between the lead tips on the other side opposite to the one side.
- the terminal formed in the step (a) is a dummy terminal
- the method further comprises the steps of: removing the dummy terminal; and forming a terminal whose tip portion is protruded to the outside of the plastic package on a surface of the lead in the area where the dummy terminal has been removed.
- slits are provided in an outer frame of the lead frame.
- terminals are arranged in two lines along each side of the plastic package in a zigzag pattern.
- a lead on which the terminal is arranged closer to the die pad has a width larger than that of a lead on which the terminal is arranged apart from the die pad.
- a jig to support the lead frame in the step (b) is provided with grooves at positions corresponding to the tip portions of the terminals.
- the upper molding die of the molding die used in the step (c) contacts to an outer frame part of the lead frame and to a connection part between the leads, and spaces other than those are used as cavities into which the resin is injected.
- bonding pads formed on a main surface of the semiconductor die are arranged in two lines along each side of the semiconductor die in a zigzag pattern.
- lead tips of the plurality of leads on the one side are bent in a thickness direction of the plastic package.
- a diameter of the terminal is larger than a width of the lead.
- a diameter of the terminal is equal to a width of the lead.
- the die support is a heat spreader
Abstract
Description
- This application is a Divisional application of U.S. application Ser. No. 10/878,269, filed Jun. 29, 2004, which is, in turn, a Divisional application of U.S. application Ser. No. 10/299,768, filed Nov. 20, 2002; and the entire disclosures of which are hereby incorporated by reference.
- The present invention relates to a semiconductor device and a manufacturing method of the same. More particularly, the present invention relates to a technique effectively applicable to the increase of the number of pins used in a resin-encapsulated semiconductor device.
- A QFN (Quad Flat Non-leaded package) can be taken as an example of a resin package in which a semiconductor die mounted on a lead frame is encapsulated in a plastic package made of molding resin.
- In the QFN, tip portions of a plurality of leads electrically connected to a semiconductor die via bonding wires are exposed from a rear surface (lower surface) of a peripheral part of a plastic package, by which terminals are formed. Also, bonding wires are connected to the surfaces opposite to the surfaces on which the terminals are exposed. More specifically, bonding wires are connected to the terminal surfaces inside the plastic package, by which the terminals and the semiconductor die are electrically connected to each other. The QFN is mounted on a wiring board by soldering these terminals to electrodes (footprint) on the wiring board. This structure of the QFN enables to obtain the advantage that the size of the mounting area can be reduced in comparison to a QFP (Quad Flat Package) in which the leads transversely extending from the side surfaces of a package (plastic package) constitute the terminals.
- The descriptions of the QFN can be found in Japanese Patent Laid-Open No. 2001-189410 (corresponding U.S. Pat. No. 6,399,423) and Japanese Patent No. 3072291.
- However, when the number of terminals is increased (increase of the number of pins) in accordance with the increasing advancement and higher performance of an LSI formed on the semiconductor die, the following problems arise in the QFN.
- That is, since the bonding wires are connected to the surfaces opposite to terminal surfaces exposed on the rear surface of the plastic package as described above, the interval between the terminals is equal to the interval between the tip portions of the leads at which the bonding wires are connected. In addition, since a predetermined size of the terminal is necessary to ensure the reliability of the mounting, it is impossible to reduce the size too much.
- Therefore, when it is intended to increase the number of pins without changing the size of the package, it is impossible to largely increase the number of terminals. Thus, it is impossible to largely increase the number of pins. Meanwhile, in the case where the size of the package is increased in order to increase the number of pins, the length between the semiconductor die and the position at which the bonding wire is connected becomes wider, and thus, the length of the bonding wire becomes longer. Therefore, the problem arises, that is, the adjoining wires are short-circuited in the wire bonding process and the resin molding process. As a result, the manufacturing yield is lowered.
- Moreover, in the case where the semiconductor die is shrunk with an aim to reduce the manufacturing cost, the length between the semiconductor die and the position at which the bonding wire is connected becomes greater. As a result, a problem arises in that the connection by the use of the bonding wire cannot be made.
- An object of the present invention is to provide a technique capable of achieving the increase of the number of pins in a QFN.
- Another object of the present invention is to provide a technique to obtain a QFN which is adapted to deal with a reduction in die size.
- The above and other objects and novel characteristics of the present invention will be apparent from the description and the accompanying drawings of this specification.
- Typical ones of the inventive aspects disclosed in this application will be briefly described as follows.
- A semiconductor device according to the present invention includes: a semiconductor die; a die pad on which the semiconductor die is mounted; a plurality of leads arranged around the semiconductor die; a plurality of wires for electrically connecting the semiconductor die and the leads; and a plastic package for encapsulating the semiconductor die, the die pad, the plurality of leads, and the plurality of wires, wherein the plurality of leads are formed so that intervals between lead tips on one side near the semiconductor die are narrower than those between leads tips on the other side opposite to the one side, and a terminal protruded from a rear surface of the plastic package to the outside is selectively provided to each of the plurality of leads.
- A method of manufacturing a semiconductor device according to the present invention includes the steps of:
- (a) preparing a lead frame on which patterns including the die pad and the plurality of leads are successively formed, and a terminal protruded in a direction perpendicular to a surface of the lead is formed on each surface of the plurality of leads;
- (b) mounting a semiconductor die on each of the plurality of die pads formed on the lead frame, and connecting the semiconductor die and the parts of the leads by the use of wires;
- (c) preparing a molding die having an upper die and a lower die, coating a surface of the lower die with a resin film, and then, mounting the lead frame on the resin film, thereby bringing the terminal formed on the surface of the lead into contact with the resin film;
- (d) pressing the resin film and the lead frame with the upper die and the lower die to push tip portions of the terminals into the resin film;
- (e) injecting resin into spaces between the upper and lower dies, thereby encapsulating the semiconductor die, the die pad, the leads, and the wires, and separating the lead frame from the molding die after forming a plurality of plastic packages in which the tip portions of the terminals are protruded to the outside; and
- (f) dicing the lead frame to obtain pieces of plastic packages.
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FIG. 1 is a plan view of an outward appearance (main surface side) of a semiconductor device according to an embodiment of the present invention; -
FIG. 2 is a plan view of an outward appearance (rear surface side) of a semiconductor device according to an embodiment of the present invention; -
FIG. 3 is a plan view of an internal structure (main surface side) of a semiconductor device according to an embodiment of the present invention; -
FIG. 4 is a plan view of an internal structure (rear surface side) of a semiconductor device according to an embodiment of the present invention; -
FIG. 5 is a sectional view of a semiconductor device according to an embodiment of the present invention; -
FIG. 6 is a plan view showing the entire lead frame used in the manufacture of a semiconductor device according to an embodiment of the present invention; -
FIG. 7 is a sectional view of the principal part of the lead frame shown inFIG. 6 for illustrating the manufacturing method of the same; -
FIG. 8 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 9 is a sectional view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 10 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 11 is a sectional view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 12 is a sectional view of the principal part of a lead frame and a molding die for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 13 is a sectional view of the principal part of a lead frame and a molding die for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 14 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 15 is a sectional view of the principal part of a lead frame and a molding die for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 16 is a plan view showing the positions where the lead frame contacts to an upper die of the molding die used in the manufacture of a semiconductor device according to an embodiment of the present invention; -
FIG. 17 is a plan view schematically showing the flowing directions of resin injected in cavities and the positions of gates of the molding die used in the manufacture of a semiconductor device according to an embodiment of the present invention; -
FIG. 18 is a plan view (main surface side) showing the entire lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 19 is a sectional view of a lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 20 is a plan view (rear surface side) showing the entire lead frame for illustrating the manufacturing method of a semiconductor device according to an embodiment of the present invention; -
FIG. 21 is a plan view of the principal part of a lead frame used in the manufacture of a semiconductor device according to another embodiment of the present invention; -
FIG. 22 is a sectional view of the principal part of a lead frame used in the manufacture of a semiconductor device according to another embodiment of the present invention; -
FIG. 23 is a sectional view of the principal part of a lead frame for illustrating the manufacturing method of a lead frame used in the manufacture of a semiconductor device according to another embodiment of the present invention; -
FIG. 24 is a sectional view for illustrating the manufacturing method of a semiconductor device by the use of the lead frame shown inFIGS. 21 and 22 ; -
FIG. 25 is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 26A is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 26B is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 26C is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 26D is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 26E is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 27A is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 27B is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 28A is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 28B is a sectional view of the principal part in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 29 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 30 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 31 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 32 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 33 is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 34 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 35 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 36 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 37 is a plan view of an internal structure (main surface side) of a semiconductor device according to another embodiment of the present invention; -
FIG. 38 is an explanatory diagram for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 39 is a plan view of the principal part of a lead frame for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 40 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 41 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 42A is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 42B is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 42C is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 42D is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 42E is a sectional view of the principal part of a semiconductor device for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 43 is a sectional view for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 44 is a sectional view of a semiconductor device according to another embodiment of the present invention; -
FIG. 45 is a sectional view of a semiconductor device according to another embodiment of the present invention; -
FIG. 46 is a sectional view of a semiconductor device according to another embodiment of the present invention; -
FIG. 47 is a sectional view of a semiconductor device according to another embodiment of the present invention; -
FIG. 48 is a sectional view of a semiconductor device according to another embodiment of the present invention; -
FIG. 49 is a sectional view of a semiconductor device according to another embodiment of the present invention; -
FIG. 50A is a sectional view of a semiconductor device according to another embodiment of the present invention; -
FIG. 50B is a sectional view of a semiconductor device according to another embodiment of the present invention; -
FIG. 51 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 52 is a plan view of an outward appearance (rear surface side) of a semiconductor device according to another embodiment of the present invention; -
FIG. 53 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 54 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 55 is a plan view of the principal part of a lead frame used in the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 56 is a plan view of the principal part of a lead frame used in the manufacture of a semiconductor device according to another embodiment of the present invention; -
FIG. 57 is a sectional view of a semiconductor device according to another embodiment of the present invention; -
FIG. 58 is a plan view of an internal structure (rear surface side) of a semiconductor device according to another embodiment of the present invention; -
FIG. 59 is a sectional view of the principal part of a molding die for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention; -
FIG. 60A is a partially enlarged sectional view of a plastic package separated from a molding die; -
FIG. 60B is a partially enlarged sectional view of a plastic package separated from a molding die; and -
FIG. 61 is a sectional view for illustrating the manufacturing method of a semiconductor device according to another embodiment of the present invention. - Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
-
FIG. 1 is a plan view showing an outward appearance (main surface side) of a QFN according to this embodiment,FIG. 2 is a plan view showing an outward appearance (rear surface side) of the QFN,FIG. 3 is a plan view showing an internal structure (main surface side) of the QFN,FIG. 4 is a plan view showing an internal structure (rear surface side) of the QFN, andFIG. 5 is a sectional view of the QFN. - The
QFN 1 according to this embodiment is a surface mounting type package in which one semiconductor die 2 is encapsulated in aplastic package 3, and has dimensions of, for example,length 12 mm,width 12 mm, and thickness 1.0 mm. - The semiconductor die 2 is mounted on a
metal die pad 4 and is arranged at the center of theplastic package 3. The semiconductor die 2 has a size of 4 mm on a side. Thedie pad 4 has a diameter smaller than that of the semiconductor die 2 (so called small tab structure) so as to enable the mounting of various types of semiconductor dies 2 with a size of 4 to 7 mm on a side. In this embodiment, the diameter of thedie pad 4 is 3 mm. Thedie pad 4 is supported by four die pad supports 5 b extending to the four corners of theplastic package 3. The die pad supports 5 b are formed integrally with thedie pad 4. - A plurality of (for example, 116) leads 5 made of the same metal as the
die pad 4 and the die pad supports 5 b are arranged around thedie pad 4 so as to surround the same. Leadtip 5 a of the lead 5 (on the side near the semiconductor die 2) is electrically connected to abonding pad 7 on the main surface of the semiconductor die 2 via agold wire 6, andlead tip 5 c of the lead 5 (near the package edge) is ended at a side surface of theplastic package 3. - Each of the
lead tips 5 a near the semiconductor die is extended to a position close to thedie pad 4 so as to reduce the length between the semiconductor die 2 and theleads 5, and the interval (P3) between the tip portions of theleads 5 is narrow (0.18 mm to 0.2 mm). Therefore, the interval between adjoininglead tips 5 a near the semiconductor die is smaller than the interval between adjoininglead tips 5 c near the package edge. The leads 5 formed in the above-described shape make it possible to reduce the length of thegold wires 6 that connect thelead tips 5 a near the semiconductor die and the bonding pads 7 (in this embodiment, 3 mm or shorter). Therefore, even if the number of pins in use is increased, and even if the interval between theleads 5 or the interval between thegold wires 6 is narrowed with the increase of the number of pins in use, it is possible to reduce the occurrence of defects such as a short-circuit between thegold wires 6 in the manufacturing process of the QFN 1 (for example, wire bonding process and resin molding process). - As shown in
FIG. 2 , a plurality of (for example, 116)external connection terminals 8 are provided on a rear surface (substrate mounting surface) of theQFN 1. Theseterminals 8 are arranged in two lines along each of the sides of theplastic package 3 in a zigzag pattern, and each of the tip portions of theterminals 8 is exposed from the rear surface of theplastic package 3 and protruded to the outside. The diameter (d) of theterminal 8 is 0.3 mm. The interval (P1) between the adjoiningterminals 8 in the same line is 0.65 mm, and the interval (P2) between the interstitial terminals in different lines is 0.325 mm. - The
terminal 8 in this embodiment is formed integrally with thelead 5, and the thickness of theterminal 8 is about 125 to 150 μm. In addition, the thickness of the part of thelead 5 other than theterminal 8, more specifically, the thickness of thelead tip 5 a near the semiconductor die and that of thelead tip 5 c near the package edge are about 65 to 75 μm. Also, at a tip portion of theterminal 8 protruded to the outside of theplastic package 3, asolder layer 9 is deposited by an electroplating method or a printing method. TheQFN 1 in this embodiment is mounted by soldering theterminals 8 to electrodes (footprint) on a wiring board. - Next, the method of manufacturing the above-described
QFN 1 will be described. First, a lead frame LF1 as shown inFIG. 6 is prepared. The lead frame LF1 is a metal sheet made of Cu, Cu alloy, or Fe—Ni alloy, in which above-described patterns such as diepads 4, leads 5, die pad supports 5 b, and the like are successively formed laterally and longitudinally. More specifically, the lead frame LF1 has a structure in which a plurality of (for example, 24) semiconductor dies are successively mounted. - The lead frame LF1 is manufactured in the following manner. That is, a
metal sheet 10 made of Cu, Cu alloy, or Fe—Ni alloy with a thickness of about 125 to 150 μm as shown inFIG. 7 is prepared, and one surface of the parts on themetal sheet 10 where thedie pad 4, theleads 5, and the die pad supports 5 b are formed is coated with aphotoresist film 11. Also, both surfaces of the parts on themetal sheet 10 where theexternal connection terminals 8 are formed are coated with thephotoresist film 11. Then, themetal sheet 10 in this state is etched by the use of etching solution, and the thickness of themetal sheet 10 whose one surface is coated with thephotoresist film 11 is reduced to about a half (65 to 75 μm) (half etching). By the etching performed in this manner, the parts of themetal sheet 10 not coated with thephotoresist film 11 on both faces are completely removed, and thedie pad 4, theleads 5, and the die pad supports 5 b each having a thickness of about 65 to 75 μm are formed on the parts of themetal sheet 10 whose one surface is coated with thephotoresist film 11. Also, since the portions of themetal sheet 10 whose both surfaces are coated with thephotoresist film 11 are not etched by the etching solution, protrusions to be theterminals 8 with the same thickness (125 to 150 μm) as that before the etching are formed in the parts. - Subsequently, the
photoresist film 11 is removed, and then, the surfaces of thelead tips 5 a near the semiconductor die are plated with silver. By doing so, the lead frame LF1 shown inFIG. 6 is completed. Note that, instead of the silver plating to thelead tips 5 a near the semiconductor die, the palladium (Pd) plating to the entire surface of the lead frame LF1 is also available. Since a thickness of a plated layer by the palladium plating is thinner in comparison to that by the silver plating, it is possible to improve the bondability between theleads 5 and thegold wires 6. In addition, the plating on the entire surface of the lead frame LF1 forms a plated layer also on the surface of theterminals 8. Therefore, it is possible to reduce the number of the plating processes. - As described above, the half etching is performed after coating, with the
photoresist film 11, one surface of the parts of themetal sheet 10 to be a base material of the lead frame LF1, and the thickness of thelead 5 is reduced to about half of the thickness of themetal sheet 10. In this manner, theleads 5 in which intervals between thelead tips 5 a on one side are extremely narrow (in this embodiment, 0.18 to 0.2 mm interval) can be processed with high accuracy. In addition, by coating both surfaces of the parts of themetal sheet 10 with thephotoresist film 11, it is possible to form theterminals 8 simultaneously with the formation of thedie pad 4, theleads 5, and the die pad supports 5 b. - Next, the manufacturing process of the
QFN 1 using the lead frame LF1 described above proceeds in the following manner. First, as shown inFIGS. 8 and 9 , the semiconductor die 2 is mounted on thedie pad 4, with a device forming surface of the semiconductor die 2 facing upward, and the semiconductor die 2 and thedie pad 4 are adhered to each other by the use of adhesives such as gold paste and epoxy adhesive. - In this process, since there are protrusions of
terminals 8 on the rear surface of the lead frame LF1, it is preferable to formgrooves 31 in ajig 30A that supports the lead frame LF1 at positions corresponding to the protrusions of theterminals 8 as shown inFIG. 9 . By doing so, it is possible to stably support the lead frame LF1. Therefore, it is possible to prevent the occurrence of defects such as deformation of the lead frame LF1 and misalignment between thedie pad 4 and the semiconductor die 2 when mounting the semiconductor die 2 on thedie pad 4. - Also, in order to allow the resin to flow uniformly in both the upper surface side and the lower surface side of the semiconductor die 2 mounted on a molding die during the resin molding, the
QFN 1 in this embodiment has a structure in which thedie pad 4 is located at a position higher than those of theleads 5 by partially bending the die pad supports 5 b (tab-lifted structure). Accordingly, as shown inFIG. 9 , aprotrusion 32 is formed on thejig 30A at a position corresponding to thedie pad 4, which makes it possible to stably support the lead frame LF1. Therefore, it is possible to prevent the occurrence of defects such as deformation of the lead frame LF1 and misalignment between thedie pad 4 and the semiconductor die 2 when mounting the semiconductor die 2 on thedie pad 4. - Next, as shown in
FIGS. 10 and 11 , thebonding pads 7 on the semiconductor die 2 and thelead tips 5 a in one side of theleads 5 are connected by thegold wires 6 by the use of a well-known ball bonding apparatus. Also in this case, as shown inFIG. 11 , the stable support of the lead frame LF1 can be achieved by forming thegrooves 31 in ajig 30B that supports the lead frame LF1 at positions corresponding to theterminals 8 and forming theprotrusion 32 on thejig 30B at a position corresponding to thedie pad 4. Therefore, the misalignment between thegold wires 6 and theleads 5 and the misalignment between thegold wires 6 and theboding pads 7 can be prevented. - Subsequently, the lead frame LF1 is mounted on a
molding die 40 shown inFIG. 12 , and then, the semiconductor die 2 is resin-encapsulated.FIG. 12 is a sectional view showing a part of the molding die 40 (area in which one QFN is formed). - In this resin encapsulation of the semiconductor die 2 using the molding die 40, a
thin resin film 41 is first laid on a surface of alower die 40B, and the lead frame LF1 is placed on theresin film 41. In this case, the surface of the lead frame LF1 on which the protrusions of theterminals 8 are formed is faced downward, and then, the lead frame LF1 is placed to contact theterminals 8 and theresin film 41. In this state, theresin film 41 and the lead frame LF1 are pressed by theupper die 40A and thelower die 40B. By doing so, as shown inFIG. 12 , theterminals 8 on the lower surface of theleads 5 are pressed to theresin film 41 by the pressing force of the molding die 40 (upper die 40A and lower die 40B), and the tip portions of theterminals 8 are pushed into theresin film 41. - Subsequently, as shown in
FIG. 13 , molten resin is injected into a space (cavity) between theupper die 40A and thelower die 40B to cast the molding resin, thereby forming theplastic package 3. Thereafter, theupper die 40A and thelower die 40B are separated from each other, and the tip portions of theterminals 8 pushed into theresin film 41 protrude to the outside from the rear surface of theplastic package 3. - Note that, when pressing the upper surface of the lead frame LF1 by the
upper die 40A, an upward force works on thelead tips 5 a, which are tip portions on one side of theleads 5, due to the spring force of the metal sheet that constitutes the lead frame LF1. Therefore, if theterminals 8 are arranged in two lines like in the lead frame LF1 in this embodiment, the force of theterminal 8 to press theresin film 41 differs between thelead 5 in which theterminal 8 is formed near thelead tip 5 a and thelead 5 in which theterminal 8 is formed apart from thelead tip 5 a. More specifically, the force to press theresin film 41 of theterminal 8 formed near thelead tip 5 a is weaker in comparison that of theterminal 8 formed apart form thelead tip 5 a (=near the contact portion between theupper die 40A and the lead 5). As a result, there is a difference in height between the terminal 8 formed near thelead tip 5 a and protruded from the rear surface of theplastic package 3 and theterminal 8 formed apart from thelead tip 5 a. If theseterminals 8 are soldered to the electrodes (footprint) on the wiring board, the difference in height may cause the open defect in which someterminals 8 and the electrodes are not contacted. - For the solution of the problem, as shown in
FIG. 14 , the width (W1) of thelead 5 on which theterminal 8 is formed near thelead tip 5 a is made larger than the width (W2) of thelead 5 on which theterminal 8 is formed apart form thelead tip 5 a (W2<W1). By doing so, the forces of theterminals 8 to press theresin film 41 become almost equal to each other in all of theleads 5. Therefore, the lengths of theterminals 8 pushed into theresin film 41, in other words, the heights of the tip portions of theterminals 8 protruded to the outside from the rear surface of theplastic package 3 become almost equal to each other in all of theleads 5. - Also, as described above, since the patterns (die
pad 4,lead 5, diepad support 5 b and the like) in the lead frame LF1 used in this embodiment are formed by the half etching, the thickness of thelead 5 is reduced to about the half of thenormal lead frame 5. Therefore, the force of the molding die 40 (upper die 40A andlower die 40B) to press the lead frame LF1 is weaker than that in the case where a normal lead frame is used. Accordingly, the force of theterminal 8 to press theresin film 41 is weaker, and thus, the height of theterminal 8 protruded to the outside of theplastic package 3 is reduced. - When it is intended to increase the height of the
terminal 8 protruded to the outside of theplastic package 3, the half etching is not performed to the part of the lead frame LF1 that contacts to theupper die 40A (enclosed by a circle inFIG. 15 ) so as to keep the thickness of the part equal to that of theterminal 8. -
FIG. 16 is a plan view in which the positions where theupper die 40A of the molding die 40 and the lead frame LF1 are contacted are marked with diagonal lines. Also,FIG. 17 is a plan view schematically showing the positions of gates of the molding die 40 and showing the directions of the resin flow injected into cavities. - As shown in
FIG. 16 , theupper die 40A of the molding die 40 contacts only to the outer frame of the lead frame LF1 and the connection parts between theleads 5, and other areas are effectively used as cavities in which the resin is injected. - In addition, as shown in
FIG. 17 , a plurality of gates G1 to G16 are provided on one side of the molding die 40, and, for example, the resin is injected through the gates G1 and G2 into the longitudinally arranged three cavities C1 to C3 on the left side ofFIG. 17 . The resin is injected through the gates G3 and G4 into the three cavities C4 to C6 adjoining the cavities C1 to C3. Meanwhile, on the side opposite to the gates G1 to G16, dummy cavities DC1 to DC8 andair vents 42 are provided. For example, when the resin is injected through the gates G1 and G2 into the cavities C1 to C3, the air in the cavities C1 to C3 is flown to the dummy cavity DC1, which makes it possible to prevent the void created in the resin in the cavity C3. -
FIG. 18 is a plan view of the lead frame LF1 separated from the molding die 40 after forming theplastic packages 3 by injecting the resin into the cavities C1 to C18 to cast the molding resin.FIG. 19 is a sectional view taken along the line X-X′ inFIG. 18 .FIG. 20 is a plan view of the rear surface of the lead frame LF1. - Next, a solder layer (9) is formed on the surface of the
terminal 8 exposed in the rear surface of the lead frame LF1, and then, marks such as product names and the like are printed on the surface of theplastic package 3. Thereafter, the lead frame LF1 and the some parts of the molding resin are cut along the dicing lines L shown inFIG. 18 . In this manner, 24 pieces ofQFN 1 according to this embodiment shown in FIGS. 1 to 5 are completed. Note that, in the case where it is desired to increase the space between theQFN 1 and the wiring board when mounting theQFN 1 on the wiring board, more specifically, in the case where it is desired to increase the standoff of theQFN 1, the thickness of thesolder layer 9 formed on the surface of theterminal 8 is increased to about 50 μm. Such athick solder layer 9 is formed by, for example, printing a solder paste on a surface of theterminal 8 by the use of a metal mask. - As described above, in the
QFN 1 according to this embodiment, thelead tip 5 a near the semiconductor die is extended to a position close to thedie pad 4. Therefore, it is possible to reduce the length between thelead tip 5 a near the semiconductor die and the semiconductor die 2, and it is also possible to reduce the length of thegold wire 6 used to connect thelead tip 5 a and the semiconductor die 2. Also, even if theterminals 8 are arranged in a zigzag pattern, the lengths of thelead tips 5 a near the semiconductor die are almost equal to each other. Therefore, the edge portions of thelead tips 5 a are substantially arranged in a row along with each of the sides of the semiconductor die 2. Accordingly, the lengths of thegold wires 6 for connecting thelead tips 5 a near the semiconductor die and the semiconductor die 2 can be made almost equal to each other, and thegold wires 6 can have the loop forms almost equal to each other. - As a result, it is possible to prevent the defects that the adjoining
gold wires 6 are short circuited and that the adjoininggold wires 6 are crossed to each other in the vicinity of the four corners of the semiconductor die 2. Therefore, the workability in the wire bonding process can be improved. In addition, since it is possible to reduce the intervals between the adjoininggold wires 6, the number of pins used in theQFN 1 can be increased. - Also, since the
lead tip 5 a near the semiconductor die is extended to a position close to thedie pad 4, the length between the terminal 8 and thelead tip 5 a is increased. Therefore, since moisture getting into theplastic package 3 through theterminal 8 exposed to the outside of theplastic package 3 cannot easily reach the semiconductor die 2, corrosion of thebonding pad 7 due to the moisture can be prevented. As a result, the reliability of theQFN 1 is improved. - Also, since the
lead tip 5 a near the semiconductor die is extended to a position close to thedie pad 4, even if the semiconductor die 2 is shrunk, the increase in length of thegold wires 6 is extremely small (for example, even if the semiconductor die 2 is shrunk from 4 mm square to 3 mm square, the increase in length of thegold wires 6 is about 0.7 mm on average). Therefore, it is possible to prevent the deterioration of the workability in the wire bonding process caused from the shrinkage of the semiconductor die 2. - The QFN manufactured by the use of the LF1 having the small tab structure has been described in the first embodiment. However, it is also possible to manufacture the QFN by the use of a lead frame LF2 in which a film-shaped
die support 33 is adhered to thelead tips 5 a near the semiconductor die as shown inFIGS. 21 and 22 . In this embodiment, thedie support 33 is made of an insulating film. - The lead frame LF2 used in the second embodiment can be manufactured in the manner similar to that of the lead frame LF1 in the first embodiment. More specifically, a
metal sheet 10 with a thickness of about 125 to 150 μm as shown inFIG. 23 is prepared, and one surface of the parts of themetal sheet 10 where theleads 5 are formed is coated with thephotoresist film 11. Also, both surfaces of the parts of themetal sheet 10, where theexternal connection terminals 8 are formed, are coated with thephotoresist film 11. Then, themetal sheet 10 is subjected to the half etching in the same manner as described in the first embodiment, thereby forming theleads 5 with a thickness of about 65 to 75 μm and theterminals 8 with a thickness of about 125 to 150 μm simultaneously. Thereafter, the surfaces of thelead tips 5 a near the semiconductor die are plated with silver, and finally, an insulatingfilm 33 is adhered to an upper surface of thelead tips 5 a. Note that, instead of the insulating film, a conductive material such as a thin metal sheet can be used to constitute thechip support 33. In this case, an insulation adhesive is preferably used to adhere the conductive material to theleads 5 in order to prevent the short circuit between theleads 5. Furthermore, it is also possible to constitute thechip support 33 by the use of a sheet obtained by coating an insulation resin on a surface of a metal foil. - In the case of using the lead frame LF2 as described above, the thickness of the
lead 5 can be reduced to about the half of the thickness of themetal sheet 10 by performing the half etching after coating one surface of the parts on themetal sheet 10 with thephotoresist film 11. Therefore, theleads 5 in which intervals between thelead tips 5 a near the semiconductor die are extremely narrow (for example, 0.18 to 0.2 mm interval) can be processed with high accuracy. In addition, by coating both surfaces of the parts on themetal sheet 10 with thephotoresist film 11, it is possible to form the protrusions of theterminals 8 simultaneously with the formation of theleads 5. - The lead frame LF2 described above is different from the lead frame LF1 used in the first embodiment in that the die pad supports 5 b for supporting the
die pad 4 are unnecessary. Therefore, it is possible to give more margin for the interval between thelead tips 5 a near the semiconductor die. - Also, since the
leads 5 are supported by thechip support 33, the length between thelead tip 5 a near the semiconductor die and the semiconductor die 2 is reduced. Therefore, it is possible to further reduce the length of thegold wires 6. Moreover, thechip support 33 can be supported more surely than the case where thedie pad 4 is supported by the four die pad supports 5 b. Therefore, it is possible to inhibit the displacement of thechip support 33 and to prevent the short circuit between thegold wires 6 in the molding process where molten resin is injected in the molding die. - As shown in
FIG. 24 , the method of manufacturing theQFN 1 by the use of the lead frame LF2 is almost the same as that described in the first embodiment. - In the first and second embodiments, the
external connection terminal 8 is constituted of the lead frame material. However, it is also possible to form the terminal in the following manner. - First, a
metal sheet 10 with a thickness of about 75 μm as shown inFIG. 25 is prepared, and both surfaces of the parts on themetal sheet 10, where thedie pad 4, theleads 5, and the die pad supports 5 b are formed, are coated with thephotoresist film 11. Then, themetal sheet 10 in this state is etched to form thedie pad 4, theleads 5, and the die supports 5 b. Subsequently, thephotoresist film 11 is removed, and the surfaces of thelead tips 5 a near the semiconductor die are plated with silver. In this manner, a lead frame LF3 is fabricated. This lead frame LF3 has the same configuration as that of the lead frame LF1 in the first embodiment except that the lead frame LF3 does not have theexternal connection terminals 8. Note that it is possible to use thedie support 33 to form the die pad of the lead frame LF3 similar to that of the lead frame LF2 in the second embodiment. In addition, it is also possible to form thedie pad 4, theleads 5, and the die pad supports 5 b of the lead frame LF3 by pressing themetal sheet 10. - Next, as shown in
FIG. 26 ,dummy terminals 12 which are not used as actual terminals are formed on some parts of the lead frame LF3. Thedummy terminals 12 are formed in the following manner. First, a screen-printing mask 15 is laminated on the rear surface of the lead frame LF3, andpolyimide 12 a is printed on some parts where external connection terminals are to be formed in the later process. Thereafter, thepolyimide 12 a is baked (FIGS. 26B to 26D). Thedummy terminal 12 is designed to have approximately the same size as that of the actual terminal formed in the later process. Note that the case where thedummy terminal 12 is formed by printing thepolyimide 12 a on the surface of thelead 5 has been described here. However, thedummy terminal 12 is not limited to this, and any materials and forming methods of the dummy terminal are available as long as it can be removed from the surface of thelead 5 in the later process. - Next, the semiconductor die 2 is mounted on the
die pad 4 in accordance with the method described in the first embodiment, and thebonding pads 7 and theleads 5 are connected by the gold wires 6 (FIG. 26E ). - Next, as shown in
FIG. 27A , the semiconductor die 2 is encapsulated in the formed molding resin, thereby forming theplastic package 3 in accordance with the method described in the first embodiment. At this time, the tip portions of thedummy terminals 12 formed on one surface of theleads 5 are protruded to the outside from the rear surface of theplastic package 3. - Next, as shown in
FIG. 27B , thedummy terminals 12 are removed from the surface of theleads 5. In the case where thedummy terminals 12 are formed of polyimide, thedummy terminals 12 can be removed by dissolving it by the use of organic solution such as hydrazine. After the removal of thedummy terminals 12, holes 35 are formed in the rear surface of theplastic package 3, and parts of the surface of theleads 5 are exposed. - Next, as shown in
FIG. 28A , a screen-printing mask 16 is laminated on the rear surface of theplastic package 3. Thereafter,solder paste 13 a is supplied to the inside of theholes 35 as shown inFIG. 28B . - Next, after the removal of the mask 16, the
solder paste 13 a is melted in a heating furnace. By doing so, solder bumps 13 are formed as shown inFIG. 29 . The solder bumps 13 are electrically connected to theleads 5 exposed in theholes 35, and the tip portions of the solder bumps 13 protrude to the outside from the rear surface of theplastic package 3. - Note that the case where the solder bumps 13 are formed by printing the
solder paste 13 a on the surface of thelead 5 has been described here. However, it is also possible to form the solder bumps 13 by supplying solder balls formed in a spherical shape into theholes 35 and then performing the reflow of the solder balls. - Note that the process of forming the solder bumps 13 by removing the
dummy terminals 12 is usually performed immediately after the completion of casting the molding resin. Thereafter, the lead frame LF3 is cut to obtain the pieces of theQFN 1. However, it is also possible to remove thedummy terminals 12 and form the solder bumps 13 after cutting the lead frame LF3 into pieces of theQFN 1. - In the above-described manufacturing method according to this embodiment, it is possible to form the terminals with a material suitable for the application of the
QFN 1 and the types of the mounting substrates in contrast to the method in which the terminals (8) are formed by the half etching of the lead frame (LF1). - The external connection terminals can also be formed in the following manner. That is, as shown in
FIG. 30 , athin metal sheet 20 with a thickness of about 75 μm is prepared, and themetal sheet 20 is etched in the same manner as that of the third embodiment, thereby fabricating a lead frame LF4 having thedie pad 4, theleads 5 and the die pad supports 5 b (not shown inFIG. 30 ). Thereafter, a middle portion of eachlead 5 is press-molded so as to have a sawtooth shape in cross section. When it is intended to adopt the structure in which a part of thedie pad support 5 b is bent upward (tab-lifted structure), the bending of thedie pad support 5 b and the formation of thelead 5 are preferably performed simultaneously. Note that it is also possible to form thedie pad 4, theleads 5, and the die pad supports 5 b can be formed by the half etching or the press-molding of thethick metal sheet 10 like that used in the first embodiment. - Next, as shown in
FIG. 31 , the semiconductor die 2 is mounted on thedie pad 4 of the lead frame LF4, and thebonding pads 7 and thelead tips 5 a near the semiconductor die are connected by thegold wires 6. Thereafter, the semiconductor die 2 is encapsulated in the molding resin, thereby forming theplastic package 3. Consequently, convex portions of theleads 5 having a sawtooth shape are exposed on the rear surface of theplastic package 3. - Next, as shown in
FIG. 32 , the lower end portion of theleads 5 exposed on the rear surface of theplastic package 3 is polished with a device such as a grinder to cut the middle portions of theleads 5, thereby dividing onelead 5 intoseveral leads - Next, as shown in
FIG. 33 , a terminal 36 is formed in each of theleads lead 5. The terminal 36 can be formed by the use of the printing of the conductive paste, the solder ball supply method, and the plating method. In addition, the process for forming theterminals 36 is usually performed immediately after the completion of theplastic package 3 by casting the molding resin. Thereafter, the lead frame LF4 is cut to obtain the pieces of theQFN 1. However, it is also possible to form thesolder terminals 36 after cutting the lead frame LF4 into pieces of theQFN 1. - Also, when using the method of forming a terminal according to this embodiment, it is possible to form a plurality of lead tips by cutting the
lead 5 in the following manner. That is, awide lead 5 as shown inFIG. 34 provided withlead tips 5 a at alternate positions apart from the semiconductor die 2 and near the semiconductor die 2 is formed, and the gold wires are bonded to thelead tips 5 a of thelead 5. Thereafter, the middle portion of thelead 5 is polished and cut as shown inFIG. 35 . According to this method, the intervals between the adjoininglead tips 5 a can be substantially eliminated. Therefore, it is possible to greatly increase the number of terminals in theQFN 1. -
FIG. 36 is a plan view of a part of a lead frame LF5 used in the manufacture of the QFN.FIG. 37 is a plan view of an internal structure (main surface side) of the QFN manufactured by the use of the lead frame LF5. - The lead frame LF5 in this embodiment has a structure in which lengths of a plurality of tips of the leads 5 (lead
tips 5 a) surrounding thedie pad 4 are alternately changed. Also, in the case of using this lead frame LF5, asemiconductor die 2 on which two lines of thebonding pads 7 are arranged along each of the sides of the main surface thereof in a zigzag pattern is used as the semiconductor die 2 to be mounted on thedie pad 4. - In the case where the lengths of the tips of the
leads 5 of the lead frame LF5 are alternately changed and thebonding pads 7 of the semiconductor die 2 are arranged in a zigzag pattern as described above, thebonding pad 7 in a line closer to the edge of the semiconductor die 2 is connected to thelead 5 having longer tip portion by theshorter gold wire 6 having a lower loop, and thebonding pad 7 in an inner line of the semiconductor die 2 is connected to thelead 5 having shorter tip portion by thelonger gold wire 6 having a higher loop as shown inFIG. 38 . - By doing so, even if the interval between the
leads 5 or the interval between thegold wires 6 is reduced with the increase of the number of pins used in the semiconductor die 2, the interference between adjoininggold wires 6 can be prevented. Therefore, it is possible to effectively prevent the occurrence of defects such as a short circuit between thegold wires 6 in the manufacturing process of the QFN (for example, wire bonding process and resin molding process). - As shown in
FIG. 39 , the above-described lead frame LF5 can be used even in the case where thesemiconductor chip 2 on which thebonding pads 7 are arranged in a line is mounted. In addition, the shape of thedie pad 4 on which the semiconductor die 2 is mounted is not limited to a circular shape, and it is possible to use thedie pad 4 having a structure in which the width of thedie pad 4 is larger than that of the die pad supports 5 b (so-called cross tab structure) like in a lead frame LF6 shown inFIG. 40 and a lead frame LF7 shown inFIG. 41 . In this case, as shown inFIG. 40 , adhesive 14 is applied to several parts on thedie pad 4 and the semiconductor die 2 is adhered thereon, by which the displacement in the rotating direction of the semiconductor die 2 can be effectively prevented. As a result, the relative location accuracy between thedie pad 4 and the semiconductor die 2 is improved. In addition, since the width of thedie pad 4 substantially functioning as a part of thedie pad support 5 b is large, the advantage of the improvement in the strength of thedie pad support 5 b can be obtained. Note that it is needless to say that thedie pad 4 of the cross tab structure can mount several types of semiconductor dies 2 with different sizes. - The terminals of the QFN can be formed in the following manner. First, as shown in
FIG. 42A , the lead frame LF3, for example, fabricated in the same manner as described in the third embodiment shown inFIG. 25 is prepared. Subsequently, as shown inFIGS. 42B to 42D, a screen-printing mask 17 is laminated on a rear surface of the lead frame LF3, andcopper paste 18 is printed on the parts where the terminals are to be formed. Then, thecopper paste 18 a are baked. In this manner,copper terminals 18 are formed. - Next, as shown in
FIG. 42E , the semiconductor die 2 is mounted on thedie pad 4 in accordance with the method described in the first embodiment, and thebonding pads 7 and theleads 5 are connected by thegold wires 6. - Subsequently, as shown in
FIG. 43 , the semiconductor die 2 is encapsulated in the formed molding resin, thereby forming theplastic package 3 in accordance with the method described in the first embodiment. Consequently, tip portions of thecopper terminals 18 formed on one surface of theleads 5 are protruded to the outside from the rear surface of theplastic package 3. - Thereafter, plating of tin and gold may be performed on the surface of the
copper terminals 18 by the use of the electroless plating method if necessary. - In the manufacturing method according to this embodiment, it is possible to simplify the terminal forming process in comparison to that of the third embodiment in which
dummy terminals 12 are formed on one surface of theleads 5 and the solder bumps 13 are formed after the removal of thedummy terminals 12. -
FIG. 44 shows an example of theQFN 1 in which thelead tips 5 a of the leads 5 (near the semiconductor die 2) are bent upward. In this structure, the difference in height between thelead tips 5 a of theleads 5 and the main surface of the semiconductor die 2 is reduced, and the loop height of thegold wires 6 that connect theleads 5 and thebonding pads 7 can be lowered. Therefore, it is possible to reduce the thickness of theplastic package 3 in proportion to the reduction. -
FIG. 45 shows an example of theQFN 1 in which thelead tips 5 a of theleads 5 are bent upward so that the height of thedie pad 4 is made equal to those of thelead tips 5 a of theleads 5, and the semiconductor die 2 is mounted on the lower surface of thedie pad 4 by using the face down bonding. In this structure, the thickness of the resin between the upper surfaces of thelead tips 5 a of theleads 5 and thedie pad 4 and that of theplastic package 3 can be made extremely thin. Therefore, an ultra-thin type QFN having theplastic package 3 with a thickness of 0.5 mm can be realized. - As shown in
FIGS. 46 and 47 , the above-described method in which thelead tips 5 a of theleads 5 are bent upward can be applied to the case where the lead frame LF2 in which thedie support 33 made from an insulating film is adhered to thelead tips 5 a of theleads 5 is used. Thedie support 33 and the semiconductor die 2 are adhered via an adhesive 19 formed on, for example, one surface of thedie support 33. Also in this case, it is possible to reduce the thickness of theplastic package 3 because of the reasons described above. -
FIGS. 48 and 49 show an example in which the die support is constituted by the use of aheat spreader 23 made of a material with high heat conductivity such as Cu and Al. Since theheat spreader 23 also functions as the die support, it is possible to realize the QFN having good heat radiation characteristics. In addition, in the case where the die support is constituted by the use of theheat spreader 23, it is possible to expose one surface of theheat spreader 23 on the surface of theplastic package 3 as shown inFIG. 50 . By doing so, the heat radiation characteristics of the QFN can be further improved. - Note that, this embodiment is applied to the QFN having the
terminals 8 formed by the half etching of the lead frame. However, it is needless to say that the application is not limited to this, and this embodiment can be applied to the various QFN having the terminals formed in accordance with the various methods described above. -
FIG. 51 is a plan view of a part of a lead frame LF8 used in the manufacture of the QFN.FIG. 52 is a plan of an outward appearance (rear surface side) of the QFN manufactured by the use of the lead frame LF8. - If the number of pins used in the QFN is increased while the package size of the QFN remains unchanged, the interval between the
terminals 8 becomes extremely narrow. Therefore, if it is intended to make the width of theterminal 8 larger than that of thelead 5 like in the lead frame LF1 used in the first embodiment, the process of the lead frame becomes extremely difficult. - For preventing the occurrence of such a case, it is desirable to make the width of the
terminals 8 equal to those of theleads 5 like in the lead frame LF8 in this embodiment. By doing so, it is possible to realize the QFN in which the pitch between the terminals is narrow and the number of pins used therein is very large. For example, the width d of theterminal 8 and lead 5 is 0.15 to 0.18 mm, and the interval P1 between the adjoiningterminals 8 in the same line is 0.5 mm, and the interval P2 between the interstitial terminals in different lines is 0.25 mm. - In this case, since the width of the
terminal 8 becomes narrower, the size of the contact area between the terminal 8 and the mounting substrate is reduced, and thus, the connection reliability is deteriorated. Therefore, as compensation means thereof, it is desirable that the length of theterminal 8 is increased to prevent the reduction in size of the contact area. In addition, since the width of thelead 5 becomes narrower, the strength of thelead 5 is also reduced. Therefore, it is desirable that thedie support 33 is adhered to the tip of thelead 5 and supports thelead 5 for the prevention of the deformation of thelead 5. Thedie support 33 can be provided in the middle portion of thelead 5 as shown inFIG. 53 . As shown inFIGS. 54 and 55 , the structure of the lead frame LF8 in which the width of theterminal 8 and that of thelead 5 are made equal to each other can be of course applied to a lead frame not having thedie support 33. - In the foregoing, the invention made by the inventors of this invention has been described in detail based on the embodiments. However, it goes without saying that the present invention is not limited to the above-described embodiments, and various changes and modifications of the invention can be made without departing from the spirit and scope of the invention.
- For example, in the case described in the first embodiment where a plurality of semiconductor dies 2 mounted on one lead frame LF1 are simultaneously resin-encapsulated by the use of the molding die 40, the lead frame LF1 before dicing may be warped or deformed due to the difference in the thermal expansion coefficient between the lead frame LF1 and the molding resin.
- For its prevention, it is effective to provide
slits 22 on the outer frame part of the lead frame LF1 as shown inFIG. 56 . It is also effective to change the amount of filler or the like contained in the molding resin that constitutes theplastic package 3 so as to control the thermal expansion coefficient of theplastic package 3 close to that of the lead frame LF1. - Also, it is possible to realize the
QFN 1 with high heat radiation characteristics by forming thedie pad 4 exposed on the rear surface of theplastic package 3 as shown inFIG. 57 . For forming thedie pad 4 exposed on the rear surface of theplastic package 3, it is required to form athick die pad 4 by coating thedie pad 4 with a photoresist film when athick metal sheet 10 is subjected to the half etching to form the thin leads 5 and the thin die pad supports 5 b. - Also, the
thin die pad 4, the thin leads 5 and the thin die pad supports 5 b are formed by the half etching of thethick metal sheet 10 in the first embodiment. However, the strength of the die pad supports 5 b becomes insufficient in some cases when a relatively large semiconductor die 2 is mounted on the thin die pad supports 5 b. For preventing the occurrence of such a case, it is effective to form the die pad supports 5 b having a large thickness without performing the half etching of the part or all of the die pad supports 5 b. In this case, since the part of (or all of) the die pad supports 5 b are exposed on the rear surface of theplastic package 3, the connection reliability between theQFN 1 and the wiring board and the heat radiation characteristics of theQFN 1 can be improved by soldering the exposed portion to the wiring board. - Also, in the above-described embodiments, the molding method in which the
resin film 41 is interposed between the molding die 40 (upper die 40A andlower die 40B) is used to form theplastic package 3. However, it is also possible to form theplastic package 3 in accordance with the molding method not using theresin film 41 as shown inFIG. 59 . In this case, a part of theterminal 8 or the entire of theterminal 8 is covered with the resin in some cases as shown inFIGS. 60A and 60B when theplastic package 3 is separated from the molding die 40. Therefore, it is required to remove the resin burr on the surface of theterminal 8 by the use of a burr removal means 37 such as a grinder as shown inFIG. 61 , and then, the metal layer is formed on the surface of theterminal 8 by the above-described printing method and the electroplating method. - The advantages achieved by the typical ones of the inventions disclosed in this application will be briefly described as follows.
- Since lead tips on one side of a plurality of leads arranged around a semiconductor die are extended to a position close to a die pad, it is possible to reduce lengths of wires that connect the leads and bonding pads. Therefore, even if the pitch between the leads or the interval between the wires is narrowed due to the increase of the number of pins in use, it is possible to reduce the occurrence of defects such as short-circuit between the wires during the manufacturing process. As a result, it is possible to achieve the increase of the number of pins used in the QFN.
- Appendix:
- The typical ones of the inventions disclosed in the embodiments will be briefly described as follows.
- 1. A semiconductor device, comprising: a semiconductor die; a die pad on which the semiconductor die is mounted; a plurality of leads arranged around the semiconductor die; a plurality of wires for electrically connecting the semiconductor die and the leads; and a plastic package for encapsulating the semiconductor die, the die pad, the plurality of leads, and the plurality of wires,
- wherein the plurality of leads are formed so that intervals between the lead tips on one side near the semiconductor die are narrower than those between the lead tips on the other side opposite to the one side, and
- a terminal protruded from a rear surface of the plastic package to the outside is selectively provided to each of the plurality of leads.
- 2. The semiconductor device according to the
above item 1, - wherein the terminal is constituted of a part of the lead protruded from the rear surface of the plastic package to the outside.
- 3. The semiconductor device according to the
above item 1, - wherein the terminal is made of a conductive material which is different from that of the lead.
- 4. The semiconductor device according to the
above item 1, - wherein a rear surface of the die pad is exposed from the rear surface of the plastic package.
- 5. The semiconductor device according to the
above item 1, - wherein the terminals are arranged in two lines along each side of the plastic package in a zigzag pattern.
- 6. The semiconductor device according to the
above item 5, - wherein, of the plurality of leads, leads on which the terminals are arranged closer to the one side have a width larger than that of leads on which the terminals are arranged closer to the other side.
- 7. The semiconductor device according to the
above item 1, - wherein an area of the die pad is smaller than that of the semiconductor die.
- 8. The semiconductor device according to the
above item 1, - wherein the die pad is supported by a plurality of die pad supports.
- 9. A semiconductor device, comprising: a semiconductor die; a die pad support having a film shape on which the semiconductor die is mounted; a plurality of leads arranged around the semiconductor die; a plurality of wires for electrically connecting the semiconductor die and the leads; and a plastic package for encapsulating the semiconductor die, the die pad support, the plurality of leads, and the plurality of wires,
- wherein the plurality of leads are formed so that intervals between the lead tips on one side near the semiconductor die are narrower than those between the lead tips on the other side opposite to the one side, and
- a terminal protruded from a rear surface of the plastic package to the outside is electrically connected to each of the plurality of leads.
- 10. The semiconductor device according to the
above item 9, - wherein the die pad support is supported by the plurality of leads.
- 11. A method of manufacturing a semiconductor device, which comprises: a semiconductor die; a die pad on which the semiconductor die is mounted; a plurality of leads arranged around the semiconductor die; a plurality of wires for electrically connecting the semiconductor die and the leads; and a plastic package for encapsulating the semiconductor die, the die pad, the plurality of leads, and the plurality of wires,
- the method comprising the steps of:
- (a) preparing a lead frame on which patterns including the die pad and the plurality of leads are successively formed, and a terminal protruded in a direction perpendicular to a surface of the lead is formed on each of the surfaces of the plurality of leads;
- (b) mounting a semiconductor die on each of the plurality of die pads formed on the lead frame, and connecting the semiconductor die and the parts of the leads by the use of wires;
- (c) preparing a molding die having an upper die and a lower die, coating a surface of the lower die with a resin film, and then, mounting the lead frame on the resin film, thereby bringing the terminal formed on the surface of the lead into contact with the resin film;
- (d) pressing the resin film and the lead frame with the upper die and the lower die to push tip portions of the terminals into the resin film;
- (e) injecting resin into spaces between the upper and lower dies, thereby encapsulating the semiconductor die, the die pad, the leads, and the wires, and separating the lead frame from the molding die after forming a plurality of plastic packages in which the tip portions of the terminals are protruded to the outside; and
- (f) dicing the lead frame to obtain pieces of plastic packages.
- 12. The method of manufacturing a semiconductor device according to the
above item 11, - wherein the step (a) includes the step of coating a part of a metal sheet with a photoresist film, and performing etching of parts of the metal sheet not coated with the photoresist film, thereby forming the plurality of leads, the die pad, and the terminals.
- 13. The method of manufacturing a semiconductor device according to the
above item 12, - wherein the plurality of leads are formed by the half etching of the metal sheet.
- 14. The method of manufacturing a semiconductor device according to the
above item 11, - wherein the plurality of leads are formed so that intervals between the lead tips on one side near the die pad are narrower than those between the lead tips on the other side opposite to the one side.
- 15. The method of manufacturing a semiconductor device according to the
above item 11, - wherein the terminal formed in the step (a) is a dummy terminal, and, after the step (e), the method further comprises the steps of: removing the dummy terminal; and forming a terminal whose tip portion is protruded to the outside of the plastic package on a surface of the lead in the area where the dummy terminal has been removed.
- 16. The method of manufacturing a semiconductor device according to the
above item 12, - wherein, in the etching of the metal sheet in the step (a), an area on the metal sheet where the die pad is to be formed is not etched.
- 17. The method of manufacturing a semiconductor device according to the
above item 12, - wherein, in the etching of the metal sheet in the step (a), an area on the metal sheet which contacts to the molding die in the step (d) is not etched.
- 18. The method of manufacturing a semiconductor device according to the
above item 11, - wherein slits are provided in an outer frame of the lead frame.
- 19. The method of manufacturing a semiconductor device according to the
above item 11, - wherein the terminals are arranged in two lines along each side of the plastic package in a zigzag pattern.
- 20. The method of manufacturing a semiconductor device according to the
above item 19, - wherein, of the plurality of leads, a lead on which the terminal is arranged closer to the die pad has a width larger than that of a lead on which the terminal is arranged apart from the die pad.
- 21. The method of manufacturing a semiconductor device according to the
above item 11, - wherein a jig to support the lead frame in the step (b) is provided with grooves at positions corresponding to the tip portions of the terminals.
- 22. The method of manufacturing a semiconductor device according to the
above item 11, - wherein the upper molding die of the molding die used in the step (c) contacts to an outer frame part of the lead frame and to a connection part between the leads, and spaces other than those are used as cavities into which the resin is injected.
- 23. The semiconductor device according to the
above item 1, - wherein the lengths of the plurality of the lead tips on the one side are alternately changed.
- 24. The semiconductor device according to the
above item 23, - wherein bonding pads formed on a main surface of the semiconductor die are arranged in two lines along each side of the semiconductor die in a zigzag pattern.
- 25. The semiconductor device according to the
above item - wherein lead tips of the plurality of leads on the one side are bent in a thickness direction of the plastic package.
- 26. The semiconductor device according to the
above item - wherein a diameter of the terminal is larger than a width of the lead.
- 27. The semiconductor device according to the
above item - wherein a diameter of the terminal is equal to a width of the lead.
- 28. The semiconductor device according to the
above item 9, - wherein the die support is a heat spreader.
Claims (12)
Priority Applications (1)
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US11/474,332 US7507606B2 (en) | 2001-12-14 | 2006-06-26 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
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JP2001381427 | 2001-12-14 | ||
JP2001-381427 | 2001-12-14 | ||
JP2002-291975 | 2002-10-04 | ||
JP2002291975A JP4173346B2 (en) | 2001-12-14 | 2002-10-04 | Semiconductor device |
US10/299,768 US6809405B2 (en) | 2001-12-14 | 2002-11-20 | Semiconductor device and method of manufacturing the same |
US10/878,269 US7160759B2 (en) | 2001-12-14 | 2004-06-29 | Semiconductor device and method of manufacturing the same |
US11/474,332 US7507606B2 (en) | 2001-12-14 | 2006-06-26 | Semiconductor device and method of manufacturing the same |
Related Parent Applications (1)
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US10/878,269 Division US7160759B2 (en) | 2001-12-14 | 2004-06-29 | Semiconductor device and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
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US20060240600A1 true US20060240600A1 (en) | 2006-10-26 |
US7507606B2 US7507606B2 (en) | 2009-03-24 |
Family
ID=26625065
Family Applications (3)
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US10/299,768 Expired - Fee Related US6809405B2 (en) | 2001-12-14 | 2002-11-20 | Semiconductor device and method of manufacturing the same |
US10/878,269 Expired - Lifetime US7160759B2 (en) | 2001-12-14 | 2004-06-29 | Semiconductor device and method of manufacturing the same |
US11/474,332 Expired - Fee Related US7507606B2 (en) | 2001-12-14 | 2006-06-26 | Semiconductor device and method of manufacturing the same |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
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US10/299,768 Expired - Fee Related US6809405B2 (en) | 2001-12-14 | 2002-11-20 | Semiconductor device and method of manufacturing the same |
US10/878,269 Expired - Lifetime US7160759B2 (en) | 2001-12-14 | 2004-06-29 | Semiconductor device and method of manufacturing the same |
Country Status (5)
Country | Link |
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US (3) | US6809405B2 (en) |
JP (1) | JP4173346B2 (en) |
KR (1) | KR20030051222A (en) |
CN (1) | CN1424757A (en) |
TW (1) | TW571421B (en) |
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Also Published As
Publication number | Publication date |
---|---|
CN1424757A (en) | 2003-06-18 |
US7507606B2 (en) | 2009-03-24 |
KR20030051222A (en) | 2003-06-25 |
JP2003243600A (en) | 2003-08-29 |
US20030111717A1 (en) | 2003-06-19 |
TW571421B (en) | 2004-01-11 |
US20040232528A1 (en) | 2004-11-25 |
JP4173346B2 (en) | 2008-10-29 |
US7160759B2 (en) | 2007-01-09 |
US6809405B2 (en) | 2004-10-26 |
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