US20060285411A1 - Single cycle refresh of multi-port dynamic random access memory (dram) - Google Patents
Single cycle refresh of multi-port dynamic random access memory (dram) Download PDFInfo
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- US20060285411A1 US20060285411A1 US11/160,273 US16027305A US2006285411A1 US 20060285411 A1 US20060285411 A1 US 20060285411A1 US 16027305 A US16027305 A US 16027305A US 2006285411 A1 US2006285411 A1 US 2006285411A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Definitions
- the field of the invention is that of multi-port dynamic random access memory.
- FIG. 1 illustrates a conventional 1T, 1C DRAM cell 10 that contains a capacitor 12 for storing the data and a pass transistor 11 controlled by a Word Line (WL) that connects the storage node to the Bitline (BL).
- WL Word Line
- BL Bitline
- the charge stored on the capacitor will, of course, leak away and the charge must be refreshed.
- the refresh cycle consists of a read operation that destructively reads the stored data followed by a write operation that writes the data back in the cell with the maximum charge that the apparatus allows. As is well known, the cell may not be written to or read from during the course of the refresh operation.
- FIG. 2 shows a transistor level schematic of a multi-port 3T1C DRAM gain cell. These cells may be written to and read from independently, since they have separate read and write ports (a read port with a Read Word Line, RWL, and a Read Bitline, RBL, and a write port with a Write Word Line, WWL, and a Write Bitline, WBL). They also must be refreshed, since the data bit is also stored in a capacitor that has a finite leakage.
- RWL Read Word Line
- RBL Read Bitline
- WBL Write Bitline
- the NMOS transistor 24 couples the storage node 22 to the write bitline WBL for a write operation, when the write wordline WWL goes high.
- the storage node 22 may preferably have a capacitor 25 to keep the data bit.
- the data bit stored in a storage node 22 can be read out to the read bitline RBL when the read wordline RWL goes high. If the storage node 22 keeps a high data, two NMOS transistors 21 and 23 are both on, discharging the RBL. If the storage node keeps a low voltage, the NMOS transistor 23 is off, keeping the RBL at the precharged voltage.
- the 3T gain cell can simultaneously realize a read operation by using RWL and RBL, and a write operation by using WWL and WBL, thereby providing a solution for a high performance memory system. It does, however, require a refresh to maintain the data. Unlike a conventional 1T cell in FIG. 1 , the 3T gain cell requires to read the data bit first by activating a RWL, and then rewrite a data bit to the cell by activating WWL. This results in a 2 cycle refresh, reducing memory availability.
- the art could benefit from a 3T1C cell that has a single cycle refresh mode that improves the memory availability for normal read and write operations.
- the invention relates to a single cycle refresh management for a 3T1C gain cell dual-port memory that defers the write back portion of the sequence until the next refresh cycle, thereby taking only one clock cycle by performing the write operation of the kth refresh during the same clock cycle as the read operation of the (k+1)th refresh.
- FIG. 1 shows a schematic of a 1T1C DRAM cell.
- FIG. 2 shows a schematic of a 3T1C DRAM cell for use with the invention.
- FIG. 3 shows a peripheral circuit including sense amp, cell driver and refresh buffer.
- FIG. 4 shows a detail of the counter arrangement for the refresh operation.
- FIG. 5 shows timing relationships in the refresh sequence.
- FIG. 6 shows row decoder and word line driver for RWL, REFWL and WWL.
- FIG. 5 shows a set of pulse trains used with the invention that illustrates the times when the normal read and write operations and the refresh read and write operations take place.
- the CLK signals 50 - 1 , - - - 50 - 5 mark off a sample of clock pulses that illustrate the operations of the system.
- Lines 2 and 3 show the timing of normal read and write operations to the memory.
- Read operations denoted with numerals 1 , 3 and 5 representing read row addresses
- write operations denoted with 2 , 4 , 6 , representing write row addresses
- WWL is activated to write the contents of the RPBUF (Read Page Buffer, stores the read data temporarily) to the memory row flagged during the preceding refresh cycle R 0 preceding the row flagged in cycle R 1 .
- RPBUF Read Page Buffer
- a slight skew not shown in the figure, separates the write and read operations in time, so that the contents of RPBUF are read out into the appropriate row and the circuits have stabilized before the read operation loads the contents of the next row into RPBUF, thus avoiding contamination of the read-in data.
- a single cycle refresh is realized by delaying a write function till the next cycle.
- a refresh row address counter (RAC) shown in FIG. 4 generates addresses n and n- 1 for RWL and WWL respectively for each refresh cycle.
- row n is read out and stored in RPBUF.
- Data conversion logic is included in RPBUF to keep the write back data polarity consistent with the read data polarity.
- the data bits are held in the RPBUF until the next refresh cycle, at which time the data in the RPBUF is written back to the appropriate row in the array.
- the non-destructive read feature of the memory cell allows for reading the data bits even if a read command is received for the row address of the data held in a RPBUF.
- the additional refresh interval required for the cell by this feature is less than 1% of the total retention requirement as long as distributed refresh is used.
- FIG. 4 shows the RAC 415 which increments the row number of the next row to be refreshed.
- the REF command will enable the transfer of the next row address to be read on line 434 and the next address to be written on line 432 .
- comparator 420 generates a hit signal when the next write address during the refresh latency period is the same as the next refresh write address(N ⁇ 1) to be written during next refresh command cycle.
- the illustrative example is non-multiplexed column architecture. All cells with a particular wordline will be read or written at one cycle. Those skilled in the art will appreciate that there are many ways to preserve the data in the other columns; i.e.
- FIG. 3 there is shown a combined peripheral circuit that connects to columns of the memory array.
- Most of the elements of FIG. 3 comprise a sense amplifier denoted with bracket 310 that further contains unit 312 that equalizes and precharges the bitlines RBL and RBLB, 314 and 316 , respectively.
- Cross coupled inverters 320 perform the usual function of responding to a difference on the bitlines to drive the lines to a higher voltage.
- Reference cell 360 maintains a reference voltage that is preferably half way between the bitline voltage associated with a logical 1 in the selected cell and the voltage associated with a logical 0 in the cell.
- Unit 370 is a reference cell which provides a reference voltage level to the RBLB, which are the inputs to sense amplifier together with RBL.
- the reference cell consists of the same memory cell as normal 3T1C cell by skipping the write access transistor.
- the read head transistor (designated ZVT) gate is tied to VREF, which is an external voltage supply.
- the VREF is the average value of GND and VDD.
- Unit 330 contains the Data Conversion Logic (DCL) and stores the data from the memory cell in question as part of RPBUF It manages the write back data polarity when we read and write back to the cells. Because the read bitline and write bitlines are twisted one and twice respectively, the read data in RPBUF needs to keep track of the data and address scramble to correctly maintain the data in the cells.
- DCL Data Conversion Logic
- unit 340 contains a conventional latch DOUT that stores and sends out the data that is read out in normal operation, and keeps the data to be fetched even after RBL and RBLB go back to the precharge state “High”.
- a driver circuit writes data to the cell that has been activated on bitlines WBL and WBLB.
- bitlines WBL and WBLB In the example illustrated here, only one WBL is used, but some memory architectures may use two bitlines for a purpose that is outside the scope of the present invention.
- unit 350 maintains the data consistency between array and RPBUF by simultaneously writing the new write data in both array and RPBUF when the Hit signal is active.
- the bitline driver will be fed by data from the Data pad when the WE signal is high and fed from unit 330 when the REF signal is high.
- FIG. 6 shows a decoder that generates RWL, REFWL and WWL signals from the read row address and write row address, respectively.
- the decoding is done in subcircuit 305 , controlling node 310 .
- the ratio of refresh cycles to ordinary read and write operations will vary with different products and as the technology changes.
- the retention time of charge in a cell will determine the overall frequency of the interval between refresh operations.
Abstract
Description
- The field of the invention is that of multi-port dynamic random access memory.
-
FIG. 1 illustrates a conventional 1T,1C DRAM cell 10 that contains a capacitor 12 for storing the data and apass transistor 11 controlled by a Word Line (WL) that connects the storage node to the Bitline (BL). The charge stored on the capacitor will, of course, leak away and the charge must be refreshed. The refresh cycle consists of a read operation that destructively reads the stored data followed by a write operation that writes the data back in the cell with the maximum charge that the apparatus allows. As is well known, the cell may not be written to or read from during the course of the refresh operation. -
FIG. 2 shows a transistor level schematic of a multi-port 3T1C DRAM gain cell. These cells may be written to and read from independently, since they have separate read and write ports (a read port with a Read Word Line, RWL, and a Read Bitline, RBL, and a write port with a Write Word Line, WWL, and a Write Bitline, WBL). They also must be refreshed, since the data bit is also stored in a capacitor that has a finite leakage. - The
NMOS transistor 24 couples thestorage node 22 to the write bitline WBL for a write operation, when the write wordline WWL goes high. Thestorage node 22 may preferably have acapacitor 25 to keep the data bit. The data bit stored in astorage node 22 can be read out to the read bitline RBL when the read wordline RWL goes high. If thestorage node 22 keeps a high data, twoNMOS transistors NMOS transistor 23 is off, keeping the RBL at the precharged voltage. - The 3T gain cell can simultaneously realize a read operation by using RWL and RBL, and a write operation by using WWL and WBL, thereby providing a solution for a high performance memory system. It does, however, require a refresh to maintain the data. Unlike a conventional 1T cell in
FIG. 1 , the 3T gain cell requires to read the data bit first by activating a RWL, and then rewrite a data bit to the cell by activating WWL. This results in a 2 cycle refresh, reducing memory availability. - The art could benefit from a 3T1C cell that has a single cycle refresh mode that improves the memory availability for normal read and write operations.
- The invention relates to a single cycle refresh management for a 3T1C gain cell dual-port memory that defers the write back portion of the sequence until the next refresh cycle, thereby taking only one clock cycle by performing the write operation of the kth refresh during the same clock cycle as the read operation of the (k+1)th refresh.
-
FIG. 1 shows a schematic of a 1T1C DRAM cell. -
FIG. 2 shows a schematic of a 3T1C DRAM cell for use with the invention. -
FIG. 3 shows a peripheral circuit including sense amp, cell driver and refresh buffer. -
FIG. 4 shows a detail of the counter arrangement for the refresh operation. -
FIG. 5 shows timing relationships in the refresh sequence. -
FIG. 6 shows row decoder and word line driver for RWL, REFWL and WWL. -
FIG. 5 shows a set of pulse trains used with the invention that illustrates the times when the normal read and write operations and the refresh read and write operations take place. - On the top row, the CLK signals 50-1, - - - 50-5 mark off a sample of clock pulses that illustrate the operations of the system.
Lines numerals lines lines - It is apparent on
lines - Within clock cycle 50-2, WWL is activated to write the contents of the RPBUF (Read Page Buffer, stores the read data temporarily) to the memory row flagged during the preceding refresh cycle R0 preceding the row flagged in cycle R1. A slight skew, not shown in the figure, separates the write and read operations in time, so that the contents of RPBUF are read out into the appropriate row and the circuits have stabilized before the read operation loads the contents of the next row into RPBUF, thus avoiding contamination of the read-in data.
- A single cycle refresh is realized by delaying a write function till the next cycle. A refresh row address counter (RAC) shown in
FIG. 4 generates addresses n and n-1 for RWL and WWL respectively for each refresh cycle. When a refresh command is received, row n is read out and stored in RPBUF. Data conversion logic is included in RPBUF to keep the write back data polarity consistent with the read data polarity. The data bits are held in the RPBUF until the next refresh cycle, at which time the data in the RPBUF is written back to the appropriate row in the array. The non-destructive read feature of the memory cell allows for reading the data bits even if a read command is received for the row address of the data held in a RPBUF. The additional refresh interval required for the cell by this feature is less than 1% of the total retention requirement as long as distributed refresh is used. - When a write command is received for the data in the RPBUF, write data will be written for the corresponding row in the array and RPBUF avoiding the possible complexities when a read after write operation for the data held in RPBUF is performed. The data path from write data pad to RPBUF is controlled by the Hit signal in
block 350 ofFIG. 3 . The Hit signal is created as shown inFIG. 4 by comparing the refresh address with the write address of a normal write. Thus, even if a write command is executed during the refresh latency period of two clock cycles, the refresh write operation that is the second part of the refresh operation is suppressed, so that the new data in the memory array is not overwritten by the data from RPBUF. This assures data consistency when writing to an address that is in the midst of a refresh. The timing diagram inFIG. 5 shows that the write operation of refreshing address R1 is separated from read operation by the refresh latency period (command interval) and done when the next refresh read operation of R2 starts. -
FIG. 4 shows the RAC 415 which increments the row number of the next row to be refreshed. In operation, the REF command will enable the transfer of the next row address to be read online 434 and the next address to be written online 432. As discussed above,comparator 420 generates a hit signal when the next write address during the refresh latency period is the same as the next refresh write address(N−1) to be written during next refresh command cycle. The illustrative example is non-multiplexed column architecture. All cells with a particular wordline will be read or written at one cycle. Those skilled in the art will appreciate that there are many ways to preserve the data in the other columns; i.e. resetting the row address counter to repeat the read operation on row (N−1) and then read the recently read data into the (N−1)th row. This repeated read may be done at any convenient time, not necessarily on the next refresh cycle. Alternatively, straightforward logic may be used to keep track of the columns written to during the latency period and refresh only the columns that are not written to in that period. - Referring now to
FIG. 3 , there is shown a combined peripheral circuit that connects to columns of the memory array. Most of the elements ofFIG. 3 comprise a sense amplifier denoted withbracket 310 that further containsunit 312 that equalizes and precharges the bitlines RBL and RBLB, 314 and 316, respectively. Cross coupledinverters 320 perform the usual function of responding to a difference on the bitlines to drive the lines to a higher voltage.Reference cell 360 maintains a reference voltage that is preferably half way between the bitline voltage associated with a logical 1 in the selected cell and the voltage associated with a logical 0 in the cell. -
Unit 370 is a reference cell which provides a reference voltage level to the RBLB, which are the inputs to sense amplifier together with RBL. The reference cell consists of the same memory cell as normal 3T1C cell by skipping the write access transistor. The read head transistor (designated ZVT) gate is tied to VREF, which is an external voltage supply. The VREF is the average value of GND and VDD. -
Unit 330 contains the Data Conversion Logic (DCL) and stores the data from the memory cell in question as part of RPBUF It manages the write back data polarity when we read and write back to the cells. Because the read bitline and write bitlines are twisted one and twice respectively, the read data in RPBUF needs to keep track of the data and address scramble to correctly maintain the data in the cells. - At the bottom of the Figure,
unit 340 contains a conventional latch DOUT that stores and sends out the data that is read out in normal operation, and keeps the data to be fetched even after RBL and RBLB go back to the precharge state “High”. - On the left side of
FIG. 3 , a driver circuit writes data to the cell that has been activated on bitlines WBL and WBLB. In the example illustrated here, only one WBL is used, but some memory architectures may use two bitlines for a purpose that is outside the scope of the present invention. - As discussed above,
unit 350 maintains the data consistency between array and RPBUF by simultaneously writing the new write data in both array and RPBUF when the Hit signal is active. Ordinarily, the bitline driver will be fed by data from the Data pad when the WE signal is high and fed fromunit 330 when the REF signal is high. -
FIG. 6 shows a decoder that generates RWL, REFWL and WWL signals from the read row address and write row address, respectively. The decoding is done insubcircuit 305, controllingnode 310. - Those skilled in the art will appreciate that the ratio of refresh cycles to ordinary read and write operations will vary with different products and as the technology changes. In particular, the retention time of charge in a cell will determine the overall frequency of the interval between refresh operations.
- While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.
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KR102026027B1 (en) * | 2010-05-14 | 2019-09-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
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