US20070020811A1 - Method and apparatus for attaching microelectronic substrates and support members - Google Patents
Method and apparatus for attaching microelectronic substrates and support members Download PDFInfo
- Publication number
- US20070020811A1 US20070020811A1 US11/480,771 US48077106A US2007020811A1 US 20070020811 A1 US20070020811 A1 US 20070020811A1 US 48077106 A US48077106 A US 48077106A US 2007020811 A1 US2007020811 A1 US 2007020811A1
- Authority
- US
- United States
- Prior art keywords
- adhesive
- support member
- projection
- microelectronic substrate
- disposing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29007—Layer connector smaller than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first surface, a second surface facing opposite the first surface, and a projection extending away from the first surface. A quantity of adhesive material can be applied to the projection to form an attachment structure, and the adhesive material can be connected to a microelectronic substrate with the attachment structure providing no electrically conductive link between the microelectronic substrate and the support member. The microelectronic substrate and the support member can then be electrically coupled, for example, with a wire bond. In one embodiment, the projection can be formed by disposing a first material on a support member while the first material is at least partially flowable, reducing the flowability of the first material, and disposing a second material (such as the adhesive) on the first material.
Description
- Conventional microelectronic device packages typically include a microelectronic substrate or die attached to a support member, such as a printed circuit board. Bond pads or other terminals on the die are electrically connected to corresponding terminals of the support member, for example, with wire bonds. The die, the support member, and the wire bonds are then encapsulated with a protective epoxy material to form a device package. The package can then be electrically connected to other microelectronic devices or circuits, for example, in a consumer or industrial electronic product such as a computer.
- In one existing arrangement shown in
FIG. 1A , amicroelectronic device package 10 a includes asupport member 20 having anaperture 21. Amicroelectronic substrate 30 is attached to thesupport member 20 with strips ofadhesive tape 40 a.Substrate bond pads 31 are then electrically connected to corresponding supportmember bond pads 22 withwire bonds 32 that extend through theaperture 21. An encapsulant 11, which includes a suspension offiller material particles 12, is disposed over themicroelectronic substrate 30 and thewire bonds 32. The sizes of thefiller material particles 12 in any givenpackage 10 a typically range in a standard distribution about a selected mean value. - One drawback with the foregoing arrangement is that the filler material particles 12 (and in particular, the largest filler material particles 12) can impinge on and damage the
microelectronic substrate 30. Because thelarger particles 12 tend to settle toward thesupport members 20, one approach to addressing the foregoing drawback is to increase the separation distance between themicroelectronic substrate 30 and thesupport member 20 by increasing the thickness of thetape 40 a. Accordingly, an advantage of thetape 40 a is that it can be selected to have a thickness sufficient to provide the desired separation between themicroelectronic substrate 30 and thesupport member 20. However, a drawback with thetape 40 a is that it can be expensive to install. A further drawback is that thetape 40 a can be difficult to accurately position between thesupport member 20 and themicroelectronic substrate 30. -
FIG. 1B illustrates another existingmicroelectronic device package 10 b having amicroelectronic substrate 30 attached to thesupport member 20 with screen printed strips ofepoxy 40 b. Theepoxy 40 b can be easier than thetape 40 a (FIG. 1A ) to dispense on thesupport member 20, but can have other problems. For example, theepoxy 40 b can apply stresses to the sides of themicroelectronic substrate 30, but it may be difficult to control how much of the sides theepoxy 40 b contacts, making it difficult to control the stress applied to themicroelectronic substrate 30. Another drawback is that the thickness of theepoxy 40 b typically ranges from about 8 microns to about 25 microns, while in some cases the desired separation betweenmicroelectronic substrate 30 and thesupport member 20 is greater than about 75 microns, for example, to avoid the particle impingement problem described above. Still another drawback is that the interfaces between theepoxy 40 b and the encapsulant 11 (one located to the outside of themicroelectronic substrate 30 and the other located beneath the microelectronic substrate 30) can delaminate, which can reduce the integrity of thepackage 10 b. The interface located beneath themicroelectronic substrate 30 can also create a high stress region that can cause a crack C to form in the encapsulant 11. The crack C can damage the integrity of thewire bond 32. - Another problem with both the
tape 40 a and theepoxy 40 b is that the coefficient of thermal expansion (CTE) of these components is typically substantially different than the CTE of other components of the package. For example, themicroelectronic substrate 30 typically has a CTE of about 3 parts per million (ppm) per ° C., thesupport member 20 typically has a coefficient CTE of about 50 ppm/° C., and the encapsulant 11 typically has a CTE of from about 10-15 ppm/° C. By contrast, thetape 40 a and theepoxy 40 b each have a CTE of about 150-400 ppm/° C. Accordingly, both thetape 40 a and theepoxy 40 b can exert substantial shear and/or normal forces on themicroelectronic substrate 30 during thermal excursions for curing, reflow and other processes. These forces can crack themicroelectronic substrate 30, and/or delaminate layers from themicroelectronic substrate 30 and/or thesupport member 20, causing the package to fail. - The present invention is directed toward microelectronic packages and methods for forming such packages. A method in accordance with one aspect of the invention includes providing a support member having a first surface, a second surface facing opposite the first surface, and a projection extending away from the first surface. The method can further include forming an attachment structure by applying a quantity of adhesive material to the projection and connecting the adhesive material to the microelectronic substrate with a surface of the microelectronic substrate facing toward the first surface of the support member and with the attachment structure providing no electrically conductive link between the microelectronic substrate and the support member. The microelectronic substrate and the support member can then be electrically connected, for example, with a wire bond.
- In one aspect of the invention, the projection can include an electrically conductive material, such as copper or aluminum. Alternatively, the projection can have the same composition as the adhesive material. In another aspect of the invention, the attachment structure can be formed by disposing a first quantity of material on at least one of the microelectronic substrate and the support member while the first quantity of material is at least partially flowable. The flowability of the first quantity of material can be at least partially reduced, and a second quantity of material can be applied to the attachment structure while the second quantity of material is at least partially flowable. The attachment structure can then be connected to the other of the microelectronic substrate and the support member.
- In other aspects of the invention, the attachment structure can have a first bond strength at a joint with the support member, and a second bond strength at a joint with the microelectronic substrate, with the second bond strength greater than the first bond strength. The height of the attachment structure can be about 35 microns or more in one embodiment, and can exceed 75 microns in another embodiment. In still further aspects of the invention, the attachment structure can be connected between two microelectronic substrates.
-
FIG. 1A is a cross-sectional view of a microelectronic device package having a tape adhesive in accordance with the prior art. -
FIG. 1B is a cross-sectional view of a microelectronic device package having an epoxy adhesive in accordance with the prior art. -
FIGS. 2A-2E illustrate a process for attaching a microelectronic substrate to a support member in accordance with an embodiment of the invention. -
FIGS. 3A-3E illustrate an in-line process for attaching a microelectronic substrate to a support member in accordance with another embodiment of the invention. -
FIG. 4 is a partially schematic isometric view of a support member having attachment structures in accordance with another embodiment of the invention. -
FIG. 5 is a cross-sectional view of a microelectronic package having attachment structures in accordance with still another embodiment of the invention. -
FIG. 6 is a cross-sectional view of a microelectronic substrate mounted to a support member to form a package in accordance with another embodiment of the invention. -
FIG. 7 is a cross-sectional view of two microelectronic substrates attached to each other with attachment structures in accordance with another embodiment of the invention. - The present disclosure describes microelectronic substrate packages and methods for forming such packages. The term “microelectronic substrate” is used throughout to include substrates upon which and/or in which microelectronic circuits or components, data storage elements or layers, and/or vias or conductive lines are or can be fabricated. Many specific details of certain embodiments of the invention are set forth in the following description and in
FIGS. 2A-7 to provide a thorough understanding of these embodiments. One skilled in the art, however, will understand that the present invention may have additional embodiments, and that the invention may be practiced without several of the details described below. -
FIGS. 2A-2E illustrate a process for attaching a microelectronic substrate to a support member to form a microelectronic package in accordance with an embodiment of the invention. Referring first toFIG. 2A , the process can include providing a support member 120 (such as a printed circuit board) having a generally flat, planar shape with afirst surface 123 and asecond surface 124 facing opposite from thefirst surface 123. Anaperture 121 can extend through thesupport member 120 from thefirst surface 123 to thesecond surface 124 to receive conductive couplers, as described in greater detail below with reference toFIG. 2E . - Referring now to
FIG. 2B , one or more attachment structures 140 (two are shown inFIG. 2B ) can be disposed on thesupport member 120. Eachattachment structure 140 can include aprojection 141 that extends away from thefirst surface 123. Theprojections 141 can be formed from any of a variety of materials in accordance with any of a variety of methods. For example, theprojections 141 can include a conductive material, such as copper or aluminum, disposed on thesupport member 120 in a process such as a chemical vapor deposition, physical vapor deposition, or electrochemical deposition process. Theprojections 141 can then be shaped using conventional etching techniques. Alternatively, theprojections 141 can include nonconductive materials, such as a solder mask material, an epoxy material, or an adhesive strip (e.g., a tape material). In one embodiment, theprojections 141 can include a flowable die attach material, as described in greater detail below with reference toFIGS. 3A-3E . In another embodiment, theprojections 141 can be formed integrally with thesupport member 120, for example during the initial manufacture of thesupport member 120. In any of these embodiments, theprojections 141 can be positioned to support a microelectronic substrate relative to thesupport member 120. -
FIG. 2C is a cross-sectional view of thesupport member 120 shown inFIG. 2B , withadhesive material portions 142 disposed on each of theprojections 141. Theadhesive materials portions 142 can include a conventional die attach material, such as QMI 536, available from Dexter Electronic Materials, a business of Loktite Corporation of Rocky Hills, Conn., or 2025D, available from Ablestik of Rancho Dominguez, Calif. In other embodiments, theadhesive material portions 142 can include other materials. For example, theadhesive material portions 142 can include adhesive tape strips, such as double-backed tape strips. In any of these embodiments, theadhesive material portions 142 can be selected to adhere to both theprojection 141 and a microelectronic substrate, as described in greater detail below with reference toFIG. 2D . - Referring now to
FIG. 2D , amicroelectronic substrate 130 can be connected to and/or carried by theattachment structures 140 by contacting themicroelectronic substrate 130 with theadhesive material portions 142 to form amicroelectronic package 110. Accordingly, theattachment structures 140 can include a first joint 143 at the interface with thesupport member 120, and a second joint 144 at the interface with themicroelectronic substrate 130. In some embodiments, the first joint 143 and the second joint 144 can be selected to have different strengths. For example, if thesupport member 120, themicroelectronic substrate 130, and/or or theattachment structure 140 have unequal coefficients of thermal expansion (CTEs), and this mismatch is large enough to cause the connection between thesupport member 120 and themicroelectronic substrate 130 to fail, it may be desirable to have the failure occur at the first joint 143 (where theattachment structure 140 joins the support member 120) rather than at the second joint 144 (where theattachment structure 140 joins the microelectronic substrate 130). In particular, if theattachment structure 140 can cause damage to the component from which it separates, it may be desirable to confine such damage to thesupport member 120 rather than allow themicroelectronic substrate 130 to be damaged. In one embodiment for which the strength of the first joint 143 is lower than the strength of the second joint 144, theprojections 141 can include the QMI 536 material referred to above, and theadhesive material portions 142 can include 2025D die attach adhesive. In other embodiments, other materials can be selected for theprojections 141 and theadhesive material portions 142. In any of these embodiments, theadhesive material portions 142 can include a material that is at least initially flowable and is disposed in its flowable state on theprojection 141. - In one aspect of an embodiment shown in
FIG. 2D , portions of theattachment structures 140 can include electrically conductive materials, but theattachment structures 140 do not provide a conductive link between thesupport member 120 and themicroelectronic substrate 130. For example, theprojections 141 can include an electrically conductive material while theadhesive material 142 includes an insulative material. In other embodiments, other portions of the attachment structures 140 (such as the projections 141) can be insulative so that theattachment structures 140 do not provide a conductive link between thesupport member 120 and themicroelectronic substrate 130. Instead, electrical communication between these components can be provided by separate conductive couplers, as described below with reference toFIG. 2E . - As shown in
FIG. 2E , themicroelectronic substrate 130 can be electrically connected to thesupport member 120 withconductive couplers 132, such as wire bonds. For example, theconductive couplers 132 can extend betweensubstrate bond pads 131 positioned on the lower surface of themicroelectronic substrate 130, and supportmember bond pads 122 positioned on thesecond surface 124 of thesupport member 120. Accordingly, theconductive couplers 132 can extend through theaperture 121 of thesupport member 120. Anencapsulant 111 can then be disposed over themicroelectronic substrate 130 and at least a portion of thesupport member 120 to protect the physical and electrical connections between themicroelectronic substrate 130 and thesupport member 120. Alternatively, theencapsulant 111 can be eliminated. For example, themicroelectronic substrate 130 and the associated electrical connections can be protected with a hollow cap disposed over thesupport member 120. - In another aspect of an embodiment shown in
FIG. 2E , a distance D1 between themicroelectronic substrate 130 and the support member 120 (i.e., the height of the attachment structure 140) can be selected to enhance the performance of thepackage 110. For example, in one embodiment, the distance D1 can be selected to be greater than 25 microns (the distance conventionally achievable with an epoxy bond) and, in a further aspect of this embodiment, the distance D1 can be selected to be 35 microns or greater. In still a further aspect of this embodiment, the distance D1 can be selected to be about 75 microns, or 100 microns, or greater to reduce the likelihood for filler material disposed in theencapsulant 111 to impinge on and damage themicroelectronic substrate 130. - In another aspect of an embodiment shown in
FIG. 2E , a distance D2 (by which theprojection 141 extends above the support member 120), and a distance D3 (by which theadhesive material volume 142 extends above the projection 141) can be selected in a variety of manners to achieve the overall separation distance D1 described above. For example, D2 can be relatively large and D3 relatively small to reduce the volume occupied by theadhesive material 142. In other embodiments, the relative values of D2 and D3 can be reversed. In one embodiment in which theprojection 141 is formed from an initially flowable material such as epoxy, the distance D2 can have a value of from about 8 microns to about 25 microns. - In yet another aspect of an embodiment described above with reference to
FIG. 2E , the lateral extent of theattachment structures 140 can be selected to enhance the performance of thepackage 110. For example, theattachment structures 140 can be positioned only beneath themicroelectronic substrate 130, rather than extending around the sides of themicroelectronic substrate 130 as typically occurs with some conventional epoxy bonds. An advantage of this arrangement, when compared to some conventional epoxy bonds is thatattachment structures 140 can be less likely to impose damaging stresses on themicroelectronic substrate 130. - In a further aspect of this embodiment, a lateral extent W1 of the
attachment structure 140 can be significantly less than a lateral extent W2 of the region of themicroelectronic substrate 130 that overlaps thesupport member 120. For example, in one embodiment, W1 can have a value of from about ⅓ to about ½ of the value of W2. A feature of this arrangement is that the volume of theattachment structure 140 can be reduced relative to the overall volume of theencapsulant 111. An advantage of this arrangement is that it can reduce or eliminate damage caused by CTE mismatch. For example, theencapsulant 111 may have a CTE that is more closely matched to that of themicroelectronic substrate 130 and/or thesupport member 120, while theattachment structure 140 may have a CTE quite different from that of themicroelectronic substrate 130 and/or thesupport member 120. Accordingly, by controlling the lateral extent W1 of theattachment structures 140, the fraction of the volume between thesupport member 120 and themicroelectronic substrate 130 occupied by theattachment structure 140 can be reduced compared with some conventional arrangements. As a result, theattachment structure 140 can be less likely to fail or cause themicroelectronic substrate 130 to fail when thepackage 110 undergoes thermal excursions. Another feature of this arrangement is that theattachment structure 140 can be recessed outwardly from the edge of theaperture 121. An advantage of this feature is that the potential high stress at the interface between theattachment structure 140 and theencapsulant 111 can be shifted outwardly and can be less likely than existing arrangements (such as that described above with reference toFIG. 1B ) to crack theencapsulant 111. -
FIGS. 3A-3E schematically illustrate a process for forming amicroelectronic package 110 generally similar to that described above with reference toFIGS. 2A-2E . In one aspect of this embodiment, the process can be performed by in-line die attach tools, such as are available from Datacon of Radfeld/Tyrole, Austria, or ESEC of Cham, Switzerland. In other embodiments, the process can be performed by other tools - Referring first to
FIG. 3A , the process can include providing asupport member 120 having anaperture 121. As shown inFIG. 3B , thesupport member 120 can be positioned beneath a dispensenozzle 350. The dispensenozzle 350 can dispose two quantities of afirst material 345 onto thesupport member 120, while thefirst material 345 is in a flowable state, to form twoprojections 341 extending away from thefirst surface 123 of thesupport member 120. Theprojections 341 can define, at least in part, correspondingattachment structures 340. In one embodiment, the dispensenozzle 350 can dispense a conventional die-attach material, such as QMI 536 or 2025D, described above. In other embodiments, the dispensenozzle 350 can dispose other initially flowable materials. In any of these embodiments, the amount of thefirst material 345 dispensed on thesupport member 120 and the distance D2 by which the resultingprojections 341 extend beyond thefirst surface 123 can be low enough that theprojections 341 maintain their shape without collapsing or slumping. For example, theprojections 341 can have a height of from about 8 microns to about 25 microns in one embodiment. - As shown in
FIG. 3C , the flowability of thefirst material 345 can be reduced or eliminated after it has been dispensed on thesupport member 120, for example, by applying heat to thefirst material 345. In one aspect of this embodiment, thefirst material 345 can be a thermoset material and can be partially cured (e.g., to B-stage) or fully cured. In a specific aspect of this embodiment, thefirst material 345 can be “snap cured”, for example by exposure to elevated temperatures from about 150° C. to about 200° C. for a period of three seconds or less. In other embodiments, thefirst material 345 can be exposed to other temperatures and/or can be exposed for other time periods, for example, time periods of up to about ten seconds. In still further embodiments, the flowability of thefirst material 345 can be reduced by other methods, for example, by cooling. In any of these embodiments, by at least reducing the flowability of thefirst material 345, thematerial 345 will tend to retain its shape and height and can more stably and securely support a second material, as described in greater detail below with reference toFIG. 3D . - Referring now to
FIG. 3D , asecond material 346 can be disposed on each of theprojections 341 while thesecond material 346 is in a flowable state to increase the height of thecorresponding attachment structures 340. In one embodiment, thesecond material 346 can have a composition identical to that of thefirst material 345. Alternatively, thesecond material 346 can have a different composition than that of thefirst material 345. In either embodiment, thesecond material 346 can be dispensed on theprojections 341 by the same dispensenozzle 350 that dispensed thefirst material 345, or by a different dispense nozzle. In any of these embodiments, thesecond material 346 can have adhesive properties, so as to adhere to thefirst material 345 and to themicroelectronic substrate 130, as described below with reference toFIG. 3E . - Referring now to
FIG. 3E , themicroelectronic substrate 130 can be attached to thesecond material 346 of theattachment structures 340. The resultingpackage 110 can then be encapsulated after themicroelectronic substrate 130 is electrically coupled to thesupport member 120. Accordingly, the foregoing process can include sequentially disposing first and second flowable materials to build up attachment structures having heights, widths, and bond strengths generally similar to those described above with reference toFIGS. 2A-2E . The in-line arrangement of this process can result in an efficient and effective package formation procedure. - In other embodiments, the attachment structures and packages described above with reference to
FIGS. 2A-3E can have other arrangements. For example, referring toFIG. 4 , thesupport member 120 can include a plurality ofattachment structures 440 that are arranged in discrete columns rather than continuous strips. Eachattachment structure 440 can include aprojection 441 formed, for example, from thefirst material 345. Alternatively, theprojections 441 can include non-flowable materials. Eachattachment structure 440 can further include asecond material 346 disposed on theprojection 441. Thesecond material 346 can be applied in a manner generally similar to any of those described above with reference toFIGS. 2A-3E . In one aspect of this embodiment, theattachment structures 440 can have a generally circular cross-sectional shape and in other embodiments, theattachment structure 440 can have other shapes. In one embodiment, theattachment structures 440 can be arranged in rows, and in other embodiments theattachment structures 440 can be arranged in other patterns or arrays. In any of these embodiments, theattachment structures 440 can be connected to a corresponding microelectronic substrate 130 (not shown inFIG. 4 ) in a manner generally similar to that described above. -
FIG. 5 is a cross-sectional view of apackage 510 having themicroelectronic substrate 130 connected to thesupport member 120 withattachment structures 540 in accordance with another embodiment of the invention. In one aspect of this embodiment, eachattachment structure 540 can include thefirst material 345, thesecond material 346 and athird material 547. In one aspect of this embodiment, the flowability of thefirst material 345 can be reduced before applying thesecond material 346, and the flowability of thesecond material 346 can be reduced before applying thethird material 547. Alternatively, thefirst material 345 can be replaced with a conductive or a nonconductive material disposed by processes generally similar to those described above with reference toFIG. 2B . In still further embodiments, theattachment structures 540 can include more than three sequentially disposed quantities of material to achieve the desired separation distance D1 and/or other characteristics. -
FIG. 6 illustrates apackage 610 having amicroelectronic substrate 630 supported on asupport member 620 in accordance with another embodiment of the invention. In one aspect of this embodiment, themicroelectronic substrate 630 can be attached to thesupport member 620 withattachment structures 640 having characteristics generally similar to any of those described above with reference toFIGS. 2A-5 . In a further aspect of this embodiment, thepackage 610 can have a “chip on board” configuration. Accordingly, thesupport member 620 can have afirst surface 623 and asecond surface 624 facing opposite from thefirst surface 623. Themicroelectronic substrate 630 can have afirst surface 634 and asecond surface 635 facing opposite thefirst surface 634 and facing toward thefirst surface 623 of thesupport member 620. Thefirst surface 634 of themicroelectronic substrate 630 can includesubstrate bond pads 631 which are connected with conductive couplers 632 (such as wire bonds) to corresponding supportmember bond pads 622 positioned on thefirst surface 623 of thesupport member 620. The physical and electrical connections between themicroelectronic substrate 630 and thesupport member 620 can be protected, for example, with an encapsulant, a shell, or a cap. -
FIG. 7 illustrates amicroelectronic package 710 having a plurality of microelectronic substrates connected to each other in accordance with another embodiment of the invention. In one aspect of this embodiment, thepackage 710 can include a firstmicroelectronic substrate 730 a havingfirst bond pads 731 a. A secondmicroelectronic substrate 730 b can be attached to the firstmicroelectronic substrate 730 a withattachment structures 740 having configurations generally similar to any of those described above with reference toFIGS. 2A-5 . The secondmicroelectronic substrate 730 b can includesecond bond pads 731 b connected to thefirst bond pads 731 a of the firstmicroelectronic substrate 730 a withconductive couplers 732, such as wire bonds.Solder balls 733 or other conductive devices can provide for electrical communication to and from thepackage 710. - From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
Claims (39)
1-115. (canceled)
116. A method for forming a microelectronic package, comprising:
forming an attachment structure by applying a quantity of adhesive to a projection extending from an adjacent surface of one of a support member and a microelectronic substrate;
connecting the adhesive to the other of the support member and the microelectronic substrate with the attachment structure providing no electrically conductive link between the microelectronic substrate and the support member; and
electrically connecting the microelectronic substrate and the support member.
117. The method of claim 116 wherein forming the attachment structure includes forming the attachment structure by applying the quantity of adhesive to the projection extending from the adjacent surface of the support member.
118. The method of claim 116 , further comprising forming the projection by disposing a material on the adjacent surface.
119. The method of claim 118 wherein disposing the material includes disposing the material to a thickness of from about 8 microns to about 25 microns.
120. The method of claim 118 wherein disposing the material includes disposing the material along an elongated axis generally in the plane of the surface.
121. The method of claim 118 wherein disposing the material includes disposing the material in a volume having a generally circular cross-sectional shape.
122. The method of claim 118 wherein disposing the material includes disposing the material at a plurality of sites to form a corresponding plurality of projections.
123. The method of claim 118 wherein the material forming the projection includes a first quantity of material, and wherein the adhesive includes a second quantity of material, and wherein the method further comprises:
selecting the first quantity of material to have a first composition;
selecting the second quantity of material to have a second composition different than the first composition;
forming a first joint between the first quantity of material and the support member, the first joint having a first bond strength; and
forming a second joint between the second quantity of material and the microelectronic substrate, the second joint having a second bond strength, the second bond strength being greater than the first bond strength.
124. The method of claim 116 wherein the projection includes a first quantity of material and wherein the adhesive includes a second quantity of material, and wherein the method further comprises selecting the second quantity of material to have a composition at least approximately the same as a composition of the first quantity of material.
125. The method of claim 116 wherein the projection includes a first quantity of material and wherein the adhesive includes a second quantity of material, and wherein the method further comprises selecting the second quantity of material to have a composition different than a composition of the first quantity of material.
126. The method of claim 116 wherein the projection includes a first quantity of material forming a first joint having a first bond strength at an interface with the support member, and wherein the method further comprises selecting the adhesive to include a second quantity of material having a second bond strength at a second joint with the microelectronic substrate, the second bond strength being greater than the first bond strength.
127. The method of claim 116 , further comprising forming the projection by disposing a material on the surface while the material is at least partially flowable and then at least partially reducing a flowability of the material.
128. The method of claim 127 wherein at least partially reducing the flowability of the material includes at least partially curing the material.
129. The method of claim 127 wherein at least partially reducing the flowability of the material includes at least partially curing the material for about three seconds or less.
130. The method of claim 127 wherein at least partially reducing the flowability of the material includes at least partially curing the material for about ten seconds or less.
131. The method of claim 127 wherein the material forming the projection includes a first quantity of material, and wherein applying the adhesive includes applying a second quantity of material while it is at least partially flowable, and wherein the method further comprises:
at least partially reducing a flowability of the second quantity of material; and
applying a third quantity of material to the second quantity of material while the third quantity of material is at least partially flowable, wherein connecting the attachment structure to the other of the microelectronic substrate and the support member includes contacting the third quantity of material with the other of the microelectronic substrate and the support member.
132. The method of claim 116 wherein the adhesive is the second of two adhesive materials, and wherein the method further comprises:
selecting a first adhesive material to have a composition at least generally the same as a composition of the second adhesive material; and
forming the projection by disposing the first adhesive material on the surface while the first adhesive material is at least partially flowable and then at least partially reducing a flowability of the first adhesive material before applying the second adhesive material.
133. The method of claim 116 wherein the adhesive material is the second of two adhesive materials, and wherein the method further comprises:
selecting a first adhesive material to have a composition different than a composition of the second adhesive material; and
forming the projection by disposing the first adhesive material on the surface while the first adhesive material is at least partially flowable and then at least partially reducing a flowability of the first adhesive material before applying the second adhesive material.
134. The method of claim 116 , further comprising selecting the projection to include an electrically conductive material.
135. The method of claim 116 , further comprising selecting the projection to include at least one of copper and aluminum.
136. The method of claim 116 , further comprising selecting the projection to include an electrically non-conductive material.
137. The method of claim 116 , further comprising selecting the projection to include a solder mask material.
138. The method of claim 116 , further comprising selecting the projection to include an epoxy.
139. The method of claim 116 , further comprising selecting the adhesive to include an epoxy.
140. The method of claim 116 wherein electrically connecting the microelectronic substrate and the support member includes wire bonding the microelectronic substrate and the support member.
141. The method of claim 116 , further comprising disposing an encapsulating material around at least a portion of at least one of the microelectronic substrate, the support member and the attachment structure.
142. The method of claim 116 , further comprising selecting both the projection and the adhesive to include an epoxy.
143. The method of claim 116 , wherein the projection includes a first material, the adhesive includes a second material, and the method further comprises adding at least a third quantity of material to the attachment structure, with the attachment structure projecting from the surface by a distance of at least about 75 microns.
144. A method for forming a microelectronic package, comprising:
forming an attachment structure by applying a quantity of adhesive to a projection extending from a surface of one of a first microelectronic substrate and a second a microelectronic substrate;
connecting the adhesive the other of the first microelectronic substrate and the second microelectronic substrate with the attachment structure providing no electrically conductive link between the first and second microelectronic substrates; and
electrically connecting the first and second microelectronic substrates to each other.
145. The method of claim 144 , further comprising:
forming the projection by disposing a first quantity of material on the one microelectronic substrate while the first quantity of material is at least partially flowable;
at least partially reducing a flowability of the first quantity of material; and
wherein applying the adhesive includes applying a second quantity of material to the first quantity of material while the second quantity of material is at least partially flowable and after at least partially reducing the flowability of the first quantity of material.
146. The method of claim 145 wherein at least partially reducing a flowability of the first quantity of material includes at least partially curing the first quantity of material.
147. The method of claim 145 wherein at least partially reducing a flowability of the first quantity of material includes at least partially curing the first quantity of material for about three seconds or less.
148. The method of claim 145 wherein disposing the first quantity of material includes disposing the first quantity of material to a thickness of from about 8 microns to about 25 microns.
149. The method of claim 145 wherein disposing the first quantity of material includes disposing a plurality of first quantities of material at a corresponding plurality of sites to form a corresponding plurality of attachment members.
150. The method of claim 145 wherein electrically connecting the first and second microelectronic substrates includes wire bonding the microelectronic substrates to each other.
151. The method of claim 145 , further comprising disposing an encapsulating material around at least a portion of at least one of the first and second microelectronic substrates.
152. The method of claim 145 , further comprising selecting at least one of the first and second quantities of material to include an epoxy.
153. The method of claim 145 , further comprising selecting the first quantity of material to have a first composition and the second quantity of material to have a second composition at least approximately the same as the first composition.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/480,771 US20070020811A1 (en) | 2002-04-04 | 2006-06-30 | Method and apparatus for attaching microelectronic substrates and support members |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/116,645 US7109588B2 (en) | 2002-04-04 | 2002-04-04 | Method and apparatus for attaching microelectronic substrates and support members |
US10/926,434 US7091064B2 (en) | 2002-04-04 | 2004-08-24 | Method and apparatus for attaching microelectronic substrates and support members |
US11/480,771 US20070020811A1 (en) | 2002-04-04 | 2006-06-30 | Method and apparatus for attaching microelectronic substrates and support members |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/926,434 Continuation US7091064B2 (en) | 2002-04-04 | 2004-08-24 | Method and apparatus for attaching microelectronic substrates and support members |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070020811A1 true US20070020811A1 (en) | 2007-01-25 |
Family
ID=28674041
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/116,645 Expired - Fee Related US7109588B2 (en) | 2002-04-04 | 2002-04-04 | Method and apparatus for attaching microelectronic substrates and support members |
US10/926,434 Expired - Fee Related US7091064B2 (en) | 2002-04-04 | 2004-08-24 | Method and apparatus for attaching microelectronic substrates and support members |
US11/480,755 Expired - Lifetime US7615871B2 (en) | 2002-04-04 | 2006-06-30 | Method and apparatus for attaching microelectronic substrates and support members |
US11/480,771 Abandoned US20070020811A1 (en) | 2002-04-04 | 2006-06-30 | Method and apparatus for attaching microelectronic substrates and support members |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/116,645 Expired - Fee Related US7109588B2 (en) | 2002-04-04 | 2002-04-04 | Method and apparatus for attaching microelectronic substrates and support members |
US10/926,434 Expired - Fee Related US7091064B2 (en) | 2002-04-04 | 2004-08-24 | Method and apparatus for attaching microelectronic substrates and support members |
US11/480,755 Expired - Lifetime US7615871B2 (en) | 2002-04-04 | 2006-06-30 | Method and apparatus for attaching microelectronic substrates and support members |
Country Status (1)
Country | Link |
---|---|
US (4) | US7109588B2 (en) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7109588B2 (en) * | 2002-04-04 | 2006-09-19 | Micron Technology, Inc. | Method and apparatus for attaching microelectronic substrates and support members |
DE102004037610B3 (en) * | 2004-08-03 | 2006-03-16 | Infineon Technologies Ag | Integrated circuit connection method e.g. for substrate and circuit assembly, involves planning flexible intermediate layer on integrated circuit and or substrate with flexible layer structured in raised and lower ranges |
EP1630865A1 (en) * | 2004-08-17 | 2006-03-01 | Optimum Care International Tech. Inc. | Adhesion of a Chip on a leadframe |
TWI241697B (en) * | 2005-01-06 | 2005-10-11 | Siliconware Precision Industries Co Ltd | Semiconductor package and fabrication method thereof |
US8278751B2 (en) * | 2005-02-08 | 2012-10-02 | Micron Technology, Inc. | Methods of adhering microfeature workpieces, including a chip, to a support member |
US20070080435A1 (en) * | 2005-10-06 | 2007-04-12 | Chun-Hung Lin | Semiconductor packaging process and carrier for semiconductor package |
US8072547B2 (en) * | 2006-03-31 | 2011-12-06 | Conexant Systems, Inc. | Comb filter that utilizes host memory |
TWI378547B (en) * | 2007-09-14 | 2012-12-01 | Chipmos Technologies Inc | Multi-chip stacked package structure |
TWI380424B (en) * | 2009-02-27 | 2012-12-21 | Walton Advanced Eng Inc | Window type semiconductor package |
KR101630394B1 (en) * | 2010-03-08 | 2016-06-24 | 삼성전자주식회사 | Package substrate, semiconductor package comprising the same and method for fabricating the semiconductor package |
US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8525327B2 (en) | 2011-10-03 | 2013-09-03 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
WO2013052373A1 (en) | 2011-10-03 | 2013-04-11 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8659142B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
EP2766928A1 (en) | 2011-10-03 | 2014-08-20 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
EP2769409A1 (en) | 2011-10-03 | 2014-08-27 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
US8345441B1 (en) | 2011-10-03 | 2013-01-01 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8653646B2 (en) | 2011-10-03 | 2014-02-18 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
US8659140B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
WO2017107030A1 (en) * | 2015-12-22 | 2017-06-29 | Intel Corporation | Eliminating die shadow effects by dummy die beams for solder joint reliability improvement |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
US11164804B2 (en) | 2019-07-23 | 2021-11-02 | International Business Machines Corporation | Integrated circuit (IC) device package lid attach utilizing nano particle metallic paste |
Citations (88)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4563811A (en) * | 1983-10-28 | 1986-01-14 | At&T Technologies, Inc. | Method of making a dual-in-line package |
US5128831A (en) * | 1991-10-31 | 1992-07-07 | Micron Technology, Inc. | High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias |
US5139973A (en) * | 1990-12-17 | 1992-08-18 | Allegro Microsystems, Inc. | Method for making a semiconductor package with the distance between a lead frame die pad and heat spreader determined by the thickness of an intermediary insulating sheet |
US5208188A (en) * | 1989-10-02 | 1993-05-04 | Advanced Micro Devices, Inc. | Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process |
US5518957A (en) * | 1991-10-10 | 1996-05-21 | Samsung Electronics Co., Ltd. | Method for making a thin profile semiconductor package |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
US5593927A (en) * | 1993-10-14 | 1997-01-14 | Micron Technology, Inc. | Method for packaging semiconductor dice |
US5614766A (en) * | 1991-09-30 | 1997-03-25 | Rohm Co., Ltd. | Semiconductor device with stacked alternate-facing chips |
US5656857A (en) * | 1994-05-12 | 1997-08-12 | Kabushiki Kaisha Toshiba | Semiconductor device with insulating resin layer and substrate having low sheet resistance |
US5739585A (en) * | 1995-11-27 | 1998-04-14 | Micron Technology, Inc. | Single piece package for semiconductor die |
USD394844S (en) * | 1997-04-25 | 1998-06-02 | Micron Technology, Inc. | Temporary package for semiconductor dice |
US5855821A (en) * | 1995-12-22 | 1999-01-05 | Johnson Matthey, Inc. | Materials for semiconductor device assemblies |
US5866953A (en) * | 1996-05-24 | 1999-02-02 | Micron Technology, Inc. | Packaged die on PCB with heat sink encapsulant |
US5871808A (en) * | 1996-12-20 | 1999-02-16 | Mcms, Inc. | Method for preserving solder paste in the manufacturing of printed circuit board assemblies |
US5883426A (en) * | 1996-04-18 | 1999-03-16 | Nec Corporation | Stack module |
US5891753A (en) * | 1997-01-24 | 1999-04-06 | Micron Technology, Inc. | Method and apparatus for packaging flip chip bare die on printed circuit boards |
US5893726A (en) * | 1997-12-15 | 1999-04-13 | Micron Technology, Inc. | Semiconductor package with pre-fabricated cover and method of fabrication |
US5920118A (en) * | 1996-12-18 | 1999-07-06 | Hyundai Electronics Industries Co., Ltd. | Chip-size package semiconductor |
US5925930A (en) * | 1996-05-21 | 1999-07-20 | Micron Technology, Inc. | IC contacts with palladium layer and flexible conductive epoxy bumps |
US5933713A (en) * | 1998-04-06 | 1999-08-03 | Micron Technology, Inc. | Method of forming overmolded chip scale package and resulting product |
US5938956A (en) * | 1996-09-10 | 1999-08-17 | Micron Technology, Inc. | Circuit and method for heating an adhesive to package or rework a semiconductor die |
US5946553A (en) * | 1991-06-04 | 1999-08-31 | Micron Technology, Inc. | Process for manufacturing a semiconductor package with bi-substrate die |
US5956236A (en) * | 1997-11-25 | 1999-09-21 | Micron Technology, Inc. | Integrated circuit package support system |
US5958100A (en) * | 1993-06-03 | 1999-09-28 | Micron Technology, Inc. | Process of making a glass semiconductor package |
US6017776A (en) * | 1997-04-29 | 2000-01-25 | Micron Technology, Inc. | Method of attaching a leadframe to singulated semiconductor dice |
US6020629A (en) * | 1998-06-05 | 2000-02-01 | Micron Technology, Inc. | Stacked semiconductor package and method of fabrication |
US6025728A (en) * | 1997-04-25 | 2000-02-15 | Micron Technology, Inc. | Semiconductor package with wire bond protective member |
US6028365A (en) * | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
US6046496A (en) * | 1997-11-04 | 2000-04-04 | Micron Technology Inc | Chip package |
US6049125A (en) * | 1997-12-29 | 2000-04-11 | Micron Technology, Inc. | Semiconductor package with heat sink and method of fabrication |
US6048744A (en) * | 1997-09-15 | 2000-04-11 | Micron Technology, Inc. | Integrated circuit package alignment feature |
US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
US6051878A (en) * | 1997-03-10 | 2000-04-18 | Micron Technology, Inc. | Method of constructing stacked packages |
US6063647A (en) * | 1997-12-08 | 2000-05-16 | 3M Innovative Properties Company | Method for making circuit elements for a z-axis interconnect |
US6072236A (en) * | 1996-03-07 | 2000-06-06 | Micron Technology, Inc. | Micromachined chip scale package |
US6072233A (en) * | 1998-05-04 | 2000-06-06 | Micron Technology, Inc. | Stackable ball grid array package |
US6075288A (en) * | 1998-06-08 | 2000-06-13 | Micron Technology, Inc. | Semiconductor package having interlocking heat sinks and method of fabrication |
US6089920A (en) * | 1998-05-04 | 2000-07-18 | Micron Technology, Inc. | Modular die sockets with flexible interconnects for packaging bare semiconductor die |
US6097087A (en) * | 1997-10-31 | 2000-08-01 | Micron Technology, Inc. | Semiconductor package including flex circuit, interconnects and dense array external contacts |
US6103547A (en) * | 1997-01-17 | 2000-08-15 | Micron Technology, Inc. | High speed IC package configuration |
US6107680A (en) * | 1995-01-04 | 2000-08-22 | Micron Technology, Inc. | Packaging for bare dice employing EMR-sensitive adhesives |
US6107122A (en) * | 1997-08-04 | 2000-08-22 | Micron Technology, Inc. | Direct die contact (DDC) semiconductor package |
US6172419B1 (en) * | 1998-02-24 | 2001-01-09 | Micron Technology, Inc. | Low profile ball grid array package |
US6175149B1 (en) * | 1998-02-13 | 2001-01-16 | Micron Technology, Inc. | Mounting multiple semiconductor dies in a package |
US6175159B1 (en) * | 1997-07-16 | 2001-01-16 | Oki Electric Industry Co., Ltd. | Semiconductor package |
US6184465B1 (en) * | 1998-11-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor package |
US6194250B1 (en) * | 1998-09-14 | 2001-02-27 | Motorola, Inc. | Low-profile microelectronic package |
US6198172B1 (en) * | 1997-02-20 | 2001-03-06 | Micron Technology, Inc. | Semiconductor chip package |
US6208519B1 (en) * | 1999-08-31 | 2001-03-27 | Micron Technology, Inc. | Thermally enhanced semiconductor package |
US6210992B1 (en) * | 1999-08-31 | 2001-04-03 | Micron Technology, Inc. | Controlling packaging encapsulant leakage |
US6215175B1 (en) * | 1998-07-06 | 2001-04-10 | Micron Technology, Inc. | Semiconductor package having metal foil die mounting plate |
US6212767B1 (en) * | 1999-08-31 | 2001-04-10 | Micron Technology, Inc. | Assembling a stacked die package |
US6218731B1 (en) * | 1999-05-21 | 2001-04-17 | Siliconware Precision Industries Co., Ltd. | Tiny ball grid array package |
US6225689B1 (en) * | 1998-08-21 | 2001-05-01 | Micron Technology, Inc. | Low profile multi-IC chip package connector |
US6228548B1 (en) * | 1998-02-27 | 2001-05-08 | Micron Technology, Inc. | Method of making a multichip semiconductor package |
US6229202B1 (en) * | 2000-01-10 | 2001-05-08 | Micron Technology, Inc. | Semiconductor package having downset leadframe for reducing package bow |
US6235554B1 (en) * | 1995-11-27 | 2001-05-22 | Micron Technology, Inc. | Method for fabricating stackable chip scale semiconductor package |
US6259153B1 (en) * | 1998-08-20 | 2001-07-10 | Micron Technology, Inc. | Transverse hybrid LOC package |
US6261865B1 (en) * | 1998-10-06 | 2001-07-17 | Micron Technology, Inc. | Multi chip semiconductor package and method of construction |
US6271058B1 (en) * | 1998-01-06 | 2001-08-07 | Nec Corporation | Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board |
US6277671B1 (en) * | 1998-10-20 | 2001-08-21 | Micron Technology, Inc. | Methods of forming integrated circuit packages |
US6281577B1 (en) * | 1996-06-28 | 2001-08-28 | Pac Tech-Packaging Technologies Gmbh | Chips arranged in plurality of planes and electrically connected to one another |
US6342728B2 (en) * | 1996-03-22 | 2002-01-29 | Hitachi, Ltd. | Semiconductor device and manufacturing method thereof |
US6365434B1 (en) * | 2000-06-28 | 2002-04-02 | Micron Technology, Inc. | Method and apparatus for reduced flash encapsulation of microelectronic devices |
US6385049B1 (en) * | 2001-07-05 | 2002-05-07 | Walsin Advanced Electronics Ltd | Multi-board BGA package |
US6396129B1 (en) * | 2001-03-05 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package |
US6400033B1 (en) * | 2000-06-01 | 2002-06-04 | Amkor Technology, Inc. | Reinforcing solder connections of electronic devices |
US6528722B2 (en) * | 1998-07-31 | 2003-03-04 | Siliconware Precision Industries Co., Ltd. | Ball grid array semiconductor package with exposed base layer |
US6528408B2 (en) * | 2001-05-21 | 2003-03-04 | Micron Technology, Inc. | Method for bumped die and wire bonded board-on-chip package |
US6548376B2 (en) * | 2001-08-30 | 2003-04-15 | Micron Technology, Inc. | Methods of thinning microelectronic workpieces |
US6548757B1 (en) * | 2000-08-28 | 2003-04-15 | Micron Technology, Inc. | Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies |
US6552910B1 (en) * | 2000-06-28 | 2003-04-22 | Micron Technology, Inc. | Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture |
US6558600B1 (en) * | 2000-05-04 | 2003-05-06 | Micron Technology, Inc. | Method for packaging microelectronic substrates |
US6560117B2 (en) * | 2000-06-28 | 2003-05-06 | Micron Technology, Inc. | Packaged microelectronic die assemblies and methods of manufacture |
US6561479B1 (en) * | 2000-08-23 | 2003-05-13 | Micron Technology, Inc. | Small scale actuators and methods for their formation and use |
US6564979B2 (en) * | 2001-07-18 | 2003-05-20 | Micron Technology, Inc. | Method and apparatus for dispensing adhesive on microelectronic substrate supports |
US6576494B1 (en) * | 2000-06-28 | 2003-06-10 | Micron Technology, Inc. | Recessed encapsulated microelectronic devices and methods for formation |
US6576495B1 (en) * | 2000-08-30 | 2003-06-10 | Micron Technology, Inc. | Microelectronic assembly with pre-disposed fill material and associated method of manufacture |
US6589820B1 (en) * | 2000-06-16 | 2003-07-08 | Micron Technology, Inc. | Method and apparatus for packaging a microelectronic die |
US6607937B1 (en) * | 2000-08-23 | 2003-08-19 | Micron Technology, Inc. | Stacked microelectronic dies and methods for stacking microelectronic dies |
US6673649B1 (en) * | 2002-07-05 | 2004-01-06 | Micron Technology, Inc. | Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages |
US20040067606A1 (en) * | 2002-10-02 | 2004-04-08 | Fehr Gerald K. | Method for stack-packaging integrated circuit die using at least one die in the package as a spacer |
US6724076B1 (en) * | 1999-11-15 | 2004-04-20 | Infineon Technologies Ag | Package for a semiconductor chip |
US20050006743A1 (en) * | 2003-07-01 | 2005-01-13 | Kim Tae-Hyun | In-line apparatus and method for manufacturing double-sided stacked multi-chip packages |
US6844618B2 (en) * | 2002-04-04 | 2005-01-18 | Micron Technology, Inc. | Microelectronic package with reduced underfill and methods for forming such packages |
US6906424B2 (en) * | 2002-08-02 | 2005-06-14 | Micron Technology, Inc. | Semiconductor package and method producing same |
US20060177970A1 (en) * | 2005-02-08 | 2006-08-10 | Micron Technology, Inc. | Methods of Adhering Microfeature Workpieces, Including A Chip, To A Support Member |
US7091064B2 (en) * | 2002-04-04 | 2006-08-15 | Micron Technology, Inc. | Method and apparatus for attaching microelectronic substrates and support members |
Family Cites Families (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE36469E (en) | 1988-09-30 | 1999-12-28 | Micron Technology, Inc. | Packaging for semiconductor logic devices |
US5252857A (en) | 1991-08-05 | 1993-10-12 | International Business Machines Corporation | Stacked DCA memory chips |
US5422435A (en) * | 1992-05-22 | 1995-06-06 | National Semiconductor Corporation | Stacked multi-chip modules and method of manufacturing |
US5677566A (en) | 1995-05-08 | 1997-10-14 | Micron Technology, Inc. | Semiconductor chip package |
US5696033A (en) | 1995-08-16 | 1997-12-09 | Micron Technology, Inc. | Method for packaging a semiconductor die |
US5691567A (en) | 1995-09-19 | 1997-11-25 | National Semiconductor Corporation | Structure for attaching a lead frame to a heat spreader/heat slug structure |
US5851845A (en) | 1995-12-18 | 1998-12-22 | Micron Technology, Inc. | Process for packaging a semiconductor die using dicing and testing |
US5733800A (en) | 1996-05-21 | 1998-03-31 | Micron Technology, Inc. | Underfill coating for LOC package |
JP3195236B2 (en) | 1996-05-30 | 2001-08-06 | 株式会社日立製作所 | Wiring tape having adhesive film, semiconductor device and manufacturing method |
JP2870497B2 (en) | 1996-08-01 | 1999-03-17 | 日本電気株式会社 | Semiconductor element mounting method |
USD402638S (en) | 1997-04-25 | 1998-12-15 | Micron Technology, Inc. | Temporary package for semiconductor dice |
US6159764A (en) | 1997-07-02 | 2000-12-12 | Micron Technology, Inc. | Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages |
US5955777A (en) | 1997-07-02 | 1999-09-21 | Micron Technology, Inc. | Lead frame assemblies with voltage reference plane and IC packages including same |
US5986209A (en) | 1997-07-09 | 1999-11-16 | Micron Technology, Inc. | Package stack via bottom leaded plastic (BLP) packaging |
US6114769A (en) | 1997-07-18 | 2000-09-05 | Mcms, Inc. | Solder paste brick |
US5989941A (en) | 1997-12-12 | 1999-11-23 | Micron Technology, Inc. | Encapsulated integrated circuit packaging |
US5994784A (en) | 1997-12-18 | 1999-11-30 | Micron Technology, Inc. | Die positioning in integrated circuit packaging |
US6117382A (en) | 1998-02-05 | 2000-09-12 | Micron Technology, Inc. | Method for encasing array packages |
US6297547B1 (en) | 1998-02-13 | 2001-10-02 | Micron Technology Inc. | Mounting multiple semiconductor dies in a package |
US6314639B1 (en) | 1998-02-23 | 2001-11-13 | Micron Technology, Inc. | Chip scale package with heat spreader and method of manufacture |
US6002165A (en) | 1998-02-23 | 1999-12-14 | Micron Technology, Inc. | Multilayered lead frame for semiconductor packages |
US6501157B1 (en) | 1998-04-15 | 2002-12-31 | Micron Technology, Inc. | Substrate for accepting wire bonded or flip-chip components |
US5990566A (en) | 1998-05-20 | 1999-11-23 | Micron Technology, Inc. | High density semiconductor package |
US6008070A (en) | 1998-05-21 | 1999-12-28 | Micron Technology, Inc. | Wafer level fabrication and assembly of chip scale packages |
JP2000156435A (en) * | 1998-06-22 | 2000-06-06 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
US6291894B1 (en) | 1998-08-31 | 2001-09-18 | Micron Technology, Inc. | Method and apparatus for a semiconductor package for vertical surface mounting |
US6326687B1 (en) | 1998-09-01 | 2001-12-04 | Micron Technology, Inc. | IC package with dual heat spreaders |
US6515355B1 (en) | 1998-09-02 | 2003-02-04 | Micron Technology, Inc. | Passivation layer for packaged integrated circuits |
US6117797A (en) | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Attachment method for heat sinks and devices involving removal of misplaced encapsulant |
US6084297A (en) | 1998-09-03 | 2000-07-04 | Micron Technology, Inc. | Cavity ball grid array apparatus |
US6743319B2 (en) | 1998-09-30 | 2004-06-01 | Paralec Inc. | Adhesiveless transfer lamination method and materials for producing electronic circuits |
US6008074A (en) | 1998-10-01 | 1999-12-28 | Micron Technology, Inc. | Method of forming a synchronous-link dynamic random access memory edge-mounted device |
US6303985B1 (en) | 1998-11-12 | 2001-10-16 | Micron Technology, Inc. | Semiconductor lead frame and package with stiffened mounting paddle |
US6455354B1 (en) * | 1998-12-30 | 2002-09-24 | Micron Technology, Inc. | Method of fabricating tape attachment chip-on-board assemblies |
US6541872B1 (en) * | 1999-01-11 | 2003-04-01 | Micron Technology, Inc. | Multi-layered adhesive for attaching a semiconductor die to a substrate |
US6310390B1 (en) | 1999-04-08 | 2001-10-30 | Micron Technology, Inc. | BGA package and method of fabrication |
US6118176A (en) | 1999-04-26 | 2000-09-12 | Advanced Semiconductor Engineering, Inc. | Stacked chip assembly utilizing a lead frame |
US6709968B1 (en) | 2000-08-16 | 2004-03-23 | Micron Technology, Inc. | Microelectronic device with package with conductive elements and associated method of manufacture |
US6670719B2 (en) | 1999-08-25 | 2003-12-30 | Micron Technology, Inc. | Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture |
US6294839B1 (en) | 1999-08-30 | 2001-09-25 | Micron Technology, Inc. | Apparatus and methods of packaging and testing die |
US6303981B1 (en) | 1999-09-01 | 2001-10-16 | Micron Technology, Inc. | Semiconductor package having stacked dice and leadframes and method of fabrication |
US6316727B1 (en) * | 1999-10-07 | 2001-11-13 | United Microelectronics Corp. | Multi-chip semiconductor package |
US6261623B1 (en) * | 1999-10-21 | 2001-07-17 | Hickory Specialties, Inc. | Method for making a liquid smoke coloring agent solution |
JP2001127246A (en) * | 1999-10-29 | 2001-05-11 | Fujitsu Ltd | Semiconductor device |
US6329220B1 (en) | 1999-11-23 | 2001-12-11 | Micron Technology, Inc. | Packages for semiconductor die |
US6331453B1 (en) | 1999-12-16 | 2001-12-18 | Micron Technology, Inc. | Method for fabricating semiconductor packages using mold tooling fixture with flash control cavities |
US6414396B1 (en) * | 2000-01-24 | 2002-07-02 | Amkor Technology, Inc. | Package for stacked integrated circuits |
JP3491595B2 (en) * | 2000-02-25 | 2004-01-26 | ソニーケミカル株式会社 | Anisotropic conductive adhesive film |
JP2001257307A (en) * | 2000-03-09 | 2001-09-21 | Sharp Corp | Semiconductor device |
US6265763B1 (en) * | 2000-03-14 | 2001-07-24 | Siliconware Precision Industries Co., Ltd. | Multi-chip integrated circuit package structure for central pad chip |
US6437446B1 (en) * | 2000-03-16 | 2002-08-20 | Oki Electric Industry Co., Ltd. | Semiconductor device having first and second chips |
US6656769B2 (en) | 2000-05-08 | 2003-12-02 | Micron Technology, Inc. | Method and apparatus for distributing mold material in a mold for packaging microelectronic devices |
JP3701542B2 (en) * | 2000-05-10 | 2005-09-28 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
US6326698B1 (en) | 2000-06-08 | 2001-12-04 | Micron Technology, Inc. | Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices |
US6501170B1 (en) * | 2000-06-09 | 2002-12-31 | Micron Technology, Inc. | Substrates and assemblies including pre-applied adhesion promoter |
TW445610B (en) * | 2000-06-16 | 2001-07-11 | Siliconware Precision Industries Co Ltd | Stacked-die packaging structure |
US6503776B2 (en) * | 2001-01-05 | 2003-01-07 | Advanced Semiconductor Engineering, Inc. | Method for fabricating stacked chip package |
US20030134451A1 (en) * | 2002-01-14 | 2003-07-17 | Picta Technology, Inc. | Structure and process for packaging back-to-back chips |
US6622380B1 (en) | 2002-02-12 | 2003-09-23 | Micron Technology, Inc. | Methods for manufacturing microelectronic devices and methods for mounting microelectronic packages to circuit boards |
US6885093B2 (en) * | 2002-02-28 | 2005-04-26 | Freescale Semiconductor, Inc. | Stacked die semiconductor device |
US6753613B2 (en) * | 2002-03-13 | 2004-06-22 | Intel Corporation | Stacked dice standoffs |
KR100429885B1 (en) * | 2002-05-09 | 2004-05-03 | 삼성전자주식회사 | Multi-chip package improving heat spread characteristics and manufacturing method the same |
US6841858B2 (en) * | 2002-09-27 | 2005-01-11 | St Assembly Test Services Pte Ltd. | Leadframe for die stacking applications and related die stacking concepts |
KR100477020B1 (en) * | 2002-12-16 | 2005-03-21 | 삼성전자주식회사 | Multi chip package |
US20050230821A1 (en) * | 2004-04-15 | 2005-10-20 | Kheng Lee T | Semiconductor packages, and methods of forming semiconductor packages |
-
2002
- 2002-04-04 US US10/116,645 patent/US7109588B2/en not_active Expired - Fee Related
-
2004
- 2004-08-24 US US10/926,434 patent/US7091064B2/en not_active Expired - Fee Related
-
2006
- 2006-06-30 US US11/480,755 patent/US7615871B2/en not_active Expired - Lifetime
- 2006-06-30 US US11/480,771 patent/US20070020811A1/en not_active Abandoned
Patent Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4563811A (en) * | 1983-10-28 | 1986-01-14 | At&T Technologies, Inc. | Method of making a dual-in-line package |
US5208188A (en) * | 1989-10-02 | 1993-05-04 | Advanced Micro Devices, Inc. | Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process |
US5139973A (en) * | 1990-12-17 | 1992-08-18 | Allegro Microsystems, Inc. | Method for making a semiconductor package with the distance between a lead frame die pad and heat spreader determined by the thickness of an intermediary insulating sheet |
US6020624A (en) * | 1991-06-04 | 2000-02-01 | Micron Technology, Inc. | Semiconductor package with bi-substrate die |
US5946553A (en) * | 1991-06-04 | 1999-08-31 | Micron Technology, Inc. | Process for manufacturing a semiconductor package with bi-substrate die |
US5614766A (en) * | 1991-09-30 | 1997-03-25 | Rohm Co., Ltd. | Semiconductor device with stacked alternate-facing chips |
US5518957A (en) * | 1991-10-10 | 1996-05-21 | Samsung Electronics Co., Ltd. | Method for making a thin profile semiconductor package |
US5128831A (en) * | 1991-10-31 | 1992-07-07 | Micron Technology, Inc. | High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
US5958100A (en) * | 1993-06-03 | 1999-09-28 | Micron Technology, Inc. | Process of making a glass semiconductor package |
US5593927A (en) * | 1993-10-14 | 1997-01-14 | Micron Technology, Inc. | Method for packaging semiconductor dice |
US5656857A (en) * | 1994-05-12 | 1997-08-12 | Kabushiki Kaisha Toshiba | Semiconductor device with insulating resin layer and substrate having low sheet resistance |
US6107680A (en) * | 1995-01-04 | 2000-08-22 | Micron Technology, Inc. | Packaging for bare dice employing EMR-sensitive adhesives |
US6235554B1 (en) * | 1995-11-27 | 2001-05-22 | Micron Technology, Inc. | Method for fabricating stackable chip scale semiconductor package |
US5739585A (en) * | 1995-11-27 | 1998-04-14 | Micron Technology, Inc. | Single piece package for semiconductor die |
US5855821A (en) * | 1995-12-22 | 1999-01-05 | Johnson Matthey, Inc. | Materials for semiconductor device assemblies |
US6072236A (en) * | 1996-03-07 | 2000-06-06 | Micron Technology, Inc. | Micromachined chip scale package |
US6342728B2 (en) * | 1996-03-22 | 2002-01-29 | Hitachi, Ltd. | Semiconductor device and manufacturing method thereof |
US5883426A (en) * | 1996-04-18 | 1999-03-16 | Nec Corporation | Stack module |
US5925930A (en) * | 1996-05-21 | 1999-07-20 | Micron Technology, Inc. | IC contacts with palladium layer and flexible conductive epoxy bumps |
US5866953A (en) * | 1996-05-24 | 1999-02-02 | Micron Technology, Inc. | Packaged die on PCB with heat sink encapsulant |
US6252308B1 (en) * | 1996-05-24 | 2001-06-26 | Micron Technology, Inc. | Packaged die PCB with heat sink encapsulant |
US6281577B1 (en) * | 1996-06-28 | 2001-08-28 | Pac Tech-Packaging Technologies Gmbh | Chips arranged in plurality of planes and electrically connected to one another |
US5938956A (en) * | 1996-09-10 | 1999-08-17 | Micron Technology, Inc. | Circuit and method for heating an adhesive to package or rework a semiconductor die |
US5920118A (en) * | 1996-12-18 | 1999-07-06 | Hyundai Electronics Industries Co., Ltd. | Chip-size package semiconductor |
US5876498A (en) * | 1996-12-20 | 1999-03-02 | Moms, Inc. | Apparatus for preserving solder paste in the manufacturing of printed circuit board assemblies |
US5871808A (en) * | 1996-12-20 | 1999-02-16 | Mcms, Inc. | Method for preserving solder paste in the manufacturing of printed circuit board assemblies |
US6103547A (en) * | 1997-01-17 | 2000-08-15 | Micron Technology, Inc. | High speed IC package configuration |
US5898224A (en) * | 1997-01-24 | 1999-04-27 | Micron Technology, Inc. | Apparatus for packaging flip chip bare die on printed circuit boards |
US5891753A (en) * | 1997-01-24 | 1999-04-06 | Micron Technology, Inc. | Method and apparatus for packaging flip chip bare die on printed circuit boards |
US6198172B1 (en) * | 1997-02-20 | 2001-03-06 | Micron Technology, Inc. | Semiconductor chip package |
US6051878A (en) * | 1997-03-10 | 2000-04-18 | Micron Technology, Inc. | Method of constructing stacked packages |
US6025728A (en) * | 1997-04-25 | 2000-02-15 | Micron Technology, Inc. | Semiconductor package with wire bond protective member |
USD394844S (en) * | 1997-04-25 | 1998-06-02 | Micron Technology, Inc. | Temporary package for semiconductor dice |
US6017776A (en) * | 1997-04-29 | 2000-01-25 | Micron Technology, Inc. | Method of attaching a leadframe to singulated semiconductor dice |
US6175159B1 (en) * | 1997-07-16 | 2001-01-16 | Oki Electric Industry Co., Ltd. | Semiconductor package |
US6107122A (en) * | 1997-08-04 | 2000-08-22 | Micron Technology, Inc. | Direct die contact (DDC) semiconductor package |
US6048744A (en) * | 1997-09-15 | 2000-04-11 | Micron Technology, Inc. | Integrated circuit package alignment feature |
US6246108B1 (en) * | 1997-09-15 | 2001-06-12 | Micron Technology, Inc. | Integrated circuit package including lead frame with electrically isolated alignment feature |
US6097087A (en) * | 1997-10-31 | 2000-08-01 | Micron Technology, Inc. | Semiconductor package including flex circuit, interconnects and dense array external contacts |
US6046496A (en) * | 1997-11-04 | 2000-04-04 | Micron Technology Inc | Chip package |
US5956236A (en) * | 1997-11-25 | 1999-09-21 | Micron Technology, Inc. | Integrated circuit package support system |
US6063647A (en) * | 1997-12-08 | 2000-05-16 | 3M Innovative Properties Company | Method for making circuit elements for a z-axis interconnect |
US5893726A (en) * | 1997-12-15 | 1999-04-13 | Micron Technology, Inc. | Semiconductor package with pre-fabricated cover and method of fabrication |
US6049125A (en) * | 1997-12-29 | 2000-04-11 | Micron Technology, Inc. | Semiconductor package with heat sink and method of fabrication |
US6271058B1 (en) * | 1998-01-06 | 2001-08-07 | Nec Corporation | Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board |
US6175149B1 (en) * | 1998-02-13 | 2001-01-16 | Micron Technology, Inc. | Mounting multiple semiconductor dies in a package |
US6172419B1 (en) * | 1998-02-24 | 2001-01-09 | Micron Technology, Inc. | Low profile ball grid array package |
US6228548B1 (en) * | 1998-02-27 | 2001-05-08 | Micron Technology, Inc. | Method of making a multichip semiconductor package |
US6429528B1 (en) * | 1998-02-27 | 2002-08-06 | Micron Technology, Inc. | Multichip semiconductor package |
US6028365A (en) * | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
US5933713A (en) * | 1998-04-06 | 1999-08-03 | Micron Technology, Inc. | Method of forming overmolded chip scale package and resulting product |
US6089920A (en) * | 1998-05-04 | 2000-07-18 | Micron Technology, Inc. | Modular die sockets with flexible interconnects for packaging bare semiconductor die |
US6072233A (en) * | 1998-05-04 | 2000-06-06 | Micron Technology, Inc. | Stackable ball grid array package |
US6020629A (en) * | 1998-06-05 | 2000-02-01 | Micron Technology, Inc. | Stacked semiconductor package and method of fabrication |
US6075288A (en) * | 1998-06-08 | 2000-06-13 | Micron Technology, Inc. | Semiconductor package having interlocking heat sinks and method of fabrication |
US6215175B1 (en) * | 1998-07-06 | 2001-04-10 | Micron Technology, Inc. | Semiconductor package having metal foil die mounting plate |
US6528722B2 (en) * | 1998-07-31 | 2003-03-04 | Siliconware Precision Industries Co., Ltd. | Ball grid array semiconductor package with exposed base layer |
US6259153B1 (en) * | 1998-08-20 | 2001-07-10 | Micron Technology, Inc. | Transverse hybrid LOC package |
US6225689B1 (en) * | 1998-08-21 | 2001-05-01 | Micron Technology, Inc. | Low profile multi-IC chip package connector |
US6258623B1 (en) * | 1998-08-21 | 2001-07-10 | Micron Technology, Inc. | Low profile multi-IC chip package connector |
US6194250B1 (en) * | 1998-09-14 | 2001-02-27 | Motorola, Inc. | Low-profile microelectronic package |
US6261865B1 (en) * | 1998-10-06 | 2001-07-17 | Micron Technology, Inc. | Multi chip semiconductor package and method of construction |
US6277671B1 (en) * | 1998-10-20 | 2001-08-21 | Micron Technology, Inc. | Methods of forming integrated circuit packages |
US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
US6184465B1 (en) * | 1998-11-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor package |
US6218731B1 (en) * | 1999-05-21 | 2001-04-17 | Siliconware Precision Industries Co., Ltd. | Tiny ball grid array package |
US6210992B1 (en) * | 1999-08-31 | 2001-04-03 | Micron Technology, Inc. | Controlling packaging encapsulant leakage |
US6208519B1 (en) * | 1999-08-31 | 2001-03-27 | Micron Technology, Inc. | Thermally enhanced semiconductor package |
US6212767B1 (en) * | 1999-08-31 | 2001-04-10 | Micron Technology, Inc. | Assembling a stacked die package |
US6724076B1 (en) * | 1999-11-15 | 2004-04-20 | Infineon Technologies Ag | Package for a semiconductor chip |
US6258624B1 (en) * | 2000-01-10 | 2001-07-10 | Micron Technology, Inc. | Semiconductor package having downset leadframe for reducing package bow |
US6229202B1 (en) * | 2000-01-10 | 2001-05-08 | Micron Technology, Inc. | Semiconductor package having downset leadframe for reducing package bow |
US6558600B1 (en) * | 2000-05-04 | 2003-05-06 | Micron Technology, Inc. | Method for packaging microelectronic substrates |
US6400033B1 (en) * | 2000-06-01 | 2002-06-04 | Amkor Technology, Inc. | Reinforcing solder connections of electronic devices |
US6589820B1 (en) * | 2000-06-16 | 2003-07-08 | Micron Technology, Inc. | Method and apparatus for packaging a microelectronic die |
US6552910B1 (en) * | 2000-06-28 | 2003-04-22 | Micron Technology, Inc. | Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture |
US6365434B1 (en) * | 2000-06-28 | 2002-04-02 | Micron Technology, Inc. | Method and apparatus for reduced flash encapsulation of microelectronic devices |
US6560117B2 (en) * | 2000-06-28 | 2003-05-06 | Micron Technology, Inc. | Packaged microelectronic die assemblies and methods of manufacture |
US6576494B1 (en) * | 2000-06-28 | 2003-06-10 | Micron Technology, Inc. | Recessed encapsulated microelectronic devices and methods for formation |
US6607937B1 (en) * | 2000-08-23 | 2003-08-19 | Micron Technology, Inc. | Stacked microelectronic dies and methods for stacking microelectronic dies |
US6561479B1 (en) * | 2000-08-23 | 2003-05-13 | Micron Technology, Inc. | Small scale actuators and methods for their formation and use |
US6672325B2 (en) * | 2000-08-23 | 2004-01-06 | Micron Technology, Inc. | Small scale actuators and methods for their formation and use |
US6548757B1 (en) * | 2000-08-28 | 2003-04-15 | Micron Technology, Inc. | Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies |
US6576495B1 (en) * | 2000-08-30 | 2003-06-10 | Micron Technology, Inc. | Microelectronic assembly with pre-disposed fill material and associated method of manufacture |
US6396129B1 (en) * | 2001-03-05 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package |
US6528408B2 (en) * | 2001-05-21 | 2003-03-04 | Micron Technology, Inc. | Method for bumped die and wire bonded board-on-chip package |
US6385049B1 (en) * | 2001-07-05 | 2002-05-07 | Walsin Advanced Electronics Ltd | Multi-board BGA package |
US6564979B2 (en) * | 2001-07-18 | 2003-05-20 | Micron Technology, Inc. | Method and apparatus for dispensing adhesive on microelectronic substrate supports |
US6548376B2 (en) * | 2001-08-30 | 2003-04-15 | Micron Technology, Inc. | Methods of thinning microelectronic workpieces |
US6844618B2 (en) * | 2002-04-04 | 2005-01-18 | Micron Technology, Inc. | Microelectronic package with reduced underfill and methods for forming such packages |
US20050016751A1 (en) * | 2002-04-04 | 2005-01-27 | Tongbi Jiang | Microelectronic package with reduced underfill and methods for forming such packages |
US7091064B2 (en) * | 2002-04-04 | 2006-08-15 | Micron Technology, Inc. | Method and apparatus for attaching microelectronic substrates and support members |
US6673649B1 (en) * | 2002-07-05 | 2004-01-06 | Micron Technology, Inc. | Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages |
US6906424B2 (en) * | 2002-08-02 | 2005-06-14 | Micron Technology, Inc. | Semiconductor package and method producing same |
US20040067606A1 (en) * | 2002-10-02 | 2004-04-08 | Fehr Gerald K. | Method for stack-packaging integrated circuit die using at least one die in the package as a spacer |
US20050006743A1 (en) * | 2003-07-01 | 2005-01-13 | Kim Tae-Hyun | In-line apparatus and method for manufacturing double-sided stacked multi-chip packages |
US20060177970A1 (en) * | 2005-02-08 | 2006-08-10 | Micron Technology, Inc. | Methods of Adhering Microfeature Workpieces, Including A Chip, To A Support Member |
US20060189036A1 (en) * | 2005-02-08 | 2006-08-24 | Micron Technology, Inc. | Methods and systems for adhering microfeature workpieces to support members |
Also Published As
Publication number | Publication date |
---|---|
US7091064B2 (en) | 2006-08-15 |
US20070018337A1 (en) | 2007-01-25 |
US20050019988A1 (en) | 2005-01-27 |
US7109588B2 (en) | 2006-09-19 |
US20030189262A1 (en) | 2003-10-09 |
US7615871B2 (en) | 2009-11-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7615871B2 (en) | Method and apparatus for attaching microelectronic substrates and support members | |
US9472485B2 (en) | Hybrid thermal interface material for IC packages with integrated heat spreader | |
US6621172B2 (en) | Semiconductor device and method of fabricating the same, circuit board, and electronic equipment | |
JP3967133B2 (en) | Manufacturing method of semiconductor device and electronic device | |
US7723839B2 (en) | Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device | |
US6736306B2 (en) | Semiconductor chip package comprising enhanced pads | |
US7015070B2 (en) | Electronic device and a method of manufacturing the same | |
US6707149B2 (en) | Low cost and compliant microelectronic packages for high i/o and fine pitch | |
JP5543086B2 (en) | Semiconductor device and manufacturing method thereof | |
US9768137B2 (en) | Stud bump structure for semiconductor package assemblies | |
US7432601B2 (en) | Semiconductor package and fabrication process thereof | |
JP2006196709A (en) | Semiconductor device and manufacturing method thereof | |
JP2002270717A (en) | Semiconductor device | |
KR102561718B1 (en) | Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof | |
US20110316150A1 (en) | Semiconductor package and method for manufacturing semiconductor package | |
US6900080B2 (en) | Microelectronic package with reduced underfill and methods for forming such packages | |
JP2007150346A (en) | Semiconductor device and method of manufacturing same, circuit board, and electronic apparatus | |
JP4652428B2 (en) | Semiconductor device and manufacturing method thereof | |
KR20070119790A (en) | Stack package having polymer bump, manufacturing method thereof, and structure mounted on mother board thereof | |
KR20070016399A (en) | chip on glass package using glass substrate | |
KR100525452B1 (en) | Semiconductor package & PCB mounted with the same | |
JP2008021712A (en) | Semiconductor module, and manufacturing method thereof | |
JPH1187561A (en) | Semiconductor device, semiconductor chip mounting member, semiconductor chip and production thereof | |
JPH10223796A (en) | Semiconductor device and manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |