US20070037320A1 - Multichip packages with exposed dice - Google Patents
Multichip packages with exposed dice Download PDFInfo
- Publication number
- US20070037320A1 US20070037320A1 US11/586,094 US58609406A US2007037320A1 US 20070037320 A1 US20070037320 A1 US 20070037320A1 US 58609406 A US58609406 A US 58609406A US 2007037320 A1 US2007037320 A1 US 2007037320A1
- Authority
- US
- United States
- Prior art keywords
- dice
- mother
- die
- daughter
- recited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates generally to semiconductor packaging and more specifically to multichip semiconductor packaging.
- FIG. 1 is a diagrammatic cross sectional view of a common multichip package 100 .
- Two dice 105 and 110 are each electrically connected to a substrate 115 via wire bonding 120 and 125 .
- Each die 105 and 110 has an exclusive electrical link to the substrate 115 .
- the multichip package 100 is arranged as a ball grid array (“BGA”), a type of package in which the input and output points are solder bumps arranged in a grid pattern.
- BGA ball grid array
- FIG. 2 is a diagrammatic cross sectional view of another multichip package 200 .
- a daughter die 205 is directly connected to a mother die 210 via wire bonding 215 .
- Both the daughter die 205 and the mother die 210 are also connected directly to the substrate 220 via wire bonding 225 and 230 .
- the present invention provides a multichip assembly that has a flipchip, a mother die, contacts and an encapsulant.
- the face of the mother die is adapted to receive the face of the flipchip such that the flipchip is in direct electrical contact with the mother die.
- the mother die is in electrical contact with the contacts, which are used to connect the dice with components external to the package.
- the encapsulant is formed around the flipchip, mother die, and contacts such that the contacts are partially exposed and the back of the flipchip is partially exposed. Ensuring that the height of the encapsulant does not exceed the flipchip is one way of exposing the back of the flipchip.
- the multichip assembly is characterized as a quad flat packs—no lead package, whereby the contacts were from a leadless leadframe panel.
- a multichip assembly in another aspect, includes a chip stack, contacts and an encapsulant.
- the chip stack (a mother die electrically connected to a daughter die) is in electrical contact with the contacts and the encapsulant partially encapsulates them both.
- the partially exposed portion of the chip stack is either the bottom of the chip stack (usually the back of the mother die), the top of the chip stack (usually the back of the daughter die) or both.
- the multichip assembly is created by first providing a semiconductor wafer that has an array of mother dice. Then, flipchips are electrically connected to the wafer. Next, the wafer is singulated to create individual chip stacks. The chip stacks are then electrically connected to contacts on a leadframe panel. Next, encapsulant is added to the chip stack and leadframe panel such that encapsulant does exceed the height of the chip stack. Finally the encapsulated chip stack and leadframe panel is singulated to create individual multichip assemblies.
- FIG. 1 is a diagrammatic cross sectional view of a prior art multichip package that allows both chips to have exclusive electrical connections to a BGA;
- FIG. 2 is a diagrammatic cross sectional view of a prior art multichip package that allows a daughter die to be directly connected to a mother die in addition to both dice being connected to the BGA;
- FIG. 3 is a diagrammatic plan view of a semiconductor wafer containing an array of flipchips
- FIG. 4 is a diagrammatic plan view of a semiconductor wafer illustrated in FIG. 3 after singulation;
- FIG. 5 is a diagrammatic plan view of a semiconductor wafer that can be used as a substrate for the singulated flipchips of FIG. 4 ;
- FIG. 6 is a diagrammatic plan view of the semiconductor wafer of FIG. 5 after attachment of the singulated flipchips of FIG. 4 ;
- FIG. 7A is a diagrammatic cross sectional view of the wafer of FIG. 6 ;
- FIG. 7B is a diagrammatic cross sectional view of the wafer of FIG. 6 if underfill material is used;
- FIG. 8A is a diagrammatic cross sectional view of the wafer of 7 A after singulation
- FIG. 8B is a diagrammatic cross sectional view of the wafer of 7 B after singulation
- FIG. 9A is a diagrammatic plan view of a leadless leadframe panel
- FIG. 9B is a diagrammatic plan view of a device area array in an enlargement of FIG. 9A ;
- FIG. 9C is a diagrammatic plan view of a device area in an enlargement of FIG. 9B ;
- FIG. 10 is a diagrammatic cross section view of the singulated chip stacks of FIG. 8A after attachment on the leadless leadframe panel of FIGS. 9A-9C ;
- FIG. 11 is a diagrammatic cross sectional view of the mounted chip stacks of FIG. 10 after wire bonding
- FIG. 12 is a diagrammatic cross sectional view of the mounted chip stacks of FIG. 11 after encapsulation
- FIG. 13 is a diagrammatic cross sectional view of the mounted chip stacks of FIG. 12 after singulation
- FIG. 14 is a diagrammatic cross section view of the singulated chip stacks of FIG. 8A after attachment to a temporary tape substrate;
- FIG. 15 is a diagrammatic cross sectional view of the chip stacks of FIG. 14 after wire bonding
- FIG. 16 is a diagrammatic cross sectional view of the mounted chip stacks of FIG. 15 after encapsulation
- FIG. 17 is a diagrammatic cross sectional view of the mounted chip stacks of FIG. 16 after singulation
- FIG. 18 is a diagrammatic cross sectional view of a package that includes a heat spreader
- FIG. 19 is a diagrammatic cross sectional view of a package that maintains a thin layer of encapsulant over the chip stack.
- FIG. 20 is a diagrammatic cross sectional view of a package that includes an additional die.
- the present invention generally allows for very thin multichip assemblies.
- a flipchip is first attached to a mother die so that only the mother die needs to be electrically connected with the package contacts.
- the back of the flip chip is typically higher than the electrical connections. Since the encapsulant only needs to be high enough to fully encapsulate the means for electrical connection (e.g., gold wire bonds), the encapsulant does not need to cover the flip chip. Accordingly, the back of the flip chip can be exposed.
- a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.
- FIG. 3 is a diagrammatic plan view of an exemplary semiconductor wafer 300 that can be used in the present invention.
- the wafer 300 contains an array of semiconductor dice. Each die 305 is separated from the other dice by saw streets 310 , which are where the wafer 300 will be cut during the dicing process.
- the dice are designed to be in a flipchip assembly and each die 305 has a set of conductive bumps 315 .
- a flipchip assembly is generally defined as the direct electrical connection of face-down (“flipped”) electronic components onto substrates by means of conductive bumps.
- a “mother chip” is the substrate in a multichip assembly.
- Common conductive bumps include solder bumps, plated bumps, stud bumps and adhesive bumps.
- the conductive bumps not only provide an electrically conductive path from the flipchip to the substrate, but can also provide thermally conductive paths to carry heat from the flipchip to the substrate and act as part of the mechanical mounting of the flipchip to the substrate.
- FIG. 4 is a diagrammatic plan view of the exemplary semiconductor wafer 300 after it has been singulated with a saw 405 . Once the flipchips are singulated, they are ready to be attached to a substrate.
- wafer 300 only a relatively small number of dice are shown. However, as will be appreciated by those skilled in the art, state of the art wafers typically include hundreds or thousands of dice on a single wafer.
- FIG. 5 is a diagrammatic plan view of an exemplary semiconductor wafer 500 that can be used as the substrate for flipchips that are created after singulating the wafer 300 of FIG. 3 .
- the wafer/substrate 500 contains an array of semiconductor dice with each die 505 separated from other dice by saw streets 510 .
- Each die 505 will eventually function as a mother die 505 , and is designed to receive the conductive bumps 315 of the flipchip 305 (the daughter die) on substrate pads 515 .
- Each mother die 505 additionally has bonding pads 520 that are eventually used to electrically connect the mother die 505 with package leads.
- FIG. 6 is a diagrammatic plan view of the wafer 500 after flipchip attachment.
- the attachment process may or may not include underfill material.
- FIGS. 7 A and 7 B are diagrammatic cross sectional views of the wafer 500 of FIG. 6 .
- FIG. 7A no underfill material is used, and in FIG. 7B , an underfill 705 is used between the flipchip 305 and the mother die 505 .
- the underfill 705 is useful if the mechanical bond between the conductive bumps 315 of the flipchip 305 and the substrate pads 515 of the mother die 505 are not strong enough to withstand singulation of the wafer 500 or other assembly operations.
- FIGS. 8A and 8B are diagrammatic cross sectional views of the wafer 500 and flipchip after singulation with a saw 805 .
- FIG. 8A is a shows the flipchips attached to mother dice without any underfill material
- FIG. 8B shows the flipchips attached to mother dice using underfill material 705 .
- FIG. 9A is a diagrammatic plan view of a leadless leadframe panel 900 .
- a leadless leadframe package (“LLP”) is a relatively new integrated circuit package design that contemplates the use of a conductive (typically copper) leadframe-type substrate structure in the formation of a chip scale package (“CSP”). The resulting packages are sometimes referred to as quad flat packs—no lead (QFN) packages.
- the leadless leadframe panel 900 is patterned (typically by stamping or etching) to define a plurality of device areas, which form semiconductor device area arrays.
- FIG. 9B is a diagrammatic plan view of a device area array 905 in an enlarged view of the leadless leadframe panel 900 .
- FIG. 9C is a diagrammatic plan view of a device area 910 isolated from the device area array 905 .
- Each device area 910 includes a die attach pad 915 and a plurality of contacts 920 disposed about their associated die attach pad 915 .
- Very fine tie bars 925 are used to support the die attach pad 915 and very fine support bars 930 are used to support the contacts 920 .
- FIG. 10 is a diagrammatic cross sectional view of the chip stack 810 on a die attach pad 915 of the leadless leadframe panel 900 .
- the bottom of the contacts 920 of the leadframe panel 900 are shown being half-etched 1005 .
- Those skilled in the art will appreciate that different styles of leadless leadframe panels can be used, including those that are half-etched on the top of the contacts and those with solid contacts (no half-etching).
- FIG. 11 is a diagrammatic cross sectional view of the chip stack 810 electrically coupled to the contacts 920 with gold wire bonds 1105 . It should be appreciated that TAB or other suitable mechanisms could be used to electrically couple the mother chip 505 to the contacts 920 .
- FIG. 12 is a diagrammatic cross sectional view of the chip stack 810 and leadless leadframe panel 900 after encapsulation.
- an opaque plastic is used as an encapsulant 1205 .
- the encapsulant 1205 serves several purposes, including holding the gold wire bonds 1105 in place, protecting the chip stack 810 and, if no underfill material 705 was used, ensuring the flipchip 305 is held to the mother chip 505 .
- the encapsulant 1205 does not need to be filled beyond the height of the flipchip 305 . Therefore, the back of the flipchip 305 can be either completely or partially exposed.
- FIG. 13 is a diagrammatic cross sectional view of the final multichip assembly 1305 . After the encapsulant 1205 hardens, the packages 1305 are singulated from each other.
- FIG. 14 is a diagrammatic cross sectional view of the chip stack 810 on a temporary tape substrate 1405 .
- the temporary tape substrate 1405 is underneath a DAPless leadless leadframe panel 1410 that does not have a die attach pad.
- FIG. 15 is a diagrammatic cross sectional view of the chip stack 810 in electrical contact with the DAPless leadless leadframe panel 1410 .
- FIG. 16 is a diagrammatic cross sectional view of the chip stack 810 and DAPless leadless leadframe panel 1410 after encapsulation with an encapsulant 1605 .
- FIG. 14 is a diagrammatic cross sectional view of the chip stack 810 on a temporary tape substrate 1405 .
- the temporary tape substrate 1405 is underneath a DAPless leadless leadframe panel 1410 that does not have a die attach pad.
- FIG. 15 is a diagrammatic cross sectional view of the chip stack 810 in electrical contact with the DAPless leadless leadframe panel 1410 .
- FIG. 16 is a diagrammatic cross section
- FIG. 17 is a diagrammatic cross sectional view of the final DAPless multichip assembly 1705 after singulation and the temporary tape substrate 1405 has been removed. Clearly, the final DAPless multichip assembly 1705 is thinner than the final multichip assembly 1305 shown in FIG. 13 because of that assembly's inclusion of the die attach pad 915 .
- FIG. 18 is a diagrammatic cross sectional view of another multichip assembly 1805 in accordance with another embodiment of the invention.
- a heat spreader 1805 which is typically a thin layer of metal, is attached to the back of the flipchip 305 in order to improve thermal performance.
- FIG. 19 is a diagrammatic cross sectional view of another multichip assembly 1905 in accordance with another embodiment of the invention.
- a thin layer of encapsulant 1910 covers the back of the flipchip 305 in order to provide additional shielding for the flipchip 305 .
- FIG. 20 is a diagrammatic cross sectional view of another multichip assembly 2005 in accordance with another embodiment of the invention in which an additional die 2010 is included in the multichip assembly 2005 .
- a spacer 2015 separates the additional die 2010 from the mother die 505 of the chip stack 810 .
- the mother die 505 and the additional die 2010 are both electrically connected to the DAPless leadless leadframe panel 1410 .
- the chips can be individually molded and mechanically singulated.
Abstract
Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher than the electrical connections. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.
Description
- This application is a continuation of U.S. patent application Ser. No. 10/890,896, filed on Jul. 13, 2004, which is a divisional of U.S. Pat. No. 6,936,929, filed on Mar. 17, 2003, both of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates generally to semiconductor packaging and more specifically to multichip semiconductor packaging.
- 2. Description of the Related Art
- In an effort to produce smaller and lighter electrical devices there is a continuing effort to reduce the size of semiconductor components. Stacking multiple chips into a single package is one technique for reducing the footprint required for semiconductor devices.
- There are several methods of designing a stacked package.
FIG. 1 is a diagrammatic cross sectional view of acommon multichip package 100. Twodice substrate 115 viawire bonding substrate 115. Themultichip package 100 is arranged as a ball grid array (“BGA”), a type of package in which the input and output points are solder bumps arranged in a grid pattern. -
FIG. 2 is a diagrammatic cross sectional view of anothermultichip package 200. A daughter die 205 is directly connected to a mother die 210 viawire bonding 215. Both the daughter die 205 and the mother die 210 are also connected directly to thesubstrate 220 viawire bonding - Although the described packages work well in many applications, there are continuing efforts to further improve multichip packages.
- The present invention provides a multichip assembly that has a flipchip, a mother die, contacts and an encapsulant. The face of the mother die is adapted to receive the face of the flipchip such that the flipchip is in direct electrical contact with the mother die. The mother die is in electrical contact with the contacts, which are used to connect the dice with components external to the package. The encapsulant is formed around the flipchip, mother die, and contacts such that the contacts are partially exposed and the back of the flipchip is partially exposed. Ensuring that the height of the encapsulant does not exceed the flipchip is one way of exposing the back of the flipchip.
- In another aspect, the multichip assembly is characterized as a quad flat packs—no lead package, whereby the contacts were from a leadless leadframe panel.
- In another aspect, a multichip assembly includes a chip stack, contacts and an encapsulant. The chip stack (a mother die electrically connected to a daughter die) is in electrical contact with the contacts and the encapsulant partially encapsulates them both. Typically, the partially exposed portion of the chip stack is either the bottom of the chip stack (usually the back of the mother die), the top of the chip stack (usually the back of the daughter die) or both.
- In a method aspect of the invention, the multichip assembly is created by first providing a semiconductor wafer that has an array of mother dice. Then, flipchips are electrically connected to the wafer. Next, the wafer is singulated to create individual chip stacks. The chip stacks are then electrically connected to contacts on a leadframe panel. Next, encapsulant is added to the chip stack and leadframe panel such that encapsulant does exceed the height of the chip stack. Finally the encapsulated chip stack and leadframe panel is singulated to create individual multichip assemblies.
- The invention may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
-
FIG. 1 is a diagrammatic cross sectional view of a prior art multichip package that allows both chips to have exclusive electrical connections to a BGA; -
FIG. 2 is a diagrammatic cross sectional view of a prior art multichip package that allows a daughter die to be directly connected to a mother die in addition to both dice being connected to the BGA; -
FIG. 3 is a diagrammatic plan view of a semiconductor wafer containing an array of flipchips; -
FIG. 4 is a diagrammatic plan view of a semiconductor wafer illustrated inFIG. 3 after singulation; -
FIG. 5 is a diagrammatic plan view of a semiconductor wafer that can be used as a substrate for the singulated flipchips ofFIG. 4 ; -
FIG. 6 is a diagrammatic plan view of the semiconductor wafer ofFIG. 5 after attachment of the singulated flipchips ofFIG. 4 ; -
FIG. 7A is a diagrammatic cross sectional view of the wafer ofFIG. 6 ; -
FIG. 7B is a diagrammatic cross sectional view of the wafer ofFIG. 6 if underfill material is used; -
FIG. 8A is a diagrammatic cross sectional view of the wafer of 7A after singulation; -
FIG. 8B is a diagrammatic cross sectional view of the wafer of 7B after singulation; -
FIG. 9A is a diagrammatic plan view of a leadless leadframe panel; -
FIG. 9B is a diagrammatic plan view of a device area array in an enlargement ofFIG. 9A ; -
FIG. 9C is a diagrammatic plan view of a device area in an enlargement ofFIG. 9B ; -
FIG. 10 is a diagrammatic cross section view of the singulated chip stacks ofFIG. 8A after attachment on the leadless leadframe panel ofFIGS. 9A-9C ; -
FIG. 11 is a diagrammatic cross sectional view of the mounted chip stacks ofFIG. 10 after wire bonding; -
FIG. 12 is a diagrammatic cross sectional view of the mounted chip stacks ofFIG. 11 after encapsulation; -
FIG. 13 is a diagrammatic cross sectional view of the mounted chip stacks ofFIG. 12 after singulation; -
FIG. 14 is a diagrammatic cross section view of the singulated chip stacks ofFIG. 8A after attachment to a temporary tape substrate; -
FIG. 15 is a diagrammatic cross sectional view of the chip stacks ofFIG. 14 after wire bonding; -
FIG. 16 is a diagrammatic cross sectional view of the mounted chip stacks ofFIG. 15 after encapsulation; -
FIG. 17 is a diagrammatic cross sectional view of the mounted chip stacks ofFIG. 16 after singulation; -
FIG. 18 is a diagrammatic cross sectional view of a package that includes a heat spreader; -
FIG. 19 is a diagrammatic cross sectional view of a package that maintains a thin layer of encapsulant over the chip stack; and -
FIG. 20 is a diagrammatic cross sectional view of a package that includes an additional die. - In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the present invention.
- The present invention generally allows for very thin multichip assemblies. Generally, a flipchip is first attached to a mother die so that only the mother die needs to be electrically connected with the package contacts. When the mother die is connected to the package contacts, the back of the flip chip is typically higher than the electrical connections. Since the encapsulant only needs to be high enough to fully encapsulate the means for electrical connection (e.g., gold wire bonds), the encapsulant does not need to cover the flip chip. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.
-
FIG. 3 is a diagrammatic plan view of anexemplary semiconductor wafer 300 that can be used in the present invention. Thewafer 300 contains an array of semiconductor dice. Each die 305 is separated from the other dice by sawstreets 310, which are where thewafer 300 will be cut during the dicing process. The dice are designed to be in a flipchip assembly and each die 305 has a set ofconductive bumps 315. A flipchip assembly is generally defined as the direct electrical connection of face-down (“flipped”) electronic components onto substrates by means of conductive bumps. A “mother chip” is the substrate in a multichip assembly. - Common conductive bumps include solder bumps, plated bumps, stud bumps and adhesive bumps. The conductive bumps not only provide an electrically conductive path from the flipchip to the substrate, but can also provide thermally conductive paths to carry heat from the flipchip to the substrate and act as part of the mechanical mounting of the flipchip to the substrate.
- One of the benefits to using a flipchip assembly is that most of the processing can be completed on the wafer level.
FIG. 4 is a diagrammatic plan view of theexemplary semiconductor wafer 300 after it has been singulated with asaw 405. Once the flipchips are singulated, they are ready to be attached to a substrate. - It should be noted that in the illustrated
wafer 300, only a relatively small number of dice are shown. However, as will be appreciated by those skilled in the art, state of the art wafers typically include hundreds or thousands of dice on a single wafer. -
FIG. 5 is a diagrammatic plan view of anexemplary semiconductor wafer 500 that can be used as the substrate for flipchips that are created after singulating thewafer 300 ofFIG. 3 . The wafer/substrate 500 contains an array of semiconductor dice with each die 505 separated from other dice by sawstreets 510. Each die 505 will eventually function as a mother die 505, and is designed to receive theconductive bumps 315 of the flipchip 305 (the daughter die) onsubstrate pads 515. Each mother die 505 additionally hasbonding pads 520 that are eventually used to electrically connect the mother die 505 with package leads. -
FIG. 6 is a diagrammatic plan view of thewafer 500 after flipchip attachment. The attachment process may or may not include underfill material. FIGS. 7A and 7B are diagrammatic cross sectional views of thewafer 500 ofFIG. 6 . InFIG. 7A no underfill material is used, and inFIG. 7B , anunderfill 705 is used between theflipchip 305 and the mother die 505. Theunderfill 705 is useful if the mechanical bond between theconductive bumps 315 of theflipchip 305 and thesubstrate pads 515 of the mother die 505 are not strong enough to withstand singulation of thewafer 500 or other assembly operations. -
FIGS. 8A and 8B are diagrammatic cross sectional views of thewafer 500 and flipchip after singulation with asaw 805.FIG. 8A is a shows the flipchips attached to mother dice without any underfill material, andFIG. 8B shows the flipchips attached to mother dice usingunderfill material 705. - Once singulated, the chip stacks 810 are packaged.
FIG. 9A is a diagrammatic plan view of aleadless leadframe panel 900. A leadless leadframe package (“LLP”) is a relatively new integrated circuit package design that contemplates the use of a conductive (typically copper) leadframe-type substrate structure in the formation of a chip scale package (“CSP”). The resulting packages are sometimes referred to as quad flat packs—no lead (QFN) packages. Theleadless leadframe panel 900 is patterned (typically by stamping or etching) to define a plurality of device areas, which form semiconductor device area arrays.FIG. 9B is a diagrammatic plan view of adevice area array 905 in an enlarged view of theleadless leadframe panel 900.FIG. 9C is a diagrammatic plan view of adevice area 910 isolated from thedevice area array 905. Eachdevice area 910 includes a die attachpad 915 and a plurality ofcontacts 920 disposed about their associated die attachpad 915. Very fine tie bars 925 are used to support the die attachpad 915 and very fine support bars 930 are used to support thecontacts 920. -
FIG. 10 is a diagrammatic cross sectional view of thechip stack 810 on a die attachpad 915 of theleadless leadframe panel 900. The bottom of thecontacts 920 of theleadframe panel 900 are shown being half-etched 1005. Those skilled in the art will appreciate that different styles of leadless leadframe panels can be used, including those that are half-etched on the top of the contacts and those with solid contacts (no half-etching). - Once the
entire leadframe panel 900 is populated with chip stacks, the mother chips are electrically connected to thecontacts 920.FIG. 11 is a diagrammatic cross sectional view of thechip stack 810 electrically coupled to thecontacts 920 withgold wire bonds 1105. It should be appreciated that TAB or other suitable mechanisms could be used to electrically couple themother chip 505 to thecontacts 920. -
FIG. 12 is a diagrammatic cross sectional view of thechip stack 810 andleadless leadframe panel 900 after encapsulation. Typically, an opaque plastic is used as anencapsulant 1205. Theencapsulant 1205 serves several purposes, including holding thegold wire bonds 1105 in place, protecting thechip stack 810 and, if nounderfill material 705 was used, ensuring theflipchip 305 is held to themother chip 505. - If the
gold wire bonds 1105 do not extend beyond the height of theflipchip 305, theencapsulant 1205 does not need to be filled beyond the height of theflipchip 305. Therefore, the back of theflipchip 305 can be either completely or partially exposed. -
FIG. 13 is a diagrammatic cross sectional view of thefinal multichip assembly 1305. After theencapsulant 1205 hardens, thepackages 1305 are singulated from each other. - The
final multichip assembly 1305 ofFIG. 13 can be made even thinner by eliminating the die attachpad 920.FIG. 14 is a diagrammatic cross sectional view of thechip stack 810 on atemporary tape substrate 1405. Thetemporary tape substrate 1405 is underneath a DAPlessleadless leadframe panel 1410 that does not have a die attach pad.FIG. 15 is a diagrammatic cross sectional view of thechip stack 810 in electrical contact with the DAPlessleadless leadframe panel 1410.FIG. 16 is a diagrammatic cross sectional view of thechip stack 810 and DAPlessleadless leadframe panel 1410 after encapsulation with anencapsulant 1605.FIG. 17 is a diagrammatic cross sectional view of the finalDAPless multichip assembly 1705 after singulation and thetemporary tape substrate 1405 has been removed. Clearly, the finalDAPless multichip assembly 1705 is thinner than thefinal multichip assembly 1305 shown inFIG. 13 because of that assembly's inclusion of the die attachpad 915. -
FIG. 18 is a diagrammatic cross sectional view of anothermultichip assembly 1805 in accordance with another embodiment of the invention. Aheat spreader 1805, which is typically a thin layer of metal, is attached to the back of theflipchip 305 in order to improve thermal performance. -
FIG. 19 is a diagrammatic cross sectional view of anothermultichip assembly 1905 in accordance with another embodiment of the invention. A thin layer ofencapsulant 1910 covers the back of theflipchip 305 in order to provide additional shielding for theflipchip 305. -
FIG. 20 is a diagrammatic cross sectional view of anothermultichip assembly 2005 in accordance with another embodiment of the invention in which anadditional die 2010 is included in themultichip assembly 2005. Aspacer 2015 separates the additional die 2010 from the mother die 505 of thechip stack 810. The mother die 505 and theadditional die 2010 are both electrically connected to the DAPlessleadless leadframe panel 1410. - Although illustrative embodiments and applications of this invention are shown and described herein, many variations and modifications are possible which remain within the concept, scope, and spirit of the invention, and these variations would become clear to those of ordinary skill in the art. For example, the chips can be individually molded and mechanically singulated. Also, in certain applications it might be beneficial to use well known modifications, such as a clear mold compound as the encapsulant for imaging applications or back-coating the exposed dice in order to prevent light from interfering with the circuitry. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
Claims (13)
1. A method of packaging integrated circuits comprising:
providing a semiconductor wafer that has an array of mother dice formed therein;
mounting a multiplicity of singulated daughter dice on the wafer, each daughter die being mounted on an associated mother die and electrically connected to the mother die by direct soldering using a flip chip mounting approach, wherein the daughter dice have shorter lengths and widths than the mother dice such that the mother dice have at least some contacts that are exposed relative to their respective daughter dice, and wherein the wafer having the array of mother dice has not been diced or singulated prior to the mounting of the daughter dice.
2. A method as recited in claim 1 , further comprising dicing the semiconductor wafer having daughter dice mounted onto the mother dice on the wafer to create a multiplicity of individual chip stacks.
3. A method as recited in claim 1 , further comprising underfilling the regions beneath the daughter dice between the daughter and mother dice at the wafer level.
4. A method of packaging integrated circuits comprising:
positioning a plurality of multi-chip stacks on a lead frame panel having a multiplicity of device areas, wherein each chip stack consists of a mother die having an active surface and a daughter die having an active surface, the active surface of the daughter die being flip chip mounted to the active surface of the mother die, and wherein each chip stack is positioned in an associated device area;
electrically connecting contacts on the mother dice of the selected chip stacks to contacts within their associated device area;
encapsulating the device areas of the lead frame panel; and
singulating the device areas after the encapsulation to create a multiplicity of individual stacked multi-chip packages.
5. A method as recited in claim 4 , wherein the daughter dice have shorter lengths and widths than the mother dice such that the mother dice have at least some contacts that are exposed relative to their respective daughter dice.
6. A method as recited in claim 4 , wherein the lead frame device area does not include a die attach pad and wherein positioning the chip stacks includes placing the chip stacks on a temporary tape substrate that is also adhered to a back surface of the lead frame panel, the method further comprising removing the temporary tape substrate after the encapsulation.
7. A method as recited in claim 4 , wherein the encapsulation covers back surfaces of the daughter dice.
8. A method as recited in claim 4 , wherein the encapsulation is arranged to expose back surfaces of the daughter dice.
9. A method as recited in claim 4 , further comprising applying heat spreaders to back surfaces of the daughter dice before the encapsulation.
10. A method as recited in claim 4 , wherein the resulting multi-chip packages are quad flat packs—no lead packages.
11. A method as recited in claim 4 , wherein selected multi-chip stacks are each mounted on a third die mounted within a device area of the lead frame panel, wherein contacts on said third dice are electrically connected to contacts within their associated device areas.
12. A method as recited in claim 11 , further comprising electrically connecting contacts on the mother dice of the selected multi-chip stacks to contacts within their associated device areas.
13. A method as recited in claim 11 , wherein a spacer is positioned between a mother die and a third die.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/586,094 US20070037320A1 (en) | 2003-03-17 | 2006-10-24 | Multichip packages with exposed dice |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/391,160 US6936929B1 (en) | 2003-03-17 | 2003-03-17 | Multichip packages with exposed dice |
US10/890,896 US7144800B2 (en) | 2003-03-17 | 2004-07-13 | Multichip packages with exposed dice |
US11/586,094 US20070037320A1 (en) | 2003-03-17 | 2006-10-24 | Multichip packages with exposed dice |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/890,896 Continuation US7144800B2 (en) | 2003-03-17 | 2004-07-13 | Multichip packages with exposed dice |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070037320A1 true US20070037320A1 (en) | 2007-02-15 |
Family
ID=33516872
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/391,160 Expired - Lifetime US6936929B1 (en) | 2003-03-17 | 2003-03-17 | Multichip packages with exposed dice |
US10/890,896 Expired - Lifetime US7144800B2 (en) | 2003-03-17 | 2004-07-13 | Multichip packages with exposed dice |
US11/586,094 Abandoned US20070037320A1 (en) | 2003-03-17 | 2006-10-24 | Multichip packages with exposed dice |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/391,160 Expired - Lifetime US6936929B1 (en) | 2003-03-17 | 2003-03-17 | Multichip packages with exposed dice |
US10/890,896 Expired - Lifetime US7144800B2 (en) | 2003-03-17 | 2004-07-13 | Multichip packages with exposed dice |
Country Status (1)
Country | Link |
---|---|
US (3) | US6936929B1 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080274589A1 (en) * | 2007-05-04 | 2008-11-06 | Chien-Hsiun Lee | Wafer-level flip-chip assembly methods |
US20080290482A1 (en) * | 2007-05-25 | 2008-11-27 | National Semiconductor Corporation | Method of packaging integrated circuits |
US20090134481A1 (en) * | 2007-11-28 | 2009-05-28 | Analog Devices, Inc. | Molded Sensor Package and Assembly Method |
US20100019392A1 (en) * | 2008-07-25 | 2010-01-28 | Tan Gin Ghee | Stacked die package having reduced height and method of making same |
US20130076384A1 (en) * | 2011-09-23 | 2013-03-28 | Powertech Technology, Inc. | Method for testing multi-chip stacked packages |
TWI464856B (en) * | 2012-07-02 | 2014-12-11 | Powertech Technology Inc | Alignment method for inversely picking and placing diced multi-dice stacked packages |
US8981574B2 (en) | 2012-12-20 | 2015-03-17 | Samsung Electronics Co., Ltd. | Semiconductor package |
WO2019074857A1 (en) * | 2017-10-10 | 2019-04-18 | Zglue Inc. | Assembly of flexible and integrated module packages with leadframes |
US11251169B2 (en) | 2018-12-19 | 2022-02-15 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor package and semiconductor package |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7799611B2 (en) * | 2002-04-29 | 2010-09-21 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US6812552B2 (en) * | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US8236612B2 (en) * | 2002-04-29 | 2012-08-07 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US20040058478A1 (en) * | 2002-09-25 | 2004-03-25 | Shafidul Islam | Taped lead frames and methods of making and using the same in semiconductor packaging |
US6856009B2 (en) | 2003-03-11 | 2005-02-15 | Micron Technology, Inc. | Techniques for packaging multiple device components |
US6936929B1 (en) * | 2003-03-17 | 2005-08-30 | National Semiconductor Corporation | Multichip packages with exposed dice |
US20060258051A1 (en) * | 2005-05-10 | 2006-11-16 | Texas Instruments Incorporated | Method and system for solder die attach |
DE102005022017B3 (en) * | 2005-05-12 | 2006-10-26 | Infineon Technologies Ag | Semiconductor chip stack manufacturing method, involves holding stabilization layer at chemical mechanical polishing- or etched stop layer while thinning wafer of isolated semiconductor chips |
US7642842B1 (en) * | 2006-02-17 | 2010-01-05 | National Semiconductor Corporation | System and method for providing communication of over-current protection and current mode control between multiple chips in an integrated circuit |
US9202776B2 (en) * | 2006-06-01 | 2015-12-01 | Stats Chippac Ltd. | Stackable multi-chip package system |
TW200746386A (en) * | 2006-06-07 | 2007-12-16 | Advanced Semiconductor Eng | System in package |
US20080054429A1 (en) * | 2006-08-25 | 2008-03-06 | Bolken Todd O | Spacers for separating components of semiconductor device assemblies, semiconductor device assemblies and systems including spacers and methods of making spacers |
CN101601133B (en) * | 2006-10-27 | 2011-08-10 | 宇芯(毛里求斯)控股有限公司 | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US7687897B2 (en) * | 2006-12-28 | 2010-03-30 | Stats Chippac Ltd. | Mountable integrated circuit package-in-package system with adhesive spacing structures |
US7750451B2 (en) * | 2007-02-07 | 2010-07-06 | Stats Chippac Ltd. | Multi-chip package system with multiple substrates |
US7598123B2 (en) * | 2007-03-02 | 2009-10-06 | Semiconductor Components Industries, L.L.C. | Semiconductor component and method of manufacture |
WO2008108334A1 (en) * | 2007-03-06 | 2008-09-12 | Nikon Corporation | Semiconductor device and method for manufacturing the semiconductor device |
JP2008258383A (en) * | 2007-04-04 | 2008-10-23 | Spansion Llc | Semiconductor device and its manufacturing method |
DE102007018914B4 (en) * | 2007-04-19 | 2019-01-17 | Infineon Technologies Ag | Semiconductor device with a semiconductor chip stack and method for producing the same |
US20090115070A1 (en) * | 2007-09-20 | 2009-05-07 | Junji Tanaka | Semiconductor device and method for manufacturing thereof |
DE102008009108A1 (en) * | 2008-02-14 | 2009-08-20 | Osram Opto Semiconductors Gmbh | Method for producing a semiconductor laser and semiconductor laser |
US7832278B2 (en) * | 2008-05-29 | 2010-11-16 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | Multi-chip package |
US8803330B2 (en) * | 2008-09-27 | 2014-08-12 | Stats Chippac Ltd. | Integrated circuit package system with mounting structure |
US7863092B1 (en) * | 2008-09-30 | 2011-01-04 | Xilinx, Inc. | Low cost bumping and bonding method for stacked die |
US7776649B1 (en) * | 2009-05-01 | 2010-08-17 | Powertech Technology Inc. | Method for fabricating wafer level chip scale packages |
US8105875B1 (en) | 2010-10-14 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approach for bonding dies onto interposers |
US9064879B2 (en) * | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8936966B2 (en) | 2012-02-08 | 2015-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods for semiconductor devices |
TWI536515B (en) * | 2010-11-02 | 2016-06-01 | 創意電子股份有限公司 | Semiconductor package device with a heat dissipation structure and the packaging method thereof |
US8450151B1 (en) * | 2011-11-22 | 2013-05-28 | Texas Instruments Incorporated | Micro surface mount device packaging |
CN102543937B (en) * | 2011-12-30 | 2014-01-22 | 北京工业大学 | Flip chip on-chip package and manufacturing method thereof |
US9786643B2 (en) | 2014-07-08 | 2017-10-10 | Micron Technology, Inc. | Semiconductor devices comprising protected side surfaces and related methods |
US9892952B2 (en) | 2014-07-25 | 2018-02-13 | Semiconductor Components Industries, Llc | Wafer level flat no-lead semiconductor packages and methods of manufacture |
US9443785B2 (en) * | 2014-12-19 | 2016-09-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package |
TWI556387B (en) * | 2015-04-27 | 2016-11-01 | 南茂科技股份有限公司 | Multi chip package structure, wafer level chip package structure and manufacturing method thereof |
DE102015219366B4 (en) * | 2015-05-22 | 2024-02-22 | Volkswagen Aktiengesellschaft | Interposer and semiconductor module for use in automotive applications |
US10304802B2 (en) * | 2016-05-02 | 2019-05-28 | International Business Machines Corporation | Integrated wafer-level processing system |
Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5216283A (en) * | 1990-05-03 | 1993-06-01 | Motorola, Inc. | Semiconductor device having an insertable heat sink and method for mounting the same |
US5851845A (en) * | 1995-12-18 | 1998-12-22 | Micron Technology, Inc. | Process for packaging a semiconductor die using dicing and testing |
US5942795A (en) * | 1997-07-03 | 1999-08-24 | National Semiconductor Corporation | Leaded substrate carrier for integrated circuit device and leaded substrate carrier device assembly |
US5952725A (en) * | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
US6133637A (en) * | 1997-01-24 | 2000-10-17 | Rohm Co., Ltd. | Semiconductor device having a plurality of semiconductor chips |
US6236109B1 (en) * | 1999-01-29 | 2001-05-22 | United Microelectronics Corp. | Multi-chip chip scale package |
US6337225B1 (en) * | 2000-03-30 | 2002-01-08 | Advanced Micro Devices, Inc. | Method of making stacked die assemblies and modules |
US6355502B1 (en) * | 2000-04-25 | 2002-03-12 | National Science Council | Semiconductor package and method for making the same |
US20020031864A1 (en) * | 1996-05-20 | 2002-03-14 | Ball Michael B. | Method of fabrication of stacked semiconductor devices |
US6376914B2 (en) * | 1999-12-09 | 2002-04-23 | Atmel Corporation | Dual-die integrated circuit package |
US20020068373A1 (en) * | 2000-02-16 | 2002-06-06 | Nova Crystals, Inc. | Method for fabricating light emitting diodes |
US20020151103A1 (en) * | 2001-04-06 | 2002-10-17 | Shigeru Nakamura | Semiconductor device and method of manufacturing the same |
US20020155638A1 (en) * | 2001-04-24 | 2002-10-24 | Yasufumi Uchida | Method for fabricating semiconductor device |
US20030057564A1 (en) * | 1997-04-04 | 2003-03-27 | Elm Technology Corporation | Three dimensional structure memory |
US20030057539A1 (en) * | 2001-09-21 | 2003-03-27 | Michel Koopmans | Bumping technology in stacked die configurations |
US20030062606A1 (en) * | 2000-03-30 | 2003-04-03 | Chun Dosung | Leadless semiconductor product packaging apparatus having a window lid and method for packaging |
US20030071341A1 (en) * | 2001-10-16 | 2003-04-17 | Jeung Boon Suan | Apparatus and method for leadless packaging of semiconductor devices |
US6555917B1 (en) * | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
US6558977B2 (en) * | 2000-12-26 | 2003-05-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20030092205A1 (en) * | 2001-11-15 | 2003-05-15 | Siliconware Precision Industries, Co., Ltd. | Crack-preventive semiconductor package |
US6630729B2 (en) * | 2000-09-04 | 2003-10-07 | Siliconware Precision Industries Co., Ltd. | Low-profile semiconductor package with strengthening structure |
US20030197284A1 (en) * | 2002-02-21 | 2003-10-23 | United Test & Assembly Center Limited | Semiconductor package |
US6710454B1 (en) * | 2000-02-16 | 2004-03-23 | Micron Technology, Inc. | Adhesive layer for an electronic apparatus having multiple semiconductor devices |
US6723585B1 (en) * | 2002-10-31 | 2004-04-20 | National Semiconductor Corporation | Leadless package |
US20040110323A1 (en) * | 2002-10-30 | 2004-06-10 | Karl-Friedrich Becker | Method for producing encapsulated chips |
US6791195B2 (en) * | 2000-04-24 | 2004-09-14 | Nec Electronics Corporation | Semiconductor device and manufacturing method of the same |
US6812552B2 (en) * | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US6815833B2 (en) * | 2002-11-13 | 2004-11-09 | Advanced Semiconductor Engineering, Inc. | Flip chip package |
US6936929B1 (en) * | 2003-03-17 | 2005-08-30 | National Semiconductor Corporation | Multichip packages with exposed dice |
-
2003
- 2003-03-17 US US10/391,160 patent/US6936929B1/en not_active Expired - Lifetime
-
2004
- 2004-07-13 US US10/890,896 patent/US7144800B2/en not_active Expired - Lifetime
-
2006
- 2006-10-24 US US11/586,094 patent/US20070037320A1/en not_active Abandoned
Patent Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5216283A (en) * | 1990-05-03 | 1993-06-01 | Motorola, Inc. | Semiconductor device having an insertable heat sink and method for mounting the same |
US5851845A (en) * | 1995-12-18 | 1998-12-22 | Micron Technology, Inc. | Process for packaging a semiconductor die using dicing and testing |
US5952725A (en) * | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
US20020031864A1 (en) * | 1996-05-20 | 2002-03-14 | Ball Michael B. | Method of fabrication of stacked semiconductor devices |
US6133637A (en) * | 1997-01-24 | 2000-10-17 | Rohm Co., Ltd. | Semiconductor device having a plurality of semiconductor chips |
US20030057564A1 (en) * | 1997-04-04 | 2003-03-27 | Elm Technology Corporation | Three dimensional structure memory |
US5942795A (en) * | 1997-07-03 | 1999-08-24 | National Semiconductor Corporation | Leaded substrate carrier for integrated circuit device and leaded substrate carrier device assembly |
US6236109B1 (en) * | 1999-01-29 | 2001-05-22 | United Microelectronics Corp. | Multi-chip chip scale package |
US6376914B2 (en) * | 1999-12-09 | 2002-04-23 | Atmel Corporation | Dual-die integrated circuit package |
US20020068373A1 (en) * | 2000-02-16 | 2002-06-06 | Nova Crystals, Inc. | Method for fabricating light emitting diodes |
US6710454B1 (en) * | 2000-02-16 | 2004-03-23 | Micron Technology, Inc. | Adhesive layer for an electronic apparatus having multiple semiconductor devices |
US20030062606A1 (en) * | 2000-03-30 | 2003-04-03 | Chun Dosung | Leadless semiconductor product packaging apparatus having a window lid and method for packaging |
US6337225B1 (en) * | 2000-03-30 | 2002-01-08 | Advanced Micro Devices, Inc. | Method of making stacked die assemblies and modules |
US6791195B2 (en) * | 2000-04-24 | 2004-09-14 | Nec Electronics Corporation | Semiconductor device and manufacturing method of the same |
US6355502B1 (en) * | 2000-04-25 | 2002-03-12 | National Science Council | Semiconductor package and method for making the same |
US6630729B2 (en) * | 2000-09-04 | 2003-10-07 | Siliconware Precision Industries Co., Ltd. | Low-profile semiconductor package with strengthening structure |
US6558977B2 (en) * | 2000-12-26 | 2003-05-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20020151103A1 (en) * | 2001-04-06 | 2002-10-17 | Shigeru Nakamura | Semiconductor device and method of manufacturing the same |
US20020155638A1 (en) * | 2001-04-24 | 2002-10-24 | Yasufumi Uchida | Method for fabricating semiconductor device |
US20030057539A1 (en) * | 2001-09-21 | 2003-03-27 | Michel Koopmans | Bumping technology in stacked die configurations |
US6555917B1 (en) * | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
US20030071341A1 (en) * | 2001-10-16 | 2003-04-17 | Jeung Boon Suan | Apparatus and method for leadless packaging of semiconductor devices |
US20030092205A1 (en) * | 2001-11-15 | 2003-05-15 | Siliconware Precision Industries, Co., Ltd. | Crack-preventive semiconductor package |
US20030197284A1 (en) * | 2002-02-21 | 2003-10-23 | United Test & Assembly Center Limited | Semiconductor package |
US6812552B2 (en) * | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US20040110323A1 (en) * | 2002-10-30 | 2004-06-10 | Karl-Friedrich Becker | Method for producing encapsulated chips |
US6723585B1 (en) * | 2002-10-31 | 2004-04-20 | National Semiconductor Corporation | Leadless package |
US6815833B2 (en) * | 2002-11-13 | 2004-11-09 | Advanced Semiconductor Engineering, Inc. | Flip chip package |
US6936929B1 (en) * | 2003-03-17 | 2005-08-30 | National Semiconductor Corporation | Multichip packages with exposed dice |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080274589A1 (en) * | 2007-05-04 | 2008-11-06 | Chien-Hsiun Lee | Wafer-level flip-chip assembly methods |
US7977155B2 (en) * | 2007-05-04 | 2011-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level flip-chip assembly methods |
US20080290482A1 (en) * | 2007-05-25 | 2008-11-27 | National Semiconductor Corporation | Method of packaging integrated circuits |
US20090134481A1 (en) * | 2007-11-28 | 2009-05-28 | Analog Devices, Inc. | Molded Sensor Package and Assembly Method |
US20100019392A1 (en) * | 2008-07-25 | 2010-01-28 | Tan Gin Ghee | Stacked die package having reduced height and method of making same |
US8710859B2 (en) * | 2011-09-23 | 2014-04-29 | Powertech Technology Inc. | Method for testing multi-chip stacked packages |
US20130076384A1 (en) * | 2011-09-23 | 2013-03-28 | Powertech Technology, Inc. | Method for testing multi-chip stacked packages |
TWI464856B (en) * | 2012-07-02 | 2014-12-11 | Powertech Technology Inc | Alignment method for inversely picking and placing diced multi-dice stacked packages |
US8981574B2 (en) | 2012-12-20 | 2015-03-17 | Samsung Electronics Co., Ltd. | Semiconductor package |
US9633973B2 (en) | 2012-12-20 | 2017-04-25 | Samsung Electronics Co., Ltd. | Semiconductor package |
WO2019074857A1 (en) * | 2017-10-10 | 2019-04-18 | Zglue Inc. | Assembly of flexible and integrated module packages with leadframes |
US11476182B2 (en) * | 2017-10-10 | 2022-10-18 | Shenzhen Chipuller Chip Technology Co., Ltd | Assembly of flexible and integrated module packages with leadframes |
US11251169B2 (en) | 2018-12-19 | 2022-02-15 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor package and semiconductor package |
US11791321B2 (en) | 2018-12-19 | 2023-10-17 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor package and semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
US20040259288A1 (en) | 2004-12-23 |
US6936929B1 (en) | 2005-08-30 |
US7144800B2 (en) | 2006-12-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7144800B2 (en) | Multichip packages with exposed dice | |
US7378298B2 (en) | Method of making stacked die package | |
US6975038B1 (en) | Chip scale pin array | |
US7521285B2 (en) | Method for fabricating chip-stacked semiconductor package | |
KR101037246B1 (en) | Multi Chip Leadframe Package | |
US7247934B2 (en) | Multi-chip semiconductor package | |
US7125747B2 (en) | Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe | |
US7911047B2 (en) | Semiconductor device and method of fabricating the semiconductor device | |
USRE39957E1 (en) | Method of making semiconductor package with heat spreader | |
US7494847B2 (en) | Method for making a semiconductor multi-package module having inverted wire bond carrier second package | |
US6468832B1 (en) | Method to encapsulate bumped integrated circuit to create chip scale package | |
US7419855B1 (en) | Apparatus and method for miniature semiconductor packages | |
US20070176269A1 (en) | Multi-chips module package and manufacturing method thereof | |
US20060097402A1 (en) | Semiconductor device having flip-chip package and method for fabricating the same | |
US20040082114A1 (en) | Fabrication method of window-type ball grid array semiconductor package | |
US20060145362A1 (en) | Semiconductor package and fabrication method of the same | |
US7187070B2 (en) | Stacked package module | |
TW200816440A (en) | Leaded stacked packages having integrated upper lead | |
US20070202680A1 (en) | Semiconductor packaging method | |
CN112185903A (en) | Electronic package and manufacturing method thereof | |
US20080290509A1 (en) | Chip Scale Package and Method of Assembling the Same | |
KR100600214B1 (en) | Semiconductor package and its manufacturing method | |
KR100446913B1 (en) | Semiconductor device without use of chip carrier and method for making the same | |
KR100370480B1 (en) | Lead frame for semiconductor package | |
KR100876876B1 (en) | Chip stack package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NATIONAL SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MOSTAFAZADEH, SHAHRAM;SMITH, JOSEPH O.;REEL/FRAME:018870/0990 Effective date: 20030313 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |