US20070145595A1

US20070145595A1 - High speed interconnect

Info

Publication number: US20070145595A1
Application number: US11/319,875
Authority: US
Inventors: Stephen Hall; Bryce Horine; Gary Brist; Howard Heck
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2005-12-27
Filing date: 2005-12-27
Publication date: 2007-06-28
Also published as: TW200810619A; GB2446336B; CN101351923B; CN101351923A; WO2007075315A1; US20080172872A1; GB2446336A; GB0809457D0; US8732942B2; DE112006003502T5

Abstract

In some embodiments a high speed interconnect includes a layer of FR4 material, a trench in the layer of FR4 material, and a pair of transmission lines located near the trench. The trench is filled with a homogenous material. Other embodiments are described and claimed.

Description

TECHNICAL FIELD

The inventions generally relate to a high speed interconnect.

BACKGROUND

In computer systems, boards (or printed circuit boards) such as motherboards and daughter cards, for example, are typically fabricated to hold computer components such as processors, chipsets, memory, etc. The boards also include features such as interconnects (for example, bus interconnects) that are used to electrically connect the various components. As bus data rates continue to scale (for example, in proportion to Moore's Law), the traditional materials used to fabricate boards such as motherboards and daughter cards begin to exhibit severe interconnect performance limitations. As frequencies increase, these limitations become one of the primary roadblocks to data rates above 8-10 Gb/s for server and desktop systems, for example.
Printed Circuit Boards (PCBs) used in the fabrication of virtually all volume motherboards and daughter cards in the Personal Computer (PC) industry begin to introduce severe performance problems for high speed interconnect channels (for example, PCI-express). These performance limitations are generally dominated by two properties of the FR4 material used to fabricate these boards. These two properties include material loss and non-homogeneous dielectric issues. Therefore, a need has arisen for boards such as motherboards and/or daughter cards that do not include performance limitations for high speed interconnect channels.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventions will be understood more fully from the detailed description given below and from the accompanying drawings of some embodiments of the inventions which, however, should not be taken to limit the inventions to the specific embodiments described, but are for explanation and understanding only.
FIG. 1 illustrates a graph 100 showing material losses in order to explain some embodiments of the inventions.
FIG. 2 illustrates a differential pair imbalance 200 in order to explain some embodiments of the inventions.
FIG. 3 illustrates an interconnect 300 according to some embodiments of the inventions.
FIG. 4 illustrates an interconnect 400 according to some embodiments of the inventions.

DETAILED DESCRIPTION

Some embodiments of the inventions relate to a high speed interconnect.
Some embodiments relate to a high performance transmission line for high data rates.
In some embodiments a high speed interconnect includes a layer of FR4 material, a trench in the layer of FR4 material, and a pair of transmission lines located near the trench. The trench is filled with a homogenous and/or low loss material.
In some embodiments a system includes a first device, a second device, and a high speed interconnect to propagate a signal between the first device and the second device. The high speed interconnect includes a layer of FR4 material, a trench in the layer of FR4 material, and a pair of transmission lines located near the trench. The trench is filled with a homogenous and/or low loss material.
In some embodiments a method of forming a high speed interconnect includes creating a trench in a layer of FR4 material, inserting a homogenous and/or low loss material into the trench, and forming a pair of transmission lines near the trench.
According to some embodiments, Printed Circuit Boards (PCBs) used in the fabrication of virtually all volume boards (for example, motherboards and daughter cards in the computing and communications industries) begin to exhibit severe interconnect performance problems for high speed interconnect channels, including material losses and non-homogenous dielectric issues.
FIG. 1 illustrates a graph 100 showing material losses due to interactions between a dielectric material (for example, FR4 material) and an electric field of a signal propagating on a transmission line. More specifically, graph 100 illustrates losses that a transmission line routed on FR4 material will induce for a 20 inch differential pair. For example, graph 100 illustrates exemplary measured differential insertion loss over a 20 inch differential pair (microstrip). The material losses are specified by the loss tangent, which is a measure of the “equivalent conductivity” of the material at a given frequency. The loss tangent (TanD) of FR4 is approximately 0.017, which will induce approximately 25 dB of signal loss over a 20 inch trace at 10 GHz (as illustrated in graph 100). This corresponds to a 20 Gbit/s data transmission rate. Consequently, in this example, the signal will be attenuated approximately 95% by the FR4 material properties alone as it propagates from the driver to the receiver. This loss will quickly close the eye seen at the receiver.
FIG. 2 illustrates a differential pair imbalance 200 due to non-homogeneous material. Differential pair transmission lines 202 are shown in a top view at the top of FIG. 2 and a side view at the bottom of FIG. 2. Transmission lines 202 are near (over) a layer of FR4 material 204 illustrated at the bottom of FIG. 2. The FR4 material 204 is shown at the bottom of FIG. 2 as containing an epoxy portion (dark) and a glass portion (oval). A differential pair imbalance is caused by the non-homogeneous nature of the FR4 material (see, for example, how the left transmission line 202 at the bottom of FIG. 2 is near the glass material of the FR4 layer 204 and the right transmission line 202 at the bottom of FIG. 2 is near the epoxy material of the FR4 layer 204).
At high frequency rates, it is necessary to use a differential pair (for example, 202 in FIG. 2) to facilitate the propagation of a data signal from a driver (for example, a microprocessor) to a receiver (for example, a chipset). Differential pair transmission line design requires that each signal in the pair be identical. The FR4 material of layer 204 is a composite manufactured by gluing sheets of fiberglass cloth together. This can, and very often does, create an imbalance between the legs of the differential pair 202 because it is possible for one leg to be routed over a glass bundle and the other leg to be routed over an epoxy trough. Since the dielectric constant between the glass (Er˜6) and epoxy (Er˜3) is high, this creates a significant imbalance within the pair 202.
The imbalance causes a differential to common mode conversion, otherwise known as AC common mode noise (ACCM). The ACCM noise induced by the non-homogenous FR4 material 204 directly reduces the signal amplitude seen at the receiver (eye height) and introduces significant timing errors (eye width) that will easily destroy the signal integrity if not controlled.
According to some embodiments a solution is provided to the dominant problems associated with propagating high speed signals on transmission lines built on traditional FR4 materials. According to some embodiments the performance of FR4 based channels is significantly increased and data rates are enabled that are greater than 10-15 Gb/s while preserving the use of low cost FR4 material as a primary material for the board (for example, motherboard).
According to some embodiments a trench is formed into FR4 material (for example, by laser etching or milling) and the trench is filled with a low loss and/or homogenous dielectric material prior to bonding of the copper layer and prior to etching of the transmission lines. This allows for a minimizing of signal degradation caused by losses and AC common mode noise.
FIG. 3 illustrates an interconnect 300 according to some embodiments. According to some embodiments the interconnect 300 is located on a board. According to some embodiments interconnect 300 includes an FR4 material layer 304, a trench 306 formed in the FR4 material layer 304, glass portions 308 of FR4 material layer 304, epoxy portions 310 of FR4 material layer 304, a controlled material 312 inserted into trench 306, a copper layer 314, and/or an FR4 core 316 including glass bundle portions 318 (for example, Er˜6) and epoxy portions 320 (for example, Er˜3). According to some embodiments additional portions include transmission lines 352, an FR4 material layer 354 including glass portions 358 and epoxy portions 360, and a copper layer 364.
According to some embodiments an interconnect 300 is formed by forming the trench 306 in the FR4 material 304 and filling trench 306 with the controlled material 312. According to some embodiments trench 306 is filled with the controlled material 312 prior to the attachment of a copper foil above trench 306 and/or prior to adding any transmission lines near (for example, over) the trench 306, controlled material 312, and/or FR4 material 304. A copper foil is later attached above controlled material 312 in trench 306 and plated in order to form conductors (for example, differential pair transmission lines) above the trench 306 (not shown in FIG. 3). According to some embodiments the trench 306 is formed in a cured FR4 material 304. According to some embodiments the trench 306 is milled out of the FR4 material 304. According to some embodiments the trench 306 is laser etched out of the FR4 material 304. According to some embodiments the controlled material 312 that is inserted into the trench 306 is a low loss and/or homogeneous material. According to some embodiments the controlled material 312 that is inserted into the trench 306 is a low loss and/or homogeneous dielectric material.
FIG. 4 illustrates an interconnect 400 according to some embodiments. According to some embodiments the interconnect 400 is located on a board. According to some embodiments interconnect 400 includes transmission lines 402, an FR4 material layer 404, a trench 406 formed in the FR4 material layer 404, glass portions 408 of FR4 material layer 404, epoxy portions 410 of FR4 material layer 404, a controlled material 412 inserted into trench 406, a copper layer 414, and/or an FR4 core 416 including glass bundle portions 418 (for example, Er˜6) and epoxy portions 420 (for example, Er˜3). According to some embodiments additional portions include transmission lines 452, an FR4 material layer 454 including glass portions 458 and epoxy portions 460, and a copper layer 464.
According to some embodiments an interconnect 400 is formed by forming the trench 406 in the FR4 material 404 and filling trench 406 with the controlled material 412. According to some embodiments trench 406 is filled with the controlled material 412 prior to the attachment of copper conductors and/or transmission lines 402 near (for example, over) the trench 406, controlled material 412, and/or FR4 material 404. The copper conductors are attached above the controlled material 412 after it has been inserted in trench 406. The copper is plated and/or laminated in order to form conductors 402 (for example, differential pair transmission lines) above the trench 406. According to some embodiments the trench 406 is formed in a cured FR4 material 404. According to some embodiments the trench 406 is milled out of the FR4 material 404. According to some embodiments the trench 406 is laser etched out of the FR4 material 404. According to some embodiments the controlled material 412 that is inserted into the trench 406 is a low loss and/or homogeneous material. According to some embodiments the controlled material 412 that is inserted into the trench 406 is a low loss and/or homogeneous dielectric material.
According to some embodiments, once the trench 406 is created and the controlled material 412 is inserted a copper foil is attached to the top of controlled material 412. The copper foil is then etched and plated to form signal conductors 402 (for example, transmission lines) that are used, for example, as a differential pair. According to some embodiments controlled material 412 is a high performance material, thus providing a localized high performance differential pair of transmission lines 402.
According to some embodiments a variety of materials may be chosen for insertion into a trench (for example, different materials for controlled material 312 of FIG. 3 and/or controlled material 412 of FIG. 4). According to some embodiments different materials may be inserted into a trench depending on desired electrical properties of the transmission line and/or differential pair.
According to some embodiments different exemplary materials that may be inserted into a trench formed in an FR4 layer include but are not limited to one or more of the following materials.
According to some embodiments an epoxy is inserted into a trench. Although epoxy is used to manufacture FR4 boards it is not always necessarily a low loss material. However, epoxy is a homogeneous material. According to some embodiments it is relatively easy and cost efficient to create a trench for a high speed transmission line that is filled with epoxy, for example, in order to eliminate ACCM effects. This is particularly useful for very high frequency channels that are, for example, less than approximately 6 inches in length. Since the length is short the losses are less consequential and ACCM noise is limited.
According to some embodiments Teflon is inserted into a trench. The loss tangent of Teflon is 0.0004, which is over 40 times less lossy than FR4. Teflon is homogenous so it produces an excellent high speed channel. Both the dielectric losses and ACCM are almost negligible using Teflon in such a manner. The speed of such a transmission line is therefore only limited by copper losses and impedance discontinuities.
According to some embodiments Nylon is inserted into a trench. Nylon is approximately 40% less lossy than FR4. Nylon can also be made to be homogeneous.
According to some embodiments, solid materials such as ceramic or alumina are inserted into a trench (although there may be some difficulties associated with inserting such materials into an FR4 trench, they may still be used in some embodiments). Ceramic is approximately 4 times less lossy than FR4, and ceramic is a homogeneous material.
According to some embodiments any low loss material is inserted into a trench. According to some embodiments any material having a loss that is lower than a loss of FR4 material is inserted into a trench.
According to some embodiments the useful life of copper interconnects may be dramatically increased by reducing the dielectric losses and the non-homogeneous nature of typical FR4 material.
According to some embodiments two of the top speed limiters of current FR4 material based channels are eliminated (material losses and non-homogeneous material).
According to some embodiments the useful life of FR4 as the preferred high volume low cost material for board (for example, motherboard) manufacture is increased. Although there may be additional cost associated with some embodiments that cost is significantly less than changing the material of the entire board (for example, motherboard, daughter card, and/or other boards).
According to some embodiments, very high speed buses may be implemented in a digital system (for example, according to some embodiments, memory buses and/or front side buses). Current research shows that currently used FR4 material will be difficult to use in designing buses with high transfer rates (for example, in some embodiments, in excess of 8-10 Gb/sec). Since loss and ACCM are two of the primary performance limiters on the interconnect channel, and the system speed is currently channel limited, according to some embodiments computers can be made to run faster. According to some embodiments interconnect speed will scale with Moore's Law.
According to some embodiments bus performance is optimized while minimizing system cost. The industry must currently live with the cost structure provided by FR4. However, according to some embodiments motherboards may be manufactured out of high performance materials to better facilitate data rates needed to keep up with processor speed. Although such high performance materials have proven to be too costly for the manufacture of volume motherboards, according to some embodiments the established low cost FR4 material is integrated with numerous high performance materials. According to some embodiments since high performance material may be used only for select, high speed interconnects and not the whole board, such integration produces the desired performance at a lower cost.
According to some embodiments as illustrated, for example, in FIG. 3 and FIG. 4, a board includes an interconnect (300, 400) on a top side of the board including transmission lines (402) located near a controlled material (312, 412) and an interconnect on a bottom side of the board including transmission lines (352, 452) not located near a controlled material but located near a typical FR4 material layer (354, 454). However, according to some embodiments the interconnect on the bottom side of the board also includes a controlled material similar to controlled material 312 located near transmission lines 352, 452 (for example, in a trench formed in layer 354, 454). In this manner a board can include two high speed interconnects, one at a top side of the board and one at the bottom side of the board according to some embodiments. Similarly, according to some embodiments a board includes only one interconnect (that is, a high speed interconnect).
Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of circuit elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
An algorithm is here, and generally, considered to be a self-consistent sequence of acts or operations leading to a desired result. These include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
Some embodiments may be implemented in one or a combination of hardware, firmware, and software. Some embodiments may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by a computing platform to perform the operations described herein. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, the interfaces that transmit and/or receive signals, etc.), and others.
An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
Although flow diagrams and/or state diagrams may have been used herein to describe embodiments, the inventions are not limited to those diagrams or to corresponding descriptions herein. For example, flow need not move through each illustrated box or state, or in exactly the same order as illustrated and described herein.
The inventions are not restricted to the particular details listed herein. Indeed, those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present inventions. Accordingly, it is the following claims including any amendments thereto that define the scope of the inventions.

Claims

1. A high speed interconnect comprising:

a layer of FR4 material;

a trench in the layer of FR4 material, wherein the trench is filled with a homogenous material;

a pair of transmission lines located near the trench.

2. The high speed interconnect of claim 1, wherein the homogenous material is at least one of an epoxy, Teflon, nylon, alumina, and ceramic.

3. The high speed interconnect of claim 1, wherein the homogenous material is a material that is less lossy than FR4.

4. The high speed interconnect of claim 1, wherein the homogenous material is a low loss material.

5. The high speed interconnect of claim 1, wherein the pair of transmission lines is a differential pair of transmission lines.

6. The high speed interconnect of claim 1, wherein the high speed interconnect is a bus.

7. The high speed interconnect of claim 6, wherein the bus is a memory bus.

8. The high speed interconnect of claim 6, wherein the bus is a front side bus.

9. The high speed interconnect of claim 1, wherein the pair of transmission lines is located over the trench.

10. A method of forming a high speed interconnect comprising:

creating a trench in a layer of FR4 material;

inserting a homogenous material into the trench; and

forming a pair of transmission lines near the trench.

11. The method of claim 10, wherein the trench in the layer of FR4 material is created by milling.

12. The method of claim 10, wherein the trench in the layer of FR4 material is created by laser etching.

13. The method of claim 10, wherein the pair of transmission lines are formed by etching.

14. The method of claim 10, wherein the homogenous material is at least one of an epoxy, Teflon, nylon, alumina, and ceramic.

15. The method of claim 10, wherein the homogenous material is a material that is less lossy than FR4.

16. The method of claim 10, wherein the homogenous material is a low loss material.

17. The method of claim 10, wherein the pair of transmission lines is a differential pair of transmission lines.

18. The method of claim 10, wherein the high speed interconnect is a bus.

19. The method of claim 10, wherein the pair of transmission lines is formed over the trench.

20. A system comprising:

a first device;

a second device; and

a high speed interconnect to propagate a signal between the first device and the second device, the high speed interconnect including:

a layer of FR4 material;

a pair of transmission lines located near the trench.

21. The system of claim 20, wherein the first device is a processor and the second device is a chipset.

22. The system of claim 20, wherein the first device is a chipset and the second device is a memory.

23. The system of claim 20, wherein the high speed interconnect is included in a board.

24. The system of claim 20, wherein the first device and the second device are on the board.

25. The system of claim 20, wherein the homogenous material is at least one of an epoxy, Teflon, nylon, alumina, and ceramic.

26. The system of claim 20, wherein the homogenous material is a material that is less lossy than FR4.

27. The system of claim 20, wherein the homogenous material is a low loss material.

28. The system of claim 20, wherein the pair of transmission lines is a differential pair of transmission lines.

29. The system of claim 20, wherein the high speed interconnect is a bus.

30. The system of claim 29, wherein the bus is a memory bus.

31. The system of claim 29, wherein the bus is a front side bus.

32. The system of claim 20, wherein the pair of transmission lines is located over the trench.