US20070176278A1 - Multi-chips stacked package - Google Patents
Multi-chips stacked package Download PDFInfo
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- US20070176278A1 US20070176278A1 US11/727,426 US72742607A US2007176278A1 US 20070176278 A1 US20070176278 A1 US 20070176278A1 US 72742607 A US72742607 A US 72742607A US 2007176278 A1 US2007176278 A1 US 2007176278A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H01L2924/0001—Technical content checked by a classifier
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Definitions
- This invention relates to a multi-chips stacked package. More particularly, the present invention is related to a multi-chips stacked package having a carrier for carrying the upper chip for preventing the upper chip from being directly disposed on the lower chip.
- chip packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance.
- Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
- MCM multi-chips module
- said MCM package mainly comprises at least two chips encapsulated therein, for example a processor unit, a memory unit and related logic units, so as to upgrade the electrical performance of said assembly package.
- the electrical paths between the chips in said MCM package are short so as to reduce the signal delay and save the reading and writing time.
- conventional MCM packages shall be a multi-chips side-by-side package or a multi-chips stacked package.
- FIG. 1 it illustrates a multi-chips stacked package and said stacked package is formed by disposing upper chips 12 and 13 on a lower chip 14 by wire-bonding and chip-stacking technology, electrically connecting the upper chips 12 and 13 to a substrate 16 respectively and electrically connecting the upper chips 12 and 13 with each other via the electrically conductive wires 18 .
- the upper chip 12 is partially disposed on the lower chip 14 and overhangs over the lower chip 14 .
- the upper chip 13 is also partially disposed on the lower chip 14 and overhangs over the lower chip 14 .
- the upper chips 12 and 13 will be damaged and cracked more easily in the operation of the wire-bonging process.
- lower chips 22 and 23 are disposed on the substrate 26 , and the upper chip 24 is mounted on the lower chips 22 and 23 simultaneously so that the upper chip 24 can be supported firmly by the lower chips 22 and 23 and the substrate 26 , and prevented from being damaged and cracked.
- the lower chips 22 and 23 When the lower chips 22 and 23 are adjacent to each other and connect with each other, the lower chip 22 will be pressed against the lower chip 23 due to thermal expansion. Thus, in order to prevent the above-mentioned problem, the lower chips 22 and 23 shall be apart from each other in a distance. However, when the distance between the lower chips 22 and 23 is larger than 50 ⁇ m, the portion 242 of the lower surface of the upper chip 24 not supported by the lower chips 22 and 23 will be damaged easily in the performance of the wire-bonding process.
- an objective of this invention is to provide a multi-chips stacked package to improve the reliability of the wire-bonding process and prevent the upper chip from being easily damaged and cracked.
- a carrier is provided on the lower chips to carry the upper chip so as to prevent the upper chip from being directly disposed on the lower chips and to solve the above-mentioned disadvantage.
- a multi-chips stacked package wherein the multi-chips stacked package mainly comprises a substrate, an upper chip, a first lower chip, a second lower chip and a carrier.
- the substrate has an upper surface for disposing the first lower chip and the second lower chip, and the lower chips are electrically connected to the substrate respectively.
- Said carrier is disposed on the first lower chip and the second lower chip, and the upper chip is mounted on the carrier and electrically connected to the carrier via a plurality of electrically conductive wires.
- the carrier may be a printed circuits board (PCB).
- the carrier comprises a core layer and a copper layer.
- the copper layer can be a circuit layer and is regarded as electrical paths for transmitting electrical signals.
- the core layer can be made of Bismaleimide-Triazine (BT) or glass epoxy resins (FR-4) so that the carrier is able to bear the wire-bonding force by the stiffness of the core layer in the performance of the wire-bonding process.
- BT Bismaleimide-Triazine
- FR-4 glass epoxy resins
- FIG. 1 is a cross-sectional view of the conventional multi-chips stacked package
- FIG. 3 is a cross-sectional view of another conventional multi-chips stacked package
- FIG. 4 is a cross-sectional view of a multi-chips stacked package according to the first embodiment
- FIG. 5 is a cross-sectional view of a multi-chips stacked package according to the second embodiment
- FIG. 6 is a cross-sectional view of a multi-chips stacked package according to the third embodiment.
- FIG. 7 is a cross-sectional view of a multi-chips stacked package according to the fourth embodiment.
- FIG. 8 is a cross-sectional view of a multi-chips stacked package according to the fifth embodiment.
- FIG. 9 is a cross-sectional view of a multi-chips stacked package according to the sixth embodiment.
- a multi-chips stacked package mainly comprises a first lower chip 32 , a second lower chip 33 , an upper chip 34 and a carrier 35 and a substrate 36 .
- the substrate 36 has an upper surface 362
- the first lower chip 32 and the second lower chip 33 are disposed on the upper surface 362 of the substrate 36 and electrically connected to the substrate 36 respectively.
- the carrier 35 is disposed on the first lower chip 32 and the second lower chip 33 simultaneously and carries the upper chip 34 , and electrically connected to the carrier 35 via the electrically conductive wires 39 .
- the carrier 35 is electrically connected to the first lower chip 32 and the second lower chip 33 through the electrically conductive wires 38 respectively.
- FIG. 5 it illustrates a second embodiment in according to this invention.
- the upper chip 34 is mounted on the carrier 35 via a plurality of electrically conductive bumps 342 , for example solder bumps and gold bumps.
- the carrier 35 further has a circuit layer 352 for electrically connecting to the electrically conductive bumps 342 .
- the upper chip 34 is electrically connected to the first lower chip 32 and the second lower chip 33 through the electrically conductive bumps 342 , the circuit layer 352 and the electrically conductive wires 38 .
- FIG. 6 it illustrates a third preferred embodiment according to this invention.
- the upper chip 34 is electrically connected to the carrier 35 via a plurality of electrically conductive bumps 342 and the upper chip 34 is electrically connected to the substrate 36 through the electrically conductive bumps 342 , the circuit layer 352 and electrically conductive wires 38 ′.
- FIG. 7 it illustrates a fourth embodiment.
- the upper chip 34 is electrically connected to the carrier 35 via a plurality of electrically conductive wires 39 by wire-bonding technology.
- the carrier 35 further comprises a circuit layer 352 so as to have the upper chip 34 electrically connected to the substrate 36 through the electrically conductive wires 39 , the circuit layer 352 and another electrically conductive wires 38 ′′.
- said carrier 35 can be a printed circuit board. Generally speaking, it is composed of a core layer and a copper layer. Therein, the copper layer is patterned to form a circuit layer to be electrical paths and the core layer is formed of a material selected from Bismaleimide-Triazine (BT) and glass epoxy resins (FR 4 ) so that the carrier 35 is able to bear the wire-bonding force by the stiffness of the core layer in the performance of the wire bonding process. Thus, the upper chip 34 can be prevented from being damaged. It should be noted that the reference numeral of each element shown in FIG. 5, 6 , and 7 are corresponding the reference one provided in FIG. 4 .
- the first lower chip 42 and the second lower chip 43 are disposed on the upper surface 462 of the substrate 46 and are electrically connected to the substrate 46 via electrically conductive bumps 424 and 434 respectively.
- the carrier 45 is disposed on the first lower chip 42 and the second lower chip 43 simultaneously, and is electrically connected to the first lower chip 42 and the second lower chip 43 through electrically conductive bumps 47 , a circuit layer 452 , electrically conductive wires 49 and redistributed layers 422 and 432 formed on the back surface of the chip 42 and 43 .
- an encapsulation 41 enclosing the first lower chip 42 , the second lower chip 43 and the upper chip 44 so as to prevent the chips 42 , 43 and 44 from being moisturized.
- first lower chip 42 and said second lower chip 43 are disposed on the upper surface 462 of the substrate 46 , and electrically connected to the substrate 46 via electrically conductive wires 48 .
- the carrier 45 is disposed on the first lower chip 42 and the second lower chip 43 simultaneously, and electrically connected to the first lower chip 42 and the second lower chip 43 through electrically conductive bumps 47 .
- the upper chip 44 is disposed on the carrier 45 and electrically connected to the first lower chip 42 and the second lower chip 43 through electrically conductive wires 49 , a circuit layer 452 , a plurality of electrically conductive bumps 47 .
- the substrate 46 After the electrical signals are transmitted from the upper chip 44 to the first lower chip 42 and the second lower chip 43 , the signals will be transmitted to the substrate 46 through electrically conductive wires 48 .
- the reference numeral of each element shown in FIG. 9 are corresponding the reference one provided in FIG. 8 .
- the substrate as mentioned above can also be replaced by a lead-frame. Accordingly, said package can be mounted to a motherboard by surface mount technology (SMT) without any further solder balls formed on the lower surface of the lead-frame.
- SMT surface mount technology
- the upper chip is not directly disposed on the first lower chip and the second lower chip with a portion not supported by the first lower chip and the second lower chip.
- the upper chip does not overhang the first lower chip and the second lower chip due to the carrier entirely carrying the upper chip.
- the carrier can prevent the upper chip from being damaged and cracked in the performance of the electrically conductive wires bonding the upper chip to the substrate.
- the carrier may be designed to dispose across the first lower chip and the second lower chip so as to carry the upper chip above the lower chips. Consequently, the length of the diagonal of the upper surface or the lower surface of the upper chip may less than said distance as shown above.
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
A multi-chips stacked package mainly comprises a substrate, a first lower chip, a second lower chip, an upper chip and a carrier. The substrate has an upper surface, and the first lower chip and the second lower chip are disposed on the upper surface of the substrate and electrically connected to the substrate. The carrier is disposed on and electrically connected to the first lower chip and the second lower chip simultaneously, and the upper chip is mounted on the carrier. Moreover, the upper chip is electrically connected to the substrate through the carrier, the first lower chip or the second lower chip.
Description
- 1. Field of Invention
- This invention relates to a multi-chips stacked package. More particularly, the present invention is related to a multi-chips stacked package having a carrier for carrying the upper chip for preventing the upper chip from being directly disposed on the lower chip.
- 2. Related Art
- Recently, integrated circuit (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
- Due to the assembly package in miniature and the integrated circuits operation in high frequency, MCM (multi-chips module) packages are commonly used in said assembly packages and electronic devices. Usually, said MCM package mainly comprises at least two chips encapsulated therein, for example a processor unit, a memory unit and related logic units, so as to upgrade the electrical performance of said assembly package. In addition, the electrical paths between the chips in said MCM package are short so as to reduce the signal delay and save the reading and writing time.
- Generally speaking, conventional MCM packages shall be a multi-chips side-by-side package or a multi-chips stacked package. As shown in
FIG. 1 , it illustrates a multi-chips stacked package and said stacked package is formed by disposingupper chips lower chip 14 by wire-bonding and chip-stacking technology, electrically connecting theupper chips substrate 16 respectively and electrically connecting theupper chips conductive wires 18. However, theupper chip 12 is partially disposed on thelower chip 14 and overhangs over thelower chip 14. Similarly, theupper chip 13 is also partially disposed on thelower chip 14 and overhangs over thelower chip 14. Thus, theupper chips FIG. 2 ,lower chips substrate 26, and theupper chip 24 is mounted on thelower chips upper chip 24 can be supported firmly by thelower chips substrate 26, and prevented from being damaged and cracked. - As mentioned above, however, there are several disadvantages as following shown. When the
lower chips lower chip 22 will be pressed against thelower chip 23 due to thermal expansion. Thus, in order to prevent the above-mentioned problem, thelower chips lower chips portion 242 of the lower surface of theupper chip 24 not supported by thelower chips - Therefore, providing another assembly package to solve the mentioned-above disadvantages is the most important task in this invention.
- In view of the above-mentioned problems, an objective of this invention is to provide a multi-chips stacked package to improve the reliability of the wire-bonding process and prevent the upper chip from being easily damaged and cracked. Therein, a carrier is provided on the lower chips to carry the upper chip so as to prevent the upper chip from being directly disposed on the lower chips and to solve the above-mentioned disadvantage.
- To achieve the above-mentioned objective, a multi-chips stacked package is provided, wherein the multi-chips stacked package mainly comprises a substrate, an upper chip, a first lower chip, a second lower chip and a carrier. Therein, the substrate has an upper surface for disposing the first lower chip and the second lower chip, and the lower chips are electrically connected to the substrate respectively. Said carrier is disposed on the first lower chip and the second lower chip, and the upper chip is mounted on the carrier and electrically connected to the carrier via a plurality of electrically conductive wires.
- As mentioned above, the carrier may be a printed circuits board (PCB). Generally speaking, the carrier comprises a core layer and a copper layer. Therein the copper layer can be a circuit layer and is regarded as electrical paths for transmitting electrical signals. The core layer can be made of Bismaleimide-Triazine (BT) or glass epoxy resins (FR-4) so that the carrier is able to bear the wire-bonding force by the stiffness of the core layer in the performance of the wire-bonding process. Thus, the upper chip can be prevented from damaging.
- The invention will become more fully understood from the detailed description given herein below illustrations only, and thus are not limitative of the present invention, and wherein:
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FIG. 1 is a cross-sectional view of the conventional multi-chips stacked package; -
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FIG. 2 is a cross-sectional view of another conventional multi-chips stacked package;
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FIG. 3 is a cross-sectional view of another conventional multi-chips stacked package; -
FIG. 4 is a cross-sectional view of a multi-chips stacked package according to the first embodiment; -
FIG. 5 is a cross-sectional view of a multi-chips stacked package according to the second embodiment; -
FIG. 6 is a cross-sectional view of a multi-chips stacked package according to the third embodiment; -
FIG. 7 is a cross-sectional view of a multi-chips stacked package according to the fourth embodiment; -
FIG. 8 is a cross-sectional view of a multi-chips stacked package according to the fifth embodiment; and -
FIG. 9 is a cross-sectional view of a multi-chips stacked package according to the sixth embodiment. - The multi-chips stacked package according to the preferred embodiment of this invention will be described herein below with reference to the accompanying drawings, wherein the same reference numbers refer to the same elements.
- In accordance with a first preferred embodiment as shown in
FIG. 4 , there is provided a multi-chips stacked package. The multi-chips stacked package mainly comprises a firstlower chip 32, a secondlower chip 33, anupper chip 34 and acarrier 35 and asubstrate 36. Therein, thesubstrate 36 has anupper surface 362, and the firstlower chip 32 and the secondlower chip 33 are disposed on theupper surface 362 of thesubstrate 36 and electrically connected to thesubstrate 36 respectively. In addition, thecarrier 35 is disposed on the firstlower chip 32 and the secondlower chip 33 simultaneously and carries theupper chip 34, and electrically connected to thecarrier 35 via the electricallyconductive wires 39. Besides, thecarrier 35 is electrically connected to the firstlower chip 32 and the secondlower chip 33 through the electricallyconductive wires 38 respectively. - Besides, as shown in
FIG. 5 , it illustrates a second embodiment in according to this invention. Theupper chip 34 is mounted on thecarrier 35 via a plurality of electricallyconductive bumps 342, for example solder bumps and gold bumps. In addition, thecarrier 35 further has acircuit layer 352 for electrically connecting to the electricallyconductive bumps 342. Thus, theupper chip 34 is electrically connected to the firstlower chip 32 and the secondlower chip 33 through the electricallyconductive bumps 342, thecircuit layer 352 and the electricallyconductive wires 38. - Furthermore, as shown in
FIG. 6 , it illustrates a third preferred embodiment according to this invention. Theupper chip 34 is electrically connected to thecarrier 35 via a plurality of electricallyconductive bumps 342 and theupper chip 34 is electrically connected to thesubstrate 36 through the electricallyconductive bumps 342, thecircuit layer 352 and electricallyconductive wires 38′. - Next, as shown in
FIG. 7 , it illustrates a fourth embodiment. Theupper chip 34 is electrically connected to thecarrier 35 via a plurality of electricallyconductive wires 39 by wire-bonding technology. Similarly, thecarrier 35 further comprises acircuit layer 352 so as to have theupper chip 34 electrically connected to thesubstrate 36 through the electricallyconductive wires 39, thecircuit layer 352 and another electricallyconductive wires 38″. - As mentioned above, said
carrier 35 can be a printed circuit board. Generally speaking, it is composed of a core layer and a copper layer. Therein, the copper layer is patterned to form a circuit layer to be electrical paths and the core layer is formed of a material selected from Bismaleimide-Triazine (BT) and glass epoxy resins (FR4) so that thecarrier 35 is able to bear the wire-bonding force by the stiffness of the core layer in the performance of the wire bonding process. Thus, theupper chip 34 can be prevented from being damaged. It should be noted that the reference numeral of each element shown inFIG. 5, 6 , and 7 are corresponding the reference one provided inFIG. 4 . - Next, referring to
FIG. 8 , a fifth preferred embodiment is provided. The firstlower chip 42 and the secondlower chip 43 are disposed on theupper surface 462 of thesubstrate 46 and are electrically connected to thesubstrate 46 via electricallyconductive bumps carrier 45 is disposed on the firstlower chip 42 and the secondlower chip 43 simultaneously, and is electrically connected to the firstlower chip 42 and the secondlower chip 43 through electricallyconductive bumps 47, acircuit layer 452, electricallyconductive wires 49 and redistributedlayers chip encapsulation 41 enclosing the firstlower chip 42, the secondlower chip 43 and theupper chip 44 so as to prevent thechips - Finally, referring to
FIG. 9 , there is provided a sixth embodiment. Said firstlower chip 42 and said secondlower chip 43 are disposed on theupper surface 462 of thesubstrate 46, and electrically connected to thesubstrate 46 via electricallyconductive wires 48. In addition, thecarrier 45 is disposed on the firstlower chip 42 and the secondlower chip 43 simultaneously, and electrically connected to the firstlower chip 42 and the secondlower chip 43 through electrically conductive bumps 47. Moreover, theupper chip 44 is disposed on thecarrier 45 and electrically connected to the firstlower chip 42 and the secondlower chip 43 through electricallyconductive wires 49, acircuit layer 452, a plurality of electricallyconductive bumps 47. After the electrical signals are transmitted from theupper chip 44 to the firstlower chip 42 and the secondlower chip 43, the signals will be transmitted to thesubstrate 46 through electricallyconductive wires 48. It should be noted that the reference numeral of each element shown inFIG. 9 are corresponding the reference one provided inFIG. 8 . Specifically, the substrate as mentioned above can also be replaced by a lead-frame. Accordingly, said package can be mounted to a motherboard by surface mount technology (SMT) without any further solder balls formed on the lower surface of the lead-frame. - In summary, according to this invention, the upper chip is not directly disposed on the first lower chip and the second lower chip with a portion not supported by the first lower chip and the second lower chip. Namely, the upper chip does not overhang the first lower chip and the second lower chip due to the carrier entirely carrying the upper chip. Accordingly, when the first lower chip is apart from the second chip with a distance more than 50 μm, the carrier can prevent the upper chip from being damaged and cracked in the performance of the electrically conductive wires bonding the upper chip to the substrate. In addition, the carrier may be designed to dispose across the first lower chip and the second lower chip so as to carry the upper chip above the lower chips. Consequently, the length of the diagonal of the upper surface or the lower surface of the upper chip may less than said distance as shown above.
- Although the invention has been described in considerable detail with reference to certain preferred embodiments, it will be appreciated and understood that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (21)
1-20. (canceled)
21. A multi-chips stacked package, comprising:
a substrate having an upper surface and a lower surface;
a first lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;
a second lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;
a carrier disposed on the first lower chip and the second lower chip simultaneously; and
an upper chip disposed on the carrier and electrically connected to the carrier,
wherein the carrier comprises a circuit layer respectively electrically connected to the first lower chip and the second lower chip through at least one electrically conductive wire, and the first lower chip and the second lower chip are respectively electrically connected to the substrate through at least one electrically conductive wire.
22. The multi-chips stacked package of claim 21 , wherein the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive wires.
23. The multi-chips stacked package of claim 21 , wherein the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive bumps.
24. The multi-chips stacked package of claim 21 , wherein the first lower chip apart from the second lower chip with a distance.
25. The multi-chips stacked package of claim 24 , wherein the distance is smaller than the length of the carrier.
26. The multi-chips stacked package of claim 21 , wherein the substrate and/or the carrier is a printed circuit board.
27. The multi-chips stacked package of claim 21 , further comprising a plurality of solder balls formed on the lower surface of the substrate.
28. A multi-chips stacked package, comprising:
a substrate having an upper surface and a lower surface;
a first lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;
a second lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;
a carrier disposed on the first lower chip and the second lower chip simultaneously; and
an upper chip disposed on the carrier and electrically connected to the carrier,
wherein the carrier comprises a circuit layer electrically connected to the substrate through at least one electrically conductive wire, and the first lower chip and the second lower chip are respectively electrically connected to the substrate through at least one electrically conductive wire.
29. The multi-chips stacked package of claim 28 , wherein the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive wires.
30. The multi-chips stacked package of claim 28 , wherein the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive bumps.
31. The multi-chips stacked package of claim 28 , wherein the first lower chip is apart from the second lower chip with a distance.
32. The multi-chips stacked package of claim 31 , wherein the distance is smaller than the length of the carrier.
33. The multi-chips stacked package of claim 28 , wherein the substrate and/or the carrier is a printed circuit board.
34. The multi-chips stacked package of claim 28 , further comprising a plurality of solder balls formed on the lower surface of the substrate.
35. A multi-chips stacked package, comprising:
a substrate having an upper surface and a lower surface;
a first lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;
a second lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;
a carrier disposed on the first lower chip and the second lower chip simultaneously; and
an upper chip disposed on the carrier and electrically connected to the carrier;
wherein the carrier comprises a core layer and a circuit layer, the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive wires, the circuit layer of the carrier is electrically connected to the first lower chip or the second lower chip through at least one electrically conductive bump, and the first lower chip and the second lower chip are respectively electrically connected to the substrate through at least one electrically conductive wire.
36. The multi-chips stacked package of claim 35 , wherein the first lower chip and/or the second lower chip are/is electrically connected to the substrate through a plurality of electrically conductive bumps.
37. The multi-chips stacked package of claim 35 , wherein the first lower chip is apart from the second lower chip with a distance.
38. The multi-chips stacked package of claim 37 , wherein the distance is smaller than the length of the carrier.
39. The multi-chips stacked package of claim 35 , wherein the substrate and/or the carrier is a printed circuit board.
40. The multi-chips stacked package of claim 35 , further comprising a plurality of solder balls formed on the lower surface of the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/727,426 US20070176278A1 (en) | 2003-03-21 | 2007-03-27 | Multi-chips stacked package |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092106424A TW588446B (en) | 2003-03-21 | 2003-03-21 | Multi-chips stacked package |
TW092106424 | 2003-03-21 | ||
US10/747,114 US7215016B2 (en) | 2003-03-21 | 2003-12-30 | Multi-chips stacked package |
US11/727,426 US20070176278A1 (en) | 2003-03-21 | 2007-03-27 | Multi-chips stacked package |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/747,114 Continuation US7215016B2 (en) | 2003-03-21 | 2003-12-30 | Multi-chips stacked package |
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US20070176278A1 true US20070176278A1 (en) | 2007-08-02 |
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US10/747,114 Active 2024-10-03 US7215016B2 (en) | 2003-03-21 | 2003-12-30 | Multi-chips stacked package |
US11/727,426 Abandoned US20070176278A1 (en) | 2003-03-21 | 2007-03-27 | Multi-chips stacked package |
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US10/747,114 Active 2024-10-03 US7215016B2 (en) | 2003-03-21 | 2003-12-30 | Multi-chips stacked package |
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US (2) | US7215016B2 (en) |
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Also Published As
Publication number | Publication date |
---|---|
US7215016B2 (en) | 2007-05-08 |
TW588446B (en) | 2004-05-21 |
TW200419764A (en) | 2004-10-01 |
US20040184250A1 (en) | 2004-09-23 |
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