US20070278583A1 - Gate stress engineering for mosfet - Google Patents
Gate stress engineering for mosfet Download PDFInfo
- Publication number
- US20070278583A1 US20070278583A1 US11/421,510 US42151006A US2007278583A1 US 20070278583 A1 US20070278583 A1 US 20070278583A1 US 42151006 A US42151006 A US 42151006A US 2007278583 A1 US2007278583 A1 US 2007278583A1
- Authority
- US
- United States
- Prior art keywords
- layer
- silicide
- gate
- forming
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000002210 silicon-based material Substances 0.000 claims abstract description 52
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000004020 conductor Substances 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 18
- 230000008859 change Effects 0.000 claims abstract description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229910052762 osmium Inorganic materials 0.000 claims description 8
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 230000001939 inductive effect Effects 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052702 rhenium Inorganic materials 0.000 claims description 3
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims 2
- 206010010144 Completed suicide Diseases 0.000 abstract description 5
- 125000006850 spacer group Chemical group 0.000 abstract description 4
- 108091006146 Channels Proteins 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910008814 WSi2 Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910018999 CoSi2 Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
Definitions
- This invention relates generally to semiconductor device manufacturing, and in particular the manufacture of metal oxide semiconductor field effect transistor (MOSFET) structures. More particularly, the invention relates to methods of making MOSFETs that apply gate stress engineering principles.
- MOSFET metal oxide semiconductor field effect transistor
- CMOS complimentary metal oxide semiconductor
- FETs field effect transistors
- tensile stress is known to enhance electron mobility (or n-channel FET (nFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents).
- the source of stress can be inserted from multiple elements in a MOSFET, such as the shallow trench isolation (STI), embedded source/drain stressors, a stressed substrate, or an additional nitride capping layer.
- STI shallow trench isolation
- embedded source/drain stressors embedded source/drain stressors
- stressed substrate or an additional nitride capping layer.
- a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon materials and a conducting material layer, above a gate dielectric, and is surrounded by a spacer, and then providing a volume change to some of the materials in the gate so that a stress is induced in the channel as a result of the volume change.
- a gate structure for a MOSFET structure may include a layer of silicon material over a gate dielectric and a first silicide and second silicide over the silicon material, where the first silicide induces a stress in a channel of the device.
- the first and second suicides may be separated by a layer of silicon material or in contact with each other.
- a first aspect of the invention provides a method of stressing a channel of a transistor, comprising: forming a gate over the channel, wherein the gate includes a plurality of materials above a gate dielectric; and creating a volume change to at least a portion of the plurality of materials, thereby inducing a stress in the channel.
- a second aspect of the invention provides a method of forming a gate structure for a MOSFET structure comprising: providing a substrate; providing a gate upon the substrate including: forming an oxide layer upon the substrate; forming a first layer of a silicon material above the oxide layer; forming a layer of a conducting material above the first layer; forming a second layer of a silicon material above the layer of conducting material, wherein the first layer, the second layer, and the conducting material layer collectively have a first volume; forming the gate from the layers; and performing a process subsequent the forming steps, whereby a silicide is formed from the conducting material and the silicon material, wherein the first layer, the second layer, and the silicide collectively have a second volume different than the first volume.
- a third aspect of the invention provides a gate structure for a MOSFET structure, comprising: a gate dielectric on a substrate; a first layer of a silicon material overlying the gate dielectric; a first silicide overlying the first layer of the silicon material and in contact therewith, wherein the first silicide induces a stress in a channel in the MOSFET structure; and a second silicide overlying the first silicide.
- FIGS. 1-3 show cross-sectional views of one embodiment of a method according to the invention.
- FIG. 4 shows a cross-sectional view of one embodiment of a structure according to the invention.
- FIG. 5 shows a cross-sectional view of another embodiment of a structure according to the invention.
- FIG. 1 shows a cross sectional view of a structure at the beginning of a method according to one embodiment of the present invention.
- the methods ultimately induce a stress in a channel 13 ( FIGS. 4 , 5 ) of a transistor 25 ( FIGS. 4 , 5 ) as a result of the particular construction of a gate structure 20 ( FIG. 4 ) in a MOSFET structure 25 ( FIGS. 4 , 5 ) thereby enhancing performance in MOSFET structure 25 ( FIGS. 4 , 5 ).
- a gate dielectric 4 may be formed over a substrate 2 .
- a first layer of a silicon material 6 is formed over gate dielectric 4 .
- a layer of a conducting material 8 is formed over first layer of silicon material 6 .
- a second layer of a silicon material 10 is then formed over layer of conducting material 8 .
- Substrate 2 may include, for example, silicon, silicon-on-insulator (SOI), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other suitable semiconductor substrates.
- SOI silicon-on-insulator
- SiGe silicon germanium
- SiC silicon carbide
- SiGeC silicon germanium carbon
- GaAs gallium arsenide
- InAs indium arsenide
- InP indium phosphide
- Gate dielectric 4 may include, for example, a silicon oxide (SiO 2 ), silicon oxynitride (SiO x N y ), silicon nitride (Si 3 N 4 ), or other metal oxides having a high dielectric constant. A thickness of gate dielectric 4 may be in range from approximately 0.5 nm to approximately 20 nm.
- First and second layers of silicon material 6 , 10 may include, for example, polysilicon (poly-Si or poly), polysilicon germanium (poly-SiGe), or amorphous silicon.
- Conducting material 8 may include a material from a group consisting of: nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), cobalt (Co), tantalum (Ta), molybdenum (Mo), osmium (Os), and rhenium (Re). Conducting material 8 may further include a metal, an alloy, germanium (Ge), and the like, or other suitable material now known or later developed, for purposes of aiding conduction. A thickness of layer of conducting material 8 formed between first layer of silicon material 6 and second layer of silicon material 10 may be in a range of approximately 10 angstroms to approximately 1,000 angstroms. Forming of conducting material 8 , gate dielectric 4 , and silicon materials 6 , 10 , may be provided by any known or later developed processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- a photoresist 12 is patterned for gate structure 20 ( FIG. 3 ) formation, and etching (e.g., reactive ion etching (RIE)) to remove portions of gate dielectric 4 , first and second layer of silicon material (e.g., poly) 6 , 10 , and conducting material 8 is performed.
- etching e.g., reactive ion etching (RIE)
- a subsequent step may include a conventional self-align processes, forming spacers, and using implants to form extensions and a source 16 and a drain 16 (see e.g., FIG. 4 ) employing now known or later developed techniques.
- one or multiple anneal steps are performed, wherein elevated temperatures are applied, as is known in the art.
- This known anneal step has a tangential benefit of also forming a silicide 9 at the elevated temperature from a reaction of conducting material 8 ( FIG. 2 ) and at least portions of adjoining silicon material 6 , 10 ( FIG. 2 ).
- silicon material 6 , 10 includes poly
- the silicon material 6 , 10 will react with a selected conducting material 8 (e.g., tungsten) to form tungsten suicide (WSi 2 ).
- the elevated temperature may be in a range of approximately 300° C. to approximately 1,400° C., or may vary as suitable depending on particular materials (e.g., first layer of silicon material 6 , conducting material 8 , second layer of silicon material 10 ) being formed in gate structure 20 .
- a volume change occurs to various materials (e.g., first layer of silicon material 6 and conducting material 8 ) upon their reaction with each other in forming silicide 9 .
- first layer of silicon material 6 , second layer of silicon material 10 , and conducting material 8 collectively may have a first volume.
- silicide 9 is formed and a portion of first layer of silicon material 6 ′, and a portion of second layer of silicon material 10 ′ remain.
- the remaining materials i.e., 6 ′, 9 , 10 ′
- Change of volume may be an increase (i.e., expansion) or a decrease (i.e., shrinking) depending on what particular conducting material 8 is formed in gate structure 20 .
- certain metals i.e., conducting material 8
- conducting material 8 such as osmium (Os)
- Os osmium
- OS 2 Si 3 osmium silicide
- certain metals i.e., conducting material 8
- conducting material 8 such as nickel (Ni), platinum (Pt), or cobalt (Co)
- polysilicon or amorphous silicon e.g., first layer of silicon material 6
- silicide 9 when reacting with polysilicon or amorphous silicon (e.g., first layer of silicon material 6 ) may decrease in volume when silicide 9 is formed therefrom.
- Induced stress in channel 13 may be compressive or tensile, depending on the type of volume change. If volume change is positive (i.e., expansion) after reaction, a tensile stress is induced in channel 13 . If volume change is negative (i.e., shrinking) after reaction, a compressive stress is induced in channel 13 .
- nFET n-type channel MOSFET
- pFET p-type channel MOSFET
- a specific conducting material 8 for formation of silicide 9 , may be selected and formed in gate structure 20 so as to create either a volume change increase or a volume change decrease and the concomitant induced compressive or tensile stress in channel 13 .
- Different conducting materials 8 have different consumption rates when reacting with silicon (e.g., first layer of silicon material 6 ) to form a silicide 9 .
- tungsten silicide WSi 2
- a ratio of thickness of silicide formed to a sum of total thickness of metal and silicon may be approximately 0.73 (i.e., less than 1), which results in a volume shrinkage inducing a compressive stress in channel 13 .
- silicide 9 i.e., tungsten silicide
- a ratio of thickness of silicide formed to a sum of total thickness of metal and silicon may be approximately 1.59 (i.e., greater than 1), which results in a volume expansion inducing a tensile stress in channel 13 .
- silicide 9 i.e., osmium silicide
- An added benefit is that performance enhancement may be achieved for either nFET and PFET structures under methods employed herein.
- Gate structure 20 may include gate dielectric 4 , a remaining portion of first layer of silicon material 6 ′, silicide 9 , a remaining portion of second layer of silicon material 10 ′, and a second, or top gate, silicide 14 . Further, portions of source 16 and drain 16 may be converted to suicides (e.g., CoSi 2 , NiSi, etc.) under known silicidation processes.
- suicides e.g., CoSi 2 , NiSi, etc.
- suicide 9 should not abut gate dielectric 4 (e.g., silicon oxide).
- First layer of silicon material 6 ′ that remains (after forming silicidation process) should have a thickness of at least approximately 10 angstroms so as to serve as a separation of silicide 9 from gate dielectric 4 .
- an initial thickness of first layer of silicon material 6 ( FIG. 1 ) formed over gate dielectric 4 should be sufficient enough so that after the silicidation process, a remaining first layer of silicon material 6 ′ is adequate (e.g., at least approximately 10 angstroms).
- FIG. 5 A completed gate structure 20 for a MOSFET structure 25 of a second embodiment is shown in FIG. 5 after completion of silicidation processes as discussed above.
- a second, or top gate, silicide 14 is in direct contact (i.e., abuts) with first silicide 9 . That is, no second silicon material 10 ′ ( FIG. 3 ) remains in gate structure 20 after silicidation.
Abstract
Description
- 1. Technical Field
- This invention relates generally to semiconductor device manufacturing, and in particular the manufacture of metal oxide semiconductor field effect transistor (MOSFET) structures. More particularly, the invention relates to methods of making MOSFETs that apply gate stress engineering principles.
- 2. Background Art
- With the aggressive scaling of complimentary metal oxide semiconductor (CMOS) technologies, stress engineering is becoming more important to improve device performance. The application of stresses to channels of field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (nFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents).
- The source of stress can be inserted from multiple elements in a MOSFET, such as the shallow trench isolation (STI), embedded source/drain stressors, a stressed substrate, or an additional nitride capping layer. In view of the foregoing, there is a need in the art for an improvement to the related art.
- Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon materials and a conducting material layer, above a gate dielectric, and is surrounded by a spacer, and then providing a volume change to some of the materials in the gate so that a stress is induced in the channel as a result of the volume change. A gate structure for a MOSFET structure may include a layer of silicon material over a gate dielectric and a first silicide and second silicide over the silicon material, where the first silicide induces a stress in a channel of the device. The first and second suicides may be separated by a layer of silicon material or in contact with each other.
- A first aspect of the invention provides a method of stressing a channel of a transistor, comprising: forming a gate over the channel, wherein the gate includes a plurality of materials above a gate dielectric; and creating a volume change to at least a portion of the plurality of materials, thereby inducing a stress in the channel.
- A second aspect of the invention provides a method of forming a gate structure for a MOSFET structure comprising: providing a substrate; providing a gate upon the substrate including: forming an oxide layer upon the substrate; forming a first layer of a silicon material above the oxide layer; forming a layer of a conducting material above the first layer; forming a second layer of a silicon material above the layer of conducting material, wherein the first layer, the second layer, and the conducting material layer collectively have a first volume; forming the gate from the layers; and performing a process subsequent the forming steps, whereby a silicide is formed from the conducting material and the silicon material, wherein the first layer, the second layer, and the silicide collectively have a second volume different than the first volume.
- A third aspect of the invention provides a gate structure for a MOSFET structure, comprising: a gate dielectric on a substrate; a first layer of a silicon material overlying the gate dielectric; a first silicide overlying the first layer of the silicon material and in contact therewith, wherein the first silicide induces a stress in a channel in the MOSFET structure; and a second silicide overlying the first silicide.
- The illustrative aspects of the present invention are designed to solve the problems herein described and/or other problems not discussed.
- These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which:
-
FIGS. 1-3 show cross-sectional views of one embodiment of a method according to the invention. -
FIG. 4 shows a cross-sectional view of one embodiment of a structure according to the invention. -
FIG. 5 shows a cross-sectional view of another embodiment of a structure according to the invention. - It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
- Referring to the drawings,
FIG. 1 shows a cross sectional view of a structure at the beginning of a method according to one embodiment of the present invention. The methods ultimately induce a stress in a channel 13 (FIGS. 4 , 5) of a transistor 25 (FIGS. 4 , 5) as a result of the particular construction of a gate structure 20 (FIG. 4 ) in a MOSFET structure 25 (FIGS. 4 , 5) thereby enhancing performance in MOSFET structure 25 (FIGS. 4 , 5). - Referring to
FIG. 1 , a gate dielectric 4 may be formed over asubstrate 2. A first layer of asilicon material 6 is formed over gate dielectric 4. A layer of a conductingmaterial 8 is formed over first layer ofsilicon material 6. Typically, a second layer of asilicon material 10 is then formed over layer of conductingmaterial 8. -
Substrate 2 may include, for example, silicon, silicon-on-insulator (SOI), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other suitable semiconductor substrates. - Gate dielectric 4 may include, for example, a silicon oxide (SiO2), silicon oxynitride (SiOxNy), silicon nitride (Si3N4), or other metal oxides having a high dielectric constant. A thickness of gate dielectric 4 may be in range from approximately 0.5 nm to approximately 20 nm. First and second layers of
silicon material - Conducting
material 8 may include a material from a group consisting of: nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), cobalt (Co), tantalum (Ta), molybdenum (Mo), osmium (Os), and rhenium (Re). Conductingmaterial 8 may further include a metal, an alloy, germanium (Ge), and the like, or other suitable material now known or later developed, for purposes of aiding conduction. A thickness of layer of conductingmaterial 8 formed between first layer ofsilicon material 6 and second layer ofsilicon material 10 may be in a range of approximately 10 angstroms to approximately 1,000 angstroms. Forming of conductingmaterial 8, gate dielectric 4, andsilicon materials - Next, as shown in
FIG. 2 , aphotoresist 12 is patterned for gate structure 20 (FIG. 3 ) formation, and etching (e.g., reactive ion etching (RIE)) to remove portions of gate dielectric 4, first and second layer of silicon material (e.g., poly) 6, 10, and conductingmaterial 8 is performed. - A subsequent step, as shown in
FIG. 3 , may include a conventional self-align processes, forming spacers, and using implants to form extensions and asource 16 and a drain 16 (see e.g.,FIG. 4 ) employing now known or later developed techniques. In one embodiment, one or multiple anneal steps are performed, wherein elevated temperatures are applied, as is known in the art. This known anneal step has a tangential benefit of also forming asilicide 9 at the elevated temperature from a reaction of conducting material 8 (FIG. 2 ) and at least portions of adjoiningsilicon material 6, 10 (FIG. 2 ). For example, ifsilicon material silicon material silicon material 6, conductingmaterial 8, second layer of silicon material 10) being formed ingate structure 20. - A volume change occurs to various materials (e.g., first layer of
silicon material 6 and conducting material 8) upon their reaction with each other in formingsilicide 9. Prior to reaction, first layer ofsilicon material 6, second layer ofsilicon material 10, and conductingmaterial 8 collectively may have a first volume. Subsequent to reaction of conductingmaterial 8 with first layer of silicon material 6 (and optionally also with second layer of silicon material 10),silicide 9 is formed and a portion of first layer ofsilicon material 6′, and a portion of second layer ofsilicon material 10′ remain. Collectively, the remaining materials (i.e., 6′, 9, 10′) may have a second volume that is unequal to first volume. Change of volume may be an increase (i.e., expansion) or a decrease (i.e., shrinking) depending on what particular conductingmaterial 8 is formed ingate structure 20. For example, certain metals (i.e., conducting material 8), such as osmium (Os), when reacting with polysilicon or amorphous silicon (e.g., first layer of silicon material 6) may increase in volume when osmium silicide (OS2Si3) assilicide 9 is formed therefrom. Conversely, certain metals (i.e., conducting material 8), such as nickel (Ni), platinum (Pt), or cobalt (Co), when reacting with polysilicon or amorphous silicon (e.g., first layer of silicon material 6) may decrease in volume whensilicide 9 is formed therefrom. - Because the silicidation process is within a confined space of
gate structure 20, when it is surrounded for example by aspacer 11, a stress will be induced in an area ofchannel 13 due to the aforementioned volume change in materials after forming ofsilicide 9. Induced stress inchannel 13 may be compressive or tensile, depending on the type of volume change. If volume change is positive (i.e., expansion) after reaction, a tensile stress is induced inchannel 13. If volume change is negative (i.e., shrinking) after reaction, a compressive stress is induced inchannel 13. It is known that a tensile stress inchannel 13 is beneficial in enhancing performance of n-type channel MOSFET (nFET); and, that a compressive stress inchannel 13 is beneficial in enhancing performance of p-type channel MOSFET (pFET). Thus, depending on whether an nFET or PFET structure is being manufactured, a specific conductingmaterial 8, for formation ofsilicide 9, may be selected and formed ingate structure 20 so as to create either a volume change increase or a volume change decrease and the concomitant induced compressive or tensile stress inchannel 13. Different conductingmaterials 8 have different consumption rates when reacting with silicon (e.g., first layer of silicon material 6) to form asilicide 9. For example, if forming tungsten silicide (WSi2) a ratio of thickness of silicide formed to a sum of total thickness of metal and silicon may be approximately 0.73 (i.e., less than 1), which results in a volume shrinkage inducing a compressive stress inchannel 13. Thus, using tungsten as conducting material 8 (FIG. 1 ) would enhance performance of a PFET, because silicide 9 (i.e., tungsten silicide) will induce compressive stress inchannel 13. Also for example, if forming osmium silicide (OS2Si3), a ratio of thickness of silicide formed to a sum of total thickness of metal and silicon may be approximately 1.59 (i.e., greater than 1), which results in a volume expansion inducing a tensile stress inchannel 13. Thus, using osmium as conducting material 8 (FIG. 1 ) would enhance performance of a nFET, because silicide 9 (i.e., osmium silicide) will induce tensile stress inchannel 13. An added benefit is that performance enhancement may be achieved for either nFET and PFET structures under methods employed herein. - Next, as shown in
FIG. 4 , a completedgate structure 20 for aMOSFET structure 25 is shown after completion of silicidation ofsource 16 and drain 16 and a conventional self-aligning process (not shown).Gate structure 20 may includegate dielectric 4, a remaining portion of first layer ofsilicon material 6′,silicide 9, a remaining portion of second layer ofsilicon material 10′, and a second, or top gate,silicide 14. Further, portions ofsource 16 and drain 16 may be converted to suicides (e.g., CoSi2, NiSi, etc.) under known silicidation processes. - In completed
gate structure 20,suicide 9 should not abut gate dielectric 4 (e.g., silicon oxide). First layer ofsilicon material 6′ that remains (after forming silicidation process) should have a thickness of at least approximately 10 angstroms so as to serve as a separation ofsilicide 9 fromgate dielectric 4. Thus, an initial thickness of first layer of silicon material 6 (FIG. 1 ) formed overgate dielectric 4 should be sufficient enough so that after the silicidation process, a remaining first layer ofsilicon material 6′ is adequate (e.g., at least approximately 10 angstroms). - A completed
gate structure 20 for aMOSFET structure 25 of a second embodiment is shown inFIG. 5 after completion of silicidation processes as discussed above. In this case, a second, or top gate,silicide 14 is in direct contact (i.e., abuts) withfirst silicide 9. That is, nosecond silicon material 10′ (FIG. 3 ) remains ingate structure 20 after silicidation. - The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/421,510 US7595233B2 (en) | 2006-06-01 | 2006-06-01 | Gate stress engineering for MOSFET |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/421,510 US7595233B2 (en) | 2006-06-01 | 2006-06-01 | Gate stress engineering for MOSFET |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070278583A1 true US20070278583A1 (en) | 2007-12-06 |
US7595233B2 US7595233B2 (en) | 2009-09-29 |
Family
ID=38789116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/421,510 Expired - Fee Related US7595233B2 (en) | 2006-06-01 | 2006-06-01 | Gate stress engineering for MOSFET |
Country Status (1)
Country | Link |
---|---|
US (1) | US7595233B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120181634A1 (en) * | 2011-01-14 | 2012-07-19 | Institute of Microelectronics, Chinese Academy of Sciences | Method of Introducing Strain Into Channel and Device Manufactured by Using the Method |
WO2018190811A1 (en) * | 2017-04-11 | 2018-10-18 | Intel Corporation | Transistors with temperature compensating gate structures |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5468684A (en) * | 1991-12-13 | 1995-11-21 | Symetrix Corporation | Integrated circuit with layered superlattice material and method of fabricating same |
US5719416A (en) * | 1991-12-13 | 1998-02-17 | Symetrix Corporation | Integrated circuit with layered superlattice material compound |
US5952701A (en) * | 1997-08-18 | 1999-09-14 | National Semiconductor Corporation | Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value |
US6214709B1 (en) * | 1998-06-08 | 2001-04-10 | United Microelectronics Corp. | Method of fabricating self-aligned silicide |
US6451693B1 (en) * | 2000-10-05 | 2002-09-17 | Advanced Micro Device, Inc. | Double silicide formation in polysicon gate without silicide in source/drain extensions |
US6455383B1 (en) * | 2001-10-25 | 2002-09-24 | Silicon-Based Technology Corp. | Methods of fabricating scaled MOSFETs |
US6455483B1 (en) * | 2000-03-28 | 2002-09-24 | Charles C. Carey | Well stimulation and formation purging composition |
US20020192932A1 (en) * | 2001-06-13 | 2002-12-19 | Taiwan Semiconductor Manufacturing Company | Salicide integration process |
US6682965B1 (en) * | 1997-03-27 | 2004-01-27 | Sony Corporation | Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect |
US6686637B1 (en) * | 2002-11-21 | 2004-02-03 | International Business Machines Corporation | Gate structure with independently tailored vertical doping profile |
US6703271B2 (en) * | 2001-11-30 | 2004-03-09 | Taiwan Semiconductor Manufacturing Company | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer |
US20050032321A1 (en) * | 2003-08-08 | 2005-02-10 | Chien-Chao Huang | Strained silicon MOS devices |
US6858506B2 (en) * | 2002-08-08 | 2005-02-22 | Macronix International Co., Ltd. | Method for fabricating locally strained channel |
US7217603B2 (en) * | 2002-06-25 | 2007-05-15 | Amberwave Systems Corporation | Methods of forming reacted conductive gate electrodes |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW432507B (en) | 1999-07-30 | 2001-05-01 | United Microelectronics Corp | Gate structure |
-
2006
- 2006-06-01 US US11/421,510 patent/US7595233B2/en not_active Expired - Fee Related
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5468684A (en) * | 1991-12-13 | 1995-11-21 | Symetrix Corporation | Integrated circuit with layered superlattice material and method of fabricating same |
US5719416A (en) * | 1991-12-13 | 1998-02-17 | Symetrix Corporation | Integrated circuit with layered superlattice material compound |
US20080176367A1 (en) * | 1997-03-27 | 2008-07-24 | Sony Corporation | Field effect transistor and fabrication thereof, semiconductor device and fabrication thereof, logic circuit including the semiconductor device, and semiconductor substrate |
US6682965B1 (en) * | 1997-03-27 | 2004-01-27 | Sony Corporation | Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect |
US5952701A (en) * | 1997-08-18 | 1999-09-14 | National Semiconductor Corporation | Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value |
US6214709B1 (en) * | 1998-06-08 | 2001-04-10 | United Microelectronics Corp. | Method of fabricating self-aligned silicide |
US6455483B1 (en) * | 2000-03-28 | 2002-09-24 | Charles C. Carey | Well stimulation and formation purging composition |
US6451693B1 (en) * | 2000-10-05 | 2002-09-17 | Advanced Micro Device, Inc. | Double silicide formation in polysicon gate without silicide in source/drain extensions |
US20020192932A1 (en) * | 2001-06-13 | 2002-12-19 | Taiwan Semiconductor Manufacturing Company | Salicide integration process |
US6455383B1 (en) * | 2001-10-25 | 2002-09-24 | Silicon-Based Technology Corp. | Methods of fabricating scaled MOSFETs |
US6703271B2 (en) * | 2001-11-30 | 2004-03-09 | Taiwan Semiconductor Manufacturing Company | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer |
US7217603B2 (en) * | 2002-06-25 | 2007-05-15 | Amberwave Systems Corporation | Methods of forming reacted conductive gate electrodes |
US6858506B2 (en) * | 2002-08-08 | 2005-02-22 | Macronix International Co., Ltd. | Method for fabricating locally strained channel |
US6686637B1 (en) * | 2002-11-21 | 2004-02-03 | International Business Machines Corporation | Gate structure with independently tailored vertical doping profile |
US20050032321A1 (en) * | 2003-08-08 | 2005-02-10 | Chien-Chao Huang | Strained silicon MOS devices |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120181634A1 (en) * | 2011-01-14 | 2012-07-19 | Institute of Microelectronics, Chinese Academy of Sciences | Method of Introducing Strain Into Channel and Device Manufactured by Using the Method |
US8748272B2 (en) * | 2011-01-14 | 2014-06-10 | Institute of Microelectronics, Chinese Academy of Sciences | Method of introducing strain into channel and device manufactured by using the method |
WO2018190811A1 (en) * | 2017-04-11 | 2018-10-18 | Intel Corporation | Transistors with temperature compensating gate structures |
US10553694B2 (en) | 2017-04-11 | 2020-02-04 | Intel Corporation | Transistors with temperature compensating gate structures |
Also Published As
Publication number | Publication date |
---|---|
US7595233B2 (en) | 2009-09-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5305907B2 (en) | High performance MOSFET including stressed gate metal silicide layer and method of manufacturing the same | |
US20080286916A1 (en) | Methods of stressing transistor channel with replaced gate | |
US7217603B2 (en) | Methods of forming reacted conductive gate electrodes | |
US6905922B2 (en) | Dual fully-silicided gate MOSFETs | |
US7545006B2 (en) | CMOS devices with graded silicide regions | |
US20060163670A1 (en) | Dual silicide process to improve device performance | |
US20070018252A1 (en) | Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same | |
US6908850B2 (en) | Structure and method for silicided metal gate transistors | |
US7569896B2 (en) | Transistors with stressed channels | |
US20080093675A1 (en) | MOS devices with continuous contact etch stop layer | |
US20090302390A1 (en) | Method of manufacturing semiconductor device with different metallic gates | |
JP2010505267A (en) | Stress application field effect transistor and method of manufacturing the same | |
JP2007081330A (en) | Semiconductor device and its manufacturing method | |
JP2008522443A (en) | Method for forming a self-aligned dual full silicide gate in a CMOS device | |
JP2009043916A (en) | Semiconductor device and manufacturing method thereof | |
US7972958B2 (en) | Method of fabricating semiconductor device | |
JP2006278369A (en) | Method of manufacturing semiconductor device | |
US7595233B2 (en) | Gate stress engineering for MOSFET | |
US20070238235A1 (en) | Semiconductor device and fabricating method thereof | |
US7718497B2 (en) | Method for manufacturing semiconductor device | |
US7955921B2 (en) | Full silicide gate for CMOS | |
US7960795B2 (en) | Partially and fully silicided gate stacks |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LUO, ZHIJIONG;ZHU, HUILONG;REEL/FRAME:017708/0689 Effective date: 20060503 Owner name: CHARTERED SEMICONDUCTOR MANUFACTURING LTD, SINGAPO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHONG, YUNG FU;REEL/FRAME:017708/0673 Effective date: 20060510 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20130929 |