US20080006870A1 - Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same - Google Patents

Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same Download PDF

Info

Publication number
US20080006870A1
US20080006870A1 US11/898,705 US89870507A US2008006870A1 US 20080006870 A1 US20080006870 A1 US 20080006870A1 US 89870507 A US89870507 A US 89870507A US 2008006870 A1 US2008006870 A1 US 2008006870A1
Authority
US
United States
Prior art keywords
floating gate
word line
insulating layer
active region
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/898,705
Inventor
Jeong-hwan Yang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/898,705 priority Critical patent/US20080006870A1/en
Publication of US20080006870A1 publication Critical patent/US20080006870A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887Programmable transistors with more than two possible different levels of programmation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • Example embodiments relate to a semiconductor memory device and a method of manufacturing the same.
  • Example embodiments also relate to a non-planar split-gate-type nonvolatile semiconductor memory device and a method of manufacturing the same.
  • EEPROM electrically erasable and programmable read only memory
  • flash memory devices have become strongly relied upon.
  • a flash memory widely used nowadays, can be electrically erased and programmed, and retains data even if the supply of power is interrupted.
  • a nonvolatile semiconductor memory device memory cells are connected to a bit line parallel to each other. If the threshold voltage of a memory cell transistor becomes lower than a voltage (normally, 0 V) applied to a control gate of a non-selection memory cell, current flows between a source region and a drain region irrespective of whether a selection memory cell is turned on or off. As a result, all the memory cells are read as if they are continuously in a turn-on state. For this reason, it is necessary to strictly control the threshold voltage in the nonvolatile memory device, which is very difficult.
  • a voltage normally, 0 V
  • split-gate-type nonvolatile semiconductor memory devices have been proposed.
  • a channel region formed by a floating gate and another channel region formed by a control gate are connected in series on the same plane.
  • FET field effect transistor
  • devices are scaled down, thereby achieving high efficiency and thus improving the operating speed.
  • the channel length of an FET has been scaled down on the level of 100 nm or less, it is very difficult to sufficiently reduce the gate length of the FET by scaling.
  • the conventional split-gate-type nonvolatile memory device has a planar channel structure. In this planar FET, the gate length can be scaled along with the scaling of a transistor.
  • the distance between a source region and a drain region decreases, it is difficult to sufficiently scale a tunneling oxide layer.
  • a split-gate-type flash memory device has a floating gate which is separated from a control gate and electrically isolated from the outside. Data storage is enabled by using a variation of current level in memory cells through injection of electrons into the floating gate (i.e., programming) and emission of the electrons from the floating gate (i.e., erasing).
  • the injection of electrons into the floating gate is performed using channel hot electron injection (CHEI), whereas the emission of electrons from the floating gate is performed by F-N tunneling mechanism using an insulating layer between the floating gate and a control gate.
  • CHEI channel hot electron injection
  • F-N tunneling mechanism using an insulating layer between the floating gate and a control gate.
  • Example embodiments relate to a nonvolatile semiconductor memory device.
  • the device is structured such that the short channel effect (SCE) is easily controlled to improve the scaling effect.
  • the active region is a non-planar silicon structure with floating gates disposed on opposite sides of the active region.
  • the device is structured such that the number of corners of a floating gate, where tips may be formed is increased.
  • a control gate overlaps at least three corners of each floating gate.
  • Example embodiments also relate to a non-planar full depletion mode nonvolatile semiconductor memory device having a double-floating gate channel. Even though the distance between a source region and a drain region decreases due to scaling, the device according to example embodiments facilitates the control of a gate by increasing coupling between a channel and a floating gate, while reducing adverse coupling between the channel and the source or the drain.
  • Example embodiments also relate to a method of manufacturing a nonvolatile semiconductor memory device. At least one embodiment of this method enhances the scaling effect and improves the current characteristics of cells by increasing the effective channel width per cell.
  • FIG. 1 is a perspective view of a nonvolatile semiconductor memory device according to example embodiments
  • FIG. 2 is a perspective view of an enlarged memory cell of the nonvolatile semiconductor memory device shown in FIG. 1 ;
  • FIG. 3 is a layout of the nonvolatile semiconductor memory shown in FIG. 1 ;
  • FIGS. 4A through 16A are sectional views taken along line 4 A- 4 A′ of FIG. 3 , illustrating process steps of a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 1 ;
  • FIGS. 4B through 15B are plan views of FIGS. 4A through 15A , respectively;
  • FIGS. 4C through 15C are partial sectional views of FIGS. 4B through 15B , respectively;
  • FIGS. 8D through 14D and 14 E are partial sectional views of FIGS. 8B through 14B , respectively.
  • FIG. 16B is a partial sectional view of FIG. 16A .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in different forms and should not be construed as being limited to the examples set forth herein. Rather, example embodiments have been provided so that the specification will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
  • the size or thickness of layers and regions are exaggerated for clarity.
  • FIG. 1 illustrates a perspective view of a nonvolatile semiconductor memory device according to example embodiments.
  • FIG. 1 illustrates a 4-bit memory cell, in which one bit is comprised of a portion denoted by reference character “A”.
  • the nonvolatile semiconductor memory device is formed on a buried oxide layer (BOX) 10 disposed on a silicon on insulator (SOI) substrate.
  • the SOI substrate is made of a substrate formed by, for example, separation by implantation of oxygen (SIMOX), and the BOX 10 has a thickness of, for example, about 1000 ⁇ to 1500 ⁇ .
  • the nonvolatile semiconductor memory device according to example embodiments comprises active regions, each of which includes a silicon island 20 obtained by patterning an SOI layer of the SOI substrate.
  • the silicon island 20 has a thickness of about 500 ⁇ and extends in an x direction on the BOX 10 in the shape of a roughly square sectional bar.
  • the silicon island 20 has a top surface that extends parallel to a main surface of the SOI substrate (i.e., the BOX 10 ) and two sidewalls that extend perpendicular to the main surface of the SOI substrate (i.e., the BOX 10 ).
  • a channel region 22 is formed inside the silicon island 20 and extends in the x direction.
  • a source line 30 is formed on a source 24 disposed inside the silicon island 20 , adjacent to the channel region 22 , and extends perpendicular to the lengthwise direction (i.e., the x direction) of the silicon island 20 (i.e., extends in a y direction).
  • a bit line that extends in the x direction is connected to a drain 26 disposed adjacent the channel region 22 .
  • the memory cell is an NMOS device
  • the silicon island 20 is doped with p-type impurity ions
  • the source 24 and the drain 26 are doped with high-concentration n-type impurity ions.
  • a pair of floating gates i.e., a first floating gate 42 and a second floating gate 44 , which face each other with the silicon island 20 therebetween, are disposed adjacent to the channel region 22 of the silicon island 20 .
  • a first coupling gate insulating layer 52 is interposed between the channel region 22 and the first floating gate 42
  • a second coupling gate insulating layer 54 is interposed between the channel region 22 and the second floating gate 44 .
  • the first floating gate 42 is electrically isolated from the second floating gate 44 .
  • a word line 60 covers the channel region 22 adjacent to the first floating gate 42 or the second floating gate 44 and extends in the y direction.
  • a first interpoly tunneling insulating layer 56 a is interposed between the first floating gate 42 and the word line 60
  • a second interpoly tunneling insulating layer 56 b is interposed between the second floating gate 44 and the word line 60 .
  • an insulating layer 58 is interposed between the channel region 22 and the word line 60 . That is, the word line 60 includes a portion that faces the channel region 22 with the insulating layer 58 therebetween.
  • a single memory cell, i.e., the portion A is defined only by a contact point between a single bit line, which are connected to the drain 26 , and a single word line.
  • the nonvolatile semiconductor memory device comprises a plurality of memory cells as shown in FIG. 1 , each of which includes a pair of floating gates, i.e., the first floating gate 42 and the second floating gate 44 .
  • a pair of channel are formed along both sidewalls of the channel region 22 perpendicular to the main surface of the SOI substrate, in the channel region 22 adjacent to the first and second coupling gate insulating layer 52 and 54 . That is, a non-planar structure, in which the two channels are formed perpendicular to the top surface of the SOI substrate, is provided.
  • FIG. 2 is an enlarged perspective view of one memory cell, i.e., the portion “A” of FIG. 1 , showing the channel region 22 , the first floating gate 42 , the second floating gate 44 , and the word line 60 .
  • the word line 60 may be formed to surround corners 42 a , 42 b , 42 c , and 42 d of the first floating gate 42 and corners 44 a , 44 b , 44 c , and 44 d of the second floating gate 44 around the channel region 22 .
  • the first floating gate 42 and the second floating gate 44 have a first overlap portion 42 s and a second overlap portion 44 s , respectively, which overlap the word line 60 .
  • first floating gate 42 and the second floating gate 44 shown in FIG. 2 , each have four corners that are surrounded by the word line 60 at the first overlap portion 42 s and the second overlap portion 44 s
  • example embodiments are not limited thereto.
  • the first floating gate 42 and the second floating gate 44 each may have at least three corners that are surrounded by the word line 60 at the first overlap portion 42 s and the second overlap portion 44 s.
  • the word line 60 includes recessed surfaces 60 a and 60 b , which are respectively recessed for the word line 60 so as to surround the first overlap portion 42 s and the second overlap portion 44 s .
  • the first interpoly tunneling insulating layer 56 a is interposed between the word line 60 and the first overlap portion 42 s to surround the corners 42 a , 42 b , 42 c , and 42 d of the first floating gate 42
  • the second interpoly tunneling insulating layer 56 b is interposed between the word line 60 and the second overlap portion 44 s to surround the corners 44 a , 44 b , 44 c , and 44 d of the second floating gate 44 .
  • the insulating layer 58 is formed between the first overlap portion 42 s and the second overlap portion 44 s on the channel region 22 .
  • the nonvolatile memory device comprises two floating gates for a single memory cell, and a control gate formed of the word line 60 . Accordingly, a split-gate-type nonvolatile semiconductor memory device having double floating gates in a single memory cell is provided.
  • the thickness of a silicon body where a channel is formed should be about 1 ⁇ 3 the gate length of the silicon body to form a full depletion mode transistor (IEDM Tech. Digest, pp. 621-624, 2001, by R. Chau et al.).
  • the nonvolatile semiconductor memory device has a double-floating gate structure, in which a single memory cell includes two floating gates. Accordingly, considering the thickness of the silicon island 20 that is controlled by each of the first and second floating gates 42 and 44 , the width L s of the top surface of the silicon island 20 formed of the SOI layer may be set about 2 ⁇ 3 the x-directional length L fg of each of the first and second floating gates 42 and 44 .
  • FIG. 3 is a layout of the nonvolatile semiconductor memory device shown in FIG. 1 .
  • reference numeral 20 A denotes an active region defined by the silicon island 20
  • 32 denotes a contact between the source 24 formed in the active region 20 A and the source line 30
  • 72 denotes a contact between the drain 26 formed in the active region 20 A and a bit line 70 .
  • a portion B denotes a single memory cell corresponding to the portion A in FIG. 1 .
  • the nonvolatile semiconductor memory device comprises a plurality of island-shaped active regions 20 A, which are formed on a BOX 10 disposed on a substrate and each of which includes two memory cells.
  • the two memory cell have one source 24 , i.e., one source line 30 , in common inside one active region 20 A.
  • the word line 60 is connected to a series of memory cells, which respectively include a series of channel regions 22 disposed in the lengthwise direction of the word line 60 , i.e., in the y direction, among channel regions 22 that are respectively formed in the plurality of active regions 20 A. Also, a series of sources 24 , which are formed inside a series of active regions 20 A disposed in the lengthwise direction of the word line 60 , i.e., in the y direction, are connected to each other via the source line 30 .
  • the first floating gate 42 and the second floating gate 44 each are formed of doped polysilicon or metal.
  • the word line 60 and the source line 30 each are formed of doped polysilicon or metal and at least one of them may include a metal silicide layer.
  • the metal silicide layer may be formed of, for example, cobalt silicide, nickel silicide, titanium silicide, hafnium silicide, platinum silicide, or tungsten silicide.
  • the programming of memory cells is performed using a CHEI method.
  • a CHEI method For example, when the memory cell is in an UV-erased initial state, if a high voltage is applied to the word line 60 of the memory cell and a high voltage is applied to the source 24 via the source line 30 , two electron channels are formed on both sidewalls of the silicon island 20 , which face the first and second floating gates 42 and 44 , respectively, due to the threshold voltage Vth applied to the word line 60 . Thus, electrons generated in the drain 26 flow into the source 24 via the two channels. Concurrently, channel hot carriers are generated to allow hot electrons to flow through the first and second coupling gate insulating layers 52 and 54 into the first and second floating gates 42 and 44 . Thus, the first and second floating gates 42 and 44 are charged with negative charges.
  • the first and second floating gates 42 and 44 each are charged to induce a negative voltage.
  • the channels which are formed on the both sidewalls of the silicon island 20 that face the first and second floating gates 42 and 44 , respectively, have an increased threshold voltage Vth, which differs from a voltage in the erased state.
  • the erasing of the memory cell is performed using F-N tunneling, which involves the first and second interpoly tunneling insulating layers 56 a and 56 b between the first and second floating gates 42 and 44 and the control gate comprised of the word line 60 .
  • F-N tunneling involves the first and second interpoly tunneling insulating layers 56 a and 56 b between the first and second floating gates 42 and 44 and the control gate comprised of the word line 60 .
  • F-N tunneling involves the first and second interpoly tunneling insulating layers 56 a and 56 b between the first and second floating gates 42 and 44 and the control gate comprised of the word line 60 .
  • F-N tunneling involves the first and second interpoly tunneling insulating layers 56 a and 56 b between the first and second floating gates 42 and 44 and the control gate comprised of the word line 60 .
  • a high voltage is applied to the word line 60 and a low voltage is applied to the source 24 .
  • a strong electric field is induced in portions surrounding the overlap portions 42 s and 44 s of the first and second floating gates 42 and 44 of the word line 60 , i.e., adjacent to the recessed surfaces 60 a and 60 b , due to the corners 42 a , 42 b , 42 c , and 42 d of the first floating gate 42 and the corners 44 a , 44 b , 44 c , and 44 d of the second floating gate 44 .
  • the strong electric field which concentrates in the corners 42 a , 42 b , 42 c , 42 d , 44 a , 44 b , 44 c , and 44 d of the first and second floating gates 42 and 44 , is sufficiently capable of tunneling the electrons stored in the first and second floating gates 42 and 44 into the word line 60 .
  • the first and second floating gates 42 and 44 are placed in an initial state, i.e., an UV-erased state. Then, the channels formed on both sidewalls of the channel region 22 that face the first and second floating gates 42 and 44 have a lower threshold voltage than that when the programming is completed, thus allowing a relatively large current to flow during the reading operation.
  • the nonvolatile semiconductor memory device is a non-planar split-gate-type device, which is formed on the SOI substrate, and each memory cell includes two floating gates 42 and 44 which are adjacent to both sidewalls of the active region, i.e., the silicon island 20 .
  • each of the floating gates 42 and 44 has at least three corners, into which the electric field can concentrate adjacent to the word line 60 . That is, a total of six or more corners of the floating gates 42 and 44 are adjacent to the word line 60 . Therefore, the number of F-N tunneling regions increases.
  • both sidewalls of the active region 20 serve as the channels so as to increase the effective channel width for each cell in the layout. As a result, a large current can be held in the memory cell.
  • FIGS. 4A, 4B , and 4 C through 16 A and 16 B illustrate process steps of a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 1 .
  • FIGS. 4A through 16A are sectional views taken along line 4 A- 4 A′ of FIG. 3
  • FIGS. 4B through 15B are plan views of FIGS. 4A through 15A , respectively.
  • FIGS. 4C through 15C are partial sectional views of FIGS. 4B through 15B , respectively
  • FIGS. 8D through 14D and 14 E are partial sectional views of FIGS. 8B through 14B , respectively.
  • FIG. 16B is a partial sectional view of FIG. 16A .
  • an SOI substrate where a silicon substrate 100 , a BOX 102 , and an SOI layer are sequentially stacked is prepared.
  • the SOI substrate may be formed by, for example, an SIMOX process.
  • the BOX 102 has a thickness of about 1000 ⁇ to 1500 ⁇
  • the SOI layer has a thickness of about 500 ⁇ .
  • a mask pattern 110 is formed on the SOI layer to define an active region.
  • the mask pattern 110 is formed of an oxide layer 112 , a nitride layer 114 , and another oxide layer 116 , which are sequentially stacked.
  • the oxide layer 112 , the nitride layer 114 , and the oxide layer 116 have a thickness of 200 ⁇ , 300 ⁇ , and 200 ⁇ , respectively.
  • the SOI layer is anisotropically etched using the mask pattern 110 as an etch mask to form a silicon island 104 .
  • the silicon island 104 extends in a first direction, i.e., in the x direction shown in FIG. 1 , in the shape of a substantially square sectional bar.
  • the silicon island 104 has a top surface 104 t , which extends parallel to a main surface of the BOX 102 , and both sidewalls 104 s extend from the BOX 102 perpendicular to the main surface of the BOX 102 .
  • FIGS. 5A, 5B , and 5 C which is a sectional view taken along line 5 C- 5 C′ of FIG. 5B , the exposed both sidewalls 104 s of the silicon island 104 are covered with a first oxide layer 118 having a thickness of about 70 ⁇ . A portion of the first oxide layer 118 will constitute a coupling gate insulating layer later.
  • the first oxide layer 118 may be formed using thermal oxidation, chemical vapor deposition (CVD), or a combination thereof.
  • channel ion implantation is performed to dope the silicon island 104 with impurity ions of a first conductivity type, e.g., p-type impurity ions.
  • a blanket conductive layer is formed to a thickness of about 400 ⁇ on the BOX 102 to cover the mask pattern 110 and the first oxide layer 118 . Then, the blanket conductive layer is anisotropically etched using the mask pattern 110 and the BOX 102 as an etch stop layer to form a first conductive layer 120 .
  • the first conductive layer 120 faces the sidewalls 104 s of the silicon island 104 on the first oxide layer 118 , and surrounds the silicon island 104 in the shape of a spacer sidewall.
  • the blanket conductive layer is anisotropically etched to form the first conductive layer 120 , but example embodiments are not limited thereto.
  • the first conductive layer 120 may be formed using other methods, for example, by processing the blanket conductive layer using a photolithography process and chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the first conductive layer 120 is formed to have a square sectional shape having four corners instead of a shape having three corners (and a fourth rounded corner) as shown in FIG. 6A .
  • the first conductive layer 120 may be formed of doped polysilicon or metal. To form the first conductive layer 120 using doped polysilicon, an undoped polysilicon may be deposited first and then doped with impurity ions, or an already doped polysilicon layer may be deposited.
  • a silicon nitride layer having a thickness of about 1000 ⁇ is formed on the BOX 102 to cover the resultant structure where the first conductive layer 120 is formed. Thereafter, the silicon nitride layer is patterned using a photolithography process so as to expose the first conductive layer 120 in a central portion of the silicon island 104 , i.e., a region where two floating gates and a source will be formed. Thus, a first protecting insulating pattern 132 is formed to protect a portion of the first conductive layer 120 .
  • a silicon oxide layer is formed to a thickness of about 1000 ⁇ on the entire surface of the resultant structure where the first protecting insulating pattern 132 is formed. Thereafter, the silicon oxide layer is anisotropically etched again to form a second protecting insulating pattern 134 on the sidewalls of the first protecting insulating pattern 132 in the shape of spacers. While the silicon oxide layer is being anisotropically etched to form the second protecting insulating pattern 134 , the oxide layer 116 constituting an uppermost portion of the mask pattern 110 is also etched.
  • the second protecting insulating pattern 134 covers and protects a portion of the first conductive layer 120 , where floating gates will be formed. Also, the first conductive layer 120 , which surrounds the silicon island 104 , is exposed between the two adjacent second protecting insulating patterns 134 .
  • FIGS. 8C and 8D are sectional views taken along lines 8 C- 8 C′ and 8 D- 8 D′, respectively, of FIG. 8B .
  • first conductive layer 120 which covers the sidewalls of the silicon island 104 in the first region 104 A, is selectively removed by using the first protecting insulating pattern 132 and the second protecting insulating pattern 134 as an etch mask.
  • first exposed sidewalls 120 a are formed adjacent to the first region 104 A on the first conductive layer 120 , and the first oxide layer 118 covering the sidewalls of the silicon island 104 is exposed in the first region 104 A.
  • the nitride layer 114 which is exposed on the silicon island 104 , is removed in the first region 104 A to expose the oxide layer 112 of the mask pattern 110 in the first region 104 A. Then, the first exposed sidewalls 120 a disposed on the first conductive layer 120 are oxidized by thermal oxidation. A second oxide layer is formed by CVD on the resultant structure and then anisotropically etched again. This forms first insulating spacers 142 to cover the first exposed sidewalls 120 a disposed on the first conductive layer 120 .
  • the thermal oxidation, for oxidizing the first exposed sidewalls 120 a may be optionally omitted.
  • spacers 144 are formed to cover the both sidewalls of the silicon island 104 in the first region 104 A.
  • the oxide layer 112 disposed on the silicon island 104 in the first region 104 A is removed to expose the top surface of the silicon island 104 .
  • a source contact will be formed on the exposed top surface of the silicon island 104 later.
  • the etching of the second oxide layer may be further performed to expose the both sidewalls of the silicon island 104 , such that even the spacers 144 covering the both sidewalls of the silicon island 104 are removed in the first region 104 A.
  • FIGS. 9C and 9D are sectional views taken along lines 9 C- 9 C′ and 9 D- 9 D′, respectively, of FIG. 9B .
  • impurity ions are implanted into the entire surface of the resultant structure to form a source 146 in the first region 104 A of the silicon island 104 .
  • impurity ions of a second conductivity type which is opposite to the first conductivity type, e.g., n-type impurity ions, are implanted at a high concentration.
  • the impurity ions for the source 146 are implanted at a higher concentration than that of the impurity ions for the channel ion implantation.
  • FIGS. 10C and 10D are sectional views taken along lines 10 C- 10 C′ and 10 D- 10 D′, respectively, of FIG. 10B .
  • a conductive material is deposited on the entire surface of the resultant structure where the source 146 is formed.
  • a second conductive layer is formed to a thickness of about 3000 ⁇ to completely fill a space between the two adjacent second protecting insulating patterns 134 in the first region 104 A.
  • the second conductive layer is then planarized using CMP to form a source line 150 connected to the source 146 .
  • the source line 150 extends in a second direction, i.e., in the y direction, perpendicular to the first direction.
  • the first protecting insulating pattern 132 and the second protecting insulating pattern 134 which are adjacent to the source line 150 , have a slightly reduced height.
  • the source line 150 forms an ohmic contact with the source 146 .
  • the second conductive layer which is used to form the source line 150 , may be formed of doped polysilicon or metal.
  • an undoped polysilicon layer may be deposited and then doped with impurity ions, or an already doped polysilicon layer may be deposited.
  • FIGS. 11C and 11D are sectional views taken along lines 11 C- 11 C′ and 11 D- 11 D′, respectively, of FIG. 11B .
  • the top surface of the source line 150 is thermally oxidized to form a thermal oxide layer 152 having a thickness of about 100 ⁇ .
  • the first protecting insulating pattern 132 which is formed of the silicon nitride layer, is wet or dry etched and removed by using the thermal oxide layer 152 and the second protecting insulating pattern 134 as an etch mask.
  • the oxide layer 116 of the mask pattern 110 which covers the top surface of the silicon island 104 , is exposed in a second region 104 B of the silicon island 104 , and portions of the first conductive layer 120 and the BOX 102 .
  • FIGS. 12C and 12D are sectional views taken along lines 12 C- 12 C′ and 12 D- 12 D′, respectively, of FIG. 12B .
  • a portion of the first conductive layer 120 which covers the second region 104 B of the silicon island 104 , is selectively removed by a dry or wet etching process using oxide layers exposed on the silicon substrate 100 , i.e., the thermal oxide layer 152 , the second protecting insulating pattern 134 , the oxide layer 116 , the first oxide layer 118 , and the BOX 102 as a hard mask.
  • a first floating gate 122 and a second floating gate 124 which are formed of the remaining portion of the first conductive layer 120 , are formed under the second protecting insulating pattern 134 .
  • the first floating gate 122 and the second floating gate 124 face each other with the silicon island 104 disposed therebetween.
  • second exposed sidewalls 120 b are formed adjacent to the second region 104 B on the remaining first conductive layer 120 , i.e., the first and second floating gates 122 and 124 .
  • the second protecting insulating pattern 134 protects a portion of the first conductive layer 120 , which remains adjacent the silicon island 104 excluding the first region 104 A and the second region 104 B.
  • FIGS. 13C and 13D are sectional views taken along lines 13 C- 13 C′ and 13 D- 13 D′, respectively, of FIG. 13B .
  • the thermal oxide layer 152 and the oxide layer 116 of the mask pattern 110 are wet etched and removed to expose the nitride layer 114 of the mask pattern 110 .
  • the exposed nitride layer 114 is wet etched and removed to expose the oxide layer 112 of the mask pattern 110 .
  • the oxide layer 112 of the mask pattern 110 is wet etched and removed to expose the top surface of the silicon island 104 in the second region 104 B.
  • the second protecting insulating pattern 134 has reduced height and width.
  • a portion of the top surfaces of the first and second floating gates 122 and 124 which is covered with the second protecting insulating pattern 134 , is exposed by a predetermined width adjacent to the second protecting insulating pattern 134 . That is, while the top surface of the silicon island 104 is being exposed in the second region 104 B, the top surface 120 c of the first and second floating gates 122 and 124 and the corners of the second exposed sidewalls 120 b are exposed.
  • a third oxide layer 160 is formed on the exposed top surface of the silicon island 104 , the second exposed sidewalls 120 b and the exposed top surface 120 c of the first conductive layer 120 by using thermal oxidation or a CVD process.
  • an insulating layer 162 is formed on the silicon island 104
  • second insulating spacers 164 a and 164 b are formed on the second exposed sidewalls 120 b and the exposed top surface 120 c of the first conductive layer 120 , which constitutes the first and second floating gates 122 and 124 .
  • the insulating layer 162 and the insulating spacers 164 a and 164 b are formed of the third oxide layer 160 .
  • the third oxide layer 160 may be formed to a thickness of about 160 ⁇ to 170 ⁇ , using thermal oxidation, a CVD process, or a combination thereof.
  • the insulating layer 162 and the second insulating spacers 164 a and 164 b are concurrently formed.
  • the second insulating spacers 164 a and 164 b are formed to cover the corners of the first floating gate 122 and the second floating gate 124 , respectively.
  • the second insulating spacers 164 a and 164 b function as a first interpoly tunneling insulating layer 164 a and a second interpoly tunneling insulating layer 164 b between the first floating gate 122 and a word line, which will be formed later, and between the second floating gate 124 and the word line.
  • the same reference numerals are used to denote the second insulating spacers and the first and second interpoly tunneling insulating layers.
  • the second insulating spacers 164 a and 164 b are formed on not only the second exposed sidewalls 120 b of the first conductive layer 120 but also on the exposed surfaces 120 c thereof, but example embodiments are not limited thereto. That is, it is possible to control the areas of the exposed top surface 120 c by varying the width of the second protecting insulating pattern 134 , and it is also possible to form the second insulating spacers only on the second exposed sidewalls 120 b without exposing the top surfaces of the first conductive layer 120 .
  • the width of the second protecting insulating pattern 134 is reduced so as to expose a portion of the top surface of the first conductive layer 120 .
  • FIGS. 14C and 14D are sectional views taken along lines 14 C- 14 C′ and 14 D- 14 D′, respectively, of FIG. 14B
  • FIG. 14E is a sectional view taken along line 14 E- 14 E′ of FIG. 14B .
  • a blanket deposit of a conductive material is deposited to a thickness of about 2000 ⁇ using CVD to cover the sidewalls and the top surface of the second protecting insulating pattern 134 .
  • a third conductive layer is formed.
  • the third conductive layer is anisotropically etched until the third oxide layer 160 disposed on the silicon island 104 is exposed, thereby forming a word line 170 on the sidewalls of the second protecting insulating pattern 134 .
  • the word line 170 extends parallel to the source line 150 , i.e., in the y direction of FIG. 1 .
  • the third conductive layer may be formed of doped polysilicon or metal. To form the third conductive layer using doped polysilicon, an undoped polysilicon layer may be deposited and then doped, or an already doped polysilicon layer may be deposited.
  • FIG. 15C is a sectional view taken along line 15 C- 15 C′ of FIG. 15B .
  • the three corners of the first floating gate 122 are surrounded by the word line 170 and separated from the word line 170 by the first interpoly tunneling insulating layer 164 a
  • the three corners of the second floating gate 124 are surrounded by the word line 170 and separated from the word line 170 by the second interpoly tunneling insulating layer 164 b .
  • the second floating gate 124 has the same structure as the first floating gate 122 shown in FIG. 15C .
  • a silicon nitride layer is deposited on the entire surface of the resultant structure where the word line 170 is formed, and etched back to form nitride spacers 172 covering the word line 170 .
  • the third oxide layer 160 which covers the top surface of the silicon island 104 , is removed due to over-etching.
  • the top surface of the silicon island 104 is exposed adjacent to the nitride spacers 172 .
  • impurity ions are implanted into the exposed top surface of the silicon island 104 by a typical ion implantation process to form a drain 148 in the silicon island 104 .
  • impurity ions of the second conductivity type that is opposite to the first conductivity type e.g., n-type impurity ions are implanted at a high concentration.
  • the impurity ions are implanted into the drain 148 at a higher concentration than that of the impurity ions for the channel ion implantation.
  • Metal silicide layers 159 , 179 , and 149 are formed on the source line 150 , the word line 170 , and the drain 148 by using typical salicide process, CVD process, or PVD process.
  • the metal silicide layers 159 , 179 , and 149 can reduce sheet resistance and contact resistance at each contact.
  • the source line 150 and the word line 170 are formed of doped polysilicon
  • a metal layer is deposited by sputtering on the entire surface of the resultant structure where the drain 148 is formed, and then a primary thermal treatment is performed to form a metal silicide layer of a first phase.
  • the metal silicide layers 159 , 179 , and 149 may be formed of, for example, cobalt silicide, nickel silicide, titanium silicide, hafnium silicide, platinum silicide, or tungsten silicide.
  • An insulating material is deposited on the entire surface of the resultant structure where the metal silicide layers 159 , 179 , and 149 are formed, to form an interlayer dielectric (ILD) 180 .
  • ILD interlayer dielectric
  • a portion of the ILD 180 is etched by a photolithography process to form a contact hole, which exposes the drain 148 of each memory cell.
  • a fourth conductive layer is formed on the ILD 180 to a sufficient thickness enough to fill the contact hole, and then patterned by a photolithography process to form a bit line 190 .
  • the fourth conductive layer may be formed of doped polysilicon or metal. To form the fourth conductive layer using doped polysilicon, an undoped polysilicon layer may be deposited first and then doped, or an already doped polysilicon layer may be deposited.
  • FIG. 16B is a partial sectional view taken along line 16 B- 16 B′ of FIG. 16A .
  • a first floating gate and a second floating gate face each other with the silicon island 104 therebetween, and the first and second floating gates are electrically insulated from each other.
  • the first coupling gate insulating layer and the second coupling gate insulating layer, each of which is formed of the second oxide layer 118 are interposed between the channel region of the silicon island 104 and the first floating gate 122 and between the channel region of the silicon island 104 and the second floating gate 124 , respectively.
  • the word line 170 extends adjacent to the first floating gate 122 and the second floating gate 124 .
  • the first interpoly tunneling insulating layer 164 a is interposed between the first floating gate 122 and the word line 170
  • the second interpoly tunneling insulating layer 164 b is interposed between the second floating gate 124 and the word line 170 .
  • two channels 200 are formed along both sidewalls of the silicon island 104 perpendicular to a main surface of the SOI substrate and adjacent to the first coupling gate insulating layer and the second coupling gate insulating layer (each of which is formed of the first oxide layer 118 ). That is, a non-planar nonvolatile semiconductor memory device, in which the two channels 200 are formed perpendicular to the main surface of the SOI substrate, is provided.
  • the nonvolatile semiconductor memory device is a non-planar split-gate-type device disposed on the SOI substrate.
  • Each memory cell includes two floating gates, which face each other with the active region, i.e., the silicon island disposed therebetween. Accordingly, each floating gate has at least three corners, which are adjacent to a control gate and on which an electric field concentrates. In other words, since each memory cell includes a total of six or more corners of the floating gates adjacent to the control gate, the areas of the floating gates, where the electric field concentrates, increase.
  • the device according to example embodiments comprises a double-floating gate structure. Both sidewalls of the active region serve as channels such that the channels are formed perpendicular to the main surface of the substrate. This improves the integration density as compared with conventional devices. Also, since the effective channel width for each memory cell can increase in a given layout, a large current can be held in the memory cell.
  • the device according to example embodiments has a full depletion mode SOI structure, thus improving a sub-threshold characteristic.
  • the non-planar structure including double floating gates, is provided such that a gate is easily controlled so as to suppress the SCE and improve drain induced barrier lowering (DIBL).
  • DIBL drain induced barrier lowering
  • the SOI structure allows complete isolation between devices and excellent radiation hardness, thus reducing soft errors.

Abstract

The nonvolatile semiconductor memory device includes a non-planar active region with floating gates disposed on opposite sides of the active region. A control gate overlaps the floating gates and a portion of the active region.

Description

  • This application is a divisional of application Ser. No. 10/913,489, filed on Aug. 9, 2004, which claims priority to Korean Patent Application No. 10-2003-0054782, filed on Aug. 7, 2003 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.
  • BACKGROUND
  • 1. Technical Field
  • Example embodiments relate to a semiconductor memory device and a method of manufacturing the same. Example embodiments also relate to a non-planar split-gate-type nonvolatile semiconductor memory device and a method of manufacturing the same.
  • 2. Description of the Related Art
  • In recent years, electrically erasable and programmable read only memory (EEPROM) or flash memory devices have become strongly relied upon. A flash memory, widely used nowadays, can be electrically erased and programmed, and retains data even if the supply of power is interrupted.
  • In a nonvolatile semiconductor memory device, memory cells are connected to a bit line parallel to each other. If the threshold voltage of a memory cell transistor becomes lower than a voltage (normally, 0 V) applied to a control gate of a non-selection memory cell, current flows between a source region and a drain region irrespective of whether a selection memory cell is turned on or off. As a result, all the memory cells are read as if they are continuously in a turn-on state. For this reason, it is necessary to strictly control the threshold voltage in the nonvolatile memory device, which is very difficult. Also, high-speed programming of memory cells necessitates generation of sufficient channel hot carriers, and high-speed erasing thereof requires generation of sufficient Fowler-Nordheim (F-N) tunneling currents. To generate sufficient channel hot carriers or sufficient F-N tunneling currents, a high voltage is indispensable.
  • To solve these problems, split-gate-type nonvolatile semiconductor memory devices have been proposed. In these conventional split-gate-type nonvolatile semiconductor memory devices, a channel region formed by a floating gate and another channel region formed by a control gate are connected in series on the same plane.
  • Also, with the increased integration density of semiconductor memory devices, various structures and manufacturing processes of semiconductor devices have been proposed to minimize alignment errors between components such as sources, drains, control gates, and floating gates.
  • Meanwhile, in recent field effect transistor (FET) techniques, devices are scaled down, thereby achieving high efficiency and thus improving the operating speed. As the channel length of an FET has been scaled down on the level of 100 nm or less, it is very difficult to sufficiently reduce the gate length of the FET by scaling. However, the conventional split-gate-type nonvolatile memory device has a planar channel structure. In this planar FET, the gate length can be scaled along with the scaling of a transistor. However, while the distance between a source region and a drain region decreases, it is difficult to sufficiently scale a tunneling oxide layer.
  • Thus, adverse coupling occurs between channel regions and the source region or the drain region. This lowers the controllability of a gate for turning on and off a semiconductor device, and leads to a short channel effect (SCE) and drain induced barrier lowering. Therefore, in the conventional planar nonvolatile semiconductor memory devices, the SCE cannot be properly controlled by scaling.
  • A split-gate-type flash memory device has a floating gate which is separated from a control gate and electrically isolated from the outside. Data storage is enabled by using a variation of current level in memory cells through injection of electrons into the floating gate (i.e., programming) and emission of the electrons from the floating gate (i.e., erasing). The injection of electrons into the floating gate is performed using channel hot electron injection (CHEI), whereas the emission of electrons from the floating gate is performed by F-N tunneling mechanism using an insulating layer between the floating gate and a control gate. Nowadays, attempts are being made to increase the erasing efficiency by forming tips at edge portions of the floating gate, adjacent to the control gate. However, in the conventional nonvolatile semiconductor memory devices, the number of corners of the floating gate where the tips can be formed is too low to improve the erasing efficiency.
  • SUMMARY
  • Example embodiments relate to a nonvolatile semiconductor memory device. In an example embodiment, the device is structured such that the short channel effect (SCE) is easily controlled to improve the scaling effect. For example, in this embodiment, the active region is a non-planar silicon structure with floating gates disposed on opposite sides of the active region. In another example embodiment, the device is structured such that the number of corners of a floating gate, where tips may be formed is increased. For example, in this embodiment, a control gate overlaps at least three corners of each floating gate.
  • Example embodiments also relate to a non-planar full depletion mode nonvolatile semiconductor memory device having a double-floating gate channel. Even though the distance between a source region and a drain region decreases due to scaling, the device according to example embodiments facilitates the control of a gate by increasing coupling between a channel and a floating gate, while reducing adverse coupling between the channel and the source or the drain.
  • Example embodiments also relate to a method of manufacturing a nonvolatile semiconductor memory device. At least one embodiment of this method enhances the scaling effect and improves the current characteristics of cells by increasing the effective channel width per cell.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other features and advantages of example embodiments will become more apparent in view of the detailed description below with reference to the attached drawings in which:
  • FIG. 1 is a perspective view of a nonvolatile semiconductor memory device according to example embodiments;
  • FIG. 2 is a perspective view of an enlarged memory cell of the nonvolatile semiconductor memory device shown in FIG. 1;
  • FIG. 3 is a layout of the nonvolatile semiconductor memory shown in FIG. 1;
  • FIGS. 4A through 16A are sectional views taken along line 4A-4A′ of FIG. 3, illustrating process steps of a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 1;
  • FIGS. 4B through 15B are plan views of FIGS. 4A through 15A, respectively;
  • FIGS. 4C through 15C are partial sectional views of FIGS. 4B through 15B, respectively;
  • FIGS. 8D through 14D and 14E are partial sectional views of FIGS. 8B through 14B, respectively; and
  • FIG. 16B is a partial sectional view of FIG. 16A.
  • DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
  • Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in different forms and should not be construed as being limited to the examples set forth herein. Rather, example embodiments have been provided so that the specification will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In the drawings, the size or thickness of layers and regions are exaggerated for clarity.
  • FIG. 1 illustrates a perspective view of a nonvolatile semiconductor memory device according to example embodiments. FIG. 1 illustrates a 4-bit memory cell, in which one bit is comprised of a portion denoted by reference character “A”.
  • As shown in FIG. 1, the nonvolatile semiconductor memory device according to example embodiments is formed on a buried oxide layer (BOX) 10 disposed on a silicon on insulator (SOI) substrate. The SOI substrate is made of a substrate formed by, for example, separation by implantation of oxygen (SIMOX), and the BOX 10 has a thickness of, for example, about 1000 Å to 1500 Å. The nonvolatile semiconductor memory device according to example embodiments comprises active regions, each of which includes a silicon island 20 obtained by patterning an SOI layer of the SOI substrate. The silicon island 20 has a thickness of about 500 Å and extends in an x direction on the BOX 10 in the shape of a roughly square sectional bar. The silicon island 20 has a top surface that extends parallel to a main surface of the SOI substrate (i.e., the BOX 10) and two sidewalls that extend perpendicular to the main surface of the SOI substrate (i.e., the BOX 10).
  • A channel region 22 is formed inside the silicon island 20 and extends in the x direction. A source line 30 is formed on a source 24 disposed inside the silicon island 20, adjacent to the channel region 22, and extends perpendicular to the lengthwise direction (i.e., the x direction) of the silicon island 20 (i.e., extends in a y direction). Also, a bit line that extends in the x direction is connected to a drain 26 disposed adjacent the channel region 22. For example, if the memory cell is an NMOS device, the silicon island 20 is doped with p-type impurity ions, and the source 24 and the drain 26 are doped with high-concentration n-type impurity ions.
  • A pair of floating gates, i.e., a first floating gate 42 and a second floating gate 44, which face each other with the silicon island 20 therebetween, are disposed adjacent to the channel region 22 of the silicon island 20. A first coupling gate insulating layer 52 is interposed between the channel region 22 and the first floating gate 42, and a second coupling gate insulating layer 54 is interposed between the channel region 22 and the second floating gate 44. The first floating gate 42 is electrically isolated from the second floating gate 44.
  • A word line 60 covers the channel region 22 adjacent to the first floating gate 42 or the second floating gate 44 and extends in the y direction. A first interpoly tunneling insulating layer 56 a is interposed between the first floating gate 42 and the word line 60, and a second interpoly tunneling insulating layer 56 b is interposed between the second floating gate 44 and the word line 60. Also, an insulating layer 58 is interposed between the channel region 22 and the word line 60. That is, the word line 60 includes a portion that faces the channel region 22 with the insulating layer 58 therebetween. A single memory cell, i.e., the portion A is defined only by a contact point between a single bit line, which are connected to the drain 26, and a single word line.
  • The nonvolatile semiconductor memory device according to example embodiments comprises a plurality of memory cells as shown in FIG. 1, each of which includes a pair of floating gates, i.e., the first floating gate 42 and the second floating gate 44. Thus, when voltages are applied to the word line 60 and the source 24, a pair of channel are formed along both sidewalls of the channel region 22 perpendicular to the main surface of the SOI substrate, in the channel region 22 adjacent to the first and second coupling gate insulating layer 52 and 54. That is, a non-planar structure, in which the two channels are formed perpendicular to the top surface of the SOI substrate, is provided.
  • FIG. 2 is an enlarged perspective view of one memory cell, i.e., the portion “A” of FIG. 1, showing the channel region 22, the first floating gate 42, the second floating gate 44, and the word line 60.
  • As shown in FIG. 2, the word line 60 may be formed to surround corners 42 a, 42 b, 42 c, and 42 d of the first floating gate 42 and corners 44 a, 44 b, 44 c, and 44 d of the second floating gate 44 around the channel region 22. The first floating gate 42 and the second floating gate 44 have a first overlap portion 42 s and a second overlap portion 44 s, respectively, which overlap the word line 60.
  • To facilitate understanding, although the first floating gate 42 and the second floating gate 44, shown in FIG. 2, each have four corners that are surrounded by the word line 60 at the first overlap portion 42 s and the second overlap portion 44 s, example embodiments are not limited thereto. According to example embodiments, the first floating gate 42 and the second floating gate 44 each may have at least three corners that are surrounded by the word line 60 at the first overlap portion 42 s and the second overlap portion 44 s.
  • The word line 60 includes recessed surfaces 60 a and 60 b, which are respectively recessed for the word line 60 so as to surround the first overlap portion 42 s and the second overlap portion 44 s. The first interpoly tunneling insulating layer 56 a is interposed between the word line 60 and the first overlap portion 42 s to surround the corners 42 a, 42 b, 42 c, and 42 d of the first floating gate 42, and the second interpoly tunneling insulating layer 56 b is interposed between the word line 60 and the second overlap portion 44 s to surround the corners 44 a, 44 b, 44 c, and 44 d of the second floating gate 44. Also, the insulating layer 58 is formed between the first overlap portion 42 s and the second overlap portion 44 s on the channel region 22.
  • As described above, the nonvolatile memory device according to example embodiments comprises two floating gates for a single memory cell, and a control gate formed of the word line 60. Accordingly, a split-gate-type nonvolatile semiconductor memory device having double floating gates in a single memory cell is provided.
  • Typically, it is reported that the thickness of a silicon body where a channel is formed should be about ⅓ the gate length of the silicon body to form a full depletion mode transistor (IEDM Tech. Digest, pp. 621-624, 2001, by R. Chau et al.). The nonvolatile semiconductor memory device according to example embodiments has a double-floating gate structure, in which a single memory cell includes two floating gates. Accordingly, considering the thickness of the silicon island 20 that is controlled by each of the first and second floating gates 42 and 44, the width Ls of the top surface of the silicon island 20 formed of the SOI layer may be set about ⅔ the x-directional length Lfg of each of the first and second floating gates 42 and 44.
  • FIG. 3 is a layout of the nonvolatile semiconductor memory device shown in FIG. 1.
  • Referring to FIG. 3, reference numeral 20A denotes an active region defined by the silicon island 20, 32 denotes a contact between the source 24 formed in the active region 20A and the source line 30, and 72 denotes a contact between the drain 26 formed in the active region 20A and a bit line 70. In FIG. 3, a portion B denotes a single memory cell corresponding to the portion A in FIG. 1.
  • The nonvolatile semiconductor memory device according to example embodiments comprises a plurality of island-shaped active regions 20A, which are formed on a BOX 10 disposed on a substrate and each of which includes two memory cells. The two memory cell have one source 24, i.e., one source line 30, in common inside one active region 20A.
  • The word line 60 is connected to a series of memory cells, which respectively include a series of channel regions 22 disposed in the lengthwise direction of the word line 60, i.e., in the y direction, among channel regions 22 that are respectively formed in the plurality of active regions 20A. Also, a series of sources 24, which are formed inside a series of active regions 20A disposed in the lengthwise direction of the word line 60, i.e., in the y direction, are connected to each other via the source line 30.
  • The first floating gate 42 and the second floating gate 44 each are formed of doped polysilicon or metal. Also, the word line 60 and the source line 30 each are formed of doped polysilicon or metal and at least one of them may include a metal silicide layer. The metal silicide layer may be formed of, for example, cobalt silicide, nickel silicide, titanium silicide, hafnium silicide, platinum silicide, or tungsten silicide.
  • Hereinafter, the operation of the nonvolatile semiconductor memory device according to example embodiments will be described in detail.
  • To begin with, the programming of memory cells is performed using a CHEI method. For example, when the memory cell is in an UV-erased initial state, if a high voltage is applied to the word line 60 of the memory cell and a high voltage is applied to the source 24 via the source line 30, two electron channels are formed on both sidewalls of the silicon island 20, which face the first and second floating gates 42 and 44, respectively, due to the threshold voltage Vth applied to the word line 60. Thus, electrons generated in the drain 26 flow into the source 24 via the two channels. Concurrently, channel hot carriers are generated to allow hot electrons to flow through the first and second coupling gate insulating layers 52 and 54 into the first and second floating gates 42 and 44. Thus, the first and second floating gates 42 and 44 are charged with negative charges.
  • After the programming, the first and second floating gates 42 and 44 each are charged to induce a negative voltage. Thus, the channels, which are formed on the both sidewalls of the silicon island 20 that face the first and second floating gates 42 and 44, respectively, have an increased threshold voltage Vth, which differs from a voltage in the erased state.
  • The erasing of the memory cell is performed using F-N tunneling, which involves the first and second interpoly tunneling insulating layers 56 a and 56 b between the first and second floating gates 42 and 44 and the control gate comprised of the word line 60. To erase data, a high voltage is applied to the word line 60 and a low voltage is applied to the source 24. Then, a strong electric field is induced in portions surrounding the overlap portions 42 s and 44 s of the first and second floating gates 42 and 44 of the word line 60, i.e., adjacent to the recessed surfaces 60 a and 60 b, due to the corners 42 a, 42 b, 42 c, and 42 d of the first floating gate 42 and the corners 44 a, 44 b, 44 c, and 44 d of the second floating gate 44. The strong electric field, which concentrates in the corners 42 a, 42 b, 42 c, 42 d, 44 a, 44 b, 44 c, and 44 d of the first and second floating gates 42 and 44, is sufficiently capable of tunneling the electrons stored in the first and second floating gates 42 and 44 into the word line 60.
  • If the electrons are emitted from the first and second floating gates 42 and 44 and flow into the word line 60 by the erasing operation, the first and second floating gates 42 and 44 are placed in an initial state, i.e., an UV-erased state. Then, the channels formed on both sidewalls of the channel region 22 that face the first and second floating gates 42 and 44 have a lower threshold voltage than that when the programming is completed, thus allowing a relatively large current to flow during the reading operation.
  • As described above, the nonvolatile semiconductor memory device according to example embodiments is a non-planar split-gate-type device, which is formed on the SOI substrate, and each memory cell includes two floating gates 42 and 44 which are adjacent to both sidewalls of the active region, i.e., the silicon island 20. Thus, each of the floating gates 42 and 44 has at least three corners, into which the electric field can concentrate adjacent to the word line 60. That is, a total of six or more corners of the floating gates 42 and 44 are adjacent to the word line 60. Therefore, the number of F-N tunneling regions increases.
  • Also, in each double-floating gate memory cell including the first floating gate 42 and the second floating gate 44, both sidewalls of the active region 20 serve as the channels so as to increase the effective channel width for each cell in the layout. As a result, a large current can be held in the memory cell.
  • FIGS. 4A, 4B, and 4C through 16A and 16B illustrate process steps of a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 1. Specifically, FIGS. 4A through 16A are sectional views taken along line 4A-4A′ of FIG. 3, and FIGS. 4B through 15B are plan views of FIGS. 4A through 15A, respectively. FIGS. 4C through 15C are partial sectional views of FIGS. 4B through 15B, respectively, and FIGS. 8D through 14D and 14E are partial sectional views of FIGS. 8B through 14B, respectively. Also, FIG. 16B is a partial sectional view of FIG. 16A.
  • Referring to FIGS. 4A and 4B, an SOI substrate where a silicon substrate 100, a BOX 102, and an SOI layer are sequentially stacked is prepared. The SOI substrate may be formed by, for example, an SIMOX process. For example, the BOX 102 has a thickness of about 1000 Å to 1500 Å, and the SOI layer has a thickness of about 500 Å. A mask pattern 110 is formed on the SOI layer to define an active region. The mask pattern 110 is formed of an oxide layer 112, a nitride layer 114, and another oxide layer 116, which are sequentially stacked. The oxide layer 112, the nitride layer 114, and the oxide layer 116 have a thickness of 200 Å, 300 Å, and 200 Å, respectively. The SOI layer is anisotropically etched using the mask pattern 110 as an etch mask to form a silicon island 104. The silicon island 104 extends in a first direction, i.e., in the x direction shown in FIG. 1, in the shape of a substantially square sectional bar.
  • As shown in FIG. 4C, a sectional view taken along line 4C-4C′ of FIG. 4B, the silicon island 104 has a top surface 104 t, which extends parallel to a main surface of the BOX 102, and both sidewalls 104 s extend from the BOX 102 perpendicular to the main surface of the BOX 102.
  • Referring to FIGS. 5A, 5B, and 5C, which is a sectional view taken along line 5C-5C′ of FIG. 5B, the exposed both sidewalls 104 s of the silicon island 104 are covered with a first oxide layer 118 having a thickness of about 70 Å. A portion of the first oxide layer 118 will constitute a coupling gate insulating layer later. The first oxide layer 118 may be formed using thermal oxidation, chemical vapor deposition (CVD), or a combination thereof.
  • Thereafter, channel ion implantation is performed to dope the silicon island 104 with impurity ions of a first conductivity type, e.g., p-type impurity ions.
  • Referring to FIGS. 6A, 6B, and 6C, which is a sectional view taken along line 6C-6C′ of FIG. 6B, a blanket conductive layer is formed to a thickness of about 400 Å on the BOX 102 to cover the mask pattern 110 and the first oxide layer 118. Then, the blanket conductive layer is anisotropically etched using the mask pattern 110 and the BOX 102 as an etch stop layer to form a first conductive layer 120. The first conductive layer 120 faces the sidewalls 104 s of the silicon island 104 on the first oxide layer 118, and surrounds the silicon island 104 in the shape of a spacer sidewall. In example embodiments, it is described that the blanket conductive layer is anisotropically etched to form the first conductive layer 120, but example embodiments are not limited thereto. Although not shown in the drawings, the first conductive layer 120 may be formed using other methods, for example, by processing the blanket conductive layer using a photolithography process and chemical mechanical polishing (CMP). In this case, the first conductive layer 120 is formed to have a square sectional shape having four corners instead of a shape having three corners (and a fourth rounded corner) as shown in FIG. 6A.
  • The first conductive layer 120 may be formed of doped polysilicon or metal. To form the first conductive layer 120 using doped polysilicon, an undoped polysilicon may be deposited first and then doped with impurity ions, or an already doped polysilicon layer may be deposited.
  • Referring to FIGS. 7A, 7B, and 7C, which is a sectional view taken along line 7C-7C′ of FIG. 7B, a silicon nitride layer having a thickness of about 1000 Å is formed on the BOX 102 to cover the resultant structure where the first conductive layer 120 is formed. Thereafter, the silicon nitride layer is patterned using a photolithography process so as to expose the first conductive layer 120 in a central portion of the silicon island 104, i.e., a region where two floating gates and a source will be formed. Thus, a first protecting insulating pattern 132 is formed to protect a portion of the first conductive layer 120.
  • Referring to FIGS. 8A and 8B, a silicon oxide layer is formed to a thickness of about 1000 Å on the entire surface of the resultant structure where the first protecting insulating pattern 132 is formed. Thereafter, the silicon oxide layer is anisotropically etched again to form a second protecting insulating pattern 134 on the sidewalls of the first protecting insulating pattern 132 in the shape of spacers. While the silicon oxide layer is being anisotropically etched to form the second protecting insulating pattern 134, the oxide layer 116 constituting an uppermost portion of the mask pattern 110 is also etched. This exposes the nitride layer 114 of the mask pattern 110 in a first region 104A, where a source will be formed inside the active region formed of the silicon island 104. The second protecting insulating pattern 134 covers and protects a portion of the first conductive layer 120, where floating gates will be formed. Also, the first conductive layer 120, which surrounds the silicon island 104, is exposed between the two adjacent second protecting insulating patterns 134.
  • FIGS. 8C and 8D are sectional views taken along lines 8C-8C′ and 8D-8D′, respectively, of FIG. 8B.
  • Referring to FIGS. 9A and 9B, a portion of the first conductive layer 120, which covers the sidewalls of the silicon island 104 in the first region 104A, is selectively removed by using the first protecting insulating pattern 132 and the second protecting insulating pattern 134 as an etch mask. As a result, first exposed sidewalls 120 a are formed adjacent to the first region 104A on the first conductive layer 120, and the first oxide layer 118 covering the sidewalls of the silicon island 104 is exposed in the first region 104A.
  • Thereafter, the nitride layer 114, which is exposed on the silicon island 104, is removed in the first region 104A to expose the oxide layer 112 of the mask pattern 110 in the first region 104A. Then, the first exposed sidewalls 120 a disposed on the first conductive layer 120 are oxidized by thermal oxidation. A second oxide layer is formed by CVD on the resultant structure and then anisotropically etched again. This forms first insulating spacers 142 to cover the first exposed sidewalls 120 a disposed on the first conductive layer 120. The thermal oxidation, for oxidizing the first exposed sidewalls 120 a, may be optionally omitted. Concurrently with the formation of the insulating spacers 142, spacers 144 are formed to cover the both sidewalls of the silicon island 104 in the first region 104A. The oxide layer 112 disposed on the silicon island 104 in the first region 104A is removed to expose the top surface of the silicon island 104. A source contact will be formed on the exposed top surface of the silicon island 104 later. If necessary, the etching of the second oxide layer may be further performed to expose the both sidewalls of the silicon island 104, such that even the spacers 144 covering the both sidewalls of the silicon island 104 are removed in the first region 104A.
  • FIGS. 9C and 9D are sectional views taken along lines 9C-9C′ and 9D-9D′, respectively, of FIG. 9B.
  • Referring to FIGS. 10A and 10B, impurity ions are implanted into the entire surface of the resultant structure to form a source 146 in the first region 104A of the silicon island 104. To form the source 146, impurity ions of a second conductivity type, which is opposite to the first conductivity type, e.g., n-type impurity ions, are implanted at a high concentration. The impurity ions for the source 146 are implanted at a higher concentration than that of the impurity ions for the channel ion implantation.
  • FIGS. 10C and 10D are sectional views taken along lines 10C-10C′ and 10D-10D′, respectively, of FIG. 10B.
  • Referring to FIGS. 11A and 11B, a conductive material is deposited on the entire surface of the resultant structure where the source 146 is formed. Thus, a second conductive layer is formed to a thickness of about 3000 Å to completely fill a space between the two adjacent second protecting insulating patterns 134 in the first region 104A. The second conductive layer is then planarized using CMP to form a source line 150 connected to the source 146. The source line 150 extends in a second direction, i.e., in the y direction, perpendicular to the first direction.
  • After the CMP process is performed, the first protecting insulating pattern 132 and the second protecting insulating pattern 134, which are adjacent to the source line 150, have a slightly reduced height. The source line 150 forms an ohmic contact with the source 146. The second conductive layer, which is used to form the source line 150, may be formed of doped polysilicon or metal. To form the source line 150 using doped polysilicon, an undoped polysilicon layer may be deposited and then doped with impurity ions, or an already doped polysilicon layer may be deposited.
  • FIGS. 11C and 11D are sectional views taken along lines 11C-11C′ and 11D-11D′, respectively, of FIG. 11B.
  • Referring to FIGS. 12A and 12B, the top surface of the source line 150 is thermally oxidized to form a thermal oxide layer 152 having a thickness of about 100 Å. Then, the first protecting insulating pattern 132, which is formed of the silicon nitride layer, is wet or dry etched and removed by using the thermal oxide layer 152 and the second protecting insulating pattern 134 as an etch mask. As a result, the oxide layer 116 of the mask pattern 110, which covers the top surface of the silicon island 104, is exposed in a second region 104B of the silicon island 104, and portions of the first conductive layer 120 and the BOX 102.
  • FIGS. 12C and 12D are sectional views taken along lines 12C-12C′ and 12D-12D′, respectively, of FIG. 12B.
  • Referring to FIGS. 13A and 13B, a portion of the first conductive layer 120, which covers the second region 104B of the silicon island 104, is selectively removed by a dry or wet etching process using oxide layers exposed on the silicon substrate 100, i.e., the thermal oxide layer 152, the second protecting insulating pattern 134, the oxide layer 116, the first oxide layer 118, and the BOX 102 as a hard mask. As a result, a first floating gate 122 and a second floating gate 124, which are formed of the remaining portion of the first conductive layer 120, are formed under the second protecting insulating pattern 134. The first floating gate 122 and the second floating gate 124 face each other with the silicon island 104 disposed therebetween. By removing the exposed first conductive layer 120, second exposed sidewalls 120 b are formed adjacent to the second region 104B on the remaining first conductive layer 120, i.e., the first and second floating gates 122 and 124. The second protecting insulating pattern 134 protects a portion of the first conductive layer 120, which remains adjacent the silicon island 104 excluding the first region 104A and the second region 104B.
  • FIGS. 13C and 13D are sectional views taken along lines 13C-13C′ and 13D-13D′, respectively, of FIG. 13B.
  • Referring to FIGS. 14A and 14B, the thermal oxide layer 152 and the oxide layer 116 of the mask pattern 110 are wet etched and removed to expose the nitride layer 114 of the mask pattern 110. Next, the exposed nitride layer 114 is wet etched and removed to expose the oxide layer 112 of the mask pattern 110. Thereafter, the oxide layer 112 of the mask pattern 110 is wet etched and removed to expose the top surface of the silicon island 104 in the second region 104B.
  • After the thermal oxide layer 152 and the oxide layers 116 and 112 are removed, the second protecting insulating pattern 134 has reduced height and width. Thus, as illustrated with dotted lines in FIG. 14B, a portion of the top surfaces of the first and second floating gates 122 and 124, which is covered with the second protecting insulating pattern 134, is exposed by a predetermined width adjacent to the second protecting insulating pattern 134. That is, while the top surface of the silicon island 104 is being exposed in the second region 104B, the top surface 120 c of the first and second floating gates 122 and 124 and the corners of the second exposed sidewalls 120 b are exposed.
  • A third oxide layer 160 is formed on the exposed top surface of the silicon island 104, the second exposed sidewalls 120 b and the exposed top surface 120 c of the first conductive layer 120 by using thermal oxidation or a CVD process. As a result, an insulating layer 162 is formed on the silicon island 104, and second insulating spacers 164 a and 164 b are formed on the second exposed sidewalls 120 b and the exposed top surface 120 c of the first conductive layer 120, which constitutes the first and second floating gates 122 and 124. The insulating layer 162 and the insulating spacers 164 a and 164 b are formed of the third oxide layer 160. The third oxide layer 160 may be formed to a thickness of about 160 Å to 170 Å, using thermal oxidation, a CVD process, or a combination thereof.
  • In example embodiments, the insulating layer 162 and the second insulating spacers 164 a and 164 b are concurrently formed. The second insulating spacers 164 a and 164 b are formed to cover the corners of the first floating gate 122 and the second floating gate 124, respectively. Also, the second insulating spacers 164 a and 164 b function as a first interpoly tunneling insulating layer 164 a and a second interpoly tunneling insulating layer 164 b between the first floating gate 122 and a word line, which will be formed later, and between the second floating gate 124 and the word line. In example embodiments, the same reference numerals are used to denote the second insulating spacers and the first and second interpoly tunneling insulating layers.
  • Here, it is described that the second insulating spacers 164 a and 164 b are formed on not only the second exposed sidewalls 120 b of the first conductive layer 120 but also on the exposed surfaces 120 c thereof, but example embodiments are not limited thereto. That is, it is possible to control the areas of the exposed top surface 120 c by varying the width of the second protecting insulating pattern 134, and it is also possible to form the second insulating spacers only on the second exposed sidewalls 120 b without exposing the top surfaces of the first conductive layer 120. Preferably, as described with reference to FIG. 2, to surround the corners of the first and second floating gates 122 and 124 with the word line 60, the width of the second protecting insulating pattern 134 is reduced so as to expose a portion of the top surface of the first conductive layer 120.
  • FIGS. 14C and 14D are sectional views taken along lines 14C-14C′ and 14D-14D′, respectively, of FIG. 14B, and FIG. 14E is a sectional view taken along line 14E-14E′ of FIG. 14B.
  • Referring to FIGS. 15A and 15B, a blanket deposit of a conductive material is deposited to a thickness of about 2000 Å using CVD to cover the sidewalls and the top surface of the second protecting insulating pattern 134. Thus, a third conductive layer is formed. Then, the third conductive layer is anisotropically etched until the third oxide layer 160 disposed on the silicon island 104 is exposed, thereby forming a word line 170 on the sidewalls of the second protecting insulating pattern 134. The word line 170 extends parallel to the source line 150, i.e., in the y direction of FIG. 1. The third conductive layer may be formed of doped polysilicon or metal. To form the third conductive layer using doped polysilicon, an undoped polysilicon layer may be deposited and then doped, or an already doped polysilicon layer may be deposited.
  • FIG. 15C is a sectional view taken along line 15C-15C′ of FIG. 15B. In FIG. 15C, the three corners of the first floating gate 122 are surrounded by the word line 170 and separated from the word line 170 by the first interpoly tunneling insulating layer 164 a, and the three corners of the second floating gate 124 are surrounded by the word line 170 and separated from the word line 170 by the second interpoly tunneling insulating layer 164 b. Although only the first floating gate 122 and its peripheral region are shown in FIG. 15C, the second floating gate 124 has the same structure as the first floating gate 122 shown in FIG. 15C.
  • Referring to FIG. 16A, a silicon nitride layer is deposited on the entire surface of the resultant structure where the word line 170 is formed, and etched back to form nitride spacers 172 covering the word line 170. During the etchback process for forming the nitride spacers 172, the third oxide layer 160, which covers the top surface of the silicon island 104, is removed due to over-etching. Thus, the top surface of the silicon island 104 is exposed adjacent to the nitride spacers 172. Thereafter, impurity ions are implanted into the exposed top surface of the silicon island 104 by a typical ion implantation process to form a drain 148 in the silicon island 104. To form the drain 148, impurity ions of the second conductivity type that is opposite to the first conductivity type, e.g., n-type impurity ions are implanted at a high concentration. The impurity ions are implanted into the drain 148 at a higher concentration than that of the impurity ions for the channel ion implantation.
  • Metal silicide layers 159, 179, and 149 are formed on the source line 150, the word line 170, and the drain 148 by using typical salicide process, CVD process, or PVD process. The metal silicide layers 159, 179, and 149 can reduce sheet resistance and contact resistance at each contact. For example, if the source line 150 and the word line 170 are formed of doped polysilicon, to form the metal silicide layers 159, 179, and 149, a metal layer is deposited by sputtering on the entire surface of the resultant structure where the drain 148 is formed, and then a primary thermal treatment is performed to form a metal silicide layer of a first phase. Next, the non-reacted metal layer is selectively removed by a wet etch process, and then a secondary thermal treatment is performed to form a metal silicide layer of a second phase, which is more stable in terms of resistance and phase than the metal silicide layer of the first phase. The metal silicide layers 159, 179, and 149 may be formed of, for example, cobalt silicide, nickel silicide, titanium silicide, hafnium silicide, platinum silicide, or tungsten silicide.
  • An insulating material is deposited on the entire surface of the resultant structure where the metal silicide layers 159, 179, and 149 are formed, to form an interlayer dielectric (ILD) 180. A portion of the ILD 180 is etched by a photolithography process to form a contact hole, which exposes the drain 148 of each memory cell. Thereafter, a fourth conductive layer is formed on the ILD 180 to a sufficient thickness enough to fill the contact hole, and then patterned by a photolithography process to form a bit line 190. The fourth conductive layer may be formed of doped polysilicon or metal. To form the fourth conductive layer using doped polysilicon, an undoped polysilicon layer may be deposited first and then doped, or an already doped polysilicon layer may be deposited.
  • FIG. 16B is a partial sectional view taken along line 16B-16B′ of FIG. 16A.
  • As shown in FIG. 16B, in the nonvolatile semiconductor memory device according to example embodiments, a first floating gate and a second floating gate face each other with the silicon island 104 therebetween, and the first and second floating gates are electrically insulated from each other. The first coupling gate insulating layer and the second coupling gate insulating layer, each of which is formed of the second oxide layer 118, are interposed between the channel region of the silicon island 104 and the first floating gate 122 and between the channel region of the silicon island 104 and the second floating gate 124, respectively. The word line 170 extends adjacent to the first floating gate 122 and the second floating gate 124. The first interpoly tunneling insulating layer 164 a is interposed between the first floating gate 122 and the word line 170, and the second interpoly tunneling insulating layer 164 b is interposed between the second floating gate 124 and the word line 170.
  • When voltages are applied to the word line 170 and the source 146, two channels 200 are formed along both sidewalls of the silicon island 104 perpendicular to a main surface of the SOI substrate and adjacent to the first coupling gate insulating layer and the second coupling gate insulating layer (each of which is formed of the first oxide layer 118). That is, a non-planar nonvolatile semiconductor memory device, in which the two channels 200 are formed perpendicular to the main surface of the SOI substrate, is provided.
  • The nonvolatile semiconductor memory device according to example embodiments is a non-planar split-gate-type device disposed on the SOI substrate. Each memory cell includes two floating gates, which face each other with the active region, i.e., the silicon island disposed therebetween. Accordingly, each floating gate has at least three corners, which are adjacent to a control gate and on which an electric field concentrates. In other words, since each memory cell includes a total of six or more corners of the floating gates adjacent to the control gate, the areas of the floating gates, where the electric field concentrates, increase.
  • Also, the device according to example embodiments comprises a double-floating gate structure. Both sidewalls of the active region serve as channels such that the channels are formed perpendicular to the main surface of the substrate. This improves the integration density as compared with conventional devices. Also, since the effective channel width for each memory cell can increase in a given layout, a large current can be held in the memory cell.
  • Further, the device according to example embodiments has a full depletion mode SOI structure, thus improving a sub-threshold characteristic. The non-planar structure, including double floating gates, is provided such that a gate is easily controlled so as to suppress the SCE and improve drain induced barrier lowering (DIBL). As a result, the scaling effect of the memory device can be enhanced. The SOI structure allows complete isolation between devices and excellent radiation hardness, thus reducing soft errors.
  • While example embodiments have been particularly shown and described herein, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims (45)

1. A nonvolatile semiconductor memory device, comprising:
an active region over a substrate;
a first floating gate at a first sidewall of the active region;
a first coupling gate insulating layer between the first floating gate and the first sidewall of the active region;
a second floating gate at a second sidewall of the active region, the second sidewall opposite to the first sidewall;
a second coupling gate insulating layer between the second floating gate and the second sidewall of the active region;
an insulating layer between the active region and a word line; and
a source and a drain in the active region.
2. The device of claim 1, wherein the active region extends in a first direction over the substrate, and the word line extends in a second direction perpendicular to the first direction.
3. The device of claim 1, wherein the first and second sidewalls of the active region provide channels when voltages are applied to the word line and the source.
4. The device of claim 3, wherein one channel is adjacent to the first coupling gate insulating layer and another channel is adjacent to the second coupling gate insulating layer.
5. The device of claim 1, wherein
the first floating gate has a first overlap portion where the word line overlaps a side and top surface of the first floating gate so as to overlap at least three corners of the first floating gate; and
the second floating gate has a second overlap portion where the word line overlaps a side and top surface of the second floating gate so as to overlap at least three corners of the second floating gate.
6. The device of claim 5, further comprising:
a first interpoly tunneling insulating layer between the word line and the first overlap portion to overlap the at least three corners of the first floating gate; and
a second interpoly tunneling insulating layer between the word line and the second overlap portion to overlap the at least three corners of the second floating gate.
7. The device of claim 5, wherein the insulating layer between the word line and the active region is on the active region between the first overlap portion and the second overlap portion.
8. The device of claim 1, wherein the active region is formed of a silicon island.
9. A nonvolatile semiconductor memory device, comprising:
a plurality of silicon islands over a substrate;
a plurality of first floating gates, each associated with one of the plurality of silicon islands and at a first sidewall of the associated silicon island;
first coupling gate insulating layers, each between an associated first floating gate and the associated silicon island;
a plurality of second floating gates, each associated with one of the plurality of silicon islands and at a second sidewall of the associated silicon island, the second sidewall opposite to the first sidewall;
second coupling gate insulating layers, each between an associated second floating gate and the associated silicon island; and
at least one word line over the silicon islands and overlapping portions of the plurality of first floating gates and portions of the plurality of second floating gates.
10. The device of claim 9, further comprising:
an insulating layer between the word line and each silicon island.
11. The device of claim 9, wherein
each of the silicon islands includes a source and at least one drain.
12. The device of claim 11, further comprising:
a source line over the silicon islands and parallel to the word line, the source line being electrically connected to the source in each of the silicon islands.
13. The device of claim 12, wherein the word line and the source line each include a metal silicide layer.
14. The device of claim 9, wherein the silicon islands are formed on an insulated substrate.
15. A nonvolatile semiconductor memory device, comprising:
an active region of a first conductivity type, the active region extending in a first direction on a first insulating layer over a substrate, the active region having a square sectional bar shape, the active region including a source and at least one drain, each of a second conductivity type opposite to the first conductivity type, and the active region including a channel region for providing channels perpendicular to an upper surface of the substrate between the source and the drain;
a first floating gate and a second floating gate on the first insulating layer and facing each other with the active region therebetween;
a first coupling gate insulating layer between the active region and the first floating gate;
a second coupling gate insulating layer between the active region and the second floating gate; and
a first word line over a portion of the active region with a second insulating layer therebetween.
16. The device of claim 15, further comprising:
a bit line connected to the drain and extending perpendicular to a lengthwise direction of the word line; and
the first floating gate and the second floating gate defining one memory cell, which has only one contact point with the bit line and only one contact point with the word line.
17. The device of claim 16, wherein the channels are two channels having surfaces that are perpendicular to the upper surface of the substrate along both sidewalls of the channel region when voltages are applied to the word line and the source.
18. The device of claim 17, wherein the two channels are adjacent to the first coupling gate insulating layer and the second coupling gate insulating layer.
19. The device of claim 15, wherein the word line extends in a second direction perpendicular to the first direction.
20. The device of claim 15, wherein
the first floating gate includes a first overlap portion facing the word line and the second floating gate includes a second overlap portion facing the word line; and
the word line has a plurality of recessed surfaces so as to surround the first overlap portion and the second overlap portion.
21. The device of claim 20, wherein the word line surrounds at least three corners of the first floating gate and at least three corners of the second floating gate.
22. The device of claim 20, further comprising:
a first interpoly tunneling insulating layer between the word line and the first overlap portion to surround the at least three corners of the first floating gate; and
a second interpoly tunneling insulating layer between the word line and the second overlap portion to surround the at least three corners of the second floating gate.
23. The device of claim 20, wherein the second insulating layer is on the channel region between the first overlap portion and the second overlap portion.
24. The device of claim 15, wherein
the source, the drain, the first floating gate, and the second floating gate define a memory cell with respect to the active region; and
a plurality of active regions are on the substrate with each of the active regions including first and second memory cells.
25. The device of claim 24, wherein the first and second memory cells of each active region have a common source.
26. The device of claim 24, wherein the first word line and a second word line are over the plurality of active regions, the first word line is connected to the first memory cell of each active region and the second word line is connected to the second memory cell of each active region.
27. The device of claim 24, wherein
the plurality of active regions are arranged in the lengthwise direction of the word line, and
the sources in the active regions are connected to each other via a source line that extends parallel to the word line.
28. The device of claim 27, wherein at least one of the word line and the source line include a metal silicide layer.
29. The device of claim 15, wherein
the first insulating layer is formed of a buried oxide layer formed in a silicon on insulator substrate; and
the active region is formed of silicon.
30. The device of claim 29, wherein
the first floating gate and the second floating gate each have a floating gate length that extends in the first direction; and
the upper surface of the active region has a width of ⅔ the floating gate length.
31. A nonvolatile semiconductor memory device, comprising:
a plurality of first memory cells, each of the plurality of first memory cells including,
a semiconductor layer extending in a first direction over an insulating layer, which is on a substrate, the semiconductor layer including a source and a first drain, and the semiconductor layer providing a channel region between the source and the first drain;
a first floating gate adjacent a first sidewall of the channel region;
a second floating gate adjacent a second sidewall of the channel region, the second sidewall opposite to the first sidewall; and
a control gate at least partially over the first and second floating gates.
32. The device of claim 31, wherein the semiconductor layer provides for a plurality of channels between the source and drain in the channel region.
33. The device of claim 32, wherein for each first memory cell,
the first and second sidewalls are perpendicular to the first insulating layer; and
an upper surface of the semiconductor layer is parallel to the first insulating layer; and
the channel region provides for a first channel and a second channel, which are adjacent to the first floating gate and the second floating gate, respectively, and are parallel to the first and second sidewalls.
34. The device of claim 33, wherein for each first memory cell,
the first floating gate and the second floating gate each have a floating gate length that extends in the first direction; and
the upper surface of the semiconductor layer has a width of ⅔ the floating gate length.
35. The device of claim 33, further comprising:
a first coupling gate insulating layer and a second coupling gate insulating layer, which are on the first and second sidewalls, respectively, of the semiconductor layer adjacent to the first channel and the second channel and between the semiconductor layer and the first and second floating gates, respectively.
36. The device of claim 32, wherein for each first memory cell,
the first and second sidewalls are perpendicular to the first insulating layer;
an upper surface of the semiconductor layer is parallel to the first insulating layer; and
the control gate is over a portion of the upper surface of the semiconductor layer.
37. The device of claim 36, further comprising:
a second insulating layer on the portion of the upper surface of the semiconductor layer between the control gate and semiconductor layer.
38. The device of claim 31, wherein for each first memory cell, the first floating gate and the second floating gate each have at least three corners covered by the control gate.
39. The device of claim 31, wherein for each first memory cell, the source and the drain each have a higher dopant concentration than in the channel region.
40. The device of claim 31, further comprising:
a plurality of second memory cells, each of the second memory cells associated with one of the first memory cells and formed from a same semiconductor layer as the associated first memory cell, each second memory cell having a same structure as the associated first memory cell.
41. The device of claim 40, wherein each second memory cell and the associated first memory cell have a common source.
42. The device of claim 41, further comprising:
a source line connected to the common sources.
43. The device of claim 42, further comprising:
a first word line parallel to the source line and connected to each control gate of the first memory cells; and
a second word line parallel to the source line and connected to each control gate of the second memory cells.
44. A nonvolatile memory cell, comprising:
a semiconductor layer over a substrate;
a first floating gate at a first side of the semiconductor layer;
a second floating gate at a second side of the semiconductor layer, the second side opposite to the first side; and
a control gate over the first and second floating gates and a portion of the semiconductor layer such that the control gate covers at least three corners of each of the first and second floating gates.
45. A method of manufacturing a memory cell, comprising:
forming a semiconductor layer over a substrate;
forming first and second floating gates at first and second sides of the semiconductor layer, the first side being opposite to the second side; and
forming a control gate over the first and second floating gates and a portion of the semiconductor layer such that the control gate covers at least three corners of each of the first and second floating gates.
US11/898,705 2003-08-07 2007-09-14 Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same Abandoned US20080006870A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/898,705 US20080006870A1 (en) 2003-08-07 2007-09-14 Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2003-0054782A KR100518588B1 (en) 2003-08-07 2003-08-07 Split gate type non-volatile semiconductor memory device having double-floating gate structure and process for manufacturing the same
KR10-2003-0054782 2003-08-07
US10/913,489 US7288810B2 (en) 2003-08-07 2004-08-09 Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same
US11/898,705 US20080006870A1 (en) 2003-08-07 2007-09-14 Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/913,489 Division US7288810B2 (en) 2003-08-07 2004-08-09 Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20080006870A1 true US20080006870A1 (en) 2008-01-10

Family

ID=33550332

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/913,489 Active 2025-04-11 US7288810B2 (en) 2003-08-07 2004-08-09 Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same
US11/898,705 Abandoned US20080006870A1 (en) 2003-08-07 2007-09-14 Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/913,489 Active 2025-04-11 US7288810B2 (en) 2003-08-07 2004-08-09 Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same

Country Status (6)

Country Link
US (2) US7288810B2 (en)
EP (1) EP1505658A3 (en)
JP (1) JP2005057296A (en)
KR (1) KR100518588B1 (en)
CN (1) CN100470809C (en)
TW (1) TWI253718B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101901813A (en) * 2010-07-20 2010-12-01 复旦大学 Semiconductor memory with vertical structure and manufacturing method thereof
US11652162B2 (en) * 2016-04-20 2023-05-16 Silicon Storage Technology, Inc. Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585111B1 (en) * 2003-11-24 2006-06-01 삼성전자주식회사 Non-planar transistor having germanium channel region and method for forming the same
US7087952B2 (en) * 2004-11-01 2006-08-08 International Business Machines Corporation Dual function FinFET, finmemory and method of manufacture
JP4761946B2 (en) * 2005-11-22 2011-08-31 株式会社東芝 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, ITS MANUFACTURING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT
JP4791868B2 (en) * 2006-03-28 2011-10-12 株式会社東芝 Fin-NAND flash memory
KR100719379B1 (en) 2006-03-30 2007-05-17 삼성전자주식회사 Nonvolatile memory device
US7829447B2 (en) * 2006-05-19 2010-11-09 Freescale Semiconductor, Inc. Semiconductor structure pattern formation
KR100745766B1 (en) * 2006-06-23 2007-08-02 삼성전자주식회사 Non-volatile memory device having four storage node films and method of operating the same
JP4250649B2 (en) * 2006-09-26 2009-04-08 株式会社東芝 Nonvolatile semiconductor memory element and nonvolatile semiconductor memory device
JP4760689B2 (en) * 2006-11-30 2011-08-31 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP2008205185A (en) * 2007-02-20 2008-09-04 Oki Electric Ind Co Ltd Manufacturing method of semiconductor memory device, and the semiconductor memory device
CN101442075B (en) * 2007-11-21 2011-03-16 南亚科技股份有限公司 Flash memory
JP2009164349A (en) * 2008-01-07 2009-07-23 Toshiba Corp Nonvolatile semiconductor storage device and method of manufacturing the same
US8513728B2 (en) * 2011-11-17 2013-08-20 Silicon Storage Technology, Inc. Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates
CN103426885A (en) * 2012-05-22 2013-12-04 亿而得微电子股份有限公司 Non-self-alignment and fixed hydrocarbon storage structure
CN104952715B (en) * 2014-03-25 2018-02-16 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
US9614088B2 (en) * 2014-08-20 2017-04-04 Taiwan Semiconductor Manufacturing Company Ltd. Metal gate structure and manufacturing method thereof
US9634018B2 (en) * 2015-03-17 2017-04-25 Silicon Storage Technology, Inc. Split gate non-volatile memory cell with 3D finFET structure, and method of making same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380057A (en) * 1980-10-27 1983-04-12 International Business Machines Corporation Electrically alterable double dense memory
US5045488A (en) * 1990-01-22 1991-09-03 Silicon Storage Technology, Inc. Method of manufacturing a single transistor non-volatile, electrically alterable semiconductor memory device
US5973356A (en) * 1997-07-08 1999-10-26 Micron Technology, Inc. Ultra high density flash memory
US6329685B1 (en) * 1999-09-22 2001-12-11 Silicon Storage Technology, Inc. Self aligned method of forming a semiconductor memory array of floating gate memory cells and a memory array made thereby
US20030038318A1 (en) * 2001-08-24 2003-02-27 Leonard Forbes Vertical transistor with horizontal gate layers
US20030042531A1 (en) * 2001-09-04 2003-03-06 Lee Jong Ho Flash memory element and manufacturing method thereof
US20030178670A1 (en) * 2002-03-19 2003-09-25 International Business Machines Corporation Finfet CMOS with NVRAM capability

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5718769Y2 (en) * 1975-12-31 1982-04-20
JPS60148168A (en) * 1984-01-13 1985-08-05 Seiko Instr & Electronics Ltd Semiconductor nonvolatile memory
JPH03126266A (en) * 1989-10-12 1991-05-29 Sony Corp Semiconductor nonvolatile memory
JP3219307B2 (en) * 1991-08-28 2001-10-15 シャープ株式会社 Semiconductor device structure and manufacturing method
JPH0745797A (en) * 1993-07-30 1995-02-14 Toshiba Corp Semiconductor storage device
JP2870478B2 (en) * 1996-04-25 1999-03-17 日本電気株式会社 Nonvolatile semiconductor memory device and method of operating the same
JP2877103B2 (en) * 1996-10-21 1999-03-31 日本電気株式会社 Nonvolatile semiconductor memory device and method of manufacturing the same
JP4384739B2 (en) * 1997-04-04 2009-12-16 聯華電子股▲ふん▼有限公司 Semiconductor device and manufacturing method thereof
JPH11220112A (en) * 1998-01-30 1999-08-10 Mitsubishi Electric Corp Semiconductor device and its manufacture
KR100368594B1 (en) * 2001-02-23 2003-01-24 삼성전자 주식회사 Split Gate Flash Memory Device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380057A (en) * 1980-10-27 1983-04-12 International Business Machines Corporation Electrically alterable double dense memory
US5045488A (en) * 1990-01-22 1991-09-03 Silicon Storage Technology, Inc. Method of manufacturing a single transistor non-volatile, electrically alterable semiconductor memory device
US5973356A (en) * 1997-07-08 1999-10-26 Micron Technology, Inc. Ultra high density flash memory
US6329685B1 (en) * 1999-09-22 2001-12-11 Silicon Storage Technology, Inc. Self aligned method of forming a semiconductor memory array of floating gate memory cells and a memory array made thereby
US20030038318A1 (en) * 2001-08-24 2003-02-27 Leonard Forbes Vertical transistor with horizontal gate layers
US20030042531A1 (en) * 2001-09-04 2003-03-06 Lee Jong Ho Flash memory element and manufacturing method thereof
US6768158B2 (en) * 2001-09-04 2004-07-27 Korea Advanced Institute Of Science And Technology Flash memory element and manufacturing method thereof
US20030178670A1 (en) * 2002-03-19 2003-09-25 International Business Machines Corporation Finfet CMOS with NVRAM capability

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101901813A (en) * 2010-07-20 2010-12-01 复旦大学 Semiconductor memory with vertical structure and manufacturing method thereof
US11652162B2 (en) * 2016-04-20 2023-05-16 Silicon Storage Technology, Inc. Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps

Also Published As

Publication number Publication date
KR20050015814A (en) 2005-02-21
TW200527610A (en) 2005-08-16
CN100470809C (en) 2009-03-18
EP1505658A3 (en) 2005-05-25
EP1505658A2 (en) 2005-02-09
US7288810B2 (en) 2007-10-30
TWI253718B (en) 2006-04-21
CN1607669A (en) 2005-04-20
JP2005057296A (en) 2005-03-03
US20050063215A1 (en) 2005-03-24
KR100518588B1 (en) 2005-10-04

Similar Documents

Publication Publication Date Title
US20080006870A1 (en) Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same
US6750525B2 (en) Non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure
US7132335B2 (en) Semiconductor device with localized charge storage dielectric and method of making same
US7256448B2 (en) Split gate type nonvolatile semiconductor memory device, and method of fabricating the same
US6809385B2 (en) Semiconductor integrated circuit device including nonvolatile semiconductor memory devices having control gates connected to common contact section
US7652322B2 (en) Split gate flash memory device having self-aligned control gate and method of manufacturing the same
KR101024336B1 (en) Nonvolatile memory cell and fabrication method thereof
US7410871B2 (en) Split gate type flash memory device and method for manufacturing same
US20040253787A1 (en) Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation
US20060006452A1 (en) EEPROM device and manufacturing method thereof
US20060001077A1 (en) Split gate type flash memory device and method of manufacturing the same
KR100297728B1 (en) Method for fabricating flash memory device and flash memory device fabricated thereby
US6441426B1 (en) Nonvolatile semiconductor memory device and method of manufacturing the same
JP3544308B2 (en) Manufacturing method of nonvolatile semiconductor memory device
US7183157B2 (en) Nonvolatile memory devices
US6486508B1 (en) Non-volatile semiconductor memory devices with control gates overlapping pairs of floating gates
JP4080485B2 (en) Bit line structure and manufacturing method thereof
CN109994542B (en) Semiconductor device and method for manufacturing the same
US7541638B2 (en) Symmetrical and self-aligned non-volatile memory structure
US20080083943A1 (en) Dual-gate memory device and optimization of electrical interaction between front and back gates to enable scaling
JP2005026696A (en) Eeprom device and manufacturing method therefor
JP5014591B2 (en) Semiconductor device and manufacturing method thereof
KR100351051B1 (en) Method for fabricating non-volatile memory cell having bilayered structured floating gate
KR100683389B1 (en) Cell transistor of flash memory and forming method
KR100789409B1 (en) Eeprom device and method for manufacturing the same

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION