US20080030286A1 - Semiconductor memory device with data bus scheme for reducing high frequency noise - Google Patents
Semiconductor memory device with data bus scheme for reducing high frequency noise Download PDFInfo
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- US20080030286A1 US20080030286A1 US11/755,791 US75579107A US2008030286A1 US 20080030286 A1 US20080030286 A1 US 20080030286A1 US 75579107 A US75579107 A US 75579107A US 2008030286 A1 US2008030286 A1 US 2008030286A1
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- data
- memory device
- semiconductor memory
- data bus
- low frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/044—Details of backplane or midplane for mounting orthogonal PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
Definitions
- the present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a data bus structure which reduces high frequency noise to data and passes only data having a low frequency.
- CPUs central processing units
- the operating voltage of a computer system is being lowered.
- the voltage level of a signal used for input and/or output data in a memory system is also being lowered.
- the structure of the bus channel of the system should be optimized so that the signal voltage is maximized and high frequency noise occurring in the system is minimized.
- FIG. 1 is a schematic diagram showing an ordinary stub-type memory bus structure.
- a bus 160 is arranged on a system board, and each memory device 130 on a memory module 140 is connected to the bus 160 through a stub 150 corresponding to the memory device 130 on the memory module 140 .
- a stub 150 has a shape that branches from the bus 160 passing through a module socket 120 .
- the entire length of a channel, that is, the bus 160 is short, and accordingly, the propagation time of a signal on the channel is short and the electromagnetic interference is small.
- a stub resistor is generally used on a bus to lessen the degradation of signal integrity due to the reflected wave noise on the channel.
- the stub resistor is serially connected to the channel.
- the stub resistor reduces the high frequency noise, and at the same time reduces the signal voltage on the channel such that if a low signal power is used, the size of a signal is further reduced.
- PCB printed circuit board
- a semiconductor memory device comprising memory modules which have memories, and a data bus which transfers data to the memory modules, wherein the data bus comprises a low frequency band data pass unit which removes a high frequency component of the data and sends the data to the memory modules.
- the low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns.
- PCB printed circuit board
- An end of each of the stubs, the end which is not connected to the data bus, is open.
- the low frequency band data pass unit comprises a plurality of plates which are connected to the data bus in parallel and are formed as PCB patterns.
- the plates are connected to the data bus through short lines formed as PCB patterns.
- the low frequency band data pass unit has a shape in which parts having a first, wide, width and parts having a second, narrow, width are alternately connected.
- the low frequency band data pass unit has a shape in which line parts having high impedance and line parts having low impedance are alternately connected.
- a semiconductor memory device having memory modules, which have memories, and a data bus which transfers data to the memory modules, comprising a plurality of stubs which are connected to the data bus in parallel and are formed as PCB patterns.
- An end of each of the stubs, the end which is not connected to the data bus, is open.
- a semiconductor memory device having memory modules, which have memories, and a data bus which transfers data to the memory modules, comprising a plurality of plates which are connected to the data bus in parallel and are formed as PCB patterns.
- the plates are connected to the data bus through short lines formed as PCB patterns.
- a semiconductor memory device comprising memory modules which have memories and a data bus which transfers data to the memory modules, wherein the data bus has a shape in which parts having a first, wide, width and parts having a second, narrow, width are alternately connected.
- a semiconductor memory device comprising memory modules which have memories and a data bus which transfers data to the memory modules, wherein the data bus has a shape in which line parts having high impedance and line parts having low impedance are alternately connected.
- a semiconductor memory device as disclosed herein can reduce the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors is reduced, and the process for attaching the passive devices is simplified.
- FIG. 1 is a schematic diagram showing a stub-type memory bus structure
- FIG. 2 is a schematic diagram showing a semiconductor memory device according to a first preferred embodiment
- FIG. 3 is a schematic diagram showing a semiconductor memory device according to a second preferred embodiment
- FIG. 4 is a schematic diagram showing a semiconductor memory device according to a third preferred embodiment
- FIG. 5 is a schematic diagram showing a semiconductor memory device according to a fourth preferred embodiment.
- FIGS. 6 (A) and 6 (B) are graphs showing simulated operations of semiconductor memory devices according to the first through fourth preferred embodiments.
- FIG. 2 is a schematic diagram showing a semiconductor memory device according to a first preferred embodiment.
- the semiconductor memory device 200 comprises a plurality of memory modules MM 1 through MM 4 , having respective memories M 1 through M 4 , and a data bus (DABUS) which transfers data to the memory modules MM 1 through MM 4 .
- the data bus (DABUS) includes a low frequency band data pass unit 220 which removes the high frequency component of data above a certain “cut-off” frequency, and transfers the filtered data to the memory modules MM 1 through MM 4 .
- FIG. 2 shows the memory controller 210 which controls the memories M 1 through M 4 , the memory modules MM 1 through MM 4 , having respective memories M 1 through M 4 , and slots S 1 through S 4 to which the memory modules MM 1 through MM 4 are mounted.
- the memory controller 210 and memories M 1 through M 4 are connected through the data bus (DABUS).
- DABUS data bus
- the data bus includes the low frequency band data pass unit 220 which removes the high frequency component of data, and transfers the data to the memory modules MM 1 through MM 4 .
- the low frequency band data pass unit 220 functions as a low pass filter which reduces the high frequency component of data, to reduce high frequency noise caused by high frequency components of the data, and passes only the low frequency components of the data.
- the low frequency band data pass unit 220 is formed as a PCB pattern.
- DABUS data bus
- the semiconductor memory device 200 of FIG. 2 includes the low frequency band data pass unit 220 which is formed by a PCB pattern, without using a separate, discrete passive device, and as a result, it is advantageous in price and manufacturing process. Also, such an arrangement increases design flexibility such that design of a variety of bus structures having different frequency characteristics becomes easier.
- the low frequency band data pass unit includes a plurality of stubs formed in parallel. One end of each stub is connected to the “through-lines” of the data bus (DABUS). The other end of each stub is open (unconnected). Beneficially, the stubs are formed as printed circuit board (PCB) patterns. The operation of the embodiment shown in FIG. 3 will be explained later.
- PCB printed circuit board
- the low frequency band data pass unit includes a plurality of plates.
- the plates are connected to the “through-lines” of the data bus (DABUS) by short connection lines formed as PCB patterns.
- the plates are formed as printed circuit board (PCB) patterns. The operation of the embodiment shown in FIG. 4 will be explained later.
- the low frequency band data pass unit has a shape wherein parts having a wide width and parts having a narrow width are alternately connected. Furthermore, the structure in FIG. 5 shows that the low frequency band data pass unit has a shape in which line parts having a high impedance, and line parts having a low impedance, are alternately connected. The operation of the embodiment shown in FIG. 5 will be explained later.
- the three embodiments of the low frequency band data pass unit 220 described above commonly perform the function of a low pass filter which reduces the high frequency noise of data.
- FIG. 3 is a schematic diagram showing a semiconductor memory device according to a second preferred embodiment.
- the semiconductor memory device 300 comprises a plurality of memory modules MM 1 through MM 4 , having respective memories M 1 through M 4 , and a data bus (DABUS) which transfers data to the memory modules MM 1 through MM 4 .
- the semiconductor memory device 300 has a plurality of stubs 320 that are formed as PCB patterns and are connected in parallel to the “through-lines” of the data bus (DABUS).
- An end of each of the stubs 320 is open or unconnected.
- the stubs 320 of FIG. 3 perform the function of the low frequency band data pass unit 220 of FIG. 2 .
- the stubs 320 are formed as PCB patterns, and, beneficially, are short lines.
- the stubs 320 are connected to the “through-lines” of the data bus (DABUS) in parallel.
- DABUS data bus
- the stubs 320 are made very short considering the wavelength of the data frequency, so that the stubs have the characteristics of capacitors in a desired signal band.
- the stubs 320 perform the function of capacitors connected to the “through-lines” of the data bus (DABUS) in parallel so that the stubs 320 play the role of a low pass filter. Therefore, the high frequency noise of the data is reduced and only the low frequency component of the data is transferred to the memory.
- DABUS data bus
- FIG. 4 is a schematic diagram showing a semiconductor memory device according to a third preferred embodiment.
- the semiconductor memory device 400 comprises a plurality of memory modules MM 1 through MM 4 , having respective memories M 1 through M 4 , and a data bus (DABUS) which transfers data to the memory modules MM 1 through MM 4 .
- the semiconductor memory device 400 has a plurality of plates 420 that are formed as PCB patterns and are connected to the “through-lines” of the data bus (DABUS) in parallel.
- the plates 420 are connected to the “through-lines” of the data bus (DABUS) through short connection lines (STB) formed as PCB patterns.
- DABUS data bus
- STB short connection lines
- the plates 420 of FIG. 4 perform the function of the low frequency band data pass unit 220 of FIG. 2 .
- the plates are formed as PCB patterns, and form a plate capacitor between the system board (not shown) and a ground surface.
- the amount of capacitance affecting the data bus can be controlled.
- FIG. 5 is a schematic diagram showing a semiconductor memory device according to a fourth preferred embodiment.
- the semiconductor memory device 500 comprises a plurality of memory modules MM 1 through MM 4 , having respective memories M 1 through M 4 , and a data bus (DABUS) which transfers data to the memory modules MM 1 through MM 4 .
- the data bus (DABUS) has a shape in which parts having a wide width and parts having a narrow width are alternately connected.
- the semiconductor memory device 500 comprising a plurality of memory modules MM 1 through MM 4 , having respective memories M 1 through M 4 , and the data bus (DABUS) which transfers data to the memory modules MM 1 through MM 4 , has a shape in which line parts having a high impedance and line parts having a low impedance are alternately connected.
- DABUS data bus
- the shape of the data bus (DABUS) of FIG. 5 performs the function of the low frequency band data pass unit 220 of FIG. 2 . That is, a part of the data bus (DABUS) having a wide width has low impedance, and a part of the data bus (DABUS) having a narrow width has high impedance. Because parts having high impedance and parts having low impedance are alternately connected, the shape of the data bus (DABUS), in which parts having a wide width and parts having a narrow width are alternately connected, plays the role of a low pass filter. Accordingly, the high frequency noise of the data is reduced and only low frequency component of the data is transferred to the memory.
- FIGS. 6 (A) and 6 (B) are graphs showing simulated operations of semiconductor memory devices according to the first through fourth preferred embodiments.
- the data bus (DABUS) used in the simulation operates at a speed of 266 Mbps, with four memory slots S 1 through S 4 mounted into the modules MM 1 through MM 4 .
- FIGS. 6 compare the waveform of a write operation when stubs, one end of each of which is open, are connected in parallel in the middle of the “through-lines” of the data bus (DABUS) by applying the method of the first preferred embodiment, and the waveform of a write operation when stubs are not used.
- DABUS data bus
- FIG. 6 (A) shows the simulation when the stubs are not used.
- the data voltage margin is substantially reduced because of undershoot.
- FIG. 6 (B) shows the simulation when the stubs are used.
- undershoot greatly decreases and the waveform of the data substantially improves as a whole.
- the semiconductor memory device reduces the high frequency noise of data transferred through a data bus without adding a separate, discrete, passive device.
- the voltage margin of the data improves, the cost for passive devices such as capacitors is reduced, and the process for attaching the passive devices is simplified.
Abstract
A semiconductor memory device includes memory modules which have memories and a data bus which transfers data to the memory modules, in which the data bus comprises a low frequency band data pass unit which removes the high frequency component of the data and sends the data to the memory modules. The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns. The low frequency band data pass unit comprises a plurality of plates that are connected to the data bus in parallel and are formed as PCB patterns. The low frequency band data pass unit has a shape in which parts having a wide width and parts having a narrow width are alternately connected. Therefore, without adding a separate passive device, the semiconductor memory device reduces the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors, is reduced, and the process for attaching the passive devices is simplified.
Description
- This is a Continuation of U.S. non-provisional patent application No. 10/424,923, filed Apr. 29, 2003, the contents of which are hereby incorporated by reference in their entirety for all purposes as if fully set forth herein.
- The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a data bus structure which reduces high frequency noise to data and passes only data having a low frequency.
- Semiconductor memory devices have been developed focusing on high integration and high capacity based on the high integration, while central processing units (CPUs) that are cores of computer system have been developed mainly focusing on high speed operation.
- As a result, the difference between the operation speeds of the CPUs and memory devices continues to increase such that the operation speed of the memory devices becomes a major factor limiting the performance of a computer system.
- In addition, in line with the recent trend in the memory systems toward high speed and low power consumption, the operating voltage of a computer system is being lowered. With the operating voltage being reduced or lowered, the voltage level of a signal used for input and/or output data in a memory system is also being lowered.
- However, since in line with the increasing operation speed, high frequency noise occurring in a computer system continues to increase, it is increasingly difficult to secure a voltage margin needed in system operation.
- In order to secure a voltage margin of a signal needed in a system operating at high speed, the structure of the bus channel of the system should be optimized so that the signal voltage is maximized and high frequency noise occurring in the system is minimized.
-
FIG. 1 is a schematic diagram showing an ordinary stub-type memory bus structure. Referring toFIG. 1 , in the ordinary stub-typememory bus structure 100, abus 160 is arranged on a system board, and eachmemory device 130 on amemory module 140 is connected to thebus 160 through astub 150 corresponding to thememory device 130 on thememory module 140. Astub 150 has a shape that branches from thebus 160 passing through amodule socket 120. - In the
bus structure 100 using the prior art stubs shown inFIG. 1 , the entire length of a channel, that is, thebus 160, is short, and accordingly, the propagation time of a signal on the channel is short and the electromagnetic interference is small. - However, by the stub structure, discontinuity and impedance mismatching on the channel occur causing reflected wave noise. Accordingly, due to the effect of reflected wave noise, at a high speed operation, serious distortion occurs in the waveform of a signal on the channel and high speed operation of the memory system is restricted.
- That is, in the stub-type bus structure, due to the reflected wave noise on the channel, signal integrity degrades.
- Therefore, in the stub-
type bus structure 100, a stub resistor is generally used on a bus to lessen the degradation of signal integrity due to the reflected wave noise on the channel. The stub resistor is serially connected to the channel. - However, the stub resistor reduces the high frequency noise, and at the same time reduces the signal voltage on the channel such that if a low signal power is used, the size of a signal is further reduced.
- Recently, in order to solve this problem, a method in which a serial resistor used for impedance matching on the channel is replaced by a parallel capacitor has been introduced. Though this method lessens signal voltage reduction caused by a serial resistor for channel matching, this method requires a complicated manufacturing process to add a capacitor to the channel in parallel.
- To solve the above problems, it would be desirable to provide a semiconductor memory device having a data bus structure in which using only a printed circuit board (PCB) pattern, high frequency noise is removed and only low frequency band data is transferred.
- According to an aspect of the present invention, there is provided a semiconductor memory device comprising memory modules which have memories, and a data bus which transfers data to the memory modules, wherein the data bus comprises a low frequency band data pass unit which removes a high frequency component of the data and sends the data to the memory modules.
- The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns.
- An end of each of the stubs, the end which is not connected to the data bus, is open.
- The low frequency band data pass unit comprises a plurality of plates which are connected to the data bus in parallel and are formed as PCB patterns.
- The plates are connected to the data bus through short lines formed as PCB patterns.
- The low frequency band data pass unit has a shape in which parts having a first, wide, width and parts having a second, narrow, width are alternately connected.
- The low frequency band data pass unit has a shape in which line parts having high impedance and line parts having low impedance are alternately connected.
- According to another aspect of the present invention, there is provided a semiconductor memory device having memory modules, which have memories, and a data bus which transfers data to the memory modules, comprising a plurality of stubs which are connected to the data bus in parallel and are formed as PCB patterns.
- An end of each of the stubs, the end which is not connected to the data bus, is open.
- According to still another aspect of the present invention, there is provided a semiconductor memory device having memory modules, which have memories, and a data bus which transfers data to the memory modules, comprising a plurality of plates which are connected to the data bus in parallel and are formed as PCB patterns.
- The plates are connected to the data bus through short lines formed as PCB patterns.
- According to yet still another aspect of the present invention, there is provided a semiconductor memory device comprising memory modules which have memories and a data bus which transfers data to the memory modules, wherein the data bus has a shape in which parts having a first, wide, width and parts having a second, narrow, width are alternately connected.
- That is, a semiconductor memory device comprising memory modules which have memories and a data bus which transfers data to the memory modules, wherein the data bus has a shape in which line parts having high impedance and line parts having low impedance are alternately connected.
- Therefore, without adding a separate discrete passive device, a semiconductor memory device as disclosed herein can reduce the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors is reduced, and the process for attaching the passive devices is simplified.
- The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
-
FIG. 1 is a schematic diagram showing a stub-type memory bus structure; -
FIG. 2 is a schematic diagram showing a semiconductor memory device according to a first preferred embodiment; -
FIG. 3 is a schematic diagram showing a semiconductor memory device according to a second preferred embodiment; -
FIG. 4 is a schematic diagram showing a semiconductor memory device according to a third preferred embodiment; -
FIG. 5 is a schematic diagram showing a semiconductor memory device according to a fourth preferred embodiment; and - FIGS. 6(A) and 6(B) are graphs showing simulated operations of semiconductor memory devices according to the first through fourth preferred embodiments.
-
FIG. 2 is a schematic diagram showing a semiconductor memory device according to a first preferred embodiment. - Referring to
FIG. 2 , thesemiconductor memory device 200 according to the first preferred embodiment comprises a plurality of memory modules MM1 through MM4, having respective memories M1 through M4, and a data bus (DABUS) which transfers data to the memory modules MM1 through MM4. The data bus (DABUS) includes a low frequency banddata pass unit 220 which removes the high frequency component of data above a certain “cut-off” frequency, and transfers the filtered data to the memory modules MM1 through MM4. - The operation of the semiconductor memory device according to the first preferred embodiment will now be explained in detail referring to
FIG. 2 . -
FIG. 2 shows thememory controller 210 which controls the memories M1 through M4, the memory modules MM1 through MM4, having respective memories M1 through M4, and slots S1 through S4 to which the memory modules MM1 through MM4 are mounted. - The
memory controller 210 and memories M1 through M4 are connected through the data bus (DABUS). - The data bus (DABUS) includes the low frequency band
data pass unit 220 which removes the high frequency component of data, and transfers the data to the memory modules MM1 through MM4. - The low frequency band
data pass unit 220 functions as a low pass filter which reduces the high frequency component of data, to reduce high frequency noise caused by high frequency components of the data, and passes only the low frequency components of the data. Beneficially, the low frequency banddata pass unit 220 is formed as a PCB pattern. - In order to reduce the high frequency noise, discrete passive devices such as capacitors may be attached to a data bus (DABUS), but this introduces restrictions caused by problems in the process of attaching the capacitors.
- In contrast, the
semiconductor memory device 200 ofFIG. 2 includes the low frequency banddata pass unit 220 which is formed by a PCB pattern, without using a separate, discrete passive device, and as a result, it is advantageous in price and manufacturing process. Also, such an arrangement increases design flexibility such that design of a variety of bus structures having different frequency characteristics becomes easier. - The structures of several embodiments of the low frequency band
data pass unit 220 will now be explained in more detail. - As shown in
FIG. 3 , in one embodiment the low frequency band data pass unit includes a plurality of stubs formed in parallel. One end of each stub is connected to the “through-lines” of the data bus (DABUS). The other end of each stub is open (unconnected). Beneficially, the stubs are formed as printed circuit board (PCB) patterns. The operation of the embodiment shown inFIG. 3 will be explained later. - As shown in
FIG. 4 , in another embodiment the low frequency band data pass unit includes a plurality of plates. The plates are connected to the “through-lines” of the data bus (DABUS) by short connection lines formed as PCB patterns. Beneficially, the plates are formed as printed circuit board (PCB) patterns. The operation of the embodiment shown inFIG. 4 will be explained later. - As shown in
FIG. 5 , in another embodiment the low frequency band data pass unit has a shape wherein parts having a wide width and parts having a narrow width are alternately connected. Furthermore, the structure inFIG. 5 shows that the low frequency band data pass unit has a shape in which line parts having a high impedance, and line parts having a low impedance, are alternately connected. The operation of the embodiment shown inFIG. 5 will be explained later. - The three embodiments of the low frequency band data pass
unit 220 described above commonly perform the function of a low pass filter which reduces the high frequency noise of data. -
FIG. 3 is a schematic diagram showing a semiconductor memory device according to a second preferred embodiment. - Referring to
FIG. 3 , thesemiconductor memory device 300 according to the second preferred embodiment comprises a plurality of memory modules MM1 through MM4, having respective memories M1 through M4, and a data bus (DABUS) which transfers data to the memory modules MM1 through MM4. Thesemiconductor memory device 300 has a plurality ofstubs 320 that are formed as PCB patterns and are connected in parallel to the “through-lines” of the data bus (DABUS). - An end of each of the
stubs 320, the end that is not connected to the “through-lines” of the data bus, is open or unconnected. - The
stubs 320 ofFIG. 3 perform the function of the low frequency band data passunit 220 ofFIG. 2 . Thestubs 320 are formed as PCB patterns, and, beneficially, are short lines. Thestubs 320 are connected to the “through-lines” of the data bus (DABUS) in parallel. - The
stubs 320 are made very short considering the wavelength of the data frequency, so that the stubs have the characteristics of capacitors in a desired signal band. - That is, the
stubs 320 perform the function of capacitors connected to the “through-lines” of the data bus (DABUS) in parallel so that thestubs 320 play the role of a low pass filter. Therefore, the high frequency noise of the data is reduced and only the low frequency component of the data is transferred to the memory. - By changing the width, length, and arrangement of the
stubs 320, a variety of low pass filters are implemented. -
FIG. 4 is a schematic diagram showing a semiconductor memory device according to a third preferred embodiment. - Referring to
FIG. 4 , thesemiconductor memory device 400 according to the third preferred embodiment comprises a plurality of memory modules MM1 through MM4, having respective memories M1 through M4, and a data bus (DABUS) which transfers data to the memory modules MM1 through MM4. Thesemiconductor memory device 400 has a plurality ofplates 420 that are formed as PCB patterns and are connected to the “through-lines” of the data bus (DABUS) in parallel. - The
plates 420 are connected to the “through-lines” of the data bus (DABUS) through short connection lines (STB) formed as PCB patterns. - The
plates 420 ofFIG. 4 perform the function of the low frequency band data passunit 220 ofFIG. 2 . The plates are formed as PCB patterns, and form a plate capacitor between the system board (not shown) and a ground surface. - By adjusting the size of the
plates 420, the amount of capacitance affecting the data bus can be controlled. - The data bus (DABUS) and the
plates 420 connected to the “through-lines” of the data bus (DABUS) in parallel play the role of a low pass filter. Accordingly, the high frequency noise of the data is reduced and only low frequency components of the data are transferred to the memory. -
FIG. 5 is a schematic diagram showing a semiconductor memory device according to a fourth preferred embodiment. - Referring to
FIG. 5 , thesemiconductor memory device 500 according to the fourth preferred embodiment comprises a plurality of memory modules MM1 through MM4, having respective memories M1 through M4, and a data bus (DABUS) which transfers data to the memory modules MM1 through MM4. The data bus (DABUS) has a shape in which parts having a wide width and parts having a narrow width are alternately connected. - That is, in the
semiconductor memory device 500 comprising a plurality of memory modules MM1 through MM4, having respective memories M1 through M4, and the data bus (DABUS) which transfers data to the memory modules MM1 through MM4, has a shape in which line parts having a high impedance and line parts having a low impedance are alternately connected. - The shape of the data bus (DABUS) of
FIG. 5 , in which parts having a wide width and parts having a narrow width are alternately connected, performs the function of the low frequency band data passunit 220 ofFIG. 2 . That is, a part of the data bus (DABUS) having a wide width has low impedance, and a part of the data bus (DABUS) having a narrow width has high impedance. Because parts having high impedance and parts having low impedance are alternately connected, the shape of the data bus (DABUS), in which parts having a wide width and parts having a narrow width are alternately connected, plays the role of a low pass filter. Accordingly, the high frequency noise of the data is reduced and only low frequency component of the data is transferred to the memory. - FIGS. 6(A) and 6(B) are graphs showing simulated operations of semiconductor memory devices according to the first through fourth preferred embodiments.
- The data bus (DABUS) used in the simulation operates at a speed of 266 Mbps, with four memory slots S1 through S4 mounted into the modules MM1 through MM4.
- In particular, FIGS. 6 compare the waveform of a write operation when stubs, one end of each of which is open, are connected in parallel in the middle of the “through-lines” of the data bus (DABUS) by applying the method of the first preferred embodiment, and the waveform of a write operation when stubs are not used.
-
FIG. 6 (A) shows the simulation when the stubs are not used. - Here, in the write operations in the first memory module (MM1) and the second memory module (MM2) in particular, the data voltage margin is substantially reduced because of undershoot.
-
FIG. 6 (B) shows the simulation when the stubs are used. - Here, undershoot greatly decreases and the waveform of the data substantially improves as a whole.
- As described above, the semiconductor memory device reduces the high frequency noise of data transferred through a data bus without adding a separate, discrete, passive device. As a result, the voltage margin of the data improves, the cost for passive devices such as capacitors is reduced, and the process for attaching the passive devices is simplified.
- Particular embodiments have been explained above and are shown. However, the present invention is not restricted to the above-described embodiments and many variations are possible within the spirit and scope of the present invention. The scope of the present invention is not determined by the above description but by the accompanying claims.
Claims (11)
1. A semiconductor memory device comprising:
memory modules which have memories; and
a data bus which transfers data to the memory modules, wherein the data bus includes a printed circuit board (PCB) pattern configured as a low frequency band data pass unit adapted to send the data to the memory modules and to remove a high frequency component of the data.
2. The semiconductor memory device of claim 1 , wherein the PCB pattern includes a plurality of stubs which are arranged in parallel.
3. The semiconductor memory device of claim 2 , wherein one end of each of the stubs is open.
4. The semiconductor memory device of claim 1 , wherein the PCB pattern includes a plurality of plates that are arranged in parallel.
5. The semiconductor memory device of claim 4 , wherein the data bus further includes through-lines, and wherein PCB pattern further includes connection lines which connect the plates to the through-lines.
6. The semiconductor memory device of claim 1 , wherein the PCB pattern has a shape in which parts having a first width and parts having a second width are alternately connected, where the first width is greater than the second width.
7. The semiconductor memory device of claim 1 , wherein the PCB pattern has a shape in which line parts having high impedance and line parts having low impedance are alternately connected.
8. A semiconductor memory device comprising:
memory modules which have memories; and
a data bus which transfers data to the memory modules, wherein the data bus includes a low frequency band data pass unit adapted to send the data to the memory modules and to remove a high frequency component of the data.
9. The semiconductor memory device of claim 8 , wherein the low frequency band data pass unit includes a plurality of stubs which are arranged in parallel.
10. The semiconductor memory device of claim 9 , wherein one end of each of the stubs is open.
11. The semiconductor memory device of claim 8 , further comprising a printed circuit board (PCB) pattern which at least partially defines the low frequency band data pass unit.
Priority Applications (1)
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US11/755,791 US20080030286A1 (en) | 2002-06-04 | 2007-05-31 | Semiconductor memory device with data bus scheme for reducing high frequency noise |
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KR10-2002-0031410A KR100450677B1 (en) | 2002-06-04 | 2002-06-04 | Semiconductor memory device with data bus scheme for reducing high frequency noise |
US10/424,923 US7239216B2 (en) | 2002-06-04 | 2003-04-29 | Semiconductor memory device with data bus scheme for reducing high frequency noise |
US11/755,791 US20080030286A1 (en) | 2002-06-04 | 2007-05-31 | Semiconductor memory device with data bus scheme for reducing high frequency noise |
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US10/424,923 Continuation US7239216B2 (en) | 2002-06-04 | 2003-04-29 | Semiconductor memory device with data bus scheme for reducing high frequency noise |
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US11/755,791 Abandoned US20080030286A1 (en) | 2002-06-04 | 2007-05-31 | Semiconductor memory device with data bus scheme for reducing high frequency noise |
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JP (1) | JP4545391B2 (en) |
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Also Published As
Publication number | Publication date |
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CN100593240C (en) | 2010-03-03 |
KR20030094569A (en) | 2003-12-18 |
CN1467850A (en) | 2004-01-14 |
US7239216B2 (en) | 2007-07-03 |
KR100450677B1 (en) | 2004-10-01 |
US20030223290A1 (en) | 2003-12-04 |
JP4545391B2 (en) | 2010-09-15 |
JP2004013900A (en) | 2004-01-15 |
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