US20080048327A1 - Electronic circuit with embedded memory - Google Patents
Electronic circuit with embedded memory Download PDFInfo
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- US20080048327A1 US20080048327A1 US11/873,719 US87371907A US2008048327A1 US 20080048327 A1 US20080048327 A1 US 20080048327A1 US 87371907 A US87371907 A US 87371907A US 2008048327 A1 US2008048327 A1 US 2008048327A1
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- G11C5/00—Details of stores covered by group G11C11/00
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- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/18—Peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates generally to semiconductor circuitry and, more particularly, to circuitry which includes memory devices.
- a typical computer system includes a main computer chip with a processor circuit, a control circuit, and a memory cache that are carried on a single major surface of a substrate.
- the typical computer system also includes main memory which is positioned on a separate memory chip outside the main computer chip. Since the memory cache is positioned on the same substrate as the processor and control circuits in the main computer chip, it is often referred to as embedded memory.
- the memory cache typically includes fast and expensive memory cells, such as Static Random Access Memory (SRAM) cells, and the main memory typically includes slower and less expensive Dynamic Random Access Memory (DRAM) cells. Both SRAM and DRAM cells are larger than the devices included in the processor and control circuits, with SRAM cells being much larger than DRAM cells.
- cache memory L 1 cache or L 2 cache, for example
- L 1 cache or L 2 cache is used to store information from a slower storage medium or subsystem, such as the main memory or peripherals like hard disks and CD-ROMs, that is accessed frequently to increase the operation of the main computer chip.
- the main computer chip is increased because its idle time is reduced. For example, when the processor circuit accesses the main memory, it does so in about 60 nanoseconds (ns). However, a typical processor circuit can have cycle times of about 2 nanoseconds. Hence, there are about 30 wasted cycles while the processor circuit accesses the main memory. As a result, the processor circuit is idle for many cycle times while it accesses the main memory.
- the processor circuit can access the cache memory in about 10 ns to 30 ns, so the idle time is significantly reduced if the information needed is stored in the cache memory.
- the access time of the processor circuit to a hard disk is even slower at about 10 milliseconds (ms) to 12 ms, and the access time to a CD-ROM drive is about 10 times greater than this.
- cache memory uses a small amount of fast and expensive memory to allow the processor circuit faster access to information normally stored by a large amount of slower, less-expensive memory.
- the size of the main memory is much larger than the size of the cache memory.
- the main memory can store 256 MB to 1 GB in a single memory chip, but the cache memory can only store about 1 MB to 2 MB. This is because the size of the memory circuitry needed to store information in SRAM is much larger than that needed for DRAM.
- a conventional SRAM circuit includes six transistors to store one bit of information and a conventional DRAM circuit includes one transistor and one capacitor, which tend to be large, to store one bit of information.
- the size of a conventional embedded SRAN cell is about 70-120 F 2 and the size of a conventional DRAM memory cell is about 15 F 2 .
- 1 F is the minimum photolithographic feature size.
- 1 F corresponds to 90 nm and 1 F 2 corresponds to an area that it 90 nm by 90 nm in size.
- 1 F corresponds to 60 nm and 1 F 2 corresponds to an area that it 60 nm by 60 nm in size.
- to increase the size of the cache memory by increasing the number of SRAM cells included therein would significantly increase the size of the computer chip and decrease its yield. Further, most of the area on the computer chip will be occupied by memory circuitry instead of processor and control circuitry.
- one problem is that the yield of computer chips in a manufacturing run decreases as their size increases.
- several computer chips are fabricated from a single large wafer in a run.
- the individual computer chips carried by the wafer are typically referred to as die.
- the die in the wafer are diced to provide separate chips.
- a wafer has defects distributed throughout it surface which can negatively impact the operation of the computer chips. If the computer chip is larger in size, then it is more likely to include a defect from the wafer and if the computer chip is smaller in size, then it is less likely to include a defect from the wafer. Hence, smaller computer chips are less likely to be defective. Further, if the computer chip is smaller in size, then more of them can be fabricated from a single wafer, which also decreases costs. Hence, smaller computer chips increase the yield and decrease the costs.
- Another problem is that it is typically desirable to increase the number of devices included in the processor and control circuitry so that the processor can operate faster and perform more complicated operations. It is desirable for computer chips to be fast so they can process more data in a given amount of time. The speed of operation of a computer chip is typically measured in the number of instructions per second it can perform.
- Computer chips can be made to process more data in a given amount of time in several ways.
- the computer chip can include devices which are smaller, but this requires advances in lithography and increasingly expensive manufacturing equipment. As discussed above, they can also be made faster by decreasing the time it takes to perform certain tasks, such as storing or retrieving information to and from memory or other peripherals and subsystems.
- Computer chips can also be made faster by increasing the number of devices included therein so that more information can be processed in a given period of time. For example, if one processor operates on 32-bit data, then another processor that operates on 64-bit data can process information twice as fast because it can perform more instructions per second. However, the 64-bit processor will need more devices since there are more bits to process at a given time. Hence, if most of the area on the computer chip is occupied by memory cells, then there is less area for the processor and control circuitry to process data with a higher number of bits. The total area of the computer chip can be increased, but as discussed above, this decreases the yield and increases the cost.
- the present invention provides circuitry which includes first and second circuits and an interconnect region.
- a first interconnect is included in the interconnect region.
- the first interconnect extends above and between the first and second circuits to provide communication therebetween.
- a third circuit is positioned on the interconnect region and a second interconnect is included in the interconnect region.
- the second interconnect extends between the third circuit and at least one of the first and second circuits to provide communication therebetween.
- the present invention also provides circuitry which includes control and digital circuitry positioned on a substrate.
- An interconnect region is positioned on surfaces of the control and digital circuitry to provide communication therebetween.
- Memory circuitry is positioned on the interconnect region so that the interconnect region provides communication between the memory circuitry and the control circuitry.
- the present invention further provides circuitry which includes a substrate and first and second processor circuits carried by the substrate.
- a control circuit is carried by the substrate and positioned near the first and second processor circuits.
- An interconnect region is carried by and extends from the substrate. The interconnect region allows the first and second processor circuits to communicate with each other and the control circuit.
- a memory circuit is positioned on the interconnect region so that the memory circuit is electrically coupled to the control circuit through the interconnect region.
- FIG. 1 is a simplified top view of a computer chip, in accordance with the present invention, with one processor positioned near a control circuit, the sectional view being taken along a cut line 1 - 1 ′ of FIG. 2 .
- FIG. 2 is a simplified sectional view of the computer chip of FIG. 1 taken along a cut-line 2 - 2 ′ of FIG. 1 .
- FIG. 3 a is a perspective view of a computer chip with memory devices positioned on the same substrate as the processor and control circuits.
- FIGS. 3 b - 3 d are simplified perspective views of different computer chips in which the memory circuit is positioned above the processor and/or control circuits in accordance with the present invention.
- FIG. 4 is a more detailed view of a memory circuit shown in FIGS. 2 and 6 .
- FIG. 5 is a simplified top view of a computer chip, in accordance with the present invention, with multiple processors separated by a control circuit, the sectional view being taken along a cut line 5 - 5 ′ of FIG. 6 .
- FIG. 6 is a simplified sectional view of the computer chip of FIG. 5 taken along a cut-line 6 - 6 ′ of FIG. 5 .
- FIG. 7 is a simplified top view of another embodiment of a computer chip, in accordance with the invention, with multiple processor circuits and multiple control circuits.
- FIG. 8 is a simplified top view of another embodiment of a computer chip, in accordance with the present invention, with multiple processor circuits surrounded by a control circuit.
- FIG. 9 is a simplified top view of another embodiment of a computer chip, in accordance with the present invention, with multiple processors partially surrounded by multiple control circuits.
- FIGS. 1 and 2 show simplified top and cross sectional views of a computer chip 100 which includes circuitry, in accordance with the present invention.
- FIG. 1 is a top view taken along a cut-line 1 - 1 ′ of FIG. 2
- FIG. 2 is a sectional view taken along a cut-line 2 - 2 ′ of FIG. 1 . It should be noted that in the following figures, like reference characters indicate corresponding elements throughout the several views.
- computer chip 100 includes processor and control circuits which are carried by a substrate and coupled together so that signals can flow between them.
- Computer chip 100 also includes a memory circuit positioned above the processor and control circuits.
- the memory circuit is spaced apart from the processor and control circuits by an interconnect region.
- the memory circuit is also coupled to the control circuit through the interconnect region so that signals can flow therebetween.
- the control circuit can receive output signals from the processor circuit and, in response, provide signals to and receive signals from the memory circuit.
- the control circuit provides input signals to the processor circuit.
- a memory circuit is discussed here and throughout the disclosure for illustrative purposes and that, in other embodiments, the memory circuit can be replaced with other circuitry which can be fabricated in the same or a similar manner.
- a processor circuit typically executes a series of machine instructions to process data. It usually includes an ALU (Arithmetic/Logic Unit) to perform mathematical operations like addition, subtraction, multiplication and division. Modern processor circuits typically include floating point processors that can perform extremely sophisticated operations on large floating point numbers. A processor circuit provide commands to the control circuit to move data from one memory location to another in the memory circuit. A processor circuit can also make decisions and jump to a new set of instructions based on those decisions.
- ALU Arimetic/Logic Unit
- FIG. 3 a is a perspective view of a computer chip 110 with a memory circuit 221 positioned on the same substrate 111 as processor and control circuits 144 and 143 .
- processor circuit 144 and control circuit 143 occupy 30% and 20%, respectively, of the total area of the chip, and memory circuit 221 occupies 50%. It should be noted, however, that they can occupy different amounts of area than that shown here.
- FIGS. 3 b - 3 d are simplified perspective views of computer chips 114 , 115 , and 116 , respectively, which are similar or identical to computer chip 100 .
- computer chips 114 , 115 , and 116 each include a substrate 142 which carries processor circuit 144 and control circuit 143 .
- Chip 100 also includes memory circuit 121 positioned above and separated from substrate 142 by an interconnect region, which is not shown for simplicity.
- processor circuit 144 and control circuit 143 include more electronic devices and occupy twice the area than they do in computer chip 110 shown in FIG. 3 a . This may be desirable so that computer chip 114 can operate with data represented by a higher number of bits. This may also be desired so that chip 114 can perform more complicated operations, such as more accurate computations or pipelining.
- memory circuit 121 also occupies twice the area so that it can store more information, which speeds up the operation of computer chip 114 .
- the area of computer chip 115 is half the size of computer chip 110 shown in FIG. 3 a because processor 144 and control circuit 143 are the same size as that shown in FIG. 3 a .
- Memory circuit 121 is positioned above substrate 142 and extends over the same area as processor circuit 144 and control circuit 143 combined. In this way, computer chip 115 in FIG. 3 c occupies half the area as chip 110 and, consequently, is less expensive to fabricate because it has a higher yield and more chips can be fabricated on a single wafer.
- FIG. 3 d the area of computer chip 116 is the same as computer chip 110 shown in FIG. 3 a , but processor 144 and control circuit 143 are the same size as that shown in FIG. 3 b .
- Memory circuit 121 is positioned above substrate 142 and extends over the same area as control circuit 143 , so its size is less than that shown in FIG. 3 b . This may be useful in applications where a lot of memory is not needed. It should be noted that memory circuit 121 can also be positioned over processor circuit 142 or it can extend over both processor and control circuits 144 and 143 .
- the processor in the computer chip discussed herein can address memory devices on a separate chip positioned outside the computer chip.
- the computer chip can include embedded memory cells on the same surface as the control and processor circuits, in addition to the memory devices positioned above them.
- These memory devices can include a cache memory and/or ROM devices.
- the ROM devices can operate as a BIOS (Basic Input/Output System) for the computer system.
- Another advantage of computer chip 100 is that the memory circuit is positioned closer to the control and processor circuits so that signals can flow therebetween in less time. This speed up operation of computer chip 100 because the access time is reduced and computer chip 100 is idle for fewer cycle times. Still another advantage of circuit 100 is that the control and processor circuits are fabricated with a different mask set than the memory circuit. Hence, the masks are less complicated and less expensive to make. A further advantage is that the memory devices are fabricated from blanket semiconductor layers after they have been bonded to the interconnect region. Hence, the memory devices do not need to be aligned with the processor and/or control circuitry, which is a complicated and expensive process.
- computer chip 100 includes control circuit 143 and processor circuit 144 carried by substrate 142 ( FIG. 2 ).
- Computer chip 100 also includes memory circuit 121 spaced apart from processor circuit 144 and control circuit 143 by an interconnect region 131 .
- memory circuit 121 is positioned above processor circuit 144 and control circuit 143 as discussed above.
- Memory circuit 121 is coupled to control circuit 143 through interconnect region 131 so that signals can flow therebetween.
- substrate 142 includes silicon, although it can include other materials which can support the subsequent structures positioned thereon.
- suitable substrate materials include gallium arsenide, indium phosphide, and silicon carbide, among others. It should be noted that substrate 142 can have portions doped n-type or p-type and some portions of substrate 142 can even be undoped.
- the preferred material for substrate 142 in this invention is single crystalline material which can have defects, but is generally better material quality compared to amorphous or polycrystalline material.
- control circuit 143 and processor circuit 144 include digital circuitry known in the art. However, the digital circuitry is not shown in FIGS. 1 or 2 for simplicity and ease of discussion.
- the digital circuitry can include electronic devices, such as transistors, which extend into substrate 142 and/or out of substrate 142 through a surface 142 a ( FIG. 2 ).
- Processor circuit 144 can operate in many different ways. For example, processor circuit 144 can operate as a central processing unit, such as those commonly found in a computer chip, a signal processor, such as those commonly found in communication systems, or a microcontroller. In other examples, processor circuit 144 can include analog circuitry, such as amplifiers and/or converters, for analog-to-digital converter applications.
- Control circuit 143 includes circuitry typically found in periphery logic circuits which read, write, and erase semiconductor memory devices. This circuitry typically includes a sense amplifier, column selector, and/or a row selector which are used to communicate with memory devices, as will be discussed in more detail below.
- interconnect region 131 is positioned on surface 142 a of substrate 142 .
- Interconnect region 131 and regions subsequently positioned thereon are not shown in FIG. 1 for simplicity.
- interconnect region 131 includes an interlayer dielectric region (ILD) 133 with interconnects extending between surface 142 a and a surface 131 a of region 131 so that signals can flow therethrough.
- ILD interlayer dielectric region
- Each interconnect typically includes one or more interconnect lines 135 and/or one or more vias 134 .
- Interconnect region 131 also typically includes one or more contacts 132 coupled to the electronic devices included in control circuit 143 or processor circuit 144 .
- the interconnects included in interconnect region 131 can be formed so that signals, such as signal S a , can flow between the various devices included in processor circuit 144 .
- the interconnects can also be coupled together so that signals can flow between control circuit 143 and processor circuit 144 .
- the interconnects, vias, and contacts can include conductive materials known in the art, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or a doped semiconductor, among others.
- signal S a can flow between processor circuit 144 and control circuit 143 through an interconnect 138 a included in interconnect region 131 , as shown in FIG. 2 .
- Interconnect 138 a includes contacts 132 a and 132 b and an interconnect line 135 a . Ends of contacts 132 a and 132 b are coupled to processor circuit 144 and control circuit 143 , respectively, and extend upwardly therefrom surface 142 a .
- Interconnect line 135 a extends between opposed ends of contacts 132 a and 132 b .
- control circuit 143 is positioned near processor circuit 144 so that the distance traveled by signals S a flowing therebetween is reduced.
- a memory circuit 121 is positioned on interconnect region 131 and bonded to surface 131 a .
- the bonding can be done in many different ways. For example, the bonding can be done by heating bonding surface 131 a and coupling memory circuit 121 thereto. Since memory circuit 121 is bonded to interconnect region 131 instead of deposited thereon, it can include better quality semiconductor material. One reason the material is better quality is because it is more crystalline. It is more crystalline than polycrystalline material which is typically deposited on dielectric regions when wafer bonding is not used. More information about wafer bonding can be found in co-pending U.S.
- Memory circuit 121 includes a bit line 120 a positioned on surface 131 a .
- a dielectric region 123 is positioned on surface 131 a and bit line 120 a .
- Bit line vias 124 a extend upwardly therefrom bit line 120 a and through dielectric region 123 .
- the number of bit line vias 124 a depends on the number of devices it is desired to form in memory circuit 121 .
- Each bit line via 124 a is coupled to an electronic device 124 .
- Electronic device 124 is typically a transistor or a memory device, although it can include other devices.
- the transistor can be a metal oxide semiconductor field effect transistor (MOSFET) and the memory device can be a negative differential resistance (NDR) static random access memory (SRAM) cell.
- An NDR SRAM includes a layer structure that operates as a transistor and a layer structure that operates as a thyristor. The transistor and thyristor are coupled together to operate as the NDR SRAM cell. More information regarding the NDR SRAM cell can be found in co-pending U.S. patent application titled “SEMICONDUCTOR MEMORY DEVICE” filed on the same date herewith by the same inventor and incorporated herein by reference.
- a reference line via 124 b is coupled to the opposite end of each device 124 .
- Each reference line via 124 b extends upwardly from its corresponding device 124 where it connects to a reference line 120 b .
- each device 124 is coupled between bit line and reference lines vias 124 a and 124 b .
- line 120 a can be used as a reference line
- line 120 b can be used as a bit line.
- a dielectric region 148 is positioned on dielectric region 123 and reference line 120 b.
- Memory circuit 121 and interconnect region 131 include interconnects so that signals can flow between control circuit 143 and bit line 120 a and reference line 120 b .
- a reference interconnect 136 extends through regions 133 and 123 so that one end is coupled to control circuit 143 and the opposite end is coupled to reference line 120 b .
- a bit interconnect 137 extends through region 133 so that one end is coupled to control circuit 143 and the other end is coupled to bit line 120 a .
- control circuit 143 can provide a bit signal to bit line 120 a through interconnect 137 and a reference signal to reference line 120 b through interconnect 136 .
- control circuit 143 can communicate with the devices included in device structure 124 .
- the reference line 120 b can be connected to an outside contact (not shown) which provides a reference voltage or current from outside of the circuit 100 .
- control circuit 143 provides signals to and receives signals from memory circuit 121 through interconnects 136 and 137 .
- the signals can be to read, write, and/or erase information in memory circuit 121 .
- Control circuit 143 then provides input signals to processor circuit 144 .
- the input signals can be data values stored by memory circuit 121 that processor circuit 144 desires to process.
- FIG. 4 shows a more detailed sectional view of memory circuit 121 .
- each electronic device 124 is a single transistor capacitorless dynamic random access memory (DRAM) device, although devices 124 can include other devices, such as a SONOS (Semiconductor Oxide Nitride Oxide Semiconductor) type nonvolatile memory device with a ONO (Oxide Nitride Oxide) dielectric.
- device 124 includes an n + pn ⁇ stack of layers, although it can include other layer structures, such as a npn stack, a p + np + stack, or a pnp stack.
- the n + pn + stack includes an n + -type doped region 125 a positioned on bit line via 124 a and a p-type doped region 125 b positioned on region 125 b .
- An n + -type doped region 125 c is positioned on region 125 c so that it is coupled between region 125 b and reference line via 124 b .
- An insulating region 125 d is positioned around the outer periphery of the stack of regions 125 a , 125 b , and 125 c .
- a control terminal 125 e is positioned around the outer periphery of insulating region 125 d.
- regions 125 a , 125 b , and/or 125 c can be adjusted in response to a word signal provided to control terminal 125 e .
- the word signal is provided by control circuit 143 through a word interconnect 139 .
- Word interconnect 139 is coupled between control circuit 143 and control terminal 125 e and extends through dielectric regions 123 and 133 similar to interconnects 136 and 137 .
- Interconnect 139 , insulator region 125 d , and control terminal 125 e are not shown in FIG. 2 for simplicity.
- FIGS. 5 and 6 show simplified top and sectional views of a computer chip 101 in accordance with the present invention.
- FIG. 5 is a top view taken along a cut-line 5 - 5 ′ of FIG. 6
- FIG. 6 is a sectional view taken along a cut-line 6 - 6 ′ of FIG. 5 .
- chip 101 includes multiple processors which can communicate with the control circuit and the memory circuit as discussed above in conjunction with FIGS. 1-2 , 3 b - 3 d , and 4 .
- the processors can also communicate with each other using an interface circuit (not shown) which provides better data flow between processors. The data flow is better because it can happen faster and with less noise so there are fewer errors in the signal.
- Computer chip 102 includes control circuit 143 and processors 144 a - 144 d which are carried by substrate 142 ( FIG. 6 ).
- control circuit 143 is positioned in a region that is cross-shaped from a top view ( FIG. 5 ) so that it extends between processors 144 a - 144 d . In this way, the processors are separated from each other by control circuit 143 .
- processors 144 a - 144 d can be the same or similar to processor circuit 144 discussed above in conjunction with FIGS. 1-2 , 3 b - 3 d , and 4 .
- Interconnect region 131 is positioned on surface 142 a of substrate 142 so that it covers control circuit 143 as well as processors 144 a - 144 d . However, in other embodiments, interconnect region 131 can be positioned so that it covers only a portion of logic circuit 143 , processor circuit 144 a , processor circuit 144 b , processor circuit 144 c , and/or processor circuit 144 d.
- various signals can flow between processors 144 a - 144 d and control circuit 143 .
- signal S a , S b , S c , and S d can flow between processor circuit 144 a , 144 b , 144 c , and 144 d , respectively, and control circuit 143 , as shown in FIG. 5 .
- Signals can also flow between processors 144 a - 144 d without flowing through control circuit 143 .
- signals S ab , S ac , S bd , and S cd can flow between processors 144 a - 144 b , 144 a - 144 c , 144 b - 144 d , and 144 c - 144 d , respectively, as shown in FIG. 5 .
- Signals S ab , S ac , S bd , and S cd can flow through interconnects which extend through interconnect region 131 .
- the interconnects can be similar to interconnect 138 , but are not shown for simplicity.
- signal S a can flow between processor circuit 144 a and control circuit 143 through an interconnect 138 a , as shown in FIG. 6 .
- Interconnect 138 a includes contacts 132 a and 132 b and interconnect line 135 a , as described above in conjunction with FIG. 2 .
- signal S b can flow between processor circuit 144 b and control circuit 143 through an interconnect 138 b .
- Interconnect 138 b includes contacts 132 c and 132 d and interconnect line 135 b . Ends of contacts 132 c and 132 d are coupled to processor circuit 144 b and control circuit 143 , respectively, and extend upwardly therefrom.
- Interconnect line 135 b extends between opposed ends of contacts 132 c and 132 d so that signal S b can flow between processor circuit 144 b and control circuit 143 . Signals S c and S d can flow between control circuit 143 and corresponding processors 144 c and 144 d with similar interconnects included in interconnect region 131 .
- chip 101 One advantage of chip 101 is that the distance between control circuit 143 and processors 144 a - 144 d is reduced so that they can communicate with each other faster. This increases the speed of computer chip 100 . Another advantage is that the design of chip 101 is convenient because each processor circuit 144 a - 144 d can have the same or a similar design which simplifies its fabrication.
- FIG. 7 is a top view of a computer chip 102 in accordance with the present invention.
- Chip 102 includes processors 144 a - 144 d positioned near each other in a manner similar to that of chip 101 shown in FIG. 5 .
- the control circuit includes separate control circuits 143 a - 143 d .
- processors 144 a and 144 b are spaced apart by control circuit 143 a
- processors 144 b and 144 d are spaced apart by control circuit 143 b
- processors 144 a and 144 c are spaced apart by control circuit 143 c
- processors 144 c and 144 d are spaced apart by control circuit 143 d .
- each control circuit 143 a - 143 d can be the same or similar to control circuit 143 shown in FIG. 4 .
- signals S a1 and S b1 flow between control circuit 143 a and processors 144 a and 144 b , respectively.
- Signals S a2 and S c1 flow between control circuit 143 c and processors 144 a and 144 c , respectively.
- Signals S b2 and S d1 flow between control circuit 143 b and processors 144 b and 144 d , respectively.
- Signals S c2 and S d2 flow between control circuit 143 d and processors 144 c and 144 d , respectively.
- Signals S a1 , S b1 , S a2 , S c1 , S b2 , S d1 , S c2 , and S d2 flow between corresponding control circuits and processors through interconnects, similar to interconnects 138 a and 138 b , as described above, in conjunction with FIG. 6 .
- Signals S ab , S ac , S bd , S ad , S bc , and S cd flow between corresponding processors 144 a - 144 d through conductive lines which extend through substrate 142 or on its surface 142 a . However, these conductive lines are not shown for simplicity.
- chip 102 One advantage of chip 102 is that signals S ab , S ac , S bd , S cd , S ad , and S bc , can flow therebetween processors 144 a - 144 d faster so that chip 102 can operate faster.
- One reason the signals can flow faster is because the interconnects are shorter so the distance of travel is shorter and their capacitance is smaller.
- FIG. 8 is a top view of a computer chip 103 in accordance with the present invention.
- Chip 103 includes processors 144 a - 144 d positioned adjacent to each other.
- control circuit 143 extends around an outer periphery of processors 144 a - 144 d .
- processors 144 a - 144 d are surrounded by control circuit 143 .
- Signals S a , S b , S c , and S d can flow between control circuit 143 and corresponding processors 144 a - 144 d through interconnects, similar to interconnects 138 a and 138 b , as described above, in conjunction with FIG. 6 .
- processors 144 a - 144 d are coupled together so that signals S ab , S ac , S bd , S ad , S bc , and S cd can flow therebetween as described above in conjunction with FIG. 7 above.
- FIG. 9 is a top view of a computer chip 104 in accordance with the present invention.
- Chip 104 includes processors 144 a - 144 d positioned near each other in a manner similar to that of chip 103 shown in FIG. 8 .
- control circuit 143 a extends along an outer periphery of processors 144 a and 144 b .
- control circuit 143 b extends along an outer periphery of processors 144 b and 144 d .
- Control circuit 143 c extends along an outer periphery of processors 144 a and 144 c and control circuit 143 d extends along an outer periphery of processors 144 c and 144 d.
- Signals S a1 , S a2 , S b1 , S b2 , S c1 , S c2 , S d1 , and S d2 can flow between corresponding control circuits 143 a - 143 d and corresponding processors 144 a - 144 d through interconnects, similar to interconnects 138 a and 138 b , as described above, in conjunction with FIG. 6 .
- processors 144 a - 144 d are coupled together so that signals S ab , S ac , S bd , S ad , S bc , and S cd can flow therebetween as described above in conjunction with FIG. 6 above.
Abstract
Description
- This application is a divisional of application Ser. No. 11/092,521, entitled “ELECTRONIC CIRCUIT WITH EMBEDDED MEMORY”, filed on Mar. 29, 2005, which claims priority to U.S. Pat. No. 7,052,941 filed on Jun. 21, 2004, the contents of both of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates generally to semiconductor circuitry and, more particularly, to circuitry which includes memory devices.
- 2. Description of the Related Art
- Advances in semiconductor manufacturing technology have provided computer chips with integrated circuits that include many millions of active and passive electronic devices, along with the interconnects to provide the desired circuit connections. As is well-known, most integrated circuits include laterally oriented active and passive electronic devices that are carried on a single major surface of a substrate. Active devices typically include transistors and passive devices typically include resistors, capacitors, and inductors. However, these laterally oriented devices consume significant amounts of chip area.
- For example, a typical computer system includes a main computer chip with a processor circuit, a control circuit, and a memory cache that are carried on a single major surface of a substrate. The typical computer system also includes main memory which is positioned on a separate memory chip outside the main computer chip. Since the memory cache is positioned on the same substrate as the processor and control circuits in the main computer chip, it is often referred to as embedded memory.
- The memory cache typically includes fast and expensive memory cells, such as Static Random Access Memory (SRAM) cells, and the main memory typically includes slower and less expensive Dynamic Random Access Memory (DRAM) cells. Both SRAM and DRAM cells are larger than the devices included in the processor and control circuits, with SRAM cells being much larger than DRAM cells. As is well-known in the art, cache memory (L1 cache or L2 cache, for example) is used to store information from a slower storage medium or subsystem, such as the main memory or peripherals like hard disks and CD-ROMs, that is accessed frequently to increase the operation of the main computer chip.
- One reason the operation of the main computer chip is increased because its idle time is reduced. For example, when the processor circuit accesses the main memory, it does so in about 60 nanoseconds (ns). However, a typical processor circuit can have cycle times of about 2 nanoseconds. Hence, there are about 30 wasted cycles while the processor circuit accesses the main memory. As a result, the processor circuit is idle for many cycle times while it accesses the main memory.
- The processor circuit, however, can access the cache memory in about 10 ns to 30 ns, so the idle time is significantly reduced if the information needed is stored in the cache memory. The access time of the processor circuit to a hard disk is even slower at about 10 milliseconds (ms) to 12 ms, and the access time to a CD-ROM drive is about 10 times greater than this. Hence, cache memory uses a small amount of fast and expensive memory to allow the processor circuit faster access to information normally stored by a large amount of slower, less-expensive memory.
- With this in mind, it seems like the operation of the computer system can be speeded up even more by increasing the size of the cache memory so that it operates as the main memory or by embedding the main memory on the same substrate as the processor and control circuit and eliminating the cache memory altogether. However, there are several problems with doing this.
- One problem with doing this is cost. As mentioned above, the SRAM cells included in cache memory are larger and expensive, so increasing the size of the cache memory would significantly increase the cost of the computer chip. DRAM cells are less expensive and smaller, but to embed them with the main computer chip will still significantly increase the cost. One reason the cost increases for both embedded SRAM and DRAM cells is because the number of masks needed to fabricate the main computer chip increases. For example, to embed SRAM and DRAM memory cells with the main computer chip would require about 3-4 and 6-8 extra masks, respectively. This is because the masks used to fabricate the processor and control circuitry are not compatible with the masks used to fabricate SRAM and DRAM memory cells. Another reason the cost increases is because, as discussed below, the yield in manufacturing computer chips decreases as the size of the computer chip increases.
- Another problem is that in today's computer systems, the size of the main memory is much larger than the size of the cache memory. For example, in current state of the art systems, the main memory can store 256 MB to 1 GB in a single memory chip, but the cache memory can only store about 1 MB to 2 MB. This is because the size of the memory circuitry needed to store information in SRAM is much larger than that needed for DRAM. A conventional SRAM circuit includes six transistors to store one bit of information and a conventional DRAM circuit includes one transistor and one capacitor, which tend to be large, to store one bit of information.
- For example, the size of a conventional embedded SRAN cell is about 70-120 F2 and the size of a conventional DRAM memory cell is about 15 F2. As is known in the art, 1 F is the minimum photolithographic feature size. Hence, if the computer chip is being fabricated using 90 nm lithography, then 1 F corresponds to 90 nm and 1 F2 corresponds to an area that it 90 nm by 90 nm in size. If the computer chip is being fabricated using 60 nm lithography, then 1 F corresponds to 60 nm and 1 F2 corresponds to an area that it 60 nm by 60 nm in size. Thus, to increase the size of the cache memory by increasing the number of SRAM cells included therein would significantly increase the size of the computer chip and decrease its yield. Further, most of the area on the computer chip will be occupied by memory circuitry instead of processor and control circuitry.
- This presents several problems. As mentioned above, one problem is that the yield of computer chips in a manufacturing run decreases as their size increases. As is well-known in the art, several computer chips are fabricated from a single large wafer in a run. The individual computer chips carried by the wafer are typically referred to as die. Once the computer chips are fabricated, the die in the wafer are diced to provide separate chips. A wafer, however, has defects distributed throughout it surface which can negatively impact the operation of the computer chips. If the computer chip is larger in size, then it is more likely to include a defect from the wafer and if the computer chip is smaller in size, then it is less likely to include a defect from the wafer. Hence, smaller computer chips are less likely to be defective. Further, if the computer chip is smaller in size, then more of them can be fabricated from a single wafer, which also decreases costs. Hence, smaller computer chips increase the yield and decrease the costs.
- Another problem is that it is typically desirable to increase the number of devices included in the processor and control circuitry so that the processor can operate faster and perform more complicated operations. It is desirable for computer chips to be fast so they can process more data in a given amount of time. The speed of operation of a computer chip is typically measured in the number of instructions per second it can perform.
- Computer chips can be made to process more data in a given amount of time in several ways. In one way, the computer chip can include devices which are smaller, but this requires advances in lithography and increasingly expensive manufacturing equipment. As discussed above, they can also be made faster by decreasing the time it takes to perform certain tasks, such as storing or retrieving information to and from memory or other peripherals and subsystems.
- Computer chips can also be made faster by increasing the number of devices included therein so that more information can be processed in a given period of time. For example, if one processor operates on 32-bit data, then another processor that operates on 64-bit data can process information twice as fast because it can perform more instructions per second. However, the 64-bit processor will need more devices since there are more bits to process at a given time. Hence, if most of the area on the computer chip is occupied by memory cells, then there is less area for the processor and control circuitry to process data with a higher number of bits. The total area of the computer chip can be increased, but as discussed above, this decreases the yield and increases the cost.
- Accordingly, it is highly desirable to provide new structures and methods for fabricating computer chips which operate faster and cost effective to fabricate.
- The present invention provides circuitry which includes first and second circuits and an interconnect region. A first interconnect is included in the interconnect region. The first interconnect extends above and between the first and second circuits to provide communication therebetween. A third circuit is positioned on the interconnect region and a second interconnect is included in the interconnect region. The second interconnect extends between the third circuit and at least one of the first and second circuits to provide communication therebetween.
- The present invention also provides circuitry which includes control and digital circuitry positioned on a substrate. An interconnect region is positioned on surfaces of the control and digital circuitry to provide communication therebetween. Memory circuitry is positioned on the interconnect region so that the interconnect region provides communication between the memory circuitry and the control circuitry.
- The present invention further provides circuitry which includes a substrate and first and second processor circuits carried by the substrate. A control circuit is carried by the substrate and positioned near the first and second processor circuits. An interconnect region is carried by and extends from the substrate. The interconnect region allows the first and second processor circuits to communicate with each other and the control circuit. A memory circuit is positioned on the interconnect region so that the memory circuit is electrically coupled to the control circuit through the interconnect region.
- These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.
-
FIG. 1 is a simplified top view of a computer chip, in accordance with the present invention, with one processor positioned near a control circuit, the sectional view being taken along a cut line 1-1′ ofFIG. 2 . -
FIG. 2 is a simplified sectional view of the computer chip ofFIG. 1 taken along a cut-line 2-2′ ofFIG. 1 . -
FIG. 3 a is a perspective view of a computer chip with memory devices positioned on the same substrate as the processor and control circuits. -
FIGS. 3 b-3 d are simplified perspective views of different computer chips in which the memory circuit is positioned above the processor and/or control circuits in accordance with the present invention. -
FIG. 4 is a more detailed view of a memory circuit shown inFIGS. 2 and 6 . -
FIG. 5 is a simplified top view of a computer chip, in accordance with the present invention, with multiple processors separated by a control circuit, the sectional view being taken along a cut line 5-5′ ofFIG. 6 . -
FIG. 6 is a simplified sectional view of the computer chip ofFIG. 5 taken along a cut-line 6-6′ ofFIG. 5 . -
FIG. 7 is a simplified top view of another embodiment of a computer chip, in accordance with the invention, with multiple processor circuits and multiple control circuits. -
FIG. 8 is a simplified top view of another embodiment of a computer chip, in accordance with the present invention, with multiple processor circuits surrounded by a control circuit. -
FIG. 9 is a simplified top view of another embodiment of a computer chip, in accordance with the present invention, with multiple processors partially surrounded by multiple control circuits. -
FIGS. 1 and 2 show simplified top and cross sectional views of acomputer chip 100 which includes circuitry, in accordance with the present invention.FIG. 1 is a top view taken along a cut-line 1-1′ ofFIG. 2 andFIG. 2 is a sectional view taken along a cut-line 2-2′ ofFIG. 1 . It should be noted that in the following figures, like reference characters indicate corresponding elements throughout the several views. - In this embodiment,
computer chip 100 includes processor and control circuits which are carried by a substrate and coupled together so that signals can flow between them.Computer chip 100 also includes a memory circuit positioned above the processor and control circuits. The memory circuit is spaced apart from the processor and control circuits by an interconnect region. The memory circuit is also coupled to the control circuit through the interconnect region so that signals can flow therebetween. In this way, the control circuit can receive output signals from the processor circuit and, in response, provide signals to and receive signals from the memory circuit. In response, the control circuit provides input signals to the processor circuit. It should be noted that a memory circuit is discussed here and throughout the disclosure for illustrative purposes and that, in other embodiments, the memory circuit can be replaced with other circuitry which can be fabricated in the same or a similar manner. - A processor circuit typically executes a series of machine instructions to process data. It usually includes an ALU (Arithmetic/Logic Unit) to perform mathematical operations like addition, subtraction, multiplication and division. Modern processor circuits typically include floating point processors that can perform extremely sophisticated operations on large floating point numbers. A processor circuit provide commands to the control circuit to move data from one memory location to another in the memory circuit. A processor circuit can also make decisions and jump to a new set of instructions based on those decisions.
- One advantage of
computer chip 100 is that the memory circuit is positioned above the control and processor circuits which is desirable since the memory circuit typically occupies much more area than the control and processor circuits. In some examples of a typical computer chip where the processor, control, and memory circuits are positioned on the same substrate, the memory circuit can occupy 50% or more of the total area of the chip. An example of this is shown inFIG. 3 a, which is a perspective view of acomputer chip 110 with amemory circuit 221 positioned on thesame substrate 111 as processor andcontrol circuits processor circuit 144 andcontrol circuit 143 occupy 30% and 20%, respectively, of the total area of the chip, andmemory circuit 221 occupies 50%. It should be noted, however, that they can occupy different amounts of area than that shown here. -
FIGS. 3 b-3 d are simplified perspective views ofcomputer chips computer chip 100. InFIGS. 3 b-3 d,computer chips substrate 142 which carriesprocessor circuit 144 andcontrol circuit 143.Chip 100 also includesmemory circuit 121 positioned above and separated fromsubstrate 142 by an interconnect region, which is not shown for simplicity. In the example shown inFIG. 3 b,processor circuit 144 andcontrol circuit 143 include more electronic devices and occupy twice the area than they do incomputer chip 110 shown inFIG. 3 a. This may be desirable so thatcomputer chip 114 can operate with data represented by a higher number of bits. This may also be desired so thatchip 114 can perform more complicated operations, such as more accurate computations or pipelining. Further,memory circuit 121 also occupies twice the area so that it can store more information, which speeds up the operation ofcomputer chip 114. - In
FIG. 3 c, the area ofcomputer chip 115 is half the size ofcomputer chip 110 shown inFIG. 3 a becauseprocessor 144 andcontrol circuit 143 are the same size as that shown inFIG. 3 a.Memory circuit 121 is positioned abovesubstrate 142 and extends over the same area asprocessor circuit 144 andcontrol circuit 143 combined. In this way,computer chip 115 inFIG. 3 c occupies half the area aschip 110 and, consequently, is less expensive to fabricate because it has a higher yield and more chips can be fabricated on a single wafer. - In
FIG. 3 d, the area ofcomputer chip 116 is the same ascomputer chip 110 shown inFIG. 3 a, butprocessor 144 andcontrol circuit 143 are the same size as that shown inFIG. 3 b.Memory circuit 121 is positioned abovesubstrate 142 and extends over the same area ascontrol circuit 143, so its size is less than that shown inFIG. 3 b. This may be useful in applications where a lot of memory is not needed. It should be noted thatmemory circuit 121 can also be positioned overprocessor circuit 142 or it can extend over both processor andcontrol circuits - It should also be noted that in some embodiments, the processor in the computer chip discussed herein can address memory devices on a separate chip positioned outside the computer chip. Further, in some embodiments, the computer chip can include embedded memory cells on the same surface as the control and processor circuits, in addition to the memory devices positioned above them. These memory devices can include a cache memory and/or ROM devices. For example the ROM devices can operate as a BIOS (Basic Input/Output System) for the computer system.
- Another advantage of
computer chip 100 is that the memory circuit is positioned closer to the control and processor circuits so that signals can flow therebetween in less time. This speed up operation ofcomputer chip 100 because the access time is reduced andcomputer chip 100 is idle for fewer cycle times. Still another advantage ofcircuit 100 is that the control and processor circuits are fabricated with a different mask set than the memory circuit. Hence, the masks are less complicated and less expensive to make. A further advantage is that the memory devices are fabricated from blanket semiconductor layers after they have been bonded to the interconnect region. Hence, the memory devices do not need to be aligned with the processor and/or control circuitry, which is a complicated and expensive process. - In this embodiment,
computer chip 100 includescontrol circuit 143 andprocessor circuit 144 carried by substrate 142 (FIG. 2 ).Computer chip 100 also includesmemory circuit 121 spaced apart fromprocessor circuit 144 andcontrol circuit 143 by aninterconnect region 131. In this way,memory circuit 121 is positioned aboveprocessor circuit 144 andcontrol circuit 143 as discussed above.Memory circuit 121 is coupled to controlcircuit 143 throughinterconnect region 131 so that signals can flow therebetween. - In this embodiment,
substrate 142 includes silicon, although it can include other materials which can support the subsequent structures positioned thereon. Other suitable substrate materials include gallium arsenide, indium phosphide, and silicon carbide, among others. It should be noted thatsubstrate 142 can have portions doped n-type or p-type and some portions ofsubstrate 142 can even be undoped. The preferred material forsubstrate 142 in this invention is single crystalline material which can have defects, but is generally better material quality compared to amorphous or polycrystalline material. - In this example,
control circuit 143 andprocessor circuit 144 include digital circuitry known in the art. However, the digital circuitry is not shown in FIGS. 1 or 2 for simplicity and ease of discussion. The digital circuitry can include electronic devices, such as transistors, which extend intosubstrate 142 and/or out ofsubstrate 142 through asurface 142 a (FIG. 2 ).Processor circuit 144 can operate in many different ways. For example,processor circuit 144 can operate as a central processing unit, such as those commonly found in a computer chip, a signal processor, such as those commonly found in communication systems, or a microcontroller. In other examples,processor circuit 144 can include analog circuitry, such as amplifiers and/or converters, for analog-to-digital converter applications.Control circuit 143 includes circuitry typically found in periphery logic circuits which read, write, and erase semiconductor memory devices. This circuitry typically includes a sense amplifier, column selector, and/or a row selector which are used to communicate with memory devices, as will be discussed in more detail below. - As shown in
FIG. 2 ,interconnect region 131 is positioned onsurface 142 a ofsubstrate 142.Interconnect region 131 and regions subsequently positioned thereon are not shown inFIG. 1 for simplicity. Here,interconnect region 131 includes an interlayer dielectric region (ILD) 133 with interconnects extending betweensurface 142 a and asurface 131 a ofregion 131 so that signals can flow therethrough. Each interconnect typically includes one ormore interconnect lines 135 and/or one ormore vias 134.Interconnect region 131 also typically includes one ormore contacts 132 coupled to the electronic devices included incontrol circuit 143 orprocessor circuit 144. - In accordance with the invention, the interconnects included in
interconnect region 131 can be formed so that signals, such as signal Sa, can flow between the various devices included inprocessor circuit 144. The interconnects can also be coupled together so that signals can flow betweencontrol circuit 143 andprocessor circuit 144. The interconnects, vias, and contacts can include conductive materials known in the art, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or a doped semiconductor, among others. - For example, signal Sa can flow between
processor circuit 144 andcontrol circuit 143 through aninterconnect 138 a included ininterconnect region 131, as shown inFIG. 2 . Interconnect 138 a includescontacts interconnect line 135 a. Ends ofcontacts processor circuit 144 andcontrol circuit 143, respectively, and extend upwardly therefromsurface 142 a.Interconnect line 135 a extends between opposed ends ofcontacts control circuit 143 is positioned nearprocessor circuit 144 so that the distance traveled by signals Sa flowing therebetween is reduced. - In this embodiment, a
memory circuit 121 is positioned oninterconnect region 131 and bonded to surface 131 a. The bonding can be done in many different ways. For example, the bonding can be done byheating bonding surface 131 a andcoupling memory circuit 121 thereto. Sincememory circuit 121 is bonded to interconnectregion 131 instead of deposited thereon, it can include better quality semiconductor material. One reason the material is better quality is because it is more crystalline. It is more crystalline than polycrystalline material which is typically deposited on dielectric regions when wafer bonding is not used. More information about wafer bonding can be found in co-pending U.S. patent applications titled “SEMICONDUCTOR LAYER STRUCTURE AND METHOD OF MAKING THE SAME,” “SEMICONDUCTOR BONDING AND LAYER TRANSFER METHOD,” and “WAFER BONDING METHOD” filed on an even date herewith by the same inventor and incorporated herein by reference. -
Memory circuit 121 includes abit line 120 a positioned onsurface 131 a. Adielectric region 123 is positioned onsurface 131 a andbit line 120 a. Bit line vias 124 a extend upwardly therefrombit line 120 a and throughdielectric region 123. The number of bit line vias 124 a depends on the number of devices it is desired to form inmemory circuit 121. Each bit line via 124 a is coupled to anelectronic device 124. -
Electronic device 124 is typically a transistor or a memory device, although it can include other devices. The transistor can be a metal oxide semiconductor field effect transistor (MOSFET) and the memory device can be a negative differential resistance (NDR) static random access memory (SRAM) cell. An NDR SRAM includes a layer structure that operates as a transistor and a layer structure that operates as a thyristor. The transistor and thyristor are coupled together to operate as the NDR SRAM cell. More information regarding the NDR SRAM cell can be found in co-pending U.S. patent application titled “SEMICONDUCTOR MEMORY DEVICE” filed on the same date herewith by the same inventor and incorporated herein by reference. - A reference line via 124 b is coupled to the opposite end of each
device 124. Each reference line via 124 b extends upwardly from itscorresponding device 124 where it connects to areference line 120 b. In this way, eachdevice 124 is coupled between bit line and reference lines vias 124 a and 124 b. It should be noted, however, that in other embodiments,line 120 a can be used as a reference line andline 120 b can be used as a bit line. Adielectric region 148 is positioned ondielectric region 123 andreference line 120 b. -
Memory circuit 121 andinterconnect region 131 include interconnects so that signals can flow betweencontrol circuit 143 andbit line 120 a andreference line 120 b. In this particular example, areference interconnect 136 extends throughregions circuit 143 and the opposite end is coupled toreference line 120 b. Similarly, abit interconnect 137 extends throughregion 133 so that one end is coupled to controlcircuit 143 and the other end is coupled tobit line 120 a. Hence,control circuit 143 can provide a bit signal tobit line 120 a throughinterconnect 137 and a reference signal toreference line 120 b throughinterconnect 136. In this way,control circuit 143 can communicate with the devices included indevice structure 124. In other examples, thereference line 120 b can be connected to an outside contact (not shown) which provides a reference voltage or current from outside of thecircuit 100. - In operation, various signals, such as signal Sa, can flow between
processor circuit 144 andcontrol circuit 143. In response,control circuit 143 provides signals to and receives signals frommemory circuit 121 throughinterconnects memory circuit 121.Control circuit 143 then provides input signals toprocessor circuit 144. The input signals can be data values stored bymemory circuit 121 thatprocessor circuit 144 desires to process. -
FIG. 4 shows a more detailed sectional view ofmemory circuit 121. In this particular example, eachelectronic device 124 is a single transistor capacitorless dynamic random access memory (DRAM) device, althoughdevices 124 can include other devices, such as a SONOS (Semiconductor Oxide Nitride Oxide Semiconductor) type nonvolatile memory device with a ONO (Oxide Nitride Oxide) dielectric. Here,device 124 includes an n+pn− stack of layers, although it can include other layer structures, such as a npn stack, a p+np+ stack, or a pnp stack. The n+pn+ stack includes an n+-type dopedregion 125 a positioned on bit line via 124 a and a p-type dopedregion 125 b positioned onregion 125 b. An n+-type dopedregion 125 c is positioned onregion 125 c so that it is coupled betweenregion 125 b and reference line via 124 b. Aninsulating region 125 d is positioned around the outer periphery of the stack ofregions control terminal 125 e is positioned around the outer periphery of insulatingregion 125 d. - In this way, the conductivity of
regions control circuit 143 through aword interconnect 139.Word interconnect 139 is coupled betweencontrol circuit 143 and control terminal 125 e and extends throughdielectric regions interconnects Interconnect 139,insulator region 125 d, and control terminal 125 e are not shown inFIG. 2 for simplicity. -
FIGS. 5 and 6 show simplified top and sectional views of acomputer chip 101 in accordance with the present invention.FIG. 5 is a top view taken along a cut-line 5-5′ ofFIG. 6 andFIG. 6 is a sectional view taken along a cut-line 6-6′ ofFIG. 5 . In this embodiment,chip 101 includes multiple processors which can communicate with the control circuit and the memory circuit as discussed above in conjunction withFIGS. 1-2 , 3 b-3 d, and 4. In this embodiment, however, the processors can also communicate with each other using an interface circuit (not shown) which provides better data flow between processors. The data flow is better because it can happen faster and with less noise so there are fewer errors in the signal. -
Computer chip 102 includescontrol circuit 143 andprocessors 144 a-144 d which are carried by substrate 142 (FIG. 6 ). Here,control circuit 143 is positioned in a region that is cross-shaped from a top view (FIG. 5 ) so that it extends betweenprocessors 144 a-144 d. In this way, the processors are separated from each other bycontrol circuit 143. It should be noted that in this example,processors 144 a-144 d can be the same or similar toprocessor circuit 144 discussed above in conjunction withFIGS. 1-2 , 3 b-3 d, and 4.Interconnect region 131 is positioned onsurface 142 a ofsubstrate 142 so that it coverscontrol circuit 143 as well asprocessors 144 a-144 d. However, in other embodiments,interconnect region 131 can be positioned so that it covers only a portion oflogic circuit 143,processor circuit 144 a,processor circuit 144 b,processor circuit 144 c, and/orprocessor circuit 144 d. - In
chip 101, various signals can flow betweenprocessors 144 a-144 d andcontrol circuit 143. For example, signal Sa, Sb, Sc, and Sd can flow betweenprocessor circuit control circuit 143, as shown inFIG. 5 . Signals can also flow betweenprocessors 144 a-144 d without flowing throughcontrol circuit 143. For example, signals Sab, Sac, Sbd, and Scd can flow betweenprocessors 144 a-144 b, 144 a-144 c, 144 b-144 d, and 144 c-144 d, respectively, as shown inFIG. 5 . Signals Sab, Sac, Sbd, and Scd can flow through interconnects which extend throughinterconnect region 131. The interconnects can be similar to interconnect 138, but are not shown for simplicity. - In a particular example, signal Sa can flow between
processor circuit 144 a andcontrol circuit 143 through aninterconnect 138 a, as shown inFIG. 6 . Interconnect 138 a includescontacts interconnect line 135 a, as described above in conjunction withFIG. 2 . Similarly, signal Sb can flow betweenprocessor circuit 144 b andcontrol circuit 143 through an interconnect 138 b. Interconnect 138 b includescontacts interconnect line 135 b. Ends ofcontacts processor circuit 144 b andcontrol circuit 143, respectively, and extend upwardly therefrom.Interconnect line 135 b extends between opposed ends ofcontacts processor circuit 144 b andcontrol circuit 143. Signals Sc and Sd can flow betweencontrol circuit 143 andcorresponding processors interconnect region 131. - One advantage of
chip 101 is that the distance betweencontrol circuit 143 andprocessors 144 a-144 d is reduced so that they can communicate with each other faster. This increases the speed ofcomputer chip 100. Another advantage is that the design ofchip 101 is convenient because eachprocessor circuit 144 a-144 d can have the same or a similar design which simplifies its fabrication. -
FIG. 7 is a top view of acomputer chip 102 in accordance with the present invention.Chip 102 includesprocessors 144 a-144 d positioned near each other in a manner similar to that ofchip 101 shown inFIG. 5 . Here, however, the control circuit includesseparate control circuits 143 a-143 d. In this example,processors control circuit 143 a,processors control circuit 143 b,processors control circuit 143 c, andprocessors control circuit 143 d. It should be noted that eachcontrol circuit 143 a-143 d can be the same or similar tocontrol circuit 143 shown inFIG. 4 . - Here, signals Sa1 and Sb1 flow between
control circuit 143 a andprocessors control circuit 143 c andprocessors control circuit 143 b andprocessors control circuit 143 d andprocessors - Signals Sa1, Sb1, Sa2, Sc1, Sb2, Sd1, Sc2, and Sd2 flow between corresponding control circuits and processors through interconnects, similar to
interconnects FIG. 6 . Signals Sab, Sac, Sbd, Sad, Sbc, and Scd flow betweencorresponding processors 144 a-144 d through conductive lines which extend throughsubstrate 142 or on itssurface 142 a. However, these conductive lines are not shown for simplicity. One advantage ofchip 102 is that signals Sab, Sac, Sbd, Scd, Sad, and Sbc, can flowtherebetween processors 144 a-144 d faster so thatchip 102 can operate faster. One reason the signals can flow faster is because the interconnects are shorter so the distance of travel is shorter and their capacitance is smaller. -
FIG. 8 is a top view of acomputer chip 103 in accordance with the present invention.Chip 103 includesprocessors 144 a-144 d positioned adjacent to each other. However, in this example,control circuit 143 extends around an outer periphery ofprocessors 144 a-144 d. In this way,processors 144 a-144 d are surrounded bycontrol circuit 143. Signals Sa, Sb, Sc, and Sd can flow betweencontrol circuit 143 andcorresponding processors 144 a-144 d through interconnects, similar tointerconnects 138 a and 138 b, as described above, in conjunction withFIG. 6 . Similarly,processors 144 a-144 d are coupled together so that signals Sab, Sac, Sbd, Sad, Sbc, and Scd can flow therebetween as described above in conjunction withFIG. 7 above. -
FIG. 9 is a top view of acomputer chip 104 in accordance with the present invention.Chip 104 includesprocessors 144 a-144 d positioned near each other in a manner similar to that ofchip 103 shown inFIG. 8 . Here, however,control circuit 143 a extends along an outer periphery ofprocessors control circuit 143 b extends along an outer periphery ofprocessors Control circuit 143 c extends along an outer periphery ofprocessors control circuit 143 d extends along an outer periphery ofprocessors - Signals Sa1, Sa2, Sb1, Sb2, Sc1, Sc2, Sd1, and Sd2 can flow between
corresponding control circuits 143 a-143 d andcorresponding processors 144 a-144 d through interconnects, similar tointerconnects FIG. 6 . Similarly,processors 144 a-144 d are coupled together so that signals Sab, Sac, Sbd, Sad, Sbc, and Scd can flow therebetween as described above in conjunction withFIG. 6 above. - The present invention is described above with reference to preferred embodiments. However, those skilled in the art will recognize that changes and modifications may be made in the described embodiments without departing from the nature and scope of the present invention. Various further changes and modifications will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof.
- Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is:
Claims (20)
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US11/873,719 US20080048327A1 (en) | 2004-06-21 | 2007-10-17 | Electronic circuit with embedded memory |
US12/040,642 US7800199B2 (en) | 2003-06-24 | 2008-02-29 | Semiconductor circuit |
US12/397,309 US7863748B2 (en) | 2003-06-24 | 2009-03-03 | Semiconductor circuit and method of fabricating the same |
US12/470,344 US8058142B2 (en) | 1996-11-04 | 2009-05-21 | Bonded semiconductor structure and method of making the same |
US12/475,294 US7799675B2 (en) | 2003-06-24 | 2009-05-29 | Bonded semiconductor structure and method of fabricating the same |
US12/581,722 US8471263B2 (en) | 2003-06-24 | 2009-10-19 | Information storage system which includes a bonded semiconductor structure |
US12/618,542 US7867822B2 (en) | 2003-06-24 | 2009-11-13 | Semiconductor memory device |
US12/637,559 US20100133695A1 (en) | 2003-01-12 | 2009-12-14 | Electronic circuit with embedded memory |
US12/731,087 US20100190334A1 (en) | 2003-06-24 | 2010-03-24 | Three-dimensional semiconductor structure and method of manufacturing the same |
US12/874,866 US8071438B2 (en) | 2003-06-24 | 2010-09-02 | Semiconductor circuit |
US12/881,628 US20110001172A1 (en) | 2005-03-29 | 2010-09-14 | Three-dimensional integrated circuit structure |
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US10/873,969 US7052941B2 (en) | 2003-06-24 | 2004-06-21 | Method for making a three-dimensional integrated circuit structure |
US11/092,521 US7633162B2 (en) | 2004-06-21 | 2005-03-29 | Electronic circuit with embedded memory |
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US11/606,523 Continuation-In-Part US7888764B2 (en) | 1996-11-04 | 2006-11-30 | Three-dimensional integrated circuit structure |
US11/873,851 Continuation-In-Part US7718508B2 (en) | 1996-11-04 | 2007-10-17 | Semiconductor bonding and layer transfer method |
US11/873,769 Continuation-In-Part US20080032463A1 (en) | 1996-11-04 | 2007-10-17 | Semiconductor memory device |
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US11/873,851 Continuation-In-Part US7718508B2 (en) | 1996-11-04 | 2007-10-17 | Semiconductor bonding and layer transfer method |
US11/873,769 Continuation-In-Part US20080032463A1 (en) | 1996-11-04 | 2007-10-17 | Semiconductor memory device |
US12/040,642 Continuation-In-Part US7800199B2 (en) | 1996-11-04 | 2008-02-29 | Semiconductor circuit |
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US11/873,719 Abandoned US20080048327A1 (en) | 1996-11-04 | 2007-10-17 | Electronic circuit with embedded memory |
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