US20080048729A1 - Comparator Circuit and Method for Operating a Comparator Circuit - Google Patents
Comparator Circuit and Method for Operating a Comparator Circuit Download PDFInfo
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- US20080048729A1 US20080048729A1 US11/782,910 US78291007A US2008048729A1 US 20080048729 A1 US20080048729 A1 US 20080048729A1 US 78291007 A US78291007 A US 78291007A US 2008048729 A1 US2008048729 A1 US 2008048729A1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
- G03F7/70516—Calibration of components of the microlithographic apparatus, e.g. light sources, addressable masks or detectors
Definitions
- the invention relates to a comparator circuit and a method for operating a comparator circuit according to the preambles of the independent claims.
- ADC analog-to-digital converters
- a typical successive approximation ADC comprises a reference voltage generator, a comparator and a successive approximation register.
- a general description of this kind of ADCs can be found for example in Allen/Holberg: “CMOS Analog Circuit Design”, Oxford University Press 2002, 668-672.
- a single-rail comparator supports a limited input voltage range only. Normally asymmetric input range, starting at some value and ranging to one of the power supply rails.
- a rail-to-rail comparator supports full input voltage swing, starting at ground and ending at the supply voltage.
- the algorithm approach does not lead to highest speeds possible in state-of-the-art technologies, this kind of ADCs offers high resolution at low area costs. Additionally, the overall power consumption is low, especially compared to so called flash analog-to-digital converters. Besides other factors the overall conversion accuracy is mainly influenced by the comparator. It is known that offset-errors and gain-errors affect the comparator accuracy. Additionally, the comparator gain is a function of the common mode input voltage which results in limiting the useable input voltage and, further, an available input voltage swing is limited by the input buffer/sample-and-hold circuit, which is usually used at the comparator input.
- a pipelined ADC architecture which achieves high resolution at high conversion rates is suggested by Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak and Bang-Sup Song, “A 10-b 20-Msamples/s Low-Power CMOS ADC”, IEEE Journal of Solid-State Circuits, Vol. 30, No. 5, pages 514-521, May 1995.
- a latch-type comparator in nMOS technology with an asymmetric output load is disclosed.
- a time-interleaved ADC combining two three-step flash converters is presented by Michael K. Mayes, Sing W. Chin, Lee L. Stoian, “A Low-Power 1 MHz, 25 mW 12-Bit Time-Interleaved Analog-to-Digital Converter”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 2, pages 169-178, February 1996.
- a rail-to-rail comparator is disclosed in D. Gardino and F. Maloberti “High Resolution Rail-to-rail ADC In CMOS Digital Technology”, Proc. of the ISCAS 1999, Vol. 2, 339-342.
- This comparator design also needs a rail-to-rail input stage. But as already mentioned above, the comparator is one of the main sources of inaccuracy in such a circuitry. Very low or very high input voltages close to the power supply rail voltages show a very low gain and yield high inaccuracy. However, a rail-to-rail comparator or operational amplifier design introduces additional offset and error sources. Full rail-to-rail operation can still not be achieved.
- a comparator circuit for comparing a first voltage signal with a second voltage signal, the circuit comprising a first comparator and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition.
- the gain of each comparator can be chosen independently from each other.
- Each comparator can be optimized for a different voltage regime, for example for high input voltages or low input voltages. Therefore, each comparator can work at its optimum.
- the selecting unit advantageously selects one of the comparators according to its optimum voltage regime. Due to this digital selection of that one comparator working in its optimum range, the useable input voltage can be extended from single rail to a rail-to-rail, although each individual comparator can be a single-rail comparator. Due to the digital selection of the proper comparator, introduction of additional offsets and errors can be avoided, and mismatch compared to analog arrangements is avoided, where distortions/mismatch can occur. A degradation of operation speed can be prevented when using the inventive comparator circuit.
- a rail-to rail comparator circuit is provided, although single-rail comparators, preferably performance-optimized single-rail comparators, can be used.
- a self-calibration comparator mode of operation is possible, providing a still more exact calibration.
- the invention can be applied to any circuit which has a limited operating voltage range, e.g. a reference voltage generator.
- a reference voltage generator e.g. a reference voltage generator
- the comparator circuit can be preferably used in a successive approximation analog-to-digital converter and the method can be favorably used for converting analog signals to digital signals.
- the selection condition is the voltage signal being above or below a threshold voltage.
- the threshold voltage can be a constant or can be variable.
- the selection unit selects one of the comparators if the voltage level is above the threshold voltage and the other one of the comparators if the voltage level is below the threshold voltage. This yields a high gain, high accuracy comparator circuit.
- this decision is made as a first step of the conversion procedure. Once the most accurate one of the comparators has been selected selected, the conversion can be continued with the selected comparator. Using a successive approximation type of analog-to-digital converter, the selection of the comparator can be included in the first (most significant bit) conversion step, when only a low comparator accuracy is needed.
- one of the comparators is a pMOS (p-channel Metal-Oxide Semiconductor field effect) transistor based device adapted for a first input voltage range and the other one of the comparators is an nMOS (n-channel Metal-Oxide Semiconductor field effect) transistor based device adapted for a second input voltage range.
- the pMOS-transistor based comparator works best at low input voltage levels, where its gain is high, whereas the gain of the nMOS-based comparator is high at high input voltage levels, yielding the comparator working at its best at high input voltage levels.
- At an input voltage level in the middle of the supply voltage both types of comparators show comparable gains and accuracies.
- the selection unit selects the nMOS-based comparator if the voltage level is above the threshold voltage and the pMOS-based comparator is selected if the voltage level is below the threshold voltage. This yields a high gain, high accuracy comparator circuit.
- the selection unit comprises a selection output port, wherein the selection unit connects an output port either of the first comparator or the second comparator to the selection output port, depending on the selection of the selection unit.
- the output signal of the selected comparator can be processed further, for example in a preferred ADC or a preferred rail-to-rail comparator building block.
- the reference voltage is defined by the voltage signals which are being compared by the comparators.
- this is the case for applications in analog-to-digital converters.
- the reference voltage applied to the comparators is altered step by step during determining the most significant bit down to the least significant bit.
- such a successive approximation procedure is well known in the art.
- means for adjusting the reference voltage depending on the voltage signals which are being compared by the comparators are coupled to the selection unit. This is preferred in an ADC using the successive approximation operation mode.
- the means comprises a voltage divider and a third comparator with an input port for a threshold voltage and an output port for a digital decision signal.
- the third comparator comprises an input port for a voltage signal which is also applied to one of the comparators.
- the third comparator is working as a voltage plane detector.
- the third comparator can be a single-rail comparator of simple design.
- the selection unit comprises a multiplexor, the output port of which is selectably connectable to one of the comparator output ports via the selection unit.
- a multiplexor By using a multiplexor, it is not necessary to choose a special kind of comparator type. Additionally or alternatively, it is possible to switch off that one comparator which has not been selected by the selection unit. In this case it may be appropriate to replace the multiplexor by a NAND (Not AND) or a NOR (Not OR) gate. Switching off the comparator means that a strobe signal is not generated in the respective comparator and/or the supply voltage is disconnected or the like. For this purpose it is advisable to choose a comparator with appropriate properties which are well known to skilled persons.
- the comparators are assigned to the comparator stage of an analog-to-digital converter, where, preferably, a sample-and-hold unit is assigned to each of the two comparators.
- At least one of the sample-and-hold units is equipped with a first and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition.
- the analog-to-digital converter is of a successive-approximation type.
- At least one of the first and second comparators can be a single-rail-type unit. A mismatch as known from analog rail-to-rail solutions as well as a speed degradation can be avoided.
- At least one of the first and second comparators is a latch-type device.
- the latch type device is equipped with a dummy inverter yielding a nearly symmetric output.
- a method for operating a comparator circuit wherein a first voltage signal is compared with a second voltage signal, and either a first comparator or a second comparator is selected depending on a selection condition.
- the selection condition is the voltage signal being above or below a threshold voltage.
- the most accurate one of the two comparators can be selected depending on the threshold voltage. Being a digital selection, distortions, inaccuracies as well as speed degradation can be avoided.
- one of the two comparators is preferably adapted for a first input voltage range and the other is adapted for a second input voltage range essentially different from the first input voltage range.
- the threshold voltage and/or a reference voltage can be defined by the voltage signals which are being compared by the comparators.
- a preferential step is to select an nMOS-based comparator if the voltage level is above the threshold voltage and a pMOS-based comparator if the voltage level is below the threshold voltage.
- Each comparator can work in an input voltage range where its gain is high, yielding a high accuracy voltage comparison.
- An analog-to-digital conversion can be made, wherein in or during a first step one of the comparators is chosen depending on the threshold voltage as selection decision.
- FIG. 1 a first preferred embodiment in the form of a rail-to-rail comparator building block
- FIG. 2 a second preferred embodiment in the form of an analog-to-digital converter
- FIG. 3 a,b a preferred pMOS based comparator (a) and a preferred nMOS based comparator (b);
- FIG. 4 a flow diagram of a successive-approximation algorithm applied on the preferred analog-to-digital converter of FIG. 2 .
- a preferred embodiment of the invention is depicted in FIG. 1 .
- a comparator circuit comprises a first comparator 20 and a second comparator 30 and a selection unit 60 .
- the selection unit 60 is indicated with a dotted line.
- the comparator circuit represents a high accuracy rail-to-rail comparator building block.
- An input voltage signal Vin_p is fed into an input port 22 and an input voltage signal Vin_n is fed into an input port 24 of the first comparator 20 .
- An output port 26 of the first comparator 20 feeds an output signal to the selection device 60 .
- An input voltage signal Vin_p is fed into an input port 32 and an input voltage signal Vin_n is fed into an input port 34 of the second comparator 30 .
- An output port 36 of the second comparator 30 feeds an output signal to the selection unit 60 .
- the first comparator 20 is equipped with pMOS transistors and therefore adapted for low input voltage levels and the second comparator 30 is equipped with nMOS transistors and therefore adapted for high input voltage levels. Details of the implementations are described in more detail in FIG. 3 a and 3 b.
- a voltage source is coupled to the selection unit 60 which, for example, comprises a simple voltage divider 120 with a first resistor unit 122 and a second resistor unit 124 .
- the center tap of the voltage divider 120 is connected to an input port 104 of a third comparator 100 .
- Another input port 102 of the third comparator 100 is connected to one of the input voltage signals Vin_p or Vin_n fed to the two comparators 20 , 30 . In this example, the input port 102 is connected to the positive Vin_p voltage signal.
- the third comparator 100 can be a low accuracy component of a simpler design than the first and second comparators 20 , 30 the third comparator 30 feeds a digital selection signal Vs from its output port 106 to a select input port 118 of a multiplexor 110 which assigned to the selection unit 60 .
- the output ports 26 , 36 of the first and second comparators 20 , 30 are connected to input ports 112 , 114 of the multiplexor 110 . Depending on a selection condition one of the input ports 112 , 114 and thus one of the output ports 26 , 36 of the first and second comparators 20 , 30 are connected through to an output port 116 of the multiplexor 110 .
- the selection condition is a threshold voltage signal.
- the selection unit 60 selects one of the comparators 20 , 30 depending on the voltage signal Vin_n, Vin_p being above or below a threshold voltage V 0 .
- the third comparator 100 feeds the appropriate decision signal Vs to the select port 118 of the multiplexor 110 .
- the selection unit 60 selects the very comparator 20 or 30 with the best gain for the actual input voltage Vin_p, Vin_n in a digital way.
- a comparator circuit comprises a first comparator 20 and a second comparator 30 and a selection unit 60 .
- the selection unit 60 is indicated with a dotted line.
- An input buffer stage 40 with an input port 42 and an output port 44 is assigned to the first comparator 20 and an input buffer stage 50 with an input port 52 and an output port 54 is assigned to the second comparator 30 .
- An input voltage signal Vin is fed through the buffer 40 into an input port 22 and an input voltage signal Vref is fed into an input port 24 of the first comparator 20 .
- An output port 26 of the first comparator 20 feeds an output signal to the selection device 60 .
- An input voltage signal Vin is fed through the buffer 50 into an input port 32 and an input voltage signal Vref is fed into an input port 34 of the second comparator 30 .
- An output port 36 of the second comparator 30 feeds an output signal to the selection unit 60 .
- the first comparator 20 is equipped with pMOS transistors and therefore adapted for low input voltage levels and the second comparator 30 is equipped with nMOS transistors and therefore adapted for high input voltage levels. Details of the implementations are described in more detail in FIG. 3 a and 3 b.
- a voltage source 70 is coupled to the selection unit 60 , yielding a reference voltage Vref, which can be biased by a digital control unit 62 .
- the reference voltage Vref corresponds to a threshold voltage V 0 equal to Vdd/2, wherein V 0 represents the selection condition.
- the comparator 20 or 30 selected in the first step is used for the following conversions steps.
- the output port 26 of the first comparator 20 and the output port 36 of the second comparator 30 are connected to the selection unit 60 via input ports 64 a and 64 b , respectively. Depending on the selection condition either the output port 26 or the output port 36 is connected directly or indirectly to an output port 66 of the selection unit 60 .
- V 0 is at Vdd/2 and equals Vref, i.e. both comparators 20 , 30 work at a high gain operating point resulting in a high accuracy. Therefore the first conversion step can be based on one of the two comparators 20 , 30 without preference.
- the result of the first conversion step indicates the voltage plane of the input voltage Vin, i.e. in the range Vin>Vdd or Vin ⁇ Vdd.
- This result can be used to switch to the comparator 20 or 30 with the appropriate gain for the expected input voltage Vin for all following conversions down to the least significant bit LSB, finally yielding in a high accuracy rail-to-rail operation of the analog-to-digital converter.
- the shown principle can even be generally expanded to the input buffer stages 40 , 50 .
- the first and second comparators 20 , 30 are latch-type comparators, as depicted in FIG. 3 a and FIG. 3 b .
- Such comparator types are generally known in the art, as for example suggested for an nMOS latch-type comparator by Won-Chul Song et al., which has already been discussed in the introduction.
- FIG. 3 a shows a comparator 20 equipped with pMOS transistors and FIG. 3 b shows a comparator 30 equipped with nMOS transistors.
- SOI silicon-on-insulator
- the pMOS based comparator works at its optimum for low input voltages Vin, with Vin ⁇ Vdd ⁇ 2Vdssat.p, wherein Vdd is the operation voltage and 2Vdssat.p is a saturation voltage of the pMOS-transistors.
- Vdssat is the saturation voltage of a transistor where the transistor is operated in its pinch-off regime, where the gain of the transistor is at its maximum.
- Vdssat is the voltage drop between the drain and the source of the transistor which is necessary to operate the transistor in its saturation regime at the respective gate-source-voltage (or the respective drain-source current).
- a preferred algorithm for operating the analog-to-digital converter shown in FIG. 2 is a successive approximation mode as depicted in FIG. 4 .
- an analog-to-digital conversion working with successive approximation is known in the art.
- the successive approximation conversion method is expanded to two comparators 20 , 30 .
- V 0 is set to Vdd/2.
- the appropriate comparator is selected in step 210 .
- the threshold voltage V 0 is equal to the reference voltage Vref.
- the first conversion step 200 can be based on one of the two comparators 20 , 30 without preference.
- the result of the first conversion step indicates the voltage plane of the input voltage Vin, i.e. in the range Vin>Vdd/2 or Vin ⁇ Vdd/2.
- the second comparator 30 is used in the first step 200 .
- step 210 a comparison is made if the input voltage signal Vin is above the threshold voltage V 0 , Vin>V 0 . If Vin is below Vin, the first comparator 20 is selected in step 400 and the MSB is cleared. If yes, that is if a high input voltage is present, the conversion is continued with the second comparator 30 and the MSB is set in step 300 . As already mentioned, the second comparator 30 is used for the following conversions in this example.
- step 304 following after step 302 , a comparison is made if the input voltage signal Vin is above the reference voltage Vref: Vin>Vref and so on, according to a usual successive approximation conversion.
- step 210 If after step 210 the comparison shows that the input voltage signal Vin is below the threshold, the first comparator 20 is selected in step 400 and the MSB is cleared. In this case, the first comparator 20 is used throughout the following conversions.
- step 404 following after step 402 , a comparison is made if the input voltage signal Vin is below the reference voltage Vref: Vin ⁇ Vref, according to a usual successive approximation conversion. The conversion is continued with the first comparator 20 .
- steps 306 and/or 406 are continued until the conversion is complete in step 220 .
Abstract
Description
- This application claims priority to Application No. 06117795.2 filed Jul. 25, 2006, the entire content of which is incorporated by reference herein.
- The invention relates to a comparator circuit and a method for operating a comparator circuit according to the preambles of the independent claims.
- Successive approximation analog-to-digital converters (ADC) are well known in the art. Such ADCs use a comparator to reject ranges of voltages, eventually settling on a final voltage range, and convert one bit per cycle. A typical successive approximation ADC comprises a reference voltage generator, a comparator and a successive approximation register. A general description of this kind of ADCs can be found for example in Allen/Holberg: “CMOS Analog Circuit Design”, Oxford University Press 2002, 668-672.
- A single-rail comparator supports a limited input voltage range only. Normally asymmetric input range, starting at some value and ranging to one of the power supply rails. A rail-to-rail comparator supports full input voltage swing, starting at ground and ending at the supply voltage.
- Although the algorithm approach does not lead to highest speeds possible in state-of-the-art technologies, this kind of ADCs offers high resolution at low area costs. Additionally, the overall power consumption is low, especially compared to so called flash analog-to-digital converters. Besides other factors the overall conversion accuracy is mainly influenced by the comparator. It is known that offset-errors and gain-errors affect the comparator accuracy. Additionally, the comparator gain is a function of the common mode input voltage which results in limiting the useable input voltage and, further, an available input voltage swing is limited by the input buffer/sample-and-hold circuit, which is usually used at the comparator input.
- Various attempts have been made to overcome these problems.
- A pipelined ADC architecture which achieves high resolution at high conversion rates is suggested by Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak and Bang-Sup Song, “A 10-b 20-Msamples/s Low-Power CMOS ADC”, IEEE Journal of Solid-State Circuits, Vol. 30, No. 5, pages 514-521, May 1995. In this paper a latch-type comparator in nMOS technology with an asymmetric output load is disclosed.
- Another pipelined algorithmic ADC is disclosed by Hae-Seung Lee, “A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC”, IEEE Journal of Solid-State Circuits, Vol. 29, No. 4, pages 509-515, April 1994.
- M. K. Mayes, Sing W. Chin disclose an alternative approach in their paper “
A 200 mW, 1Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, page 1868, December 1996. - A time-interleaved ADC combining two three-step flash converters is presented by Michael K. Mayes, Sing W. Chin, Lee L. Stoian, “A Low-
Power 1 MHz, 25 mW 12-Bit Time-Interleaved Analog-to-Digital Converter”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 2, pages 169-178, February 1996. - Another comparator ADC with a level shifter is proposed by M. K. Mayes and Sing W. Chin “A 200 mW, 1 Msample/s, 16-b Pipelined A/D Converter with on-chip 32-b Microcontroller”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, pages 1862-1872, December 1996.
- A rail-to-rail comparator is disclosed in D. Gardino and F. Maloberti “High Resolution Rail-to-rail ADC In CMOS Digital Technology”, Proc. of the ISCAS 1999, Vol. 2, 339-342. This comparator design also needs a rail-to-rail input stage. But as already mentioned above, the comparator is one of the main sources of inaccuracy in such a circuitry. Very low or very high input voltages close to the power supply rail voltages show a very low gain and yield high inaccuracy. However, a rail-to-rail comparator or operational amplifier design introduces additional offset and error sources. Full rail-to-rail operation can still not be achieved.
- It is therefore an object of the invention to provide a comparator circuit which provides a rail-to-rail operation with high accuracy. Another object is to provide a method for operating the comparator circuit.
- The objects are achieved by the comparator circuit and the method according to the independent claims.
- The other claims and the description disclose advantageous embodiments of the comparator circuit and the method operating a comparator circuit according to the invention.
- A comparator circuit is proposed for comparing a first voltage signal with a second voltage signal, the circuit comprising a first comparator and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition. Advantageously, the gain of each comparator can be chosen independently from each other. Each comparator can be optimized for a different voltage regime, for example for high input voltages or low input voltages. Therefore, each comparator can work at its optimum. With an actual input signal present, the selecting unit advantageously selects one of the comparators according to its optimum voltage regime. Due to this digital selection of that one comparator working in its optimum range, the useable input voltage can be extended from single rail to a rail-to-rail, although each individual comparator can be a single-rail comparator. Due to the digital selection of the proper comparator, introduction of additional offsets and errors can be avoided, and mismatch compared to analog arrangements is avoided, where distortions/mismatch can occur. A degradation of operation speed can be prevented when using the inventive comparator circuit.
- High accuracy with low process dependency, low voltage dependency as well as low temperature dependency can be achieved. By expanding the operating voltage range of the comparator circuit according to the invention, a higher resolution for measurements of on-chip data is available, such as thermal sensors, supply voltage sensors, noise sensors. A rail-to rail comparator circuit is provided, although single-rail comparators, preferably performance-optimized single-rail comparators, can be used. A self-calibration comparator mode of operation is possible, providing a still more exact calibration.
- Generally spoken, the invention can be applied to any circuit which has a limited operating voltage range, e.g. a reference voltage generator. For such a circuit it is also possible to build two versions, one optimized for low output voltage operation and another one optimized for high output voltage operation. The comparator circuit can be preferably used in a successive approximation analog-to-digital converter and the method can be favorably used for converting analog signals to digital signals.
- Preferably, the selection condition is the voltage signal being above or below a threshold voltage. The threshold voltage can be a constant or can be variable.
- In a preferred embodiment, the selection unit selects one of the comparators if the voltage level is above the threshold voltage and the other one of the comparators if the voltage level is below the threshold voltage. This yields a high gain, high accuracy comparator circuit. In a preferred analog-to-digital converter, where such a comparator circuit is implemented, this decision is made as a first step of the conversion procedure. Once the most accurate one of the comparators has been selected selected, the conversion can be continued with the selected comparator. Using a successive approximation type of analog-to-digital converter, the selection of the comparator can be included in the first (most significant bit) conversion step, when only a low comparator accuracy is needed.
- In a favorable embodiment, one of the comparators is a pMOS (p-channel Metal-Oxide Semiconductor field effect) transistor based device adapted for a first input voltage range and the other one of the comparators is an nMOS (n-channel Metal-Oxide Semiconductor field effect) transistor based device adapted for a second input voltage range. The pMOS-transistor based comparator works best at low input voltage levels, where its gain is high, whereas the gain of the nMOS-based comparator is high at high input voltage levels, yielding the comparator working at its best at high input voltage levels. At an input voltage level in the middle of the supply voltage both types of comparators show comparable gains and accuracies.
- In a further preferred embodiment, the selection unit selects the nMOS-based comparator if the voltage level is above the threshold voltage and the pMOS-based comparator is selected if the voltage level is below the threshold voltage. This yields a high gain, high accuracy comparator circuit.
- In another preferred embodiment, the selection unit comprises a selection output port, wherein the selection unit connects an output port either of the first comparator or the second comparator to the selection output port, depending on the selection of the selection unit. Thus, the output signal of the selected comparator can be processed further, for example in a preferred ADC or a preferred rail-to-rail comparator building block.
- According to a preferred embodiment, the reference voltage is defined by the voltage signals which are being compared by the comparators. Preferably, this is the case for applications in analog-to-digital converters. In such an ADC the reference voltage applied to the comparators is altered step by step during determining the most significant bit down to the least significant bit. In general, such a successive approximation procedure is well known in the art.
- According to a further embodiment, means for adjusting the reference voltage depending on the voltage signals which are being compared by the comparators are coupled to the selection unit. This is preferred in an ADC using the successive approximation operation mode.
- According to another preferred embodiment, the means comprises a voltage divider and a third comparator with an input port for a threshold voltage and an output port for a digital decision signal. This can be favorably used in a general comparator circuit. Preferably in this embodiment, the third comparator comprises an input port for a voltage signal which is also applied to one of the comparators. In this configuration the third comparator is working as a voltage plane detector. The third comparator can be a single-rail comparator of simple design.
- Preferably, in a rail-to-rail comparator building block the selection unit comprises a multiplexor, the output port of which is selectably connectable to one of the comparator output ports via the selection unit. By using a multiplexor, it is not necessary to choose a special kind of comparator type. Additionally or alternatively, it is possible to switch off that one comparator which has not been selected by the selection unit. In this case it may be appropriate to replace the multiplexor by a NAND (Not AND) or a NOR (Not OR) gate. Switching off the comparator means that a strobe signal is not generated in the respective comparator and/or the supply voltage is disconnected or the like. For this purpose it is advisable to choose a comparator with appropriate properties which are well known to skilled persons.
- In a very useful embodiment, the comparators are assigned to the comparator stage of an analog-to-digital converter, where, preferably, a sample-and-hold unit is assigned to each of the two comparators.
- Principally, it is even possible that at least one of the sample-and-hold units is equipped with a first and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition.
- Most preferably, the analog-to-digital converter is of a successive-approximation type.
- At least one of the first and second comparators can be a single-rail-type unit. A mismatch as known from analog rail-to-rail solutions as well as a speed degradation can be avoided.
- Most preferably, at least one of the first and second comparators is a latch-type device. This yields a very fast comparator circuit. Advantageously, the latch type device is equipped with a dummy inverter yielding a nearly symmetric output.
- A method for operating a comparator circuit is proposed, wherein a first voltage signal is compared with a second voltage signal, and either a first comparator or a second comparator is selected depending on a selection condition.
- Preferably, the selection condition is the voltage signal being above or below a threshold voltage. The most accurate one of the two comparators can be selected depending on the threshold voltage. Being a digital selection, distortions, inaccuracies as well as speed degradation can be avoided. Further, one of the two comparators is preferably adapted for a first input voltage range and the other is adapted for a second input voltage range essentially different from the first input voltage range.
- Particularly, the threshold voltage and/or a reference voltage can be defined by the voltage signals which are being compared by the comparators.
- A preferential step is to select an nMOS-based comparator if the voltage level is above the threshold voltage and a pMOS-based comparator if the voltage level is below the threshold voltage. Each comparator can work in an input voltage range where its gain is high, yielding a high accuracy voltage comparison.
- An analog-to-digital conversion can be made, wherein in or during a first step one of the comparators is chosen depending on the threshold voltage as selection decision.
- Favorably, in the beginning of the successive approximation analog-to-digital conversion the selection of one of the comparators and a first analog-to-digital conversion is performed in the same step.
- The present invention together with the above-mentioned and other objects and advantages may best be understood from the following detailed description of the embodiments, but not restricted to the embodiments, wherein is shown in:
-
FIG. 1 a first preferred embodiment in the form of a rail-to-rail comparator building block; -
FIG. 2 a second preferred embodiment in the form of an analog-to-digital converter; -
FIG. 3 a,b a preferred pMOS based comparator (a) and a preferred nMOS based comparator (b); and -
FIG. 4 a flow diagram of a successive-approximation algorithm applied on the preferred analog-to-digital converter ofFIG. 2 . - In the drawings identical elements or elements with identical functions are referred to with the same reference numeral.
- A preferred embodiment of the invention is depicted in
FIG. 1 . A comparator circuit comprises afirst comparator 20 and asecond comparator 30 and aselection unit 60. Theselection unit 60 is indicated with a dotted line. In this embodiment, the comparator circuit represents a high accuracy rail-to-rail comparator building block. - An input voltage signal Vin_p is fed into an
input port 22 and an input voltage signal Vin_n is fed into aninput port 24 of thefirst comparator 20. Anoutput port 26 of thefirst comparator 20 feeds an output signal to theselection device 60. - An input voltage signal Vin_p is fed into an
input port 32 and an input voltage signal Vin_n is fed into aninput port 34 of thesecond comparator 30. Anoutput port 36 of thesecond comparator 30 feeds an output signal to theselection unit 60. - Most preferably, the
first comparator 20 is equipped with pMOS transistors and therefore adapted for low input voltage levels and thesecond comparator 30 is equipped with nMOS transistors and therefore adapted for high input voltage levels. Details of the implementations are described in more detail inFIG. 3 a and 3 b. - A voltage source is coupled to the
selection unit 60 which, for example, comprises asimple voltage divider 120 with afirst resistor unit 122 and asecond resistor unit 124. The center tap of thevoltage divider 120 is connected to aninput port 104 of athird comparator 100. Anotherinput port 102 of thethird comparator 100 is connected to one of the input voltage signals Vin_p or Vin_n fed to the twocomparators input port 102 is connected to the positive Vin_p voltage signal. - The
third comparator 100 can be a low accuracy component of a simpler design than the first andsecond comparators third comparator 30 feeds a digital selection signal Vs from itsoutput port 106 to aselect input port 118 of amultiplexor 110 which assigned to theselection unit 60. - The
output ports second comparators ports multiplexor 110. Depending on a selection condition one of theinput ports output ports second comparators output port 116 of themultiplexor 110. - Preferably, the selection condition is a threshold voltage signal. The
selection unit 60 selects one of thecomparators voltage divider 120 and is, for example, in the middle of the operating voltage Vdd of the devices with V0=Vdd/2. If the input voltage Vin_p, Vin_n is above V0, theoutput port 36 of thesecond comparator 30 is connected to theoutput port 106 of themultiplexor 110. If the input voltage Vin_p, Vin_n is below V0, theoutput port 26 of thefirst comparator 20 is connected to theoutput port 106 of themultiplexor 110. Thethird comparator 100 feeds the appropriate decision signal Vs to theselect port 118 of themultiplexor 110. Theselection unit 60 selects thevery comparator - This results in an optimal selection of the most sensitive component, either
comparator 20 orcomparator 30, especially for the most critical cases, where both input voltage signals Vin_p and Vin_n are close together and a high comparator gain is needed. - The preferred embodiment depicted in
FIG. 2 represents a preferred high accuracy rail-to-rail analog-to digital converter. A comparator circuit comprises afirst comparator 20 and asecond comparator 30 and aselection unit 60. Theselection unit 60 is indicated with a dotted line. - An
input buffer stage 40 with aninput port 42 and anoutput port 44 is assigned to thefirst comparator 20 and aninput buffer stage 50 with aninput port 52 and anoutput port 54 is assigned to thesecond comparator 30. - An input voltage signal Vin is fed through the
buffer 40 into aninput port 22 and an input voltage signal Vref is fed into aninput port 24 of thefirst comparator 20. Anoutput port 26 of thefirst comparator 20 feeds an output signal to theselection device 60. - An input voltage signal Vin is fed through the
buffer 50 into aninput port 32 and an input voltage signal Vref is fed into aninput port 34 of thesecond comparator 30. Anoutput port 36 of thesecond comparator 30 feeds an output signal to theselection unit 60. - Most preferably, the
first comparator 20 is equipped with pMOS transistors and therefore adapted for low input voltage levels and thesecond comparator 30 is equipped with nMOS transistors and therefore adapted for high input voltage levels. Details of the implementations are described in more detail inFIG. 3 a and 3 b. - A
voltage source 70 is coupled to theselection unit 60, yielding a reference voltage Vref, which can be biased by adigital control unit 62. In the first conversion step for the most significant bit MSB, the reference voltage Vref corresponds to a threshold voltage V0 equal to Vdd/2, wherein V0 represents the selection condition. Thecomparator - The
output port 26 of thefirst comparator 20 and theoutput port 36 of thesecond comparator 30 are connected to theselection unit 60 viainput ports output port 26 or theoutput port 36 is connected directly or indirectly to anoutput port 66 of theselection unit 60. - For a first conversion step of the analog to digital conversion, when the most significant bit MSB is determined, V0 is at Vdd/2 and equals Vref, i.e. both
comparators comparators - This result can be used to switch to the
comparator - Preferably, the first and
second comparators FIG. 3 a andFIG. 3 b. Such comparator types are generally known in the art, as for example suggested for an nMOS latch-type comparator by Won-Chul Song et al., which has already been discussed in the introduction. -
FIG. 3 a shows acomparator 20 equipped with pMOS transistors andFIG. 3 b shows acomparator 30 equipped with nMOS transistors. Other than in the prior art cited above, these devices comprise adummy inverter - Whereas the gain of the nMOS based comparator is in acceptable range at high input voltages Vin, with Vin>2Vdssat.n, wherein Vdssat.n is a saturation voltage of the nMOS-transistors, the pMOS based comparator works at its optimum for low input voltages Vin, with Vin<Vdd−2Vdssat.p, wherein Vdd is the operation voltage and 2Vdssat.p is a saturation voltage of the pMOS-transistors. As known in the art, Vdssat is the saturation voltage of a transistor where the transistor is operated in its pinch-off regime, where the gain of the transistor is at its maximum. Vdssat is the voltage drop between the drain and the source of the transistor which is necessary to operate the transistor in its saturation regime at the respective gate-source-voltage (or the respective drain-source current).
- A preferred algorithm for operating the analog-to-digital converter shown in
FIG. 2 is a successive approximation mode as depicted inFIG. 4 . In principle, an analog-to-digital conversion working with successive approximation is known in the art. For the preferred embodiment ofFIG. 2 , the successive approximation conversion method is expanded to twocomparators - For a
first conversion step 200 of the analog to digital conversion, when the most significant bit MSB is determined, V0 is set to Vdd/2. After thefirst conversion step 200, the appropriate comparator is selected instep 210. In thisfirst step 200, the threshold voltage V0 is equal to the reference voltage Vref. - At this point, both
comparators first conversion step 200 can be based on one of the twocomparators second comparator 30 is used in thefirst step 200. - In step 210 a comparison is made if the input voltage signal Vin is above the threshold voltage V0, Vin>V0. If Vin is below Vin, the
first comparator 20 is selected instep 400 and the MSB is cleared. If yes, that is if a high input voltage is present, the conversion is continued with thesecond comparator 30 and the MSB is set instep 300. As already mentioned, thesecond comparator 30 is used for the following conversions in this example. - In
step 302, following afterstep 300, the reference voltage Vref is set to the middle of the voltage interval: Vref=Vdd/2+Vdd/4, which is equal to middle of the detected voltage interval in the first step and the proper voltage interval for the next bit is selected. - In
step 304, following afterstep 302, a comparison is made if the input voltage signal Vin is above the reference voltage Vref: Vin>Vref and so on, according to a usual successive approximation conversion. - If after
step 210 the comparison shows that the input voltage signal Vin is below the threshold, thefirst comparator 20 is selected instep 400 and the MSB is cleared. In this case, thefirst comparator 20 is used throughout the following conversions. - Then in
step 402, following afterstep 400, the reference voltage Vref is set to Vref=Vdd/2−Vdd/4, which is equal to middle of the detected voltage interval in the first step. - In
step 404, following afterstep 402, a comparison is made if the input voltage signal Vin is below the reference voltage Vref: Vin<Vref, according to a usual successive approximation conversion. The conversion is continued with thefirst comparator 20. - Several following
steps 306 and/or 406 are continued until the conversion is complete instep 220.
Claims (20)
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US11/965,186 US20080178129A1 (en) | 2006-07-25 | 2007-12-27 | Comparator Circuit and Method for Operating a Comparator Circuit |
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EP06117795 | 2006-07-25 | ||
DE06117795.2 | 2006-07-25 |
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US11/965,186 Continuation-In-Part US20080178129A1 (en) | 2006-07-25 | 2007-12-27 | Comparator Circuit and Method for Operating a Comparator Circuit |
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US11/782,910 Abandoned US20080048729A1 (en) | 2006-07-25 | 2007-07-25 | Comparator Circuit and Method for Operating a Comparator Circuit |
US11/828,666 Expired - Fee Related US7477365B2 (en) | 2006-07-25 | 2007-07-26 | Optical spot geometric parameter determination using calibration targets |
US12/173,857 Abandoned US20090027660A1 (en) | 2006-07-25 | 2008-07-16 | Optical spot geometric parameter determination using calibration targets |
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US11/828,666 Expired - Fee Related US7477365B2 (en) | 2006-07-25 | 2007-07-26 | Optical spot geometric parameter determination using calibration targets |
US12/173,857 Abandoned US20090027660A1 (en) | 2006-07-25 | 2008-07-16 | Optical spot geometric parameter determination using calibration targets |
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US20100231285A1 (en) * | 2009-03-12 | 2010-09-16 | Boomer James B | Mipi analog switch for automatic selection of multiple image sensors |
US20130310897A1 (en) * | 2012-05-17 | 2013-11-21 | Boston Scientific Neuromodulation Corportion | Pulse-by-Pulse Compliance Voltage Generation for an Implantable Stimulator |
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CN110620373A (en) * | 2018-06-18 | 2019-12-27 | 爱思开海力士有限公司 | Voltage clamp circuit, and semiconductor device and semiconductor system including the same |
KR20190142535A (en) * | 2018-06-18 | 2019-12-27 | 에스케이하이닉스 주식회사 | Voltage clamping circuit, semiconductor apparatus and semiconductor system including the same |
US10719095B2 (en) * | 2018-06-18 | 2020-07-21 | SK Hynix Inc. | Voltage clamping circuit, semiconductor apparatus, and semiconductor system including the voltage clamping circuit |
Also Published As
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US20080024781A1 (en) | 2008-01-31 |
US20090027660A1 (en) | 2009-01-29 |
US7477365B2 (en) | 2009-01-13 |
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