US20080197497A1 - Barrier for use in 3-d integration of circuits - Google Patents
Barrier for use in 3-d integration of circuits Download PDFInfo
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- US20080197497A1 US20080197497A1 US12/110,009 US11000908A US2008197497A1 US 20080197497 A1 US20080197497 A1 US 20080197497A1 US 11000908 A US11000908 A US 11000908A US 2008197497 A1 US2008197497 A1 US 2008197497A1
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- 230000004888 barrier function Effects 0.000 title claims abstract description 30
- 230000010354 integration Effects 0.000 title description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 8
- 239000010941 cobalt Substances 0.000 claims abstract description 8
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 8
- 239000003989 dielectric material Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 27
- 235000012431 wafers Nutrition 0.000 description 43
- 230000008901 benefit Effects 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LFGFZXXKZPSRMB-UHFFFAOYSA-N [B].[Mo].[Co] Chemical compound [B].[Mo].[Co] LFGFZXXKZPSRMB-UHFFFAOYSA-N 0.000 description 1
- NWIWEUGCAJTIJV-UHFFFAOYSA-N [B].[Ni].[Re] Chemical compound [B].[Ni].[Re] NWIWEUGCAJTIJV-UHFFFAOYSA-N 0.000 description 1
- UYNAGLMEARBXEG-UHFFFAOYSA-N [B].[Re].[Co] Chemical compound [B].[Re].[Co] UYNAGLMEARBXEG-UHFFFAOYSA-N 0.000 description 1
- CPJYFACXEHYLFS-UHFFFAOYSA-N [B].[W].[Co] Chemical compound [B].[W].[Co] CPJYFACXEHYLFS-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- IJIMPXOIJZHGTP-UHFFFAOYSA-N boranylidynemolybdenum nickel Chemical compound [Ni].B#[Mo] IJIMPXOIJZHGTP-UHFFFAOYSA-N 0.000 description 1
- IGLTYURFTAWDMX-UHFFFAOYSA-N boranylidynetungsten nickel Chemical compound [Ni].B#[W] IGLTYURFTAWDMX-UHFFFAOYSA-N 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- JMANVNJQNLATNU-UHFFFAOYSA-N oxalonitrile Chemical compound N#CC#N JMANVNJQNLATNU-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Definitions
- This invention relates in general to 3-D integration of circuits and more specifically to a barrier for use in 3-D integration of circuits.
- 3-D integration of circuits is achieved using face-to-face bonding of wafers, such as acceptor wafers and donor wafers, or dies.
- Acceptor wafer is typically the bottom wafer and donor wafer is typically the top wafer.
- Interconnects in the bonded wafers or dies are connected using various techniques, such as stitch vias.
- stitch vias which are typically formed on the backside of a donor wafer, is, however, time consuming and requires additional steps for achieving 3-D integration of wafers or dies. In particular, for example, formation of stitch vias requires two inter-wafer vias having differing lengths that are linked on the backside of the donor wafer.
- etching of inter-wafer vias can cause several problems for etch processing.
- etching of such inter-wafer vias in low-K dielectric wafers requires etching through multiple types of dielectric materials, such as silicon nitride, silicon carbon-nitride, silicon-oxide, and SiCOH containing low-K dielectrics.
- This in turn requires a wide range of etch processes, such as both physical and chemical etch processes.
- Certain physical and chemical etch processes can redistribute the copper into the dielectric layers. This problem, for example, especially occurs when inter-wafer connects are used as embedded etch masks.
- FIG. 1 is a partial side view of one embodiment of an exemplary acceptor wafer during a processing stage, consistent with one embodiment of the invention
- FIG. 2 is a partial side view of one embodiment of an exemplary acceptor wafer, consistent with one embodiment of the invention
- FIG. 3 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention
- FIG. 4 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention
- FIG. 5 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention
- FIG. 6 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention.
- FIG. 7 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention.
- FIG. 8 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention.
- FIG. 9 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention.
- a method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer.
- the second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening.
- the method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material.
- the selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.
- a method for forming a semiconductor device includes providing a first integrated circuit having a landing pad.
- the method further includes attaching a second integrated circuit to the first integrated circuit using at least one bonding layer, the second integrated circuit having an inter-circuit trace, the inter-circuit trace having an opening.
- the method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening.
- the method further includes forming a selective barrier on exposed portions of the inter-circuit trace in the opening, the selective barrier comprising at least one material selected from a group consisting of cobalt and nickel.
- the method further includes extending the opening through the at least one bonding layer to the landing pad.
- the method further includes after extending the opening, filling the opening with a conductive fill material, wherein the conductive fill is electrically connected to the inter-circuit trace and the landing pad.
- a semiconductor device including a first integrated circuit having a landing pad and at least one bonding layer over the landing pad.
- the semiconductor device further includes a second integrated circuit having an inter-circuit trace and at least one bonding layer over the inter-circuit trace, wherein the at least one bonding layer of the second integrated circuit is attached to the at least one bonding layer of the first integrated circuit.
- the semiconductor device further includes a conductive interconnect extending through the second integrated circuit, through an opening in the inter-circuit trace, through the at least one bonding layer of the second integrated circuit, and through the at least one bonding layer of the first integrated circuit to the landing pad, the conductive interconnect electrically connecting the inter-circuit trace to the landing pad.
- the semiconductor device further includes a barrier layer adjacent the inter-circuit trace comprising at least one material selected from a group consisting of cobalt and nickel and located in the opening of the inter-circuit trace, between the inter-circuit trace and the conductive interconnect.
- FIG. 1 is a partial side view of one embodiment of an acceptor wafer during a processing stage, consistent with one embodiment of the invention.
- Acceptor wafer 10 may include an interconnect layer 12 , an active layer 14 , and a semiconductor layer 16 .
- Interconnect layer 12 may include interconnect 20 and via 22 .
- a landing feature, such as a landing pad 18 may be formed as part of interconnect layer 12 , as well.
- a conductive barrier 24 having cobalt or nickel may be formed on top of landing pads.
- FIG. 1 shows only one of each of interconnect layer 12 , active layer 14 , and semiconductor layer 16 , acceptor wafer 10 may include additional such layers.
- a bonding layer 26 may be formed on top of interconnect layer 12 .
- a donor wafer 30 may be bonded face-to-face with acceptor wafer 10 .
- Donor wafer 30 may include similar layers as acceptor wafer 10 .
- donor wafer 30 may include an interconnect layer 32 , an active layer 34 , and a semiconductor layer 36 .
- Interconnect layer 32 may include an inter-wafer connect trace 38 with an opening 40 formed in inter-wafer connect trace 38 .
- Inter-wafer connect trace 38 may look like a line with a hole (opening 40 ) in it.
- Inter-wafer connect trace 38 may be formed using copper or any other suitable conductive material.
- inter-wafer connect trace 38 may act as an inter-circuit trace in a wafer or a die.
- Donor wafer 30 may have an etch-stop layer 50 formed on interconnect layer 32 .
- a bonding layer 42 may be formed over etch-stop layer 50 .
- FIG. 3 shows separately formed bonding layer 42 and etch-stop layer 50
- etch-stop layer may be formed as part of bonding layer 42 .
- bonding layer 42 may act as an etch-stop layer.
- only one of acceptor wafer 10 and donor wafer 30 may have a bonding layer.
- active layer 34 and semiconductor layer 36 may include align-keys 46 and 48 , which may be used to find features in interconnect layer 32 , for example.
- align-keys 46 and 48 may be used to align patterns on the backside of donor wafer 30 , which is the top surface of the bonded wafer.
- FIG. 3 shows align-keys 46 and 48 , these may not be necessary in a SOI wafer, where features may be visible through active layer 34 and semiconductor layer 36 .
- Isolation windows 47 and 49 may be formed in active layer 34 and semiconductor layer 36 of donor wafer 30 . Isolation windows 47 and 49 may be used to isolate conductive fill material formed in vias, as explained further with respect to FIGS. 8 and 9 .
- Isolation windows 47 and 49 may contain an insulating material, such as an oxide.
- FIG. 3 shows only one of each of interconnect layer 32 , active layer 34 , and semiconductor layer 36 , donor wafer 30 may include additional such layers. Additionally, although FIG. 3 shows face-to-face bonding of acceptor wafer 10 and donor wafer 30 , they may be bonded in other configurations, as well.
- a barrier layer 52 may be formed on at least top and side surfaces of inter-wafer connect trace 38 .
- Barrier layer 52 may be formed using tantalum, titanium, tungsten or alloys thereof.
- FIG. 3 does not show barrier layer 52 formed over other interconnect traces ( 20 , for example), barrier layer 52 may be formed over other interconnect traces in acceptor wafer 10 and donor wafer 30 , as well.
- semiconductor layer 36 of donor wafer 30 may be thinned using mechanical-chemical or chemical-mechanical processes to form thinned semiconductor layer 44 .
- a patterned masking layer 54 may be formed over thinned semiconductor layer 44 .
- an opening 58 extending through opening 40 (shown in FIG. 5 ) in donor wafer 30 may be formed.
- etch-stop layer 50 is shown in FIG. 4 as being directly adjacent to bonding layer 42 , etch-stop layer 50 may be placed at a different location in donor wafer 30 .
- etch-stop layer 50 may be placed directly under inter-wafer connect trace 38 , if interconnect layer 32 did not have inter-wafer connect trace 39 or if inter-wafer connect trace 39 were at the same level as inter-wafer connect trace 38 .
- the etch-stop layer may always be positioned directly below the inter-wafer connect trace of an interconnect layer, such as interconnect layer 32 , that is closest to the bonding surface of the wafer. Additional openings, as necessary, may be formed.
- FIG. 6 shows an additional opening 56 . Openings 56 and 58 may expose portions of inter-wafer connect trace 38 and 39 .
- the etching process may etch away parts of barrier layer 52 to expose portions of inter-wafer connect trace 38 and 39 .
- a barrier ( 60 , 62 ) may be selectively formed on exposed portions of inter-wafer connect trace 38 and 39 .
- barrier ( 60 , 62 ) may be formed only on the exposed portions of inter-wafer connect trace 38 and 39 .
- exposed portions of inter-wafer connect trace 38 and 39 may be treated prior to forming barrier ( 60 , 62 ) exposed portions of inter-wafer connect trace 38 and 39 may be treated. Such treatment may include completely or partially removing barrier layer 52 or treating the exposed portions with catalytic materials, such as palladium or platinum. Exposed portions of inter-wafer connect trace 38 and 39 may result in the trace material, such as copper being exposed.
- Barrier ( 60 , 62 ) may be formed directly on the exposed copper, for example.
- Barrier ( 60 , 62 ) may be cobalt or nickel containing material, such as cobalt-tungsten-boron, cobalt-tungsten-phosphorous, cobalt-molybdenum-boron, cobalt-molybdenum-phosphorous, cobalt-rhenium-boron, cobalt-rhenium-phosphorous, nickel-tungsten-boron, nickel-tungsten-phosphorous, nickel-molybdenum-boron, nickel-molybdenum-phosphorous, nickel-rhenium-boron, nickel-rhenium-phosphorous, or it may be any other suitable etch resistant material.
- exposed portions of inter-wafer connect trace 38 and 39 may still have a portion of barrier layer 52 with at least some of the copper exposed. Exposed portions of inter-wafer connect trace 38 and 39 may be used to grow the barrier layer. Exposed portions of inter-wafer connect trace 38 and 39 may first be treated using palladium and/or platinum, prior to growing the barrier layer.
- opening 58 may be extended to a landing pad (e.g., a landing pad similar to landing pad 18 ).
- opening 56 may be extended to another landing pad.
- FIG. 8 shows openings 56 and 58 extending to landing pads, these openings may extend to any metal line of acceptor wafer 10 to make appropriate interconnections.
- conductive fill material 64 and 66 may be filled into openings 58 and 56 , respectively, for electrically interconnecting acceptor wafer 10 and donor wafer 30 .
- Conductive fill material 64 and 66 may be filled using processes, such as electroplating. Isolation windows 47 and 49 may keep active layer 34 and thinned semiconductor layer 44 electrically isolated from conductive fill material.
- a liner and seed layers may be formed in openings 56 and 58 prior to filling conductive fill material 64 and 66 into these openings. These layers may be formed using a chemical vapor deposition or a physical vapor deposition process.
Abstract
Description
- 1. Field of the Invention
- This invention relates in general to 3-D integration of circuits and more specifically to a barrier for use in 3-D integration of circuits.
- 2. Description of the Related Art
- Traditionally, 3-D integration of circuits is achieved using face-to-face bonding of wafers, such as acceptor wafers and donor wafers, or dies. Acceptor wafer is typically the bottom wafer and donor wafer is typically the top wafer. Interconnects in the bonded wafers or dies are connected using various techniques, such as stitch vias. Formation of stitch vias, which are typically formed on the backside of a donor wafer, is, however, time consuming and requires additional steps for achieving 3-D integration of wafers or dies. In particular, for example, formation of stitch vias requires two inter-wafer vias having differing lengths that are linked on the backside of the donor wafer.
- Additionally, etching of inter-wafer vias can cause several problems for etch processing. For example, etching of such inter-wafer vias in low-K dielectric wafers requires etching through multiple types of dielectric materials, such as silicon nitride, silicon carbon-nitride, silicon-oxide, and SiCOH containing low-K dielectrics. This in turn requires a wide range of etch processes, such as both physical and chemical etch processes. Certain physical and chemical etch processes can redistribute the copper into the dielectric layers. This problem, for example, especially occurs when inter-wafer connects are used as embedded etch masks.
- Thus, there is a need for improved 3-D integration of circuits.
- The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
-
FIG. 1 is a partial side view of one embodiment of an exemplary acceptor wafer during a processing stage, consistent with one embodiment of the invention; -
FIG. 2 is a partial side view of one embodiment of an exemplary acceptor wafer, consistent with one embodiment of the invention; -
FIG. 3 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention; -
FIG. 4 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention; -
FIG. 5 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention; -
FIG. 6 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention; -
FIG. 7 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention; -
FIG. 8 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention; and -
FIG. 9 is a partial side view of one embodiment of a semiconductor device during a processing stage, consistent with one embodiment of the invention. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
- The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.
- In one aspect, a method for forming a semiconductor device is provided. The method includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.
- In another aspect, a method for forming a semiconductor device is provided. The method includes providing a first integrated circuit having a landing pad. The method further includes attaching a second integrated circuit to the first integrated circuit using at least one bonding layer, the second integrated circuit having an inter-circuit trace, the inter-circuit trace having an opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening. The method further includes forming a selective barrier on exposed portions of the inter-circuit trace in the opening, the selective barrier comprising at least one material selected from a group consisting of cobalt and nickel. The method further includes extending the opening through the at least one bonding layer to the landing pad. The method further includes after extending the opening, filling the opening with a conductive fill material, wherein the conductive fill is electrically connected to the inter-circuit trace and the landing pad.
- In yet another aspect, a semiconductor device including a first integrated circuit having a landing pad and at least one bonding layer over the landing pad, is provided. The semiconductor device further includes a second integrated circuit having an inter-circuit trace and at least one bonding layer over the inter-circuit trace, wherein the at least one bonding layer of the second integrated circuit is attached to the at least one bonding layer of the first integrated circuit. The semiconductor device further includes a conductive interconnect extending through the second integrated circuit, through an opening in the inter-circuit trace, through the at least one bonding layer of the second integrated circuit, and through the at least one bonding layer of the first integrated circuit to the landing pad, the conductive interconnect electrically connecting the inter-circuit trace to the landing pad. The semiconductor device further includes a barrier layer adjacent the inter-circuit trace comprising at least one material selected from a group consisting of cobalt and nickel and located in the opening of the inter-circuit trace, between the inter-circuit trace and the conductive interconnect.
-
FIG. 1 is a partial side view of one embodiment of an acceptor wafer during a processing stage, consistent with one embodiment of the invention.Acceptor wafer 10 may include aninterconnect layer 12, anactive layer 14, and asemiconductor layer 16.Interconnect layer 12 may includeinterconnect 20 and via 22. A landing feature, such as alanding pad 18 may be formed as part ofinterconnect layer 12, as well. By way of example, aconductive barrier 24 having cobalt or nickel may be formed on top of landing pads. AlthoughFIG. 1 shows only one of each ofinterconnect layer 12,active layer 14, andsemiconductor layer 16,acceptor wafer 10 may include additional such layers. Further, as shown inFIG. 2 , abonding layer 26 may be formed on top ofinterconnect layer 12. - Referring now to
FIG. 3 , a donor wafer 30 may be bonded face-to-face withacceptor wafer 10.Donor wafer 30 may include similar layers asacceptor wafer 10. By way of example,donor wafer 30 may include aninterconnect layer 32, anactive layer 34, and asemiconductor layer 36.Interconnect layer 32 may include an inter-wafer connecttrace 38 with an opening 40 formed in inter-wafer connecttrace 38. Inter-wafer connecttrace 38 may look like a line with a hole (opening 40) in it. Inter-wafer connecttrace 38 may be formed using copper or any other suitable conductive material. Although described with respect to a wafer, inter-wafer connecttrace 38 may act as an inter-circuit trace in a wafer or a die.Donor wafer 30 may have an etch-stop layer 50 formed oninterconnect layer 32. Abonding layer 42 may be formed over etch-stop layer 50. AlthoughFIG. 3 shows separately formedbonding layer 42 and etch-stop layer 50, etch-stop layer may be formed as part ofbonding layer 42. Alternatively,bonding layer 42 may act as an etch-stop layer. In addition, only one ofacceptor wafer 10 anddonor wafer 30 may have a bonding layer. - Further, as shown in
FIG. 3 ,active layer 34 andsemiconductor layer 36 may include align-keys interconnect layer 32, for example. In particular, align-keys donor wafer 30, which is the top surface of the bonded wafer. AlthoughFIG. 3 shows align-keys active layer 34 andsemiconductor layer 36.Isolation windows active layer 34 andsemiconductor layer 36 ofdonor wafer 30.Isolation windows FIGS. 8 and 9 .Isolation windows FIG. 3 shows only one of each ofinterconnect layer 32,active layer 34, andsemiconductor layer 36,donor wafer 30 may include additional such layers. Additionally, althoughFIG. 3 shows face-to-face bonding ofacceptor wafer 10 anddonor wafer 30, they may be bonded in other configurations, as well. - Referring still to
FIG. 3 , abarrier layer 52 may be formed on at least top and side surfaces ofinter-wafer connect trace 38.Barrier layer 52 may be formed using tantalum, titanium, tungsten or alloys thereof. AlthoughFIG. 3 does not showbarrier layer 52 formed over other interconnect traces (20, for example),barrier layer 52 may be formed over other interconnect traces inacceptor wafer 10 anddonor wafer 30, as well. - Referring now to
FIG. 4 ,semiconductor layer 36 ofdonor wafer 30 may be thinned using mechanical-chemical or chemical-mechanical processes to form thinnedsemiconductor layer 44. Next, as shown inFIG. 5 , apatterned masking layer 54 may be formed over thinnedsemiconductor layer 44. Next, as shown inFIG. 6 , by etching and using etch-stop layer 50, anopening 58 extending through opening 40 (shown inFIG. 5 ) indonor wafer 30 may be formed. Although etch-stop layer 50 is shown inFIG. 4 as being directly adjacent tobonding layer 42, etch-stop layer 50 may be placed at a different location indonor wafer 30. For example, etch-stop layer 50 may be placed directly underinter-wafer connect trace 38, ifinterconnect layer 32 did not haveinter-wafer connect trace 39 or if inter-wafer connecttrace 39 were at the same level asinter-wafer connect trace 38. Thus, by way of example, the etch-stop layer may always be positioned directly below the inter-wafer connect trace of an interconnect layer, such asinterconnect layer 32, that is closest to the bonding surface of the wafer. Additional openings, as necessary, may be formed. For example,FIG. 6 shows anadditional opening 56.Openings inter-wafer connect trace barrier layer 52 to expose portions ofinter-wafer connect trace - Next, as shown in
FIG. 7 , a barrier (60, 62) may be selectively formed on exposed portions ofinter-wafer connect trace inter-wafer connect trace inter-wafer connect trace barrier layer 52 or treating the exposed portions with catalytic materials, such as palladium or platinum. Exposed portions ofinter-wafer connect trace inter-wafer connect trace barrier layer 52 with at least some of the copper exposed. Exposed portions ofinter-wafer connect trace inter-wafer connect trace - Next, as shown in
FIG. 8 , using a second etch process, opening 58 may be extended to a landing pad (e.g., a landing pad similar to landing pad 18). Similarly, as part of the second etch process, opening 56 may be extended to another landing pad. AlthoughFIG. 8 showsopenings acceptor wafer 10 to make appropriate interconnections. - Referring now to
FIG. 9 ,conductive fill material openings acceptor wafer 10 anddonor wafer 30.Conductive fill material Isolation windows active layer 34 and thinnedsemiconductor layer 44 electrically isolated from conductive fill material. Although not shown, a liner and seed layers may be formed inopenings conductive fill material selective barrier 60 results in a better bottom sidewall coverage of liner and seed layers. Additionally, although not shown, additional steps may be performed subsequently to create singulated integrated circuits, for example. - In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
- Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims (4)
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US12/110,009 US20080197497A1 (en) | 2006-03-30 | 2008-04-25 | Barrier for use in 3-d integration of circuits |
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US11/278,042 US7378339B2 (en) | 2006-03-30 | 2006-03-30 | Barrier for use in 3-D integration of circuits |
US12/110,009 US20080197497A1 (en) | 2006-03-30 | 2008-04-25 | Barrier for use in 3-d integration of circuits |
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US12/110,009 Abandoned US20080197497A1 (en) | 2006-03-30 | 2008-04-25 | Barrier for use in 3-d integration of circuits |
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KR101030299B1 (en) * | 2008-08-08 | 2011-04-20 | 주식회사 동부하이텍 | Semiconductor device and method for manufacturing the device |
JP5985136B2 (en) | 2009-03-19 | 2016-09-06 | ソニー株式会社 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
US9406561B2 (en) * | 2009-04-20 | 2016-08-02 | International Business Machines Corporation | Three dimensional integrated circuit integration using dielectric bonding first and through via formation last |
US9293366B2 (en) * | 2010-04-28 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias with improved connections |
JP5577965B2 (en) * | 2010-09-02 | 2014-08-27 | ソニー株式会社 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
US9142581B2 (en) | 2012-11-05 | 2015-09-22 | Omnivision Technologies, Inc. | Die seal ring for integrated circuit system with stacked device wafers |
US10367031B2 (en) * | 2016-09-13 | 2019-07-30 | Imec Vzw | Sequential integration process |
JP6905040B2 (en) * | 2018-08-08 | 2021-07-21 | キヤノン株式会社 | Semiconductor device manufacturing method |
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KR20020010974A (en) * | 2000-07-31 | 2002-02-07 | 박종섭 | Method for forming FeRAM capable of reducing steps of metal wire forming |
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2007
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- 2007-02-22 KR KR1020087023823A patent/KR101352732B1/en active IP Right Grant
- 2007-03-16 TW TW096109128A patent/TWI416691B/en active
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US5563084A (en) * | 1994-09-22 | 1996-10-08 | Fraunhofer-Gesellschaft zur F orderung der angewandten Forschung e.V. | Method of making a three-dimensional integrated circuit |
US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US6642081B1 (en) * | 2002-04-11 | 2003-11-04 | Robert Patti | Interlocking conductor method for bonding wafers to produce stacked integrated circuits |
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WO2007130731A2 (en) | 2007-11-15 |
KR101352732B1 (en) | 2014-01-16 |
TW200742022A (en) | 2007-11-01 |
JP2009532874A (en) | 2009-09-10 |
US20070231950A1 (en) | 2007-10-04 |
KR20090004895A (en) | 2009-01-12 |
WO2007130731A3 (en) | 2008-09-18 |
US7378339B2 (en) | 2008-05-27 |
TWI416691B (en) | 2013-11-21 |
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