US20080237823A1

US20080237823A1 - Aluminum Based Bonding of Semiconductor Wafers

Info

Publication number: US20080237823A1
Application number: US12/013,310
Authority: US
Inventors: John R. Martin
Original assignee: Analog Devices Inc
Current assignee: Analog Devices Inc
Priority date: 2007-01-11
Filing date: 2008-01-11
Publication date: 2008-10-02
Also published as: WO2008086530A3; WO2008086537A2; US8100012B2; WO2008086530A2; US20080168838A1; WO2008086537A3

Abstract

Aluminum or aluminum alloy on each of a pair of semiconductor wafers is thermocompression bonded. Aluminum-based seal rings or electrical interconnects between layers may be thus formed. On a MEMS device, the aluminum-based seal ring surrounds an area occupied by a movably attached microelectromechanical structure. According to a manufacturing method, wafers have an aluminum or aluminum alloy deposited thereon are etched to form an array of aluminum-based rings. The wafers are placed so as to bring the arrays of aluminum-based rings into alignment. Heat and compression bonds the rings. The wafers are singulated to separate out the individual semiconductor devices each with a bonded aluminum-based ring.

Description

The present application claims priority from U.S. provisional application Ser. No. 60/879,903, filed Jan. 11, 2007, the full disclosure of which is hereby incorporated by reference herein.
The present application is related to an application entitled “MEMS Sensor with Cap Electrode”, by inventors John R. Martin and Xin Zhang, being filed on the same date as the present application, the full disclosure of which is hereby incorporated by reference herein.

TECHNICAL FIELD

The present invention relates to bonding of semiconductor wafers.

BACKGROUND ART

The demand for semiconductor devices, in particular, MEMS devices is increasing dramatically. Product makers using these semiconductor devices are in turn demanding smaller product size and lower prices. Wafer scale packaging is an important step to providing cost efficient mass production of semiconductor devices. Several wafer scale packaging processes have been reported. In the field of MEMS accelerometers, the typical wafer packaging processes include glass frit and anodic bonding.
Glass frit bonding of inertial MEMS devices is hermetic, cost-effective, requires reasonably low process temperatures and readily accommodates wafer topography. Unfortunately, there are a number of limitations suffered by users of glass frit bonding. Screen printing of glass frit does not meet integrated circuit contamination standards, so integration of capping with the fab process is not a prudent option. Glass is a dielectric so EMI shielding and control of stray charges require a separate electrical connection to the caps. Package thickness may increase if this connection is a bond wire to the top surface.
Glass frit seals are typically 150 to 400 microns in width on each side of the microstructure. This adds to the overall size of the semiconductor devices. Moreover, glass and silicon have different thermal expansion coefficients so a stress field is set up near the microstructure as the wafers cool from the bonding temperature.
Anodic bonding applies several hundred volts across a glass-silicon bond pair at about 350-420° C. The electric field causes mobile ions in the glass to move away from the interface and towards the cathode (outer surface of the glass wafer). The bound negative charges that remain in the glass near the interface produce a field that pulls the surfaces together and anodically oxidizes the silicon surface. Anodic bonding is fast and applies minimal pressure.
However, anodic bonding has its limitations as well. Flat wafer topography is required because hermetic bonding requires closely mated surfaces. Imposing a high voltage during high temperature bonding limits integration of MEMS and electronics on wafers. Some provision is required to shield the microstructures from electrostatic forces that can cause microstructure stiction during the bonding process. Glass-silicon bond pairs may require wider saw streets than silicon wafers.
An alternative possibility for wafer bonding that has been considered is the use of metals. Two approaches to using metal include solder processes and thermocompression bonding. Solder based processes readily accommodate wafer topography. High temperature solders are preferable because many end-use applications of the capped devices require that they survive plastic package transfer molding stresses at 175° C. Environmental and regulatory considerations make the use of non-lead solders highly desirable. Minimizing solder creep during high temperature aging is also important (solder creep and stress relaxation will affect device parametrics). Gold-tin is a candidate, but gold cannot be used in an integrated circuit fab because it is a deep trap contaminant.
Thermocompression bonding requires bond pressures and wafer topography that create atomic-scale contact between the mating metal surfaces. Gold is commonly described as a candidate for thermocompression bonding. Gold is attractive because it is relatively soft and can thus achieve atomic scale contact with reasonable bonder force. Furthermore, it advantageously does not form a native oxide. Gold also forms low temperature eutectics. On the other hand, as noted above gold cannot be used in an integrated circuit fab.
Thermocompression bonding can also be used in forming electrical connections between wafers. Copper has been used for this application, despite the fact that it is also a deep trap contaminant. Copper is a conductive material which oxidizes. While the oxide interferes with thermocompression bonding, the oxidation of the copper takes place slowly. Thus, processes have been developed that form copper electrical connections between wafers with thermocompression bonding.

SUMMARY OF THE INVENTION

In embodiments of the invention, aluminum or aluminum alloy is used on a pair of wafers to form a plurality of aluminum-based seal rings. A first wafer having an array of microelectronic dies is bonded to a second wafer. A plurality of seal rings, each associated with one of the microelectronic dies, forms seals between at least a portion of the dies on the first wafer and an adjacent region of the second wafer. The seal rings are made of aluminum and/or aluminum alloy. The seal rings may have a wall width between 3 and 90 microns and more preferably between 5 and 30 microns.
For MEMS devices, each microelectronic die includes a microelectromechanical structure movably attached to a semiconductor die. A conductive seal ring is formed entirely of aluminum and/or aluminum alloy. The seal ring surrounds an area occupied by the microelectromechanical structure. The semiconductor die and the microelectromechanical structure may be formed in any type of semiconductor wafer including SOI wafers. The MEMS device may be an inertial sensor or more particularly a capacitive inertial sensor, for example.
A method of the invention includes depositing aluminum or aluminum alloy on a first and second semiconductor wafer. The resulting aluminum-based layers are patterned to form an array of aluminum-based rings. Typically, the patterns are achieved through etching. The wafers are placed together with their respective aluminum-based rings in alignment. The wafers are then brought into contact, compressed and heated to bond the aluminum-based rings on the first wafer to their respective aluminum-based rings on the second wafer. In a preferred embodiment, the heating need not exceed 500° C. The pressure applied may be over about 30 MPa. If an anti-stiction treatment is performed on the wafers, pressures over about 90 MPa may be required. Bond strength may be improved by annealing the bonded wafer pair, at a temperature of about 450° C. for example. In addition, it may be helpful to planarize the aluminum-based rings before the compression bonding. After the bond process is completed, the bonded wafers are singulated to form individual semiconductor devices each with a bonded aluminum-based ring.
Embodiments of the invention further include using the process of thermocompressing aluminum-based deposits on a first wafer with aluminum-based deposits on a second wafer to create electrical interconnects in a semiconductor device. The electrical interconnects extend between a layer from the first wafer and a layer from the second wafer. The wafers are singulated to separate off the individual semiconductor devices. In this embodiment, a plurality of contact points, each associated with one of the microelectronic dies on the first wafer, forms electrical connections to the adjacent points of the second wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of the invention will be more readily understood by reference to the following detailed description, taken with reference to the accompanying drawings, in which:

FIG. 1 is a flow chart of an embodiment of a method of the present invention.

FIG. 2 is a plan view of a wafer with an array of deposited aluminum-based rings in accordance with the method of FIG. 1.

FIG. 3 is a side view of bonded wafers made according to the method of FIG. 1.

FIG. 4 is a side cross-sectional view of a MEMS device of an embodiment of the present invention.

FIG. 5 is a plan view of the cap in the MEMS device of FIG. 4.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Definitions. As used in this description and the accompanying claims, the following terms shall have the meanings indicated, unless the context otherwise requires:
The term “aluminum-based” means made from aluminum and/or aluminum alloy.
FIG. 1 schematically shows an illustrative process of making semiconductor devices. It should be noted that various steps of this process may be performed in a different order than that discussed. In addition, those skilled in the art should understand that additional steps may be performed, while others may be omitted.
An array of dies is formed 10 on a first wafer. The wafer is preferably a semiconductor and more particularly, a silicon-based material having semiconductor dies formed thereon. Silicon-based materials include single crystal silicon, silicon germanium and SOI. In alternative embodiments, however, other types of materials may be used. While conventional processes may be used to form the array of dies on the wafer, in accordance with embodiments of the present invention, it will be possible to more closely space the dies relative to one another than was practical with glass frit bonding. As a result, a greater number of devices can be made from a single wafer.
Aluminum or aluminum alloy is deposited 12 on a top face of the first wafer. For example, a layer of aluminum or aluminum alloy may be sputter deposited or e-beam evaporated onto the face of the wafer. It is often desirable to apply a titanium-tungsten barrier to the wafer before depositing the aluminum or aluminum alloy. The titanium-tungsten helps adhere the aluminum based layer and also serves to prevent spiking. In other words, it acts as a barrier against diffusion of the aluminum and silicon into each other. A particular aluminum alloy considered particularly suitable for use in embodiments of the present invention is aluminum with 1% copper, but other aluminum alloys may also be used within the scope of the invention. The aluminum-based layer may be more than one or two microns in thickness. Given a substantially flat substrate and the conformability of aluminum-based films when they yield, a thickness near two microns is sufficient to achieve thermocompression bonding. But if necessary, planarization 14 may be conducted to achieve the desirable flat surface. Upon exposure to air the aluminum based layer quickly oxidizes forming an impervious surface oxide. Unfortunately, the oxide interferes with the desire to obtain a bond between two aluminum-based components.
Nevertheless, in accordance with embodiments of the present invention, the aluminum-based layer is etched 16 to leave a desired pattern of aluminum-based rings, one for each of the semiconductor dies. A wafer 100 with an array of aluminum-based rings 110 thereon after etching is illustrated in FIG. 2. The array of aluminum-based rings 110 coincides with the array of microelectronic dies, such that each die has an aluminum-based ring. The wall width W of each aluminum-based ring is advantageously small thereby providing smaller size dies and allowing a greater density of dies to be made on a single wafer. The wall width may be between 3 and 90 microns, or more preferably between 5 and 30 microns.
In the specific case of making MEMS devices, conventional micromachining may be used to form MEMS dies and complete 18 the MEMS wafer. For example, the microelectromechanical structure may be formed by etching into the surface of the wafer. For each device, a microelectromechanical structure is released so as to be movable with respect to the die to which it is attached. The aluminum-based ring coincident with the die surrounds the area occupied by microelectromechanical structure. MEMS wafers may or may not include electronic circuitry.
A cap wafer 120 is also formed 20. In a manner similar to the first wafer, the cap wafer may be formed from single crystal silicon (or other material) in accordance with conventional processes (e.g., surface and bulk micromachining processes). The cap wafer and hence the caps may be flat as shown in FIG. 4. Alternatively, the cap wafer may be formed with an array of cavities, one for each cap to accommodate movement of microstructures on the die to which it gets bonded.
Despite the expected formation of oxide, a layer of aluminum or aluminum alloy is deposited 22 on the bottom side of the cap wafer. The deposition may be performed, for example, by sputtering. The aluminum or aluminum alloy selected for the cap wafer may be the same as the aluminum or aluminum alloy used on the first wafer, but it does not need to be the same. One wafer can use aluminum while the other uses an aluminum alloy. As was the case for the first wafer, the aluminum-based layer may be more than one or two microns thick. Again, the layer may be sufficiently flat as deposited or it may be put through a planarizing 24 process to achieve desired flatness.
The aluminum-based layer is etched 26 to form an array of rings that correspond in location to the array of rings on the first wafer. In alternative embodiments, an aluminum-based area may be left within each ring for use as a z-axis electrode in the cap. As indicated above, the wall width of each ring is advantageously small thereby allowing a greater density of devices to be made with a single wafer. The wall width may be between 3 and 90 microns, or more preferably between 5 and 30 microns. It may be useful to make the wall widths on the cap wafer different from the wall width on the first wafer. By including rings with a wider wall than its corresponding ring on the opposing wafer, slight misalignments of the two wafers can be tolerated. The metallized cap wafer then may be placed 28 with respect to the first wafer so that the array of aluminum-based rings on the first wafer contacts and aligns with the array of aluminum-based rings on the second wafer. Differing wall widths offers a less exacting requirement when aligning the arrays. The narrow wall does not need to be centered on the wider wall. It should, however, be in contact with the wider wall over the entire width of the narrow wall. Alignment is generally achieved before placing the wafer pair into a wafer bonder on one of the bonder platens. The platens in the wafer bonder may be inside a chamber to allow control of vacuum level, gas composition and gas pressure. With this capability, gases may be evacuated and backfilled one or more times in order to create the desired bond environment. Clean surfaces will bond at lower pressures and temperatures. If a gap is held between the aligned wafers, a reactive gas may optionally be introduced into the bond chamber during this process in order to clean the bond surfaces at a temperature not to exceed 500° C. The gas can react with contamination on the aluminum-based surfaces. Examples of such reactive gases include forming gas and formic acid. The gap between the aligned wafers might be held at between 10 to 500 microns by suitably sized spacers. After the optional cleaning step, the bond chamber environment is adjusted to the desired vacuum level or gas composition and pressure. While if forming gas is used it may remain in the chamber, in the case of formic acid it is recommended that the chamber be evacuated and backfilled after cleaning.
The heated platens of the bonder subjects the first wafer and the cap wafer to relatively high temperatures and pressures 30 to bond the aluminum-based rings together. Robust bonds between aluminum-based alloys have been achieved at 440° C. and bond pressures of about 30 MPa and above. If an anti-stiction film (used in some MEMS devices) is present, similar performance is achieved above about 90 MPa. An example of such an anti-stiction treatment is contained in U.S. Pat. No. 7,220,614, “Process for Wafer Level Treatment to Reduce Stiction and Passivate Micromachined Surfaces and Compounds Used Therefor”, the full disclosure of which is hereby incorporated by reference herein In a particularly preferred embodiment when anti-stiction films are present, wafer pairs are bonded at 440° C. and a bond pressure near 300 MPa for 15 minutes. The actual temperature and pressure used will depend on the materials selected. While greater temperatures allow for lower pressures to be used, adequate bonding of the aluminum-based rings is generally possible without requiring the temperature to exceed 500° C. The bonding pressure must be sufficient to break the surface films, including the oxide formed on the aluminum-based rings. Atomic contact between the aluminum in the ring of the first wafer and the aluminum in the ring of the cap wafer is desired. At high pressure and temperature, the aluminum re-crystallizes and grows laterally out from both sides of a well-formed seal at the interface between the adjoining aluminum-based rings. This recrystallization can be used as a non-destructive bond quality test as it can be seen through silicon with a confocal IR microscope. Any seal that does not have re-crystallized material along the edges may not have received sufficient pressure to achieve a high-quality seal.
For a device on the wafers to be adequately bonded, the area of that device must have been subjected to an adequate minimum pressure. To obtain high yield of bonded devices, it should be ensured that the minimum pressure be applied over the entire area of the wafers occupied by the devices. Even high quality wafers have small local thickness variations. In addition, it has been found that platens on some wafer bonders may deform slightly when bonding forces are applied at high temperatures. These small effects may cause the bonder to apply insufficient pressure to achieve robust bonds in local areas. One response is to increase the overall force. However, this may be limited by bonder capacity. Another approach is to insert graphite films above and/or below the pair of wafers being bonded. Under pressure, the graphite deforms to substantially equalize the bonding pressure across the wafers. Soft graphite may also reduce wafer cracking initiated by particle contaminants on either the bonder or wafer surfaces.
After the wafers are held at the target temperature and bond pressure for a suitable time, the bonded wafer pair is cooled and the pressure removed. It may be further useful to perform an annealing 32 process after thermocompression bonding. Annealing at about 450° C. has been found to increase bond strength.
Once thermocompression and, if used, annealing is completed, the resulting intermediate product is bonded wafers. In a side view, the bonded wafers are illustrated in FIG. 3. The bonded rings form a seal ring 230 between a die and its cap. If proper pressure was applied in the process, the seal ring will form a hermetic seal between the die and the cap. Given a thickness of 2 microns for each aluminum-based ring, the seal ring will hold the die at least two microns apart from the cap. The high pressure and temperature of thermocompression bonding breaks through thin surface oxides and other dielectric films to create electrically conductive aluminum-based connections. The original interface is virtually indistinguishable when cross-sections are examined in an SEM because these films dissolve and disperse into the aluminum. The conductivity can be used to drive the cap potential or to form a ground shield for the device in specific applications. Alternatively, the conductive seal ring may be electrically isolated from the die and the cap by dielectric layers 240.
Further processing of the bonded wafers may be performed according to conventional techniques. For example, the bottom portion of the first wafer may be subjected to a thinning process (e.g., backgrinding or etch back processes) to expose vias in the dies. Conductive contacts can then be mounted to the bottom of the vias, which then can be mounted to corresponding contacts on the top surface of a circuit die. After any such post-bonding processing is completed, the wafers then can be singulated into individual devices. Singulation is a cutting or dicing operation that separates the individual devices. There may be a sequence of singulation steps in order to singulate caps before completing singulation of the individual devices through the wafer carrying the dies.
The resulting devices may be mounted in a package, flip chip mounted on a circuit board (after contacts are formed on one side), or used in any conventional manner.
Another embodiment of the invention more generally relates to forming electrical contacts between a first wafer and a second wafer. It includes depositing aluminum or aluminum alloy on a first and second semiconductor wafer. The resulting aluminum-based layers are preferably etched to form an array of aluminum-based contacts. The wafers are placed together with their respective aluminum-based contacts in alignment. This is preferably performed before placing the wafer pair into a wafer bonder on one of the bonder platens. The platens in the wafer bonder may be inside a chamber to allow control of vacuum level, gas composition and gas pressure. With this capability, gases may be evacuated and backfilled one or more times in order to create the desired bond environment. If a gap is held between the aligned wafers, a reactive gas may optionally be introduced into the bond chamber during this process in order to clean the bond surfaces at a temperature not to exceed 500° C. Examples of such reactive gases include forming gas and formic acid. After the optional cleaning step, the bond chamber environment is adjusted to the desired vacuum level or gas composition and pressure. The wafers are then brought into contact (if not already in contact) and compressed between the heated platens in order to bond the aluminum-based contacts on the first wafer to their respective aluminum-based contacts on the second wafer. After the wafers are held at the target temperature and bond pressure for a suitable time, the bonded wafer pair is cooled and the pressure removed. The bonded pair may optionally be annealed at this point. In a preferred embodiment, the heating need not exceed 500° C. Robust bonds between aluminum-based alloys have been achieved at 440° C. and bond pressures of about 30 MPa and above. If an anti-stiction film (used in some MEMS devices) is present, similar performance is achieved above about 90 MPa. In a particularly preferred embodiment when anti-stiction films are present, wafer pairs are bonded at 440° C. and a bond pressure near 300 MPa for 15 minutes. Bond strength may be improved by annealing the bonded wafer pair, at a temperature of about 450° C. for example. In addition, it may be helpful to planarize the aluminum-based contacts before the compression bonding. After the bond process is completed, the bonded wafers are singulated to form individual semiconductor devices, each with bonded aluminum-based electrical connections between layers. There may be a sequence of singulation steps in order to individually singulate portions of the first wafer and portions the second wafer. The die formed in this process have at least two layers of silicon mechanically joined by aluminum-based structures. One or more of the aluminum-based structures may function as electrically active connections electrically isolated from each other. The die may or may not incorporate a MEMS device. While bonding of wafers and forming of interconnects has been described with respect to two wafers, the methods set forth herein also apply to bonding and interconnects between more than two wafers.
Without limiting the application of embodiments of the invention to any particular semiconductor device or MEMS device, it is worthwhile to note a few examples, such as inertial sensors. Inertial sensors are used for single and multi-axis accelerometers and gyroscopes. In an accelerometer for example, the microelectromechanical structure is a movable mass. Briefly, the mass is mounted to the semiconductor die with anchors so that it can move back and forth along a desired axis. The mass has fingers extending perpendicular to the axis and between sets of stationary parallel plates. When the fingers move, a change in capacitance between the plates is detected, thus allowing the acceleration of the mass along the axis to be determined.
Reference is now made to FIGS. 4 and 5, which illustrate one specific type of device manufacturable by the above-described method. A MEMS device conventionally includes a semiconductor die 200, a microelectromechanical structure 210 movably attached to the semiconductor die and a cap 220. Manufacture of the microelectromechanical structure on the semiconductor die can be effected by any of a variety of accepted processes. In accordance with embodiments of the present invention, the cap 220 is bonded to the semiconductor die by a conductive seal ring 230 made of aluminum and/or aluminum alloy. The illustration exaggerates the difference in wall widths of the aluminum-based rings that make up the conductive seal ring 230 for ease of understanding. It should be understood that after thermocompression bonding this has become a single seal ring 230 with atomic contact between the original separate aluminum-based seal rings. Aluminum and aluminum alloy exhibit the characteristic of not spreading much when bonded. Thus, the wall widths can be small and repeatable in manufacture. The wall width may be between 3 and 90 microns wide, or more preferably between 5 and 30 microns wide. The seal ring 230 forms a hermetic seal between the die 200 and the cap 220. A dielectric layer 240 may be included on one or both of the wafers to electrically isolate the conductive seal ring 230 from the underlying substrate.
In alternative embodiments, an aluminum-based electrode 250 may be left on the cap wafer 220. Such an electrode can be used as part of a z-axis sensor. The electrode 250 can be electrically connected to the semiconductor die through a bond pad 260, bonded to the electrode during thermocompression bonding. The bond pad 260 is an example of an electrical interconnect formed by use of thermocompression bonding. It was formed from aligned aluminum-based deposits on the cap wafer and the die wafer. Accuracy of the z-axis sensor can be enhanced by use of a fixed reference electrode 270 formed on the semiconductor die adjacent to the movable structure 210, as shown in FIG. 5.
The conductivity afforded by the aluminum-based seal ring 230 can be harnessed by providing an electrical connection pad 270. In FIG. 5, the pad 270 is shown in electrical contact with the cap 220. Such an electrical connection can be used for connecting to the cap in order to control its electrical potential for a variety of reasons such as formation of an electrical shield.
The embodiments of the invention described above are intended to be merely exemplary; numerous variations and modifications will be apparent to those skilled in the art. All such variations and modifications are intended to be within the scope of the present invention as defined in any appended claims.

Claims

1. Bonded wafers comprising:

a first wafer including an array of microelectronic dies;

a second wafer; and

a plurality of seal rings each associated with one of the microelectronic dies and forming a seal between the first wafer and the second wafer wherein each seal ring consists essentially of aluminum and/or aluminum alloy.

2. The bonded wafers of claim 1 wherein the seal rings each hermetically seal the volume within the seal rings from the outside environment.

3. The bonded wafers of claim 1 wherein the plurality of seal rings hold the first wafer and second wafer at least 2 microns apart.

4. The bonded wafers of claim 1 wherein each of the seal rings has a wall width of between 3 and 90 microns.

5. The bonded wafers of claim 4 wherein each of the seal rings has a wall width of between 5 and 30 microns.

6. The bonded wafers of claim 1 wherein each of the microelectronic dies comprises a movable microelectromechanical structure.

7. A MEMS device comprising:

a semiconductor die;

a microelectromechanical structure movably attached to the semiconductor die;

a cap; and

a conductive seal ring formed entirely of at least one from the group of aluminum and aluminum alloy, the seal ring being bonded between the semiconductor die and the cap and surrounding an area occupied by the microelectromechanical structure.

8. The MEMS device of claim 7 wherein the micromechanical structure is an inertial sensor.

9. The MEMS device of claim 7 wherein the microelectromechanical structure is formed in an SOI wafer.

10. The MEMS device of claim 7 wherein the microelectromechanical structure is formed in a standard silicon wafer.

11. The method of claim 10 wherein thin film depositions are used in the formation of the microelectromechanical structure.

12. The method of claim 10 wherein the microelectromechanical structure is substantially formed by etching into the surface of the wafer.

13. The MEMS device of claim 7 wherein the conductive seal ring hermetically seals the volume within the seal ring from the outside environment.

14. The MEMS device of claim 7 wherein the seal ring holds the semiconductor die and the cap at least 2 microns apart.

15. The MEMS device of claim 7 wherein the seal ring has a wall width of between 3 and 90 microns.

16. The MEMS device of claim 15 wherein the seal ring has a wall width of between 5 and 30 microns.

17. A method of making semiconductor devices comprising:

depositing aluminum or aluminum alloy to form an aluminum-based layer on a first semiconductor wafer;

patterning the aluminum-based layer to form an array of aluminum-based rings;

depositing aluminum or aluminum alloy to form an aluminum-based layer on a second semiconductor wafer;

patterning the aluminum-based layer to form an array of aluminum-based rings;

placing the second wafer on the first wafer so that the array of aluminum-based rings on the first wafer aligns with the array of aluminum-based rings on the second wafer;

heating the first and second wafers;

compressing the first and second wafers against each other to form a bond between aluminum-based rings on the first wafer with their respective aluminum-based rings on the second wafer; and

singulating the first and second wafers into individual semiconductor devices each having a bonded aluminum-based ring.

18. The method of claim 17 wherein patterning comprises etching.

19. The method of claim 17 wherein heating is performed up to less than 500° C.

20. The method of claim 19 wherein compressing applies over about 30 MPa.

21. The method of claim 19 further comprising performing an anti-stiction treatment on at least one of the wafers.

22. The method of claim 21 wherein compressing applies over about 90 MPa.

23. The method of claim 19 further comprising annealing the bonded aluminum-based rings.

24. The method of claim 23 wherein annealing is conducted at about 450° C.

25. The method of claim 19 further comprising planarizing the aluminum-based layer on each of the first and second wafers.

26. The method of claim 17 wherein the aluminum-based rings each have a wall width between 3 and 90 microns.

27. The method of claim 26 wherein the aluminum-based rings each have a wall width between 5 and 30 microns.

28. A semiconductor device, said device made by a process comprising:

thermocompressing an aluminum-based deposit on a first semiconductor wafer against an aluminum-based deposit on a second semiconductor wafer; and

singulating the wafers to separate the semiconductor device.

29. The semiconductor device of claim 28 further comprising a microelectromechanical structure movably attached to a semiconductor die singulated from one of the first or second semiconductor wafers.

30. The semiconductor device of claim 28 wherein the aluminum-based deposits on the first semiconductor wafer and on the second semiconductor wafer are in the form of rings, such that conductive seal rings are formed upon thermocompressing.

31. The semiconductor device of claim 30 wherein thermocompressing forms a conductive seal ring having a wall width of between 3 and 90 microns.

32. The semiconductor device of claim 31 wherein the conductive seal ring has a wall width between 5 and 30 microns.

33. The semiconductor device of claim 28 wherein the aluminum-based deposits form an electrical connection between a layer from the first semiconductor wafer and a layer from the second semiconductor wafer upon thermocompressing.

34. A method of determining the quality of thermocompression bonds formed between aluminum and/or aluminum alloy surfaces comprising:

inspecting an interface between the aluminum-based surfaces with an IR microscope for presence and amount of re-crystallization of aluminum-based material.