US20080237857A1

US20080237857A1 - Semiconductor package

Info

Publication number: US20080237857A1
Application number: US12/000,245
Authority: US
Inventors: Andrew Wye Choong Low; Mee Sing Tiong
Original assignee: Unisem M Bhd
Current assignee: Unisem M Bhd
Priority date: 2003-09-23
Filing date: 2007-12-11
Publication date: 2008-10-02
Also published as: US7544541B2; US20050062172A1; MY140980A

Abstract

There is disclosed a method of making an electronic package (10) by: forming a metal base (50) on which to build the components of an electronic package; applying a mask layer (60) on the base to an area that is not to be occupied by interconnection pads (200) or die attachment pads (201) of the package; plating layers of metal on the un-masked areas of the base to form the interconnection and die attachment pads (200, 201); removing the mask layer; mounting a semiconductor die (302) to at least one die attachment pad (201); electrically connecting the semiconductor die (302) to one or more interconnection pads (200); embedding the components on the base in an encapsulation material (300) to form a package; removing the metal base (50) to leave a package panel; and cutting the panel into discrete package units.

Description

FIELD OF THE INVENTION

The present invention relates to a method for manufacturing a semiconductor package that is typically a quad flat no-lead (QFN) packaging having matrix array packaging (MAP). The invention also relates to a semiconductor package manufactured by this method.

BACKGROUND OF THE INVENTION

MAP type QFN semiconductor packages consist of multiple units arranged in an array format. Multiple units are manufactured on one substrate bar and are then divided into single units by sawing through the bar. The bar has the function of facilitating the process of bonding the wires from the die to the package terminals, which is more easily carried out if the package units are supported on a single substrate.
FIG. 1 illustrates the typical construction of QFN semi conductor package. The package comprises a semi conductor die 302 supported on a die attachment pad 201 and connected through wires 202 to interconnection pads 200. The whole assembly is encapsulated in an encapsulation material 300, typically a polymer. Such packages are then placed on motherboards to form part of an electronic circuit.
The process for producing a typical package is illustrated in FIGS. 2 a) to 2 g) and is carried out by first attaching an etched leadframe onto backing tape (FIG. 2 a). FIG. 2 b) illustrates that the semiconductor die is next attached onto the die attachment pads on the leadframe. Electric connection is then created between the semiconductor die and interconnection pads by bonding wirebonds, such as gold wirebonds, between the semiconductor die and interconnection pads. FIG. 2 d) shows that the assembly is then encapsulated to form a package. The backing tape prevents mould bleed of the filler material.
After the encapsulation material has cured the backing tape is removed. This is illustrated in FIG. 2 e). The panel is then mounted on a tape or chuck and sawn with a saw blade to divide the panel into discrete package units. The saw is required to cut through two materials, namely the leadframe material and the encapsulation material. FIG. 2 g) illustrates the final product of semi conductor packages in single units.
Tie bars are also used to hold the units together in a single panel.
These known methods for manufacturing semiconductor packages have problems with limited design flexibility with respect to leadframe positioning and limitations on reducing the size of the package. Semiconductor packages made from this method are also often not sufficiently robust to withstand certain end uses.
A semiconductor package, and a method for making the same, is required that is more flexible in design with respect to the location of the contact pads and die attachment pads and also in terms of the size and weight of the package.

SUMMARY OF THE INVENTION

One aspect of the present invention provides A method of making an electronic package characterised by:
forming a metal base on which to build the components of an electronic package;
applying a mask layer on the base to an area that is not to be occupied by interconnection pads or die attachment pads of the package;
plating layers of metal on the un-masked areas of the base to form the interconnection and die attachment pads;
removing the mask layer;
mounting a semiconductor die to at least one die attachment pad;
electrically connecting the semiconductor die to one or more interconnection pads;
embedding the components on the base in an encapsulation material to form a package;
removing the metal base to leave a package panel; and
cutting the panel into discrete package units.
Another aspect of the invention provides the method claimed in claim 17 characterised by forming the enlarged head by plating the layers of metal forming the interconnection and die attachment pads over and above the top of the mask layer such that the head flares over the mask layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is described further by way of example with reference to the accompanying drawings of which:

FIG. 1 illustrates a prior art QFN semiconductor package in cross section;

FIGS. 2 a) to 2 g) illustrate the steps in manufacturing the QFN semiconductor package;

FIG. 3 a) is a schematic sectional plan view of a semiconductor package according to the present invention;

FIG. 3 b) is a side sectional view of the package of FIG. 3 a);

FIG. 3 c) schematically illustrates in plan an alternate embodiment of the present invention;

FIG. 4 illustrates eight options of plating leadframe material;

FIG. 5 schematically illustrates a side section view a package according to the present invention;

FIG. 6 illustrates a further embodiment of the package of FIG. 5;

FIG. 7 a) illustrates the semiconductor package with wire bonding;

FIG. 7 b) illustrates the semiconductor package with flip chip bonding;

FIGS. 8 a) to 8 e) illustrate a raised embodiment of the semiconductor package;

FIGS. 9 a) to 9 j) illustrate the steps in producing one embodiment of the semiconductor package;

FIGS. 10 a) to 10 m) illustrate the steps in producing another embodiment of the semiconductor package;

FIGS. 11 a) to 11 j) illustrate the steps in producing yet another embodiment of the semiconductor package;

FIGS. 12 a) to 12 m) illustrate the steps in producing yet another embodiment of the semiconductor package; and

FIGS. 13 a) to 13 f) illustrate the steps in producing a component of the semiconductor package.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

One embodiment of an electronic package 10 is illustrated in FIGS. 3 a) and 3 b). The electronic package is based on a quad flat no-lead type package where the leadframe is formed using a plated mask to create interconnection pads 200 and die attachment pads 201 without stamping or etching.
The result is an ultra thin small leadless package that can have a minimum of one die attachment pad and one interconnection pad. By plating a base substrate layer with a mask the pads can be positioned in any desirable configuration (not limited by stamping and etching tools) and can be placed closer together to form smaller packages.
The interconnection pads may be arranged uniformly around a die attachment pad in a single row or in multiple rows (staggered) as illustrated in FIG. 3 c). The interconnection pads are separated by an equal pitch and are electrically connected to the semiconductor die in the package through wirebonds.
The semiconductor package is formed by plating several metal layers onto a base carrier layer 50 by way of electrolysis and defining the location of the metal layers by using a mask layer.
FIG. 9 illustrates the method for forming the semiconductor package. The semiconductor of this embodiment uses wirebond connections.
A flat and elongate metal base 50 is pre-etched to the required dimension depending on the dimensions allowed by the handling equipment. Base 50 forms the base on which the semiconductor package is built (FIG. 9 a). A photo resistant and heat resistant, mask layer 60 is coated at specified locations on base 50 so as to leave exposed only the area to be plated in forming the interconnection and die attachment pads.
FIG. 9 c) illustrates a number of metal layers plated on the metal base 50. The metal layers form the interconnection pads 200 and die attachment pads 201 of the package. These layers correspond to any one of the optional plating constructions illustrated in FIG. 4 discussed in greater detail below.
As shown in FIG. 9 d) mask layer 60 is then stripped away from base 50 to leave the plated segments that will form the interconnection pads 200 and die attachment pads 201.
A semiconductor die 302 is attached on top of each die attachment pad 201 by means of adhesive or other standard techniques. This is illustrated in FIG. 9 e). FIG. 9 f) illustrates that wirebonds 202 are next connected between semiconductor die 302 and interconnection pads 200 to form an electrical connection therebetween (FIG. 9 f).
The entire construction is then encapsulated with an encapsulation material 300, which is typically a polymer to form the package. FIG. 9 g) illustrates encapsulation material 300 covering and filling the spaces inbetween pads 200, 201, semiconductor dies 302 and wirebonds 202. A rectangular package is formed.
Metal base 50 is then etched or removed in an appropriate manner to expose the undersurface of the interconnection pads 200 and die attachment pads 201 embedded in the encapsulation material 300 (FIG. 9 h). The panel construction remaining is then mounted on a tape or chuck then divided by sawing with a saw 65 as illustrated in FIG. 9 i) into individual units to form discrete electronic packages 10 illustrated in FIG. 9 j).
Several alternatives in the configuration of metal layers of the pads are shown in the eight options of FIG. 4. These options illustrate the different materials that may be used to build-up interconnection and die attachment pads in a package. These options illustrate preferred pad material constructions and are not intended to exclude other material selections and combinations that may also be suitable.
The base 50 supports formation of the interconnection pads 200 and die attachment pads 201. It is from this layer that the rest of the package is built upon. After building the pads the base is removed by etching so as to expose the undersides of the interconnection pads 200 and die attachment pads 201. The base layer is therefore made of a metal that is able to be easily etched off. Copper is a suitable material in this respect and is also readily available.
As illustrated in FIG. 4, a solderable metal layer 51 is the first layer to be plated on base 50. This is the layer of the package that will be exposed after the base is etched away. The solderable layer 51 must be of a stable metal with solderable characteristics to allow the package to be soldered to substrates. Accordingly, gold is the preferred solderable metal. A layer of gold or gold strike is illustrated plated on base 50 in all options of FIG. 4.
The pad layer 53 is the next layer of material that is used to build up the major portion of the interconnection pads and die attachment pads. Nickel or copper are preferred materials for forming the pad layer.
The interconnection layer 54 is plated at the last stage of the plating process and provides a finishing layer suitable for electrical interconnection. Gold or silver are both suitable materials to use for the interconnection layer.
The softer metal layers are prone to diffusion at higher temperatures. Therefore a barrier metal layer 52 is sometimes required to prevent two layers of metal diffusing. An example of a good barrier metal is palladium or nickel palladium. Generally this layer is plated onto the gold layer and inbetween the other layers. This also has the benefit of reducing the required thickness of the gold layer.
FIGS. 8 a) to 8 e) illustrate a modification to the above method for making semiconductor packages. The modification illustrated in these Figures is to the interconnection and die attachment pads 200 and 201 which in this embodiment protrude further from the underside of the package 10 than the standard package described above. Compare FIG. 8 a) which illustrates a standard electronic package according to the present invention and FIG. 8 b) illustrating a modified stand-off, or raised package.
The raised package illustrated in FIGS. 8 b) to 8 e) has the benefit of allowing the semiconductor package 10 to be mounted on a substrate, or board 70, in a raised position. This provides for easier attachment of the package to the board and reliable leveling therebetween. The pitch space between the interconnection pads may be reduced and finely adjusted. Extra solder filler may be inserted between the pads to strengthen the bond between the package and the board.
FIGS. 10 a) to 10 m) illustrate the steps in manufacturing the raised package version. The process begins with forming base layer 50 but instead of plating mask layer 60 in the areas not to be formed into pads 200 or 201, first mask layer 61 is plated over the areas on which interconnection and die attachment pads will be formed. Accordingly, the non-pad areas inbetween can be built up as illustrated in FIG. 10 c) by plating a layer of the same metal as is used to make the base 50 (normally copper). This raises the effective thickness of the base at filled pockets 67 inbetween the masked areas. The reasoning for this is that the pockets 67 will be etched or scraped away along with base 50 near the end of the process. Once pockets 67 are filled with base material, the mask layer 61 is removed as shown in FIG. 10 d).
Up to now the steps in the process have been directed to creating a deeper cavity 68 in which to form a thicker interconnection pad or die attachment pad layer. A second masking layer. 60 is then reapplied on top of the filled pockets 67 (FIG. 10 e).
Interconnection pads 200 and die attachment pads 201 are then formed by filling the cavity 68 with the appropriate material, which can be selected from, but not restricted to, one of the options in FIG. 4. This step is illustrated in FIG. 10 f). The pad layer is brought to substantially the same height as the mask layer 60.
FIG. 10 g) illustrates the masks 60 stripped from the construction. A semiconductor die 302 is next attached onto each die attachment pad 201 of each unit carried by the metal base 50 (FIG. 10 h). The wirebonding and encapsulation steps are carried out in a similar manner to that described in FIG. 9.
The base 50 and filler material 67 inbetween the pads 200, 201 is then removed by etching or stripping away so as to leave pads 200, 201 protruding from the underside of the package 10.
As with the previous embodiment the panel is then mounted onto a tape or chuck and sawn into discrete units.
FIG. 7 a) illustrates in cross section the electronic package with wire bonding. In place of wire bonding the package may be constructed using flip chip bonding technologies as illustrated in FIG. 7 b). The flip chip version uses flip chip solder balls 203 rather than wirebonds 202. The semiconductor die 302 spans across the interconnection and die attachment pads 200, 201 with electrical connections formed by the solder balls between the die and the pads. In an alternate embodiment the solder balls may be replaced by metal deposited at the wafer lever (that is above the pad level) in the form of pillar bumps, collar bumps, stud bumps or any other suitable form.
FIGS. 11 a) to 11 j) illustrate the process for producing the semiconductor package using flip chip interconnections. FIGS. 11 a) to 11 d) illustrate the same process steps as the wirebond version illustrated in FIG. 9 a) to 9 d).
FIG. 11 e) illustrates flux or solder 81 deposited or printed on the die attachment pads 201 and interconnection pads 200. This forms the attachment points for the flip chip bumps 80. A semiconductor die 302 having pre-attached flip chip bumps 203 is then flipped so that the bumps are on the underside of the die and attached to the die attachment pads 201 and interconnection pads 200 by way of the flux or solder on these pads (see FIG. 11 f). The entire construction is then passed through a reflow oven to cure the soldered joints which electrically connect the semiconductor die 302 to the pads 200, 201.
FIG. 11 g) shows encapsulation of the construction with encapsulation material 300. In the remaining steps base 50 is removed and the panel divided into discrete units in steps corresponding to FIGS. 9 g) to 9 j).
FIGS. 12 a) to 12 m) illustrate the steps involved in constructing the electronic package using flip chip interconnection and incorporating protruding pads 200, 201 to produce a raised package. In this process the solder points 81 are applied to the interconnection and die attachment pads 200, 201 after the masks 60 have been removed from between pads 200, 201. The remaining steps are a combination of steps illustrated in FIGS. 10 and 11.
FIG. 6 illustrates an embodiment of the semiconductor package 10 which provides a solder finish 204 on the underside of the interconnection or die attachment pads. This allows the package to be directly mounted onto a substrate, such as a motherboard, without having to first deposit or print solder onto the motherboard.
To obtain this solder finish, the package 10 as illustrated in FIG. 5 is taken through a solder dipping process to coat the exposed interconnection pads 200 and die attachment pads 201 with solder. While still attached as a single panel and before being sawn into individual units, the array or packages are held by a dipping jig, dipped into molten solder then removed and cooled. Aside from providing a stable support, the dipping jig also acts as a heat sink to reduce the heat flow from the moltend solder into the package.
FIG. 5 illustrates how the shape of a die attachment pad or an interconnection pad can be formed into a “mushroom” shape which, it has been found, improves the hold of the encapsulation material 300 on the die attachment and interconnection pads 201, 200. The enlarged area of FIG. 5 illustrates in perspective view a single pad having a flared top which, in a stylised manner, resembles a mushroom and hence draws the mushroom reference.
FIG. 5 also illustrates the semiconductor package 10 with the interconnection and die attachment pads embedded in the encapsulation material 300. With the mushroom feature, the pads are less inclined to detach or become dislodged from the encapsulation material.
FIGS. 13 a) to 13 f) illustrate the steps in producing the “mushroom”-shaped interconnection or die attachment pads. FIG. 13 a) begins at the step with base 50 and mask layer 60 already established. FIG. 13 b) shows the first layer of the pads plated onto the base 50. This is the solderable, usually gold, layer. In FIG. 13 c) the pad layer of material is plated on top of the solderable layer to build up the thickness of the pad up and above the height of mask layer 60 so that the material overflows and expands slightly over and onto the mask layer 60 to create a flared mushroom shape. A final interconnection, or bondable, metal layer is plated across the top of the “mushroom” shaped pad 200, 201 by electrolysis.
The described pad construction is the basic construction illustrated in option 1 of FIG. 4. However, other suitable construction shown in FIG. 4 or otherwise may also be used.
The mask layer 60 is then stripped away leaving islands of interconnection pads and die attachment pads having a larger “mushroom” head which assists in locking the pads when embedded in the encapsulating material.
The present semiconductor package is a leadless package developed from a QFN platform. It can be made a very thin and very small restricted only by mask layer dimensions and associated handling equipment. This offers advantages in applications where small size, thickness and weight is desired. The package and method of making the package also allows flexibility in design with respect to leads and contact pads to allow customisation of the package. The pattern of mask layer 60 can easily be changed to suit the purpose. The present package and method remove the dependence of forming the package on a connecting panel bar and using entire bars to hold the units in place until they are divided. Furthermore, base 50 used in manufacturing the package effectively prevents mould bleed during manufacturing.
It is to be understood that, if any prior art publication is referred to herein, such reference does not constitute an admission that the publication forms a part of the common general knowledge in the art, in Malaysia or any other country.
It will be understood to persons skilled in the art of the invention that many modifications may be made without departing from the scope of the invention.

Claims

1. A method of making an electronic package (10) characterised by:

forming a metal base (50) on which to build the components of an electronic package;

applying a mask layer (60) on the base to an area that is not to be occupied by interconnection pads (200) or die attachment pads (201) of the package;

plating layers of metal on the un-masked areas of the base to form the interconnection and die attachment pads (200, 201);

removing the mask layer;

mounting a semiconductor die (302) to at least one die attachment pad (201);

electrically connecting the semiconductor die (302) to one or more interconnection pads (200);

embedding the components on the base in an encapsulation material (300) to form a package;

removing the metal base (50) to leave a package panel; and

cutting the panel into discrete package units.

2. The method of claim 1 characterised by applying a mask layer (60) that is photo resistant and/or heat resistant.

3. The method of claim 1 or claim 2 characterised by forming the interconnection and die attachment pads by first plating a solderable layer (51) on the base (50), followed by plating a pad layer (53) on the solderable layer and plating an interconnection layer (54) on the pad layer.

4. The method of claim 3 characterised by plating a barrier layer (52) between the solderable layer (51) and pad layer (53) and/or between the pad layer (53) and interconnection layer (54).

5. The method claimed in claim 3 or claim 4 characterised by combining two or more metals to form a layer.

6. The method claimed in any one of claims 3 to 5 characterised by using copper as the material for the base.

7. The method claimed in any one of claims 3 to 6 characterised by using gold or gold strike as the material for the solderable layer.

8. The method claimed in any one of claims 3 to 7 characterised by using nickel or copper for the material for the pad layer.

9. The method claimed in any one of claim 3 to 8 characterised by using gold or silver as the material for the interconnection layer.

10. The method claimed in any one of claims 3 to 9 characterised by using palladium or nickel palladium as the material for the barrier layer.

11. The method claimed in any one of the preceding claims characterised by electrically connecting the semiconductor die to one or more interconnection pads using wirebonds (202).

12. The method claimed in any one of claims 1 to 10 characterised by electrically connecting the semi conductor die to one or more interconnection pads using flip chip bumps (203) pre-attached to the semiconductor die.

13. The method claimed in claim 12 characterised by after removing the mask layer depositing flux or solder (81) on at least one interconnection pad (200) and at least one die attachment pad (201); and

mounting a flip chip semiconductor die (302) onto the flux or solder to form an electrical connection between the semiconductor die and at least one interconnection pad.

14. The method claimed in any one of the preceding claims characterised by forming interconnection and die attachment pads protruding from the underside of the package by carrying out the following steps inbetween the steps of forming a metal base and applying a mask layer (60):

applying an additional mask layer (61) on the base (50) to the areas that are to be occupied by the interconnection and die attachment pads of the package;

plating the remaining exposed areas of the base with the metal base material (50) to increase the thickness of the base inbetween where the interconnection and die attachment pads are to be formed; and

removing the additional mask layer (61).

15. The method claimed in any one of the preceding claims characterised by applying a solder finish (204) to the exposed interconnection and die attachment pads on the underside of the package after removal of the base.

16. The method claimed in claim 15 characterised by mounting the package panel in a dipping jig and dipping the underside of the package into molten solder before cutting the panel into discrete package units.

17. The method claimed in any one of the preceding claims characterised by forming the interconnection pads and die attachment pads with an enlarged “mushroom” head.

18. The method claimed in claim 17 characterised by forming the enlarged head by plating the layers of metal forming the interconnection and die attachment pads over and above the top of the mask layer such that the head flares over the mask layer.

19. An semiconductor package (10) made according to the method of claim 1 characterised in that the package comprises a semi conductor die (302) mounted on a die attachment pad (201) and electrically connected to at least one interconnection pad (200) by an electrical connection, all embedded in an encapsulation material (300).

20. The semiconductor package claimed in claim 19 characterised in that the mask layer (60) used in making the package is photo resistant and/or heat resistant.

21. The semiconductor package claimed in claims 19 or 20 characterised in that the layers of metal forming the interconnection and die attachment pads include a solderable layer (51), a pad layer (53) and an interconnection layer (54).

22. The semiconductor package claimed in claim 21 characterised in that a barrier layer (52) is plated inbetween any two of the solderable layer, interconnection layer and pad layer.

23. The semiconductor package claimed in either claim 21 or claim 22 characterised in that the base is made of copper.

24. The semiconductor package claimed in any one of claims 21 to 23 characterised in that the solderable layer is made of gold or gold strike.

25. The semiconductor package claimed in any one of claims 21 to 24 characterised in that the pad layer is made of nickel or copper.

26. The semiconductor package claimed in any one of claims 21 to 25 characterised in that the interconnection layer is made of gold or silver.

27. The semiconductor package claimed in any one of claims 21 to 26 characterised in that the barrier layer is made of palladium or nickel palladium.

28. The semiconductor package claimed in any one of claims 21 to 27 characterised in that the base is made of copper.

29. The semiconductor package claimed in any one of claims 21 to 28 characterised in that the electrical connection is a wirebond (202) or a flip chip bump (203).

30. The semiconductor package claimed in any one of claims 21 to 29 characterised in that the interconnection pads and die attachment pads protrude from the underside of the package.

31. The semiconductor package claimed in any one of claims 21 to 30 characterised in that a solder finish (204) is applied to the exposed interconnection pads and die attachment pads on the underside of the package.

32. The semiconductor package claimed in any one of claims 21 to 31 characterised in that the interconnection pads and die attachment pads are shaped with an enlarged head to increase the hold on the pads in the encapsulated package.