US20080237896A1 - Wafer level packages capable of reducing chipping defect and manufacturing methods thereof - Google Patents
Wafer level packages capable of reducing chipping defect and manufacturing methods thereof Download PDFInfo
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- US20080237896A1 US20080237896A1 US12/076,903 US7690308A US2008237896A1 US 20080237896 A1 US20080237896 A1 US 20080237896A1 US 7690308 A US7690308 A US 7690308A US 2008237896 A1 US2008237896 A1 US 2008237896A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Definitions
- Embodiments of the present invention relate to semiconductor chip packages, and methods of manufacturing thereof. More particularly, embodiments of the present invention relate to wafer level chip packages and methods of manufacturing wafer level chip packages that are capable of providing improved protection against damage, e.g., during handling and/or subsequent wafer and/or chip processing, and reducing chipping and/or cracking defects.
- semiconductor chip packages are provided to physically protect a semiconductor chip while establishing input and output connection portion(s) for connecting the semiconductor chip to other device(s).
- semiconductor chip packages As electronic devices are becoming smaller and more complex, it is desirable to package a semiconductor chip as soon as possible after the semiconductor chip is formed to help protect the electronic devices of the semiconductor chip from damage that may occur during subsequent handling, etc.
- the semiconductor chips of a wafer are first completely separated from the wafer before being packaged. In such cases, however, the semiconductor chips are susceptible to damage that may occur during the dicing process itself, i.e., process for separating the semiconductor chip(s) from the wafer.
- wafer level packaging is employed to package the semiconductor chip(s) while the semiconductor chip(s) are still on the wafer.
- Wafer level packaging may offer many advantages, e.g., protection during dicing, relatively small, e.g., thinner, package size, relatively lighter package weight, and/or reduced manufacturing cost, etc.
- conventional wafer level packages fail to cover all sides, e.g., all six sides, of a semiconductor chip, and/or conventional methods of wafer-level packaging semiconductor devices generally employ, e.g., multiple depositing steps and/or multiple planarization steps. Therefore, improved wafer level packages and simplified methods of packaging semiconductor chips at the wafer level are desired.
- Embodiments of the present invention are therefore directed to semiconductor packages and methods of manufacturing such semiconductor packages, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
- a packaged semiconductor device including a substrate including at least one device layer and at least one connector arranged thereon, and a resin cover covering each side of the substrate, wherein the resin cover on at least one side of the substrate may include an opening exposing the connector and the resin cover on at least one other side of the substrate may expose a portion of the substrate.
- the resin cover may be an outermost layer on each of the sides of the substrate. Each outer surface of the resin cover may be substantially or completely planar. A portion of the resin cover exposing the portion of the substrate may abut a sidewall of the exposed portion of the substrate, and an outer surface of the abutting portion of the resin cover may extend along a same plane as a plane along which a surface of the exposed portion of the substrate extends.
- the substrate may include a top side, a bottom side, and a plurality of lateral sides, and the top side may include a plurality of the connectors arranged thereon, the resin cover on the top side may include a plurality of openings respectively exposing the connectors, and the resin cover on the another side of the substrate may be on at least one of the lateral sides, and may expose a portion of at least one of the lateral sides of substrate.
- the resin cover may expose a portion of each of the lateral sides of the substrate.
- the resin cover may expose a portion of only two of the lateral sides of the substrate, the two lateral sides may be opposite each other.
- the resin cover may expose a portion of only one of the lateral sides of the substrate.
- the resin cover may completely encapsulate the substrate.
- the resin cover may be a single continuous layer.
- the exposed portion of the substrate may correspond to a lateral corner portion of the substrate.
- a portion of the resin cover on the side of the substrate including the at least one connector may surround a lower portion of the connector, and may have a height of about 10% to about 80% of a height of the at least one connector along a direction substantially perpendicular to a plane along which a surface of the substrate on which the connector is arranged extends.
- the substrate may have been cut from a wafer along a scribe lane of the wafer, the scribe lane having a width, such that the substrate may be a portion of the semiconductor wafer, and a thickness, relative to the other side of the substrate, of at least a portion of the resin cover abutting the at least one exposed portion of the substrate may be equal to or less than about 50% of the width of the scribe lane.
- the packaged semiconductor may be an MCP.
- At least one of the above and other features and advantages of the present invention may be separately realized by providing a method of manufacturing a wafer level package, including forming at least one opening in a portion of a wafer surrounding a predetermined sub-portion of the wafer corresponding to a device to be separated from a remaining portion of the wafer, the opening completely extending from a top side of the wafer to a bottom side of the wafer, and the wafer sub-portion remaining connected to the remaining portion of the wafer by at least one wafer connecting portion, covering the wafer sub-portion with a resin cover, wherein the resin cover may fill the opening formed in the portion of the wafer surrounding the wafer sub-portion and cover each side of the wafer sub-portion, and completely separate the wafer sub-portion from the remaining portion of the wafer along a boundary defined by the at least one wafer connecting portion and the portion of resin cover corresponding to the filled opening.
- At least one side of the wafer sub-portion may include a connector arranged thereon, and covering the wafer sub-portion may include completely covering the side of the wafer sub-portion having the at least one connector arranged thereon, except for the at least one connector arranged thereon.
- Covering the wafer sub-portion may include completely encapsulating the wafer sub-portion, other than the at least one connector of the device and a separated side of the wafer connecting portion, wherein the separated side may correspond to the side of the wafer connecting portion exposed when separating the wafer sub-portion from the remaining portion of the wafer.
- Covering the wafer sub-portion with the resin cover may include one of dipping the wafer in a thermosetting epoxy resin solution, and applying an epoxy layer using a spin coating process. Applying the epoxy layer using a spin coating process may include coating at least a top portion of the at least one connector with a coating repellent before covering the wafer sub-portion with the resin cover.
- Applying the epoxy layer using a spin coating process may include, during the spin coating process using a spin chuck, temporarily elevating the wafer sub-portion away from an upper surface of the spin chuck to cover the bottom side of the wafer while simultaneously filling the opening and covering each of the other sides of the wafer sub-portion.
- Dipping the wafer in a thermosetting epoxy resin solution may include partially dipping the wafer in the epoxy resin solution such that, other than an upper portion of the at least one connector, a remainder of the wafer is dipped into the epoxy resin solution.
- Forming the at least one opening may include using at least one of a diamond blade and a laser having a first width
- completely separating the wafer sub-portion may include using at least one of a diamond blade and a laser having a second width, wherein the first width may be greater than the second width
- Forming the at least one opening may include removing a portion of the wafer in a scribe lane of the wafer, and a thickness of a remaining portion of the resin cover relative to the respective side of the wafer-sub portion may be equal to or less than about 50% of a width of the scribe lane of the wafer.
- Covering the wafer sub-portion with the resin cover may be performed in a single covering process such that the opening formed in the portion of the wafer surrounding the wafer sub-portion and each side of the wafer sub-portion may be simultaneously or substantially simultaneously filled and covered, respectively.
- the method may further include, before covering or before completely separating, stacking at least another wafer on the wafer, wherein the at least another wafer may include another device to be integrated with the device on the wafer.
- FIG. 1 illustrates a top-side view of a first exemplary embodiment of a wafer level package of a semiconductor chip
- FIG. 2 illustrates a top-side view of a second exemplary embodiment of a wafer level package of a semiconductor chip
- FIG. 3 illustrates a top-side view of a third exemplary embodiment of a wafer level package of a semiconductor chip
- FIG. 4 illustrates a top-side view of fourth exemplary embodiment of a wafer level package of a semiconductor chip
- FIG. 5 illustrates a top view of an exemplary wafer including a plurality of semiconductor chips
- FIG. 6 illustrates a flow-chart of an exemplary method for fabricating a wafer level package according to one or more aspects of the invention
- FIG. 7 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package of FIG. 1 ;
- FIG. 8 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package of FIG. 2 ;
- FIG. 9 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package of FIG. 3 ;
- FIG. 10 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package of FIG. 4 ;
- FIGS. 11 , 12 , 13 and 14 illustrate additional stages in the exemplary method for fabricating the wafer level packages of FIGS. 1 through 4 according to one or more aspects of the invention
- FIGS. 15 , 16 , 17 and 18 illustrate stages in a second exemplary method for fabricating a wafer level package according to one or more aspects of the invention
- FIG. 19 illustrates an exemplary memory card that may be implemented according to one or more aspects of the invention.
- FIG. 20 illustrates an exemplary electronic system that may be implemented according to one or more aspects of the invention.
- Korean Patent Application No. 10-2007-0031931 filed on Mar. 30, 2007, in the Korean Intellectual Property Office, and entitled: “WAFER LEVEL PACKAGE PREVENTING A CHIPPING DEFECT AND MANUFACTURING METHOD THEREOF,” is incorporated by reference herein in its entirety.
- FIG. 1 illustrates a first exemplary embodiment of a wafer level package 100 A of a semiconductor chip 104 (see FIGS. 5 and 7 ).
- the wafer level package 100 A may include a cover 112 , which may be formed of, e.g., a resin, other molding materials known in art, etc.
- the resin may include, e.g., an epoxy resin, a phenolic resin, etc.
- the semiconductor chip 104 covered by the wafer level package 100 A may include one or more connectors 110 , and at least one protruding portion 116 A exposed by the cover 112 of the wafer level package 100 A.
- the connector(s) 110 may be provided on a first side, e.g., a top side, of the semiconductor chip 104
- the protruding portion(s) 116 A may be provided on a different side(s), e.g., lateral side(s), of the semiconductor chip 104 .
- Embodiments of the invention are not, however, limited to such a configuration.
- the connector(s) 110 may be arranged on at least one side of the semiconductor chip 104 , and may be employed to connect the semiconductor chip 104 to external devices (not shown).
- the connector(s) 110 may include conductive material, and may be, e.g., a solder ball, a solder bump, a Cu bump (or Cu pillar), or Cu+ solder bump/pillar.
- the protruding portion(s) 116 A may be provided on at least one side of the semiconductor chip 104 , and may correspond, e.g., to a portion of a substrate (not shown) of the semiconductor chip 104 that protrudes beyond other portion(s) of the respective side of the substrate. That is, e.g., the protruding portion(s) 116 A may protrude beyond all other portion(s) of the respective side of the substrate from which it protrudes. More particularly, e.g., in some embodiments of the invention, the respective side(s) of the substrate including the protruding portion(s) 116 A may be substantially or completely planar, but for the protruding portion(s) 116 A protruding therefrom.
- the substrate may be, e.g., a respective portion of a semiconductor wafer 102 (see FIG. 5 ) such as a silicon wafer corresponding to the semiconductor chip 104 , i.e., a portion of the semiconductor wafer diced from a remaining portion of the semiconductor wafer on which a plurality of semiconductor chips 104 may have been formed.
- the protruding portion(s) 116 A may serve to help protect the semiconductor chip 104 even after the semiconductor chip 104 is packaged. That is, e.g., together with the cover 112 , the protruding portion(s) 116 A may serve to protect the semiconductor chip 104 from damage.
- the semiconductor chip 104 has a rectangular shape including six sides, i.e., a top side, a bottom side, and four lateral sides extending between the top and bottom sides.
- the top side may correspond to an upper surface extending along a XY plane
- the bottom side may correspond to a lower surface, i.e., lower relative to a Z axis, extending along another XY plane
- the lateral sides may extend along different YZ or XZ planes.
- embodiments of the invention are not limited thereto.
- the semiconductor chip may have a substantially circular or rounded shape along the XY plane, and in such cases, may have, e.g., a single continuous lateral surface.
- the connector(s) 110 are provided on the top side of the semiconductor chip 104 , and the bottom side of the semiconductor chip is substantially or completely planar.
- Embodiments of the invention are not, however, limited thereto, and persons of ordinary skill in the art will appreciate the applicability of one or more aspects of the invention to a semiconductor chip irrespective of a shape thereof and/or the side(s) of the semiconductor chip including the connector(s) 110 and/or protruding portion(s) 116 A.
- the protruding portion(s) 116 A may be provided at various portions, substantially central portion, corner portion, substantially left or right portion, etc., of the respective side of the semiconductor chip 104 .
- the protruding portions 116 A are provided at substantially central portions of the respective lateral sides of the semiconductor chip 104 .
- the protruding portion(s) 116 A may occupy a relatively small portion of the respective side of the semiconductor chip 104 from which they protrude such that a majority of the sides of the semiconductor chip 104 are covered by the cover 112 .
- only one protruding portion 116 A may be provided on the semiconductor chip 104 , while in other embodiments, e.g., more than one protruding portions 116 A may be provided.
- at least one protruding portion 116 A may be provided on two sides, e.g., two opposing lateral sides, of the semiconductor chip 104 .
- a plurality of protruding portion 116 A may be provided on only one lateral side of the of the semiconductor chip 104 .
- a plurality of the protruding portions 116 A may be provided on a plurality of lateral sides of the semiconductor chip 104 .
- a single and/or a plurality of the protruding portions 116 A may be provided on each lateral side of the semiconductor chip 104 .
- the exemplary wafer level package 100 A illustrated in FIG. 1 includes one protruding portion 116 A at a central portion of each lateral side of the semiconductor chip 104 and/or a central portion of each lateral side of the cover 112 .
- Embodiments of the invention are not, however, limited thereto.
- an exposed surface of the protruding portion(s) 116 A i.e., surface(s) exposed by the cover 112
- a surface may be substantially planar
- the respective surface may not be a smooth surface, i.e., the surface may be rugged or rough.
- various surfaces may be described as being substantially and/or completely planar, embodiments of the invention are not limited thereto.
- the respective portion(s) of the cover 112 may abut, and substantially and/or completely align with the respective protruding portion(s) 116 A so as to form a substantially continuous surface. That is, e.g., in some embodiments of the invention, but for the connector(s) 110 , the resulting wafer level package 100 A may have substantially and/or completely planar surfaces as a result of respective portion(s) of the cover 112 , alone or in combination with the respective protruding portion(s) 116 A.
- the substantially continuous surface e.g., two surfaces arranged close to and/or abutting each other, resulting from the abutting arrangement of the respective outer surface portion(s) of the cover 112 and the respective protruding portion(s) 116 A may be substantially and/or completely planar.
- Embodiments of the invention are not limited to such planar and/or completely planar surfaces for the wafer level package 100 A and/or cover 112 . That is, e.g., the protecting nature of the cover 112 , may not depend on the respective surface(s) of the cover 112 being substantially and/or completely planar, i.e., may rather depend on a thickness of the cover 112 .
- a relatively precise tool or method may be employed to completely separate the semiconductor chip 104 from the wafer 102 , the tool or method need not necessarily establish a smooth or planar surface.
- the protruding portion 116 A may correspond to a substantially rectangular shaped portion of the substrate of the semiconductor chip 104 , and as shown in FIG. 1 , other than the exposed surface(s) of the protruding portion 116 A, which may be aligned with the respective outer surface portion(s) of the cover 112 , the protruding portion(s) 116 (A) may be completely surrounded by the cover 112 .
- the cover 112 may substantially completely and/or completely encapsulate the semiconductor chip 104 .
- respective portions of the cover 112 may support and/or surround the connectors 110 , and may improve joint reliability of the connector(s) 110 . That is, e.g., lower portions of the connector(s) 110 may be surrounded respective portions of the cover 112 .
- the cover 112 may have a height H 1 (see FIG. 13 ) of about 10% to about 80% of a height H 2 (see FIG. 13 ) of the connector 110 relative to a respective surface, e.g., top surface, of the semiconductor chip 104 .
- the cover 112 may have a height H 1 of about 10% to about 80% of the height H 2 of the connector 110 along the Z direction. More particularly, if, e.g., the height H 1 of the cover 112 is more than about 80% of the height H 2 of the connector 110 , electrical connectivity characteristics of the connector 110 may be threatened, and if, e.g., the height H 1 of the cover 112 is less than about 10% of the height H 2 of the connector 110 , the cover 112 may not adequate serve to improve joint reliability of the connector 110 to the semiconductor chip 104 .
- a protruding height, i.e., thickness, of protruding portion(s) 116 A relative to the respective side of the substrate may be no more than about 50% of a width W s of scribe lane 106 (see FIG. 7 ).
- the semiconductor chip 104 may be diced, i.e., separated from, the substrate, e.g., semiconductor wafer, by cutting within the scribe lane(s) 106 surrounding the semiconductor chip 104 . More particularly, e.g., if two semiconductor dies are formed adjacent to each on the substrate with a respective scribe lane therebetween, the substrate may be diced such that about 50% of the scribe lane remains on each of the resulting semiconductor chips 104 . Further, in such embodiments, respective portion(s) of the cover 112 may have a thickness of less than about 50% of the width W s of the corresponding scribe lane 106 .
- FIG. 2 illustrates a second exemplary embodiment of a wafer level package 100 B of a semiconductor chip 104 A (see FIG. 8 ) including at least one protruding portion(s) 116 B, arranged differently than protruding portion(s) 116 A of the first exemplary embodiment illustrated in FIG. 1 .
- FIG. 8 illustrates a second exemplary embodiment of a wafer level package 100 B of a semiconductor chip 104 A (see FIG. 8 ) including at least one protruding portion(s) 116 B, arranged differently than protruding portion(s) 116 A of the first exemplary embodiment illustrated in FIG. 1 .
- the wafer level package 100 B may include a cover 112 A, and the protruding portion(s) 116 B of the semiconductor substrate may be arranged at edge, e.g., corner, portion(s) of the semiconductor chip 104 A.
- edge e.g., corner
- at least one corner portion of the cover 112 A may correspond to an exposed portion of the substrate of the semiconductor chip 104 A.
- each corner portion of the cover 112 A may include an exposed portion of the substrate of the semiconductor chip 104 A.
- each of the four lateral corners of the wafer-level package 100 B may include a portion of the cover 112 A and a respective exposed portion of the substrate of the semiconductor chip 104 A.
- FIG. 3 illustrates a third exemplary embodiment of a wafer level package 100 C of a semiconductor chip 104 B (see FIG. 9 ) including at least one protruding portion(s) 116 C, arranged differently than protruding portion(s) 116 A of the first exemplary embodiment illustrated in FIG. 1 .
- the first exemplary wafer level package 100 A illustrated in FIG. 1 and the third exemplary embodiment of the wafer level package 100 C will be described below.
- the wafer level package 100 C may include a plurality of protruding portions 116 C and a cover 112 B.
- the protruding portions 116 C may be arranged on opposing lateral sides of the cover 112 B or opposing lateral sides of the semiconductor chip 104 B. More particularly, e.g., the exemplary wafer level package 100 C illustrated in FIG. 3 includes two protruding portions 116 C arranged at substantially central portions of two opposing lateral sides of the cover 112 B, i.e., corresponding to substantially central portions of two opposing lateral sides of the semiconductor chip 104 B.
- FIG. 4 illustrates a fourth exemplary embodiment of a wafer level package 100 D of a semiconductor chip 104 C (see FIG. 10 ) including at least one protruding portion(s) 116 D, arranged differently than protruding portion(s) 116 A of the first exemplary embodiment illustrated in FIG. 1 .
- first exemplary wafer level package 100 A illustrated in FIG. 1 and the fourth exemplary embodiment of the wafer level package 100 D will be described below.
- the wafer level package 100 D may include protruding portion(s) 116 D and a cover 112 C.
- the protruding portion(s) 116 D may be arranged off-center from, e.g., substantially to a left or right side of a respective lateral side of the cover 112 C or substantially to a left or right side of a respective lateral side of the semiconductor chip 104 C.
- the exemplary wafer level package 100 D illustrated in FIG. 4 includes a single protruding portion 116 D substantially to a left or right side of a lateral side of the cover 112 C.
- the single protruding portion 116 D may be arranged at a substantially central portion or a corner portion of the cover 112 C.
- FIGS. 1 through 4 may be employed.
- FIGS. 5 through 14 An exemplary method of fabricating a wafer level package according to one or more aspects of the invention will be described below with reference to FIGS. 5 through 14 .
- FIG. 5 illustrates a top view of a wafer 102 including a plurality of semiconductor chips 104 .
- the plurality of semiconductor chips 104 i.e., semiconductor dies corresponding to respective semiconductor chips 104
- the semiconductor chips 104 may be diced, i.e., separated, from a remaining portion of the wafer 102 by, e.g., cutting or breaking within the scribe lane 106 (see FIG. 7 ) surrounding each semiconductor chip 104 .
- the respective semiconductor chips 104 may each include a portion of the wafer 102 as the substrate of the semiconductor chip 104 .
- the wafer 102 may be, e.g., a semiconductor wafer such as a silicon wafer.
- FIG. 6 illustrates a flow-chart of an exemplary method for fabricating a wafer level package according to one or more aspects of the invention
- FIG. 7 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package of FIG. 1
- FIG. 8 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package of FIG. 2
- FIG. 9 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package of FIG. 3
- FIG. 10 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package of FIG. 4
- FIGS. 11 , 12 , 13 and 14 illustrate additional stages in the exemplary method for fabricating the wafer level packages of FIGS. 1 through 4 according to one or more aspects of the invention.
- fabricating the wafer level package 100 A may begin at step S 60 during which a wafer 102 including at least one semiconductor chip 104 formed thereon may be provided.
- the exemplary method may then proceed to step S 64 during which at least one opening 108 A may be formed in a portion of the wafer 102 surrounding the semiconductor chip 104 to partially separate the semiconductor wafer 104 from a remaining portion of the wafer 102 .
- the opening(s) 108 A may completely extend through a thickness of the wafer 102 , e.g., completely from the top side of the wafer 102 to the bottom side of the wafer 102 along the Z direction (e.g., a peek-hole like opening through the wafer 102 enabling one to see something arranged below the wafer 102 from a point above the wafer 102 ).
- the opening(s) 108 A may extend completely through a thickness of the wafer 102
- the opening(s) 108 A define at least one connecting portion 136 for keeping the semiconductor chip 104 partially connected to the remaining portion of the wafer 102 at this stage in exemplary the wafer level package fabricating method. At least some of the connecting portion 136 may be shared between two or more adjacent ones of the semiconductor chips 104 on the wafer 102 .
- the opening(s) 108 A may be formed within the scribe lanes 106 surrounding the respective semiconductor chip 104 .
- the opening(s) 108 A may be formed by, e.g., sawing corresponding portion(s) of the wafer 102 using, e.g., a laser, a diamond blade, or other known cutting/sawing materials and/or methods.
- a width of the opening(s) 108 A may be substantially the same as or less than the width W s of the scribe lane 106 , e.g., a first cutting width of a first laser cutting step may be substantially the same as or less than the width W s of the scribe lane 106 .
- the openings 108 A may correspond to one or more of the semiconductor chips 104 .
- the openings 108 A may extend from one lateral side of the wafer 102 to an opposing lateral side of the wafer 102 and may be associated with a plurality of semiconductor chips 104 arranged in, e.g., a row or column, while in some other embodiments, the openings 108 A may be associated with, e.g., one, two or four semiconductor chips 104 .
- the opening(s) 108 A may have various shapes depending on an arrangement of the at least one protruding portion 116 A to be provided. More particularly, e.g., the openings 108 A may be provided to form the wafer level package 100 A of FIG. 1 .
- the openings 108 A may form the connecting portion 136 on each lateral side of the semiconductor chip 104 .
- a total of four connecting portions 136 may be provided as a result of, e.g., respective portions of, e.g., four openings 108 A partially surrounding the semiconductor chip 104 .
- the connecting portions 136 may be provided at a substantially central portion of each lateral side of the semiconductor chip 104 .
- Embodiments of the invention are not, however, limited to such an arrangement and/or number of openings 108 A and/or connecting portions 136 .
- openings 108 B may be provided to form the wafer level package 100 B of FIG. 2 .
- the openings 108 B illustrated in FIG. 8 may also extend completely through a thickness of the wafer 102 .
- the openings 108 B may form, e.g., a connecting portion 136 A at each corner of the semiconductor wafer 104 A.
- connecting portions 136 A may be at least partially defined as a result of, e.g., respective portions of, e.g., four openings 108 B partially surrounding the semiconductor chip 104 A.
- the connecting portions 136 A may be provided at, e.g., each lateral corner portion of the semiconductor chip 104 A.
- openings 108 C may be provided to form the wafer level package 100 C of FIG. 3 .
- the openings 108 C illustrated in FIG. 9 may also extend completely through a thickness of the wafer 102 .
- the openings 108 C may form, e.g., a connecting portion 136 B at opposing lateral sides of the semiconductor wafer 104 B.
- two connecting portions 136 B may be defined as a result of, e.g., respective portions of, e.g., two openings 108 C partially surrounding the semiconductor chip 104 B.
- the connecting portions 136 B may be provided at, e.g., central portions of the respective lateral opposing sides of the semiconductor chip 104 A.
- openings 108 D may be provided to form the wafer level package 100 D of FIG. 4 .
- the openings 108 D illustrated in FIG. 10 may also extend completely through a thickness of the wafer 102 .
- the openings 108 D may form, e.g., a connecting portion 136 C at one lateral side of the semiconductor wafer 104 C. More particularly, in this exemplary embodiment, a single connecting portion 136 C may be defined as a result of a single opening 108 D partially surrounding the semiconductor chip 104 C.
- the connecting portion 136 C may be provided at, e.g., a central portion or a left or right side portion of the lateral side of the semiconductor chip 104 C. That is, in some embodiments of the invention, e.g., a single opening, such as opening 108 D, may be formed to define a single connecting portion 136 C for each of the semiconductor chips 104 C on the wafer 102 .
- the exemplary method may then proceed to step S 68 .
- the semiconductor chip e.g., 104 , 104 A, 104 B, 104 C, may be covered with, e.g., a resin.
- each side of the semiconductor chip e.g. 104 , 104 A, 104 B, 104 C may be covered with resin and the respective opening(s), e.g., 108 A, 108 B, 108 C, 108 D, may be filled.
- a thickness of the resin on respective sides of the semiconductor chip e.g., 104 , 104 A, 104 B, 104 C, may be substantially uniform, while in some other embodiments, a thickness of the resin may vary on some or all sides of the semiconductor chip, e.g., 104 , 104 A, 104 B, 104 C.
- each side of the semiconductor chip e.g., 104 , 104 A, 104 B, 104 C may be completely covered with the resin, as shown in FIGS. 1 through 4 , upper portions of the respective connectors 110 remain exposed.
- the remaining steps of the exemplary method will be described with reference to the exemplary wafer level package 100 A illustrated in FIG. 1 .
- the method described may be used to form any of the described exemplary wafer level packages 100 A, 100 B, 100 C, 100 D and other embodiments of the invention.
- FIG. 11 illustrates an exemplary method of covering the semiconductor chip 104 with resin by dipping the wafer 102 including semiconductor chips 104 , including opening(s) 108 in a bath 120 containing, e.g., epoxy resin 122 , i.e., a thermosetting polymer.
- the epoxy resin 122 may include, e.g., a catalyzing agent, i.e., hardener, such that the cover 112 may be formed when the wafer 102 is covered by the epoxy resin 122 . More particularly, the wafer 102 may be partially dipped in the epoxy resin 122 such that upper portion(s) of the connector(s) 110 may remain resin-free, i.e., exposed.
- embodiments of the invention may provide a simplified method of substantially completely encapsulating the semiconductor chip(s) 104 , e.g., completely encapsulating the semiconductor chip(s) 104 except for the connector(s) 110 and the at least one connecting portion 136 , in a single covering step.
- the bath 120 may be vibrated while the wafer 102 is dipped therein to help ensure that the epoxy resin 122 covers all sides of the semiconductor chip(s) 104 and fills, e.g., completely fills, the opening(s) 108 A surrounding the semiconductor chip(s) 104 .
- a dipping method is illustrated in FIG. 11 for covering the semiconductor chip 104 with, e.g., the resin
- other methods of covering the semiconductor chip 104 may be employed. More particularly, e.g., other known methods for simultaneously covering all sides of the semiconductor chip 104 in a single covering step may be employed.
- FIG. 12 illustrates a cross-sectional view of the wafer 102 after covering all the sides of the semiconductor chip(s) 104 , i.e., after the covering step S 68
- FIG. 13 illustrates a more detailed cross-sectional view of a portion of the wafer 102 after the covering step S 68
- the cover 112 may substantially completely encapsulate the semiconductor chip(s) 104 , except for the connector(s) 110 and the at least one connecting portion 136 .
- the height H 1 of the cover may be about 10% to about 80% of the height H 2 of the connector 110 .
- step S 68 after covering all the sides of the semiconductor chip(s) 104 on the wafer 102 , i.e., step S 68 , the method may proceed to step S 72 .
- step S 72 the semiconductor chip(s) 104 may be completely separated from the wafer 102 .
- FIG. 14 illustrates a cross-sectional view of the wafer 102 after covering all the sides of the semiconductor chip(s) 104 , i.e., after the covering step S 68 , including second cutting boundary 114 .
- Another cutting step employing, e.g., a laser or diamond blade, may be performed to completely separate the semiconductor chip(s) 104 by cutting along the respective cutting boundary 114 .
- the cutting boundary 114 may correspond to an imaginary predetermined line, lane or region between, e.g., the respective semiconductor chip(s) 104 .
- portions of the respective connecting portion(s) 136 may correspond to the protruding portion(s) 116 A.
- the width W s of the scribe lane 106 may be substantially the same as or less than the width W s of the scribe lane 106 .
- a second cutting width may be less than the first cutting width.
- step S 72 may be carried out so as to provide the resulting portion of the cover 112 , corresponding to where the resin 122 filled the opening(s) 108 , with a sufficient width to protect the semiconductor chip 104 a from damage, e.g., external impact. That is, a relationship between the first cutting width and the second cutting width may determine a distance that the resulting protruding portion(s) 116 A may protrude from the respective side(s) of the semiconductor chip 104 , and thus, may determine an efficacy of the protruding portion 116 A as a protection member.
- a width of the resulting protruding portion 116 A of the cover 112 after step S 72 may be about 30 ⁇ m.
- the exemplary method may then be complete, i.e., step S 76 .
- FIGS. 15 , 16 , 17 and 18 illustrate stages in a second exemplary method for fabricating a wafer level package according to one or more aspects of the invention. In general, only differences between the exemplary embodiment illustrated in FIGS. 15-18 and the exemplary embodiment described above will be described below.
- the resin coating process includes a spin coating method instead of the dipping method.
- the process may begin by forming a coating repellent 211 on upper portions of each connector 210 provided on semiconductor chip 204 formed on a wafer 202 .
- a thickness of the coating repellent 211 on the upper portion of each connector 210 may not exceed about 50% of a height of the connector 210 , e.g., a distance that the connector 210 projects above a top surface of the wafer 202 .
- At least one opening 208 may be formed in the wafer 202 around the respective semiconductor chip 204 .
- the opening 208 may correspond, e.g., to any of the exemplary openings 108 A, 108 B, 108 C, 108 D described above.
- a spin coating process may be performed to coat all sides of the semiconductor chip 204 during a single coating step.
- the wafer 202 may be arranged on a chuck (not shown) and may be spun while resin is deposited thereon. While the wafer 202 is being spun by the chuck, the wafer may be slightly elevated above a surface of the chuck such that the resin may coat a bottom surface of the wafer 202 while coating a top surface thereof and filling, e.g., completely filling, the opening(s) 208 to form a cover 212 .
- the cover 212 may substantially completely encapsulate the semiconductor chip 204 , except for the connector(s) 210 and at least one protruding portion (not shown) thereof.
- the semiconductor chip(s) 204 may be completely separated from the wafer 202 by a second cutting step along a cutting boundary 214 using, e.g., a laser or a diamond blade having a width that less than a width of a laser or diamond blade used to form the opening(s) 208 .
- a distance that resulting protruding portions protrude from a respective side of the semiconductor wafer 204 may be controlled to ensure that that cover 212 may serve to protect the semiconductor wafer 204 therein.
- Multi-chip packages enable discrete components, which may be implemented in a same or different technology, to be integrated into a single IC package.
- MCPs are increasing in popularity for a wide range of applications, e.g., MCPs for mobile phone applications, MCP memories that integrate, e.g., flash memory and a controller. Aspects of packaging embodiments discussed above may be employed, e.g., to implement such MCPs. For example, when fabricating MCPs, the covering step S 68 and/or the completely separating step S 72 may be executed after vertically stacking wafers including discrete components of the MCP to be integrated.
- FIG. 19 illustrates an exemplary card system 700 , e.g., a multi-media card or a secure digital card, which may be implemented according one or more aspects of the invention.
- the card 700 may include a controller 710 and a memory 720 .
- the memory 720 may be, e.g., a flash memory, a PRAM, a DRAM, etc.
- the memory 720 , the controller 710 and an interface therebetween for exchanging, e.g., data and/or commands, may be packaged together as an MCP using one or more aspects of the invention.
- FIG. 20 illustrates an exemplary electronic system 800 , which may be implemented according to one or more aspects of the invention.
- the system 800 may include a processor 810 , a memory 820 , an I/O (input/output) device 830 and a bus 840 .
- the system 800 may be, e.g., a mobile phone, an MP3 device, a navigation system, a solid state disk (SSD), a household appliance, etc.
- the memory 820 , the processor 810 , the I/O device 830 and the bus 840 may be packaged together as an MCP using one or more aspects of the invention.
- one, some or all of the memory 820 , the processor 810 and the I/O device 840 may be vertically stacked on each other before being packaged as an MCP according to one or more aspects of the packaging embodiments described above.
Abstract
Description
- 1. Field of the Invention
- Embodiments of the present invention relate to semiconductor chip packages, and methods of manufacturing thereof. More particularly, embodiments of the present invention relate to wafer level chip packages and methods of manufacturing wafer level chip packages that are capable of providing improved protection against damage, e.g., during handling and/or subsequent wafer and/or chip processing, and reducing chipping and/or cracking defects.
- 2. Description of the Related Art
- In general, semiconductor chip packages are provided to physically protect a semiconductor chip while establishing input and output connection portion(s) for connecting the semiconductor chip to other device(s). As electronic devices are becoming smaller and more complex, it is desirable to package a semiconductor chip as soon as possible after the semiconductor chip is formed to help protect the electronic devices of the semiconductor chip from damage that may occur during subsequent handling, etc. In some cases, the semiconductor chips of a wafer are first completely separated from the wafer before being packaged. In such cases, however, the semiconductor chips are susceptible to damage that may occur during the dicing process itself, i.e., process for separating the semiconductor chip(s) from the wafer.
- Therefore, in some cases, wafer level packaging is employed to package the semiconductor chip(s) while the semiconductor chip(s) are still on the wafer. Wafer level packaging may offer many advantages, e.g., protection during dicing, relatively small, e.g., thinner, package size, relatively lighter package weight, and/or reduced manufacturing cost, etc. In general, conventional wafer level packages fail to cover all sides, e.g., all six sides, of a semiconductor chip, and/or conventional methods of wafer-level packaging semiconductor devices generally employ, e.g., multiple depositing steps and/or multiple planarization steps. Therefore, improved wafer level packages and simplified methods of packaging semiconductor chips at the wafer level are desired.
- Embodiments of the present invention are therefore directed to semiconductor packages and methods of manufacturing such semiconductor packages, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
- It is therefore a feature of an embodiment of the present invention to provide packages that completely encapsulate the semiconductor chip, except for connector(s) formed and predetermined protruding portion(s) of a substrate of the semiconductor chip.
- It is therefore a separate feature of an embodiment of the present invention to provide simplified methods of manufacturing wafer level packages that completely encapsulate the semiconductor chip, except for connector(s) formed and predetermined protruding portion(s) of a substrate of the semiconductor chip.
- It is therefore a separate feature of an embodiment of the present invention to provide a method of manufacturing wafer level packages that completely encapsulate the semiconductor chip, except for connector(s) formed and predetermined protruding portion(s) of a substrate of the semiconductor chip, which requires only a single resin covering step such that all sides of the semiconductor chip are simultaneously covered.
- At least one of the above and other features and advantages of the present invention may be realized by providing a packaged semiconductor device, including a substrate including at least one device layer and at least one connector arranged thereon, and a resin cover covering each side of the substrate, wherein the resin cover on at least one side of the substrate may include an opening exposing the connector and the resin cover on at least one other side of the substrate may expose a portion of the substrate.
- The resin cover may be an outermost layer on each of the sides of the substrate. Each outer surface of the resin cover may be substantially or completely planar. A portion of the resin cover exposing the portion of the substrate may abut a sidewall of the exposed portion of the substrate, and an outer surface of the abutting portion of the resin cover may extend along a same plane as a plane along which a surface of the exposed portion of the substrate extends.
- The substrate may include a top side, a bottom side, and a plurality of lateral sides, and the top side may include a plurality of the connectors arranged thereon, the resin cover on the top side may include a plurality of openings respectively exposing the connectors, and the resin cover on the another side of the substrate may be on at least one of the lateral sides, and may expose a portion of at least one of the lateral sides of substrate.
- The resin cover may expose a portion of each of the lateral sides of the substrate. The resin cover may expose a portion of only two of the lateral sides of the substrate, the two lateral sides may be opposite each other. The resin cover may expose a portion of only one of the lateral sides of the substrate.
- Other than the exposed at least one connector and the exposed portion of the at least one other side, the resin cover may completely encapsulate the substrate. The resin cover may be a single continuous layer. The exposed portion of the substrate may correspond to a lateral corner portion of the substrate.
- A portion of the resin cover on the side of the substrate including the at least one connector may surround a lower portion of the connector, and may have a height of about 10% to about 80% of a height of the at least one connector along a direction substantially perpendicular to a plane along which a surface of the substrate on which the connector is arranged extends.
- The substrate may have been cut from a wafer along a scribe lane of the wafer, the scribe lane having a width, such that the substrate may be a portion of the semiconductor wafer, and a thickness, relative to the other side of the substrate, of at least a portion of the resin cover abutting the at least one exposed portion of the substrate may be equal to or less than about 50% of the width of the scribe lane. The packaged semiconductor may be an MCP.
- At least one of the above and other features and advantages of the present invention may be separately realized by providing a method of manufacturing a wafer level package, including forming at least one opening in a portion of a wafer surrounding a predetermined sub-portion of the wafer corresponding to a device to be separated from a remaining portion of the wafer, the opening completely extending from a top side of the wafer to a bottom side of the wafer, and the wafer sub-portion remaining connected to the remaining portion of the wafer by at least one wafer connecting portion, covering the wafer sub-portion with a resin cover, wherein the resin cover may fill the opening formed in the portion of the wafer surrounding the wafer sub-portion and cover each side of the wafer sub-portion, and completely separate the wafer sub-portion from the remaining portion of the wafer along a boundary defined by the at least one wafer connecting portion and the portion of resin cover corresponding to the filled opening.
- At least one side of the wafer sub-portion may include a connector arranged thereon, and covering the wafer sub-portion may include completely covering the side of the wafer sub-portion having the at least one connector arranged thereon, except for the at least one connector arranged thereon.
- Covering the wafer sub-portion may include completely encapsulating the wafer sub-portion, other than the at least one connector of the device and a separated side of the wafer connecting portion, wherein the separated side may correspond to the side of the wafer connecting portion exposed when separating the wafer sub-portion from the remaining portion of the wafer.
- Covering the wafer sub-portion with the resin cover may include one of dipping the wafer in a thermosetting epoxy resin solution, and applying an epoxy layer using a spin coating process. Applying the epoxy layer using a spin coating process may include coating at least a top portion of the at least one connector with a coating repellent before covering the wafer sub-portion with the resin cover.
- Applying the epoxy layer using a spin coating process may include, during the spin coating process using a spin chuck, temporarily elevating the wafer sub-portion away from an upper surface of the spin chuck to cover the bottom side of the wafer while simultaneously filling the opening and covering each of the other sides of the wafer sub-portion.
- Dipping the wafer in a thermosetting epoxy resin solution may include partially dipping the wafer in the epoxy resin solution such that, other than an upper portion of the at least one connector, a remainder of the wafer is dipped into the epoxy resin solution.
- Forming the at least one opening may include using at least one of a diamond blade and a laser having a first width, and completely separating the wafer sub-portion may include using at least one of a diamond blade and a laser having a second width, wherein the first width may be greater than the second width.
- Forming the at least one opening may include removing a portion of the wafer in a scribe lane of the wafer, and a thickness of a remaining portion of the resin cover relative to the respective side of the wafer-sub portion may be equal to or less than about 50% of a width of the scribe lane of the wafer.
- Covering the wafer sub-portion with the resin cover may be performed in a single covering process such that the opening formed in the portion of the wafer surrounding the wafer sub-portion and each side of the wafer sub-portion may be simultaneously or substantially simultaneously filled and covered, respectively. The method may further include, before covering or before completely separating, stacking at least another wafer on the wafer, wherein the at least another wafer may include another device to be integrated with the device on the wafer.
- The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
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FIG. 1 illustrates a top-side view of a first exemplary embodiment of a wafer level package of a semiconductor chip; -
FIG. 2 illustrates a top-side view of a second exemplary embodiment of a wafer level package of a semiconductor chip; -
FIG. 3 illustrates a top-side view of a third exemplary embodiment of a wafer level package of a semiconductor chip; -
FIG. 4 illustrates a top-side view of fourth exemplary embodiment of a wafer level package of a semiconductor chip; -
FIG. 5 illustrates a top view of an exemplary wafer including a plurality of semiconductor chips; -
FIG. 6 illustrates a flow-chart of an exemplary method for fabricating a wafer level package according to one or more aspects of the invention; -
FIG. 7 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 1 ; -
FIG. 8 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 2 ; -
FIG. 9 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 3 ; -
FIG. 10 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 4 ; -
FIGS. 11 , 12, 13 and 14 illustrate additional stages in the exemplary method for fabricating the wafer level packages ofFIGS. 1 through 4 according to one or more aspects of the invention; -
FIGS. 15 , 16, 17 and 18 illustrate stages in a second exemplary method for fabricating a wafer level package according to one or more aspects of the invention; -
FIG. 19 illustrates an exemplary memory card that may be implemented according to one or more aspects of the invention; and -
FIG. 20 illustrates an exemplary electronic system that may be implemented according to one or more aspects of the invention. - Korean Patent Application No. 10-2007-0031931, filed on Mar. 30, 2007, in the Korean Intellectual Property Office, and entitled: “WAFER LEVEL PACKAGE PREVENTING A CHIPPING DEFECT AND MANUFACTURING METHOD THEREOF,” is incorporated by reference herein in its entirety.
- The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
- In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Additionally, it will be understood that when an element is referred to as being “continuous,” the element is a single integrally formed member, while “substantially continuous” corresponds to separate portions of a member arranged next to each other, e.g., abutting, relatively close to each other, to form the member. Like reference numerals refer to like elements throughout the specification.
-
FIG. 1 illustrates a first exemplary embodiment of awafer level package 100A of a semiconductor chip 104 (seeFIGS. 5 and 7 ). Thewafer level package 100A may include acover 112, which may be formed of, e.g., a resin, other molding materials known in art, etc. In such embodiments, the resin may include, e.g., an epoxy resin, a phenolic resin, etc. - The
semiconductor chip 104 covered by thewafer level package 100A may include one ormore connectors 110, and at least one protrudingportion 116A exposed by thecover 112 of thewafer level package 100A. In some embodiments of the invention, e.g., the connector(s) 110 may be provided on a first side, e.g., a top side, of thesemiconductor chip 104, and the protruding portion(s) 116A may be provided on a different side(s), e.g., lateral side(s), of thesemiconductor chip 104. Embodiments of the invention are not, however, limited to such a configuration. - The connector(s) 110 may be arranged on at least one side of the
semiconductor chip 104, and may be employed to connect thesemiconductor chip 104 to external devices (not shown). The connector(s) 110 may include conductive material, and may be, e.g., a solder ball, a solder bump, a Cu bump (or Cu pillar), or Cu+ solder bump/pillar. - The protruding portion(s) 116A may be provided on at least one side of the
semiconductor chip 104, and may correspond, e.g., to a portion of a substrate (not shown) of thesemiconductor chip 104 that protrudes beyond other portion(s) of the respective side of the substrate. That is, e.g., the protruding portion(s) 116A may protrude beyond all other portion(s) of the respective side of the substrate from which it protrudes. More particularly, e.g., in some embodiments of the invention, the respective side(s) of the substrate including the protruding portion(s) 116A may be substantially or completely planar, but for the protruding portion(s) 116A protruding therefrom. Embodiments of the invention are not, however, limited to such substantially or completely planar sides. More particularly, the substrate may be, e.g., a respective portion of a semiconductor wafer 102 (seeFIG. 5 ) such as a silicon wafer corresponding to thesemiconductor chip 104, i.e., a portion of the semiconductor wafer diced from a remaining portion of the semiconductor wafer on which a plurality ofsemiconductor chips 104 may have been formed. Further, the protruding portion(s) 116A may serve to help protect thesemiconductor chip 104 even after thesemiconductor chip 104 is packaged. That is, e.g., together with thecover 112, the protruding portion(s) 116A may serve to protect thesemiconductor chip 104 from damage. - In the description of exemplary embodiments, it will be assumed that the
semiconductor chip 104 has a rectangular shape including six sides, i.e., a top side, a bottom side, and four lateral sides extending between the top and bottom sides. For example, the top side may correspond to an upper surface extending along a XY plane, the bottom side may correspond to a lower surface, i.e., lower relative to a Z axis, extending along another XY plane, and the lateral sides may extend along different YZ or XZ planes. However, embodiments of the invention are not limited thereto. For example, the semiconductor chip may have a substantially circular or rounded shape along the XY plane, and in such cases, may have, e.g., a single continuous lateral surface. More particularly, in the description of exemplary embodiments, it will be assumed that the connector(s) 110 are provided on the top side of thesemiconductor chip 104, and the bottom side of the semiconductor chip is substantially or completely planar. Embodiments of the invention are not, however, limited thereto, and persons of ordinary skill in the art will appreciate the applicability of one or more aspects of the invention to a semiconductor chip irrespective of a shape thereof and/or the side(s) of the semiconductor chip including the connector(s) 110 and/or protruding portion(s) 116A. - The protruding portion(s) 116A may be provided at various portions, substantially central portion, corner portion, substantially left or right portion, etc., of the respective side of the
semiconductor chip 104. In the exemplary embodiment of thewafer level package 100A illustrated inFIG. 1 , the protrudingportions 116A are provided at substantially central portions of the respective lateral sides of thesemiconductor chip 104. The protruding portion(s) 116A may occupy a relatively small portion of the respective side of thesemiconductor chip 104 from which they protrude such that a majority of the sides of thesemiconductor chip 104 are covered by thecover 112. - Further, e.g., in some embodiments of the invention, only one protruding
portion 116A may be provided on thesemiconductor chip 104, while in other embodiments, e.g., more than one protrudingportions 116A may be provided. For example, in some embodiments at least one protrudingportion 116A may be provided on two sides, e.g., two opposing lateral sides, of thesemiconductor chip 104. In some other embodiments of the invention, a plurality of protrudingportion 116A may be provided on only one lateral side of the of thesemiconductor chip 104. In some other embodiments of the invention, a plurality of the protrudingportions 116A may be provided on a plurality of lateral sides of thesemiconductor chip 104. In yet some other embodiments of the invention, a single and/or a plurality of the protrudingportions 116A may be provided on each lateral side of thesemiconductor chip 104. More particularly, the exemplarywafer level package 100A illustrated inFIG. 1 , includes one protrudingportion 116A at a central portion of each lateral side of thesemiconductor chip 104 and/or a central portion of each lateral side of thecover 112. Embodiments of the invention are not, however, limited thereto. - In some embodiments of the invention, an exposed surface of the protruding portion(s) 116A, i.e., surface(s) exposed by the
cover 112, may be substantially and/or completely planar, and may extend along a same plane as respective outer surface of portion(s) of thecover 112. In some embodiments of the invention, while a surface may be substantially planar, the respective surface may not be a smooth surface, i.e., the surface may be rugged or rough. Further, while various surfaces may be described as being substantially and/or completely planar, embodiments of the invention are not limited thereto. - More particularly, the respective portion(s) of the
cover 112 may abut, and substantially and/or completely align with the respective protruding portion(s) 116A so as to form a substantially continuous surface. That is, e.g., in some embodiments of the invention, but for the connector(s) 110, the resultingwafer level package 100A may have substantially and/or completely planar surfaces as a result of respective portion(s) of thecover 112, alone or in combination with the respective protruding portion(s) 116A. More particularly, in some embodiments of the invention, the substantially continuous surface, e.g., two surfaces arranged close to and/or abutting each other, resulting from the abutting arrangement of the respective outer surface portion(s) of thecover 112 and the respective protruding portion(s) 116A may be substantially and/or completely planar. Embodiments of the invention, however, are not limited to such planar and/or completely planar surfaces for thewafer level package 100A and/orcover 112. That is, e.g., the protecting nature of thecover 112, may not depend on the respective surface(s) of thecover 112 being substantially and/or completely planar, i.e., may rather depend on a thickness of thecover 112. Thus, while a relatively precise tool or method may be employed to completely separate thesemiconductor chip 104 from thewafer 102, the tool or method need not necessarily establish a smooth or planar surface. - More particularly, e.g., in some embodiments of the invention, the protruding
portion 116A may correspond to a substantially rectangular shaped portion of the substrate of thesemiconductor chip 104, and as shown inFIG. 1 , other than the exposed surface(s) of the protrudingportion 116A, which may be aligned with the respective outer surface portion(s) of thecover 112, the protruding portion(s) 116(A) may be completely surrounded by thecover 112. - As shown in
FIG. 1 , in some embodiments of the invention, except for the exposed connector(s) 110 and the protruding portion(s) 116A, thecover 112 may substantially completely and/or completely encapsulate thesemiconductor chip 104. - Further, by providing portion(s) of the
cover 112 even on the side(s), e.g., the top side, of thesemiconductor chip 104 including the connector(s) 110, respective portions of thecover 112 may support and/or surround theconnectors 110, and may improve joint reliability of the connector(s) 110. That is, e.g., lower portions of the connector(s) 110 may be surrounded respective portions of thecover 112. In some embodiments of the invention, thecover 112 may have a height H1 (seeFIG. 13 ) of about 10% to about 80% of a height H2 (seeFIG. 13 ) of theconnector 110 relative to a respective surface, e.g., top surface, of thesemiconductor chip 104. For example, in embodiments of the invention in which the connector(s) 110 are provided on the top side of thesemiconductor chip 104 extending along a XY plane, thecover 112 may have a height H1 of about 10% to about 80% of the height H2 of theconnector 110 along the Z direction. More particularly, if, e.g., the height H1 of thecover 112 is more than about 80% of the height H2 of theconnector 110, electrical connectivity characteristics of theconnector 110 may be threatened, and if, e.g., the height H1 of thecover 112 is less than about 10% of the height H2 of theconnector 110, thecover 112 may not adequate serve to improve joint reliability of theconnector 110 to thesemiconductor chip 104. - A protruding height, i.e., thickness, of protruding portion(s) 116A relative to the respective side of the substrate may be no more than about 50% of a width Ws of scribe lane 106 (see
FIG. 7 ). As described in more detail below, thesemiconductor chip 104 may be diced, i.e., separated from, the substrate, e.g., semiconductor wafer, by cutting within the scribe lane(s) 106 surrounding thesemiconductor chip 104. More particularly, e.g., if two semiconductor dies are formed adjacent to each on the substrate with a respective scribe lane therebetween, the substrate may be diced such that about 50% of the scribe lane remains on each of the resulting semiconductor chips 104. Further, in such embodiments, respective portion(s) of thecover 112 may have a thickness of less than about 50% of the width Ws of thecorresponding scribe lane 106. -
FIG. 2 illustrates a second exemplary embodiment of awafer level package 100B of asemiconductor chip 104A (seeFIG. 8 ) including at least one protruding portion(s) 116B, arranged differently than protruding portion(s) 116A of the first exemplary embodiment illustrated inFIG. 1 . In general, only differences between the first exemplarywafer level package 100A illustrated inFIG. 1 and the second exemplary embodiment of thewafer level package 100B will be described below. - Referring to
FIG. 2 , thewafer level package 100B may include acover 112A, and the protruding portion(s) 116B of the semiconductor substrate may be arranged at edge, e.g., corner, portion(s) of thesemiconductor chip 104A. Thus, according to this exemplary embodiment, at least one corner portion of thecover 112A may correspond to an exposed portion of the substrate of thesemiconductor chip 104A. More particularly, in the exemplary embodiment illustrated inFIG. 2 , each corner portion of thecover 112A may include an exposed portion of the substrate of thesemiconductor chip 104A. Thus, in such an embodiment, assuming that thesemiconductor chip 104A has a rectangular shape, each of the four lateral corners of the wafer-level package 100B may include a portion of thecover 112A and a respective exposed portion of the substrate of thesemiconductor chip 104A. -
FIG. 3 illustrates a third exemplary embodiment of awafer level package 100C of asemiconductor chip 104B (seeFIG. 9 ) including at least one protruding portion(s) 116C, arranged differently than protruding portion(s) 116A of the first exemplary embodiment illustrated inFIG. 1 . In general, only differences between the first exemplarywafer level package 100A illustrated inFIG. 1 and the third exemplary embodiment of thewafer level package 100C will be described below. - Referring to
FIG. 3 , thewafer level package 100C may include a plurality of protrudingportions 116C and acover 112B. The protrudingportions 116C may be arranged on opposing lateral sides of thecover 112B or opposing lateral sides of thesemiconductor chip 104B. More particularly, e.g., the exemplarywafer level package 100C illustrated inFIG. 3 includes two protrudingportions 116C arranged at substantially central portions of two opposing lateral sides of thecover 112B, i.e., corresponding to substantially central portions of two opposing lateral sides of thesemiconductor chip 104B. -
FIG. 4 illustrates a fourth exemplary embodiment of awafer level package 100D of asemiconductor chip 104C (seeFIG. 10 ) including at least one protruding portion(s) 116D, arranged differently than protruding portion(s) 116A of the first exemplary embodiment illustrated inFIG. 1 . In general, only differences between the first exemplarywafer level package 100A illustrated inFIG. 1 and the fourth exemplary embodiment of thewafer level package 100D will be described below. - Referring to
FIG. 4 , thewafer level package 100D may include protruding portion(s) 116D and acover 112C. The protruding portion(s) 116D may be arranged off-center from, e.g., substantially to a left or right side of a respective lateral side of thecover 112C or substantially to a left or right side of a respective lateral side of thesemiconductor chip 104C. More particularly, e.g., the exemplarywafer level package 100D illustrated inFIG. 4 includes a single protrudingportion 116D substantially to a left or right side of a lateral side of thecover 112C. Embodiments of the invention are not limited, however, to such an arrangement. For example, the single protrudingportion 116D may be arranged at a substantially central portion or a corner portion of thecover 112C. - Further, in some embodiments of the invention, a combination of the exemplary configurations illustrated in, e.g.,
FIGS. 1 through 4 may be employed. - An exemplary method of fabricating a wafer level package according to one or more aspects of the invention will be described below with reference to
FIGS. 5 through 14 . -
FIG. 5 illustrates a top view of awafer 102 including a plurality ofsemiconductor chips 104. As illustrated inFIG. 5 , the plurality ofsemiconductor chips 104, i.e., semiconductor dies corresponding torespective semiconductor chips 104, may be formed on awafer 102, e.g., a semiconductor wafer. The semiconductor chips 104 may be diced, i.e., separated, from a remaining portion of thewafer 102 by, e.g., cutting or breaking within the scribe lane 106 (seeFIG. 7 ) surrounding eachsemiconductor chip 104. After being diced from thewafer 102, therespective semiconductor chips 104 may each include a portion of thewafer 102 as the substrate of thesemiconductor chip 104. Thewafer 102 may be, e.g., a semiconductor wafer such as a silicon wafer. -
FIG. 6 illustrates a flow-chart of an exemplary method for fabricating a wafer level package according to one or more aspects of the invention;FIG. 7 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 1 ;FIG. 8 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 2 ;FIG. 9 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 3 ;FIG. 10 illustrates a top view of a stage in an exemplary method for fabricating the wafer level package ofFIG. 4 ; andFIGS. 11 , 12, 13 and 14 illustrate additional stages in the exemplary method for fabricating the wafer level packages ofFIGS. 1 through 4 according to one or more aspects of the invention. - Referring to
FIGS. 1 , 6 and 7, fabricating thewafer level package 100A according to one or more aspects of the invention may begin at step S60 during which awafer 102 including at least onesemiconductor chip 104 formed thereon may be provided. - Still referring to
FIGS. 6 and 7 , the exemplary method may then proceed to step S64 during which at least oneopening 108A may be formed in a portion of thewafer 102 surrounding thesemiconductor chip 104 to partially separate thesemiconductor wafer 104 from a remaining portion of thewafer 102. The opening(s) 108A may completely extend through a thickness of thewafer 102, e.g., completely from the top side of thewafer 102 to the bottom side of thewafer 102 along the Z direction (e.g., a peek-hole like opening through thewafer 102 enabling one to see something arranged below thewafer 102 from a point above the wafer 102). In embodiments of the invention, while the opening(s) 108A may extend completely through a thickness of thewafer 102, the opening(s) 108A define at least one connectingportion 136 for keeping thesemiconductor chip 104 partially connected to the remaining portion of thewafer 102 at this stage in exemplary the wafer level package fabricating method. At least some of the connectingportion 136 may be shared between two or more adjacent ones of the semiconductor chips 104 on thewafer 102. - Referring to
FIG. 7 , the opening(s) 108A may be formed within thescribe lanes 106 surrounding therespective semiconductor chip 104. The opening(s) 108A may be formed by, e.g., sawing corresponding portion(s) of thewafer 102 using, e.g., a laser, a diamond blade, or other known cutting/sawing materials and/or methods. A width of the opening(s) 108A may be substantially the same as or less than the width Ws of thescribe lane 106, e.g., a first cutting width of a first laser cutting step may be substantially the same as or less than the width Ws of thescribe lane 106. Theopenings 108A may correspond to one or more of the semiconductor chips 104. For example, in some embodiments, theopenings 108A may extend from one lateral side of thewafer 102 to an opposing lateral side of thewafer 102 and may be associated with a plurality ofsemiconductor chips 104 arranged in, e.g., a row or column, while in some other embodiments, theopenings 108A may be associated with, e.g., one, two or foursemiconductor chips 104. - The opening(s) 108A may have various shapes depending on an arrangement of the at least one protruding
portion 116A to be provided. More particularly, e.g., theopenings 108A may be provided to form thewafer level package 100A ofFIG. 1 . Theopenings 108A may form the connectingportion 136 on each lateral side of thesemiconductor chip 104. In this exemplary embodiment, a total of four connectingportions 136 may be provided as a result of, e.g., respective portions of, e.g., fouropenings 108A partially surrounding thesemiconductor chip 104. More particularly, in this exemplary embodiment, the connectingportions 136 may be provided at a substantially central portion of each lateral side of thesemiconductor chip 104. Embodiments of the invention are not, however, limited to such an arrangement and/or number ofopenings 108A and/or connectingportions 136. - For example, referring to
FIG. 8 ,openings 108B may be provided to form thewafer level package 100B ofFIG. 2 . In general, only differences between theopenings 108B illustrated inFIG. 8 and theopenings 108A illustrated inFIG. 7 will be described below. Thus, e.g., theopenings 108B may also extend completely through a thickness of thewafer 102. In this exemplary embodiment, theopenings 108B may form, e.g., a connectingportion 136A at each corner of thesemiconductor wafer 104A. More particularly, in this exemplary embodiment, four connectingportions 136A may be at least partially defined as a result of, e.g., respective portions of, e.g., fouropenings 108B partially surrounding thesemiconductor chip 104A. The connectingportions 136A may be provided at, e.g., each lateral corner portion of thesemiconductor chip 104A. - In another exemplary embodiment, referring to
FIG. 9 ,openings 108C may be provided to form thewafer level package 100C ofFIG. 3 . In general, only differences between theopenings 108C illustrated inFIG. 9 and theopenings 108A illustrated inFIG. 7 will be described below. Thus, e.g., theopenings 108C may also extend completely through a thickness of thewafer 102. In this exemplary embodiment, theopenings 108C may form, e.g., a connectingportion 136B at opposing lateral sides of thesemiconductor wafer 104B. More particularly, in this exemplary embodiment, two connectingportions 136B may be defined as a result of, e.g., respective portions of, e.g., twoopenings 108C partially surrounding thesemiconductor chip 104B. The connectingportions 136B may be provided at, e.g., central portions of the respective lateral opposing sides of thesemiconductor chip 104A. - In another exemplary embodiment, referring to
FIG. 10 ,openings 108D may be provided to form thewafer level package 100D ofFIG. 4 . In general, only differences between theopenings 108D illustrated inFIG. 10 and theopenings 108A illustrated inFIG. 7 will be described below. Thus, e.g., theopenings 108D may also extend completely through a thickness of thewafer 102. In this exemplary embodiment, theopenings 108D may form, e.g., a connectingportion 136C at one lateral side of thesemiconductor wafer 104C. More particularly, in this exemplary embodiment, a single connectingportion 136C may be defined as a result of asingle opening 108D partially surrounding thesemiconductor chip 104C. The connectingportion 136C may be provided at, e.g., a central portion or a left or right side portion of the lateral side of thesemiconductor chip 104C. That is, in some embodiments of the invention, e.g., a single opening, such asopening 108D, may be formed to define a single connectingportion 136C for each of thesemiconductor chips 104C on thewafer 102. - Referring back to
FIG. 6 , after forming the openings, e.g., 108A, 108B, 108C, 108D during step S64, the exemplary method may then proceed to step S68. During step S68, the semiconductor chip, e.g., 104, 104A, 104B, 104C, may be covered with, e.g., a resin. - More particularly, each side of the semiconductor chip, e.g. 104, 104A, 104B, 104C may be covered with resin and the respective opening(s), e.g., 108A, 108B, 108C, 108D, may be filled. In some embodiments, a thickness of the resin on respective sides of the semiconductor chip, e.g., 104, 104A, 104B, 104C, may be substantially uniform, while in some other embodiments, a thickness of the resin may vary on some or all sides of the semiconductor chip, e.g., 104, 104A, 104B, 104C. While each side of the semiconductor chip, e.g., 104, 104A, 104B, 104C may be completely covered with the resin, as shown in
FIGS. 1 through 4 , upper portions of therespective connectors 110 remain exposed. For simplicity, the remaining steps of the exemplary method will be described with reference to the exemplarywafer level package 100A illustrated inFIG. 1 . However, the method described may be used to form any of the described exemplarywafer level packages -
FIG. 11 illustrates an exemplary method of covering thesemiconductor chip 104 with resin by dipping thewafer 102 includingsemiconductor chips 104, including opening(s) 108 in abath 120 containing, e.g.,epoxy resin 122, i.e., a thermosetting polymer. Theepoxy resin 122 may include, e.g., a catalyzing agent, i.e., hardener, such that thecover 112 may be formed when thewafer 102 is covered by theepoxy resin 122. More particularly, thewafer 102 may be partially dipped in theepoxy resin 122 such that upper portion(s) of the connector(s) 110 may remain resin-free, i.e., exposed. That is, by dipping thewafer 102 in the epoxy resin, all sides of the semiconductor chip(s) 104 and/or the respective opening(s) 108 may be simultaneously and/or substantially simultaneously covered with, e.g.,epoxy resin 122 in a single processing step. Thus, embodiments of the invention may provide a simplified method of substantially completely encapsulating the semiconductor chip(s) 104, e.g., completely encapsulating the semiconductor chip(s) 104 except for the connector(s) 110 and the at least one connectingportion 136, in a single covering step. - More particularly, the
bath 120 may be vibrated while thewafer 102 is dipped therein to help ensure that theepoxy resin 122 covers all sides of the semiconductor chip(s) 104 and fills, e.g., completely fills, the opening(s) 108A surrounding the semiconductor chip(s) 104. Although a dipping method is illustrated inFIG. 11 for covering thesemiconductor chip 104 with, e.g., the resin, other methods of covering thesemiconductor chip 104 may be employed. More particularly, e.g., other known methods for simultaneously covering all sides of thesemiconductor chip 104 in a single covering step may be employed. -
FIG. 12 illustrates a cross-sectional view of thewafer 102 after covering all the sides of the semiconductor chip(s) 104, i.e., after the covering step S68, andFIG. 13 illustrates a more detailed cross-sectional view of a portion of thewafer 102 after the covering step S68. As shown inFIG. 12 , after the covering step S68, thecover 112 may substantially completely encapsulate the semiconductor chip(s) 104, except for the connector(s) 110 and the at least one connectingportion 136. - Referring to
FIG. 13 , in some embodiments of the invention, the height H1 of the cover may be about 10% to about 80% of the height H2 of theconnector 110. - Referring again to
FIG. 6 , after covering all the sides of the semiconductor chip(s) 104 on thewafer 102, i.e., step S68, the method may proceed to step S72. During step S72, the semiconductor chip(s) 104 may be completely separated from thewafer 102. -
FIG. 14 illustrates a cross-sectional view of thewafer 102 after covering all the sides of the semiconductor chip(s) 104, i.e., after the covering step S68, including second cuttingboundary 114. Another cutting step employing, e.g., a laser or diamond blade, may be performed to completely separate the semiconductor chip(s) 104 by cutting along therespective cutting boundary 114. The cuttingboundary 114 may correspond to an imaginary predetermined line, lane or region between, e.g., the respective semiconductor chip(s) 104. Further, after the completely separating step S72, portions of the respective connecting portion(s) 136 may correspond to the protruding portion(s) 116A. - As discussed above, during the first cutting step for forming the opening(s) 108, the width Ws of the
scribe lane 106, corresponding to the first cutting width, i.e., step S64, may be substantially the same as or less than the width Ws of thescribe lane 106. In some embodiments of the invention, during the second cutting step for completely separating the semiconductor chip(s) 104 from thewafer 102, i.e., step S72, a second cutting width may be less than the first cutting width. That is, in embodiments of the invention, step S72 may be carried out so as to provide the resulting portion of thecover 112, corresponding to where theresin 122 filled the opening(s) 108, with a sufficient width to protect the semiconductor chip 104 a from damage, e.g., external impact. That is, a relationship between the first cutting width and the second cutting width may determine a distance that the resulting protruding portion(s) 116A may protrude from the respective side(s) of thesemiconductor chip 104, and thus, may determine an efficacy of the protrudingportion 116A as a protection member. More particularly, e.g., if the first cutting width was about 80 μm and the second cutting width is about 20 μm, a width of the resultingprotruding portion 116A of thecover 112 after step S72, may be about 30 μm. Referring toFIG. 6 , the exemplary method may then be complete, i.e., step S76. -
FIGS. 15 , 16, 17 and 18 illustrate stages in a second exemplary method for fabricating a wafer level package according to one or more aspects of the invention. In general, only differences between the exemplary embodiment illustrated inFIGS. 15-18 and the exemplary embodiment described above will be described below. - Referring to
FIG. 15 , according to the second exemplary embodiment, the resin coating process includes a spin coating method instead of the dipping method. According to the second exemplary method, the process may begin by forming acoating repellent 211 on upper portions of eachconnector 210 provided onsemiconductor chip 204 formed on awafer 202. In some embodiments of the invention, a thickness of thecoating repellent 211 on the upper portion of eachconnector 210 may not exceed about 50% of a height of theconnector 210, e.g., a distance that theconnector 210 projects above a top surface of thewafer 202. - Next, referring to
FIG. 16 , at least oneopening 208 may be formed in thewafer 202 around therespective semiconductor chip 204. Theopening 208 may correspond, e.g., to any of theexemplary openings - Next, referring to
FIG. 17 , a spin coating process may be performed to coat all sides of thesemiconductor chip 204 during a single coating step. In this exemplary embodiment, thewafer 202 may be arranged on a chuck (not shown) and may be spun while resin is deposited thereon. While thewafer 202 is being spun by the chuck, the wafer may be slightly elevated above a surface of the chuck such that the resin may coat a bottom surface of thewafer 202 while coating a top surface thereof and filling, e.g., completely filling, the opening(s) 208 to form acover 212. Thecover 212 may substantially completely encapsulate thesemiconductor chip 204, except for the connector(s) 210 and at least one protruding portion (not shown) thereof. - Next, referring to
FIG. 18 , similar to the process described above with regard toFIG. 14 , the semiconductor chip(s) 204 may be completely separated from thewafer 202 by a second cutting step along a cutting boundary 214 using, e.g., a laser or a diamond blade having a width that less than a width of a laser or diamond blade used to form the opening(s) 208. By using, e.g., a laser or diamond blade during the second cutting step, i.e., the completely separating step S72, that has a smaller width than a width of the laser or diamond blade used during the first cutting step, i.e., the partially separating step, a distance that resulting protruding portions protrude from a respective side of thesemiconductor wafer 204 may be controlled to ensure that thatcover 212 may serve to protect thesemiconductor wafer 204 therein. - Multi-chip packages (MCPs) enable discrete components, which may be implemented in a same or different technology, to be integrated into a single IC package. MCPs are increasing in popularity for a wide range of applications, e.g., MCPs for mobile phone applications, MCP memories that integrate, e.g., flash memory and a controller. Aspects of packaging embodiments discussed above may be employed, e.g., to implement such MCPs. For example, when fabricating MCPs, the covering step S68 and/or the completely separating step S72 may be executed after vertically stacking wafers including discrete components of the MCP to be integrated.
-
FIG. 19 illustrates anexemplary card system 700, e.g., a multi-media card or a secure digital card, which may be implemented according one or more aspects of the invention. Referring toFIG. 19 , thecard 700 may include acontroller 710 and amemory 720. Thememory 720 may be, e.g., a flash memory, a PRAM, a DRAM, etc. For example, thememory 720, thecontroller 710 and an interface therebetween for exchanging, e.g., data and/or commands, may be packaged together as an MCP using one or more aspects of the invention. -
FIG. 20 illustrates an exemplaryelectronic system 800, which may be implemented according to one or more aspects of the invention. Referring toFIG. 20 , thesystem 800 may include aprocessor 810, amemory 820, an I/O (input/output)device 830 and abus 840. Thesystem 800 may be, e.g., a mobile phone, an MP3 device, a navigation system, a solid state disk (SSD), a household appliance, etc. For example, thememory 820, theprocessor 810, the I/O device 830 and thebus 840 may be packaged together as an MCP using one or more aspects of the invention. More particularly, e.g., in some cases, one, some or all of thememory 820, theprocessor 810 and the I/O device 840 may be vertically stacked on each other before being packaged as an MCP according to one or more aspects of the packaging embodiments described above. - Exemplary embodiments of the present invention have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Claims (25)
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KR1020070031931A KR100871707B1 (en) | 2007-03-30 | 2007-03-30 | Wafer level package preventing a chipping defect and manufacturing method thereof |
KR10-2007-0031931 | 2007-03-30 |
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US20080237896A1 true US20080237896A1 (en) | 2008-10-02 |
US8026601B2 US8026601B2 (en) | 2011-09-27 |
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US10559512B2 (en) | 2015-11-16 | 2020-02-11 | Hewlett-Packard Development Company, L.P. | Circuit package |
US11183437B2 (en) | 2015-11-16 | 2021-11-23 | Hewlett-Packard Development Company, L.P. | Circuit package |
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US8026601B2 (en) | 2011-09-27 |
KR20080088990A (en) | 2008-10-06 |
KR100871707B1 (en) | 2008-12-05 |
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