US20090146684A1 - Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same - Google Patents
Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same Download PDFInfo
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- US20090146684A1 US20090146684A1 US12/364,656 US36465609A US2009146684A1 US 20090146684 A1 US20090146684 A1 US 20090146684A1 US 36465609 A US36465609 A US 36465609A US 2009146684 A1 US2009146684 A1 US 2009146684A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4065—Low level details of refresh operations
Definitions
- the present invention relates to a semiconductor memory apparatus, and more particularly, to a circuit for controlling a driver of a semiconductor memory apparatus.
- a semiconductor memory apparatus includes a plurality of drivers with different impedance values so as to correspond to various data input and output impedances, and the plurality of drivers can selectively operated so as to implement various input and output impedances.
- a semiconductor memory apparatus has a pre-emphasis function for lowering the impedance at the time of driving transited data, so as to improve the driving capability. Therefore, the semiconductor memory apparatus needs a separate driver to achieve the pre-emphasis function.
- the circuit for controlling a driver of a semiconductor memory apparatus includes first to third drivers 40 , 70 and 100 ; an impedance adjusting unit 10 that outputs a first code PC ⁇ 0:5> and a second code NC ⁇ 0:5> for adjusting the impedance value of each of the first to third drivers 40 , 70 and 100 to a set value; driver control units 20 , 50 and 80 , each of which outputs the first code PC ⁇ 0:5> and the second code NC ⁇ 0:5> according to a driver enable signal stinf ⁇ 0:2>; data processing units 30 , 60 and 90 that output data (UP: pull-up data, and DN: pull-down data) to the corresponding first to third drivers 40 , 70 and 100 according to the first code PC ⁇ 0:5> and the second code NC ⁇ 0:5>; an auxiliary driver 120 that reinforces the driving capabilities of the first to third drivers 40 , 70 and 100 according to input auxiliary codes; an auxiliary code processing unit 110 that
- Each of the first to third drivers 40 , 70 and 100 , and the auxiliary driver 120 includes a pull-up driver having a plurality of PMOS transistors and a pull-down driver having a plurality of NMOS transistors.
- the source is connected in common to a power supply terminal VDDQ, and the drain is connected to a resistor.
- the drain is connected in common to a ground terminal, and the source is connected to a resistor.
- the number of drivers depends on the circuit design, and FIG. 1 shows an exemplary circuit using three drivers and one auxiliary driver.
- the impedance adjusting unit 10 outputs a first code PC ⁇ 0:5> and a second code NC ⁇ 0:5> for adjusting the impedance of each driver, such that the impedance value of each driver is matched with a prescribed value.
- the driver control units 20 , 50 and 80 output the first code PC ⁇ 0:5> and the second code NC ⁇ 0:5> to the corresponding data processing units 30 , 60 and 90 , or intercept them according to the driver enable signals stinf ⁇ 0:2>. For example, when the signal stinf ⁇ 0> is enabled at a logic high level, the driver control unit 20 outputs the first code PC ⁇ 0:5> and the second code NC ⁇ 0:5> to the data processing unit 30 , but when the signal stinf ⁇ 0> is disabled at a logic low level, the driver control unit 20 does not output the first code PC ⁇ 0:5> and the second code NC ⁇ 0:5> to the data processing unit 30 .
- the data processing units 30 , 60 and 90 output the pull-up data UP to the first to third drivers 40 , 70 and 100 according to the first code PC ⁇ 0:5>, and output the pull-down data DN to the corresponding first to third drivers 40 , 70 and 100 according to the second code NC ⁇ 0:5>.
- the first to third drivers 40 , 70 , and 100 drive the pull-up data UP and the pull-down data DN.
- the driving reinforcing enable signal PE becomes enabled and the auxiliary code processing unit 110 outputs the prescribed auxiliary code.
- the auxiliary driver 120 reinforces the driving capability.
- the first to third drivers 40 , 70 and 100 and the auxiliary driver 120 are connected to each other, and internal resistors thereof are connected in parallel to one another. Therefore, when the auxiliary driver 120 operates, the total impedance value of all of the drivers is reduced, thereby reinforcing the driving capability.
- the circuit for controlling a driver of a semiconductor memory apparatus has the following problems.
- Embodiments of the present invention provide a circuit for controlling a driver of a semiconductor memory apparatus, in which impedance characteristics may be improved and layout area may be reduced.
- An embodiment of the present invention provides a circuit for controlling the driver of a semiconductor memory apparatus.
- the apparatus for controlling the driver of a semiconductor memory apparatus may include a driving unit having an impedance that is set according to a code value; a driving reinforcing control unit configured to output an adjustment code for a predetermined time; and a driving reinforcing unit configured to output a reinforcing code obtained by adjusting the code value using the adjustment code, wherein the reinforcing code reinforce a driving capability of the driving unit.
- FIG. 1 is a block diagram illustrating the structure of a circuit for controlling a driver of a semiconductor memory apparatus according to the related art
- FIG. 2 is a block diagram illustrating the structure of a circuit for controlling a driver of a semiconductor memory apparatus according to an embodiment of the present invention
- FIG. 3 is a circuit diagram illustrating the internal structure of a driving reinforcing control unit of FIG. 2 ;
- FIG. 4 is a circuit diagram illustrating the internal structure of a driving reinforcing unit of FIG. 2 ;
- FIG. 5 is a circuit diagram illustrating the internal structure of a driver control unit of FIG. 2 ;
- FIG. 6 is a circuit diagram illustrating the internal structure of a data processing unit of FIG. 2 .
- FIG. 2 is a block diagram illustrating the structure of a circuit for controlling a driver of a semiconductor memory apparatus according to an embodiment of the present invention.
- the circuit for controlling a driver of a semiconductor memory apparatus according to an embodiment of the present invention may be constructed such that a pre-emphasis function can be performed without a separate driver.
- the circuit for controlling a driver of a semiconductor memory apparatus may include a plurality of drivers 250 , 280 and 310 ; an impedance adjusting unit 200 that outputs a first code PC ⁇ 0:5> and a second code NC ⁇ 0:5> for adjusting the impedance value of each of the plurality of drivers 250 , 280 and 310 to a set value; a driving reinforcing control unit 210 that outputs an adjustment code PEC ⁇ 0:5> according to offset data offset ⁇ 0:5> for a predetermined time corresponding to timing data TD ⁇ 0:N>; a driving reinforcing unit 220 that outputs a first reinforcing code PC_E ⁇ 0:5> and a second reinforcing code NC_E ⁇ 0:5> obtained by adjusting a value of the first code PC ⁇ 0:5> and a value of the second code NC ⁇ 0:5> using the adjustment code PEC ⁇ 0:5>, so as to reinforce
- the driver 250 may include a pull-up driver 251 having a plurality of PMOS transistors and a pull-down driver 252 having a plurality of NMOS transistors.
- the source is coupled in common to a power supply terminal VDDQ and the drain is coupled to a resistor.
- the source is coupled in common to a ground terminal and the drain is coupled to a data pull-down resistor.
- the number of drivers depends on the circuit design, and FIG. 2 shows an exemplary embodiment using three drivers.
- each of the pull-up driver 251 and the pull-down driver 252 has six transistors and six resistors. Of course, other numbers of drivers, transistors and resistors may be used.
- the impedance values of the drivers 250 , 280 and 310 may be different from desired values according to element characteristics and environmental factors. Accordingly, an impedance value may be matched with the desired value by adjusting the number of coupled resistors through code input and selectively turning on transistors in the driver. As shown in FIG. 2 , when each of the pull-up driver 251 and the pull-down driver 252 has six transistors, both the first code and the second code have six bits.
- FIG. 3 is a circuit diagram illustrating the internal structure of a driving reinforcing control unit of FIG. 2 .
- the driving reinforcing control unit 210 may include a timing control unit 211 that enables a code output enable signal CE for a predetermined time set by timing data TD ⁇ 0:N>, and an adjustment code output unit 212 that outputs an adjustment code PEC ⁇ 0:5> according to offset data offset ⁇ 0:5> at an enable time of the code output enable signal CE.
- the timing data TD ⁇ 0:N> and offset data offset ⁇ 0:5> are set in a mode register that sets various operational conditions of a semiconductor memory apparatus, and may be supplied at the time of operation. Values of the timing data TD ⁇ 0:N> and offset data offset ⁇ 0:5> may be reset or changed.
- the timing control unit 211 may include a timing signal generator 211 - 1 that has a plurality of delay elements and generates timing signals obtained by delaying a DLL (Delay Locked Loop) clock DLL_CLK for a predetermined amount of time; a multiplexer 211 - 2 that has a plurality of switches SW that receive the timing signals outputted by the timing signal generator 211 - 1 and outputs one of the timing signals according to the timing data TD ⁇ 0:N>; and a code output enable signal generator 211 - 3 that generates the code output enable signal CE using the timing signal outputted by the multiplexer 211 - 2 .
- a timing signal generator 211 - 1 that has a plurality of delay elements and generates timing signals obtained by delaying a DLL (Delay Locked Loop) clock DLL_CLK for a predetermined amount of time
- a multiplexer 211 - 2 that has a plurality of switches SW that receive the timing signals outputted by the timing signal generator 211 -
- the code output enable signal generator 211 - 3 includes a first inverter IV 11 that receives the output of the multiplexer 211 - 2 , a first NAND gate ND 11 that receives the output of the first inverter IV 11 and the DLL clock DLL_CLK, and a second inverter IV 12 that receives the output of the first NAND gate ND 11 and outputs the code output enable signal CE.
- the adjustment code output unit 212 may include second to seventh NAND gates ND 12 to ND 17 , each of which has a first input terminal receiving offset data offset ⁇ 0:5> and a second input terminal receiving the code output enable signal CE, and third to eighth inverters IV 13 to IV 18 that receive the output of the respective second to seventh NAND gate ND 12 to ND 17 and output the adjustment codes PEC ⁇ 0:5>, respectively.
- FIG. 4 is a circuit diagram illustrating the internal structure of a driving reinforcing unit of FIG. 2 .
- the driving reinforcing unit 220 may include an adder 221 that adds the adjustment code PEC ⁇ 0:5> to the first code PC ⁇ 0:5> and the second code NC ⁇ 0:5> and outputs a first reinforcing code PC_E ⁇ 0:5> and a second reinforcing code NC_EC ⁇ 0:5>.
- FIG. 5 is a circuit diagram illustrating the internal structure of a driver control unit of FIG. 2 .
- the driver control unit 230 may include a data converting unit 231 that converts data so as to enable pull-up and pull-down driving, a pull-up driver control unit 232 that determines whether or not to output the first reinforcing code PC_E ⁇ 0:5> according to a driver enable signal stinf ⁇ 0>, and a pull-down driver control unit 233 that determines whether or not to output the second reinforcing code NC_E ⁇ 0:5> according to the driver enable signal stinf ⁇ 0>.
- Each of the driver control units 260 and 290 has the same structure as the driver control unit 230 .
- the data converting unit 231 may include a first inverter IV 21 that receives pull-up data UP and outputs inverted pull-up data Upb, and a second inverter IV 22 that receives pull-down data DN and outputs inverted pull-down data DNb.
- the pull-up driver control unit 232 may include a third inverter IV 23 that receives a driver enable signal stinf ⁇ 0> and outputs an inverted driver enable signal stinfb ⁇ 0>; fourth to ninth inverters IV 24 to IV 29 that receive the first reinforcing codes PC_E ⁇ 0:5>, respectively; and first to sixth NOR gates NR 21 to NR 26 , each of which has a first input terminal commonly inputted with the inverted driver enable signal stinfb ⁇ 0> and a second input terminal receiving the output of the respective fourth to ninth inverter IV 24 to IV 29 , which output the first reinforcing code PC_E ⁇ 0:5>.
- the pull-down driver control unit 233 may include first to sixth NAND gates ND 21 to ND 26 , each of which has a first input terminal commonly inputted with the driver enable signal stinfb ⁇ 0>, and a second input terminal receiving a second reinforcing code NC_E ⁇ 0:5>, which output an inverted second reinforcing code NC_Eb ⁇ 0:5>.
- FIG. 6 is a circuit diagram illustrating the internal structure of a data processing unit of FIG. 2 .
- the data processing unit 240 may include a pull-up data processing unit 241 that outputs inverted pull-up data UPb to the driver 250 according to the first reinforcing code PC_E ⁇ 0:5>, and a pull-down data processing unit 242 that outputs inverted pull-down data DNb to the driver 250 according to the inverted second reinforcing code NC_Eb ⁇ 0:5>.
- Each of the data processing units 270 and 300 has the same structure as the data processing unit 240 .
- the pull-up data processing unit 241 includes logic circuits that determine whether or not to output the inverted pull-up data Upb with the same number of bits as the first reinforcing code PC_E ⁇ 0:5>. Since all of the logic circuits have the same structure, the structure of a logic circuit that receives the first reinforcing code PC_E ⁇ 0> will be described below.
- the logic circuit includes a first inverter IV 31 that receives the inverted pull-up data Upb, a second inverter IV 32 that receives the code PC_E ⁇ 0>, a pass gate PG 31 that has an input terminal receiving the output of the first inverter IV 31 , a first control terminal receiving the output of the second inverter IV 32 , and a second control terminal receiving the code PC_E ⁇ 0>, a transistor M 31 with its gate receiving the output of the second inverter IV 32 , its source coupled to the output terminal of the pass gate PG 31 , and its drain coupled to a ground, and a third inverter IV 33 whose input terminal is coupled to the source of the transistor M 31 .
- the pull-down data processing unit 242 may include logic circuits that determine whether or not to output the inverted pull-down data DNb with the same number of bits as the inverted second reinforcing code NC_Eb ⁇ 0:5>. Since all of the logic circuits may have the same structure, the structure of a logic circuit that receives the code NC_Eb ⁇ 0> is herein described.
- the logic circuit includes a first inverter IV 41 that receives the inverted pull-down data DNb, a second inverter IV 42 that receives the code NC_Eb ⁇ 0>, a pass gate PG 41 that has an input terminal receiving the output of the first inverter IV 41 , a first control terminal receiving the code NC_Eb ⁇ 0>, and a second control terminal receiving the output of the second inverter IV 42 , a transistor M 41 with its gate receiving output of the second inverter IV 42 , its drain coupled to the output terminal of the pass gate PG 41 , and its source coupled to a power supply VDD, and a third inverter IV 43 whose input terminal is coupled to the drain of the transistor M 41 .
- the timing signal generator 211 - 1 in the timing control unit 211 of the driving reinforcing control unit 210 of FIG. 3 delays a DLL clock DLL_CLK through a plurality of delay elements Delay so as to generate a timing signal.
- One of the plurality of switch SW included in the multiplexer 211 - 2 is turned on according to timing data TD ⁇ 0:5>.
- the code output enable signal generator 211 - 3 synchronizes the output of the multiplexer 211 - 2 with the DLL clock DLL_CLK and outputs a code output enable signal CE having a predetermined enable period.
- the adjustment code output unit 212 outputs the adjustment code PEC ⁇ 0:5> during a period where the voltage level of the code output enable signal CE becomes enabled at a logic high level.
- the code value of the adjustment code PEC ⁇ 0:5> is fixed to a low level during an period where the voltage level of the code output enable signal CE becomes disabled at a logic low level.
- the adder 221 of the driving reinforcing unit 220 of FIG. 4 outputs the first reinforcing code PC_E ⁇ 0:5> and the second reinforcing code NC_E ⁇ 0:5>, which are respectively obtained by adding the adjustment code PEC ⁇ 0:5> to the first code PC ⁇ 0:5> and the second code NC ⁇ 0:5> outputted by the impedance adjusting unit 210 , to the plurality of driver control units 230 , 260 and 290 .
- Each of the first reinforcing code PC_E ⁇ 0:5> and the second reinforcing code NC_E ⁇ 0:5> is a code that adjusts the impedance of the drivers 250 , 280 and 310 to the impedance necessary for driving reinforcement.
- the driver control unit 230 of FIG. 5 outputs the inverted pull-up data UPb and the inverted pull-down data DNb, which have been inverted by the data converting unit 231 .
- the pull-up driver control unit 232 When the stinf ⁇ 0> is enabled at a logic high level, the pull-up driver control unit 232 outputs the first reinforcing code PC_E ⁇ 0:5> to the data processing unit 240 , and when the stinf ⁇ 0> is enabled at a logic high level, the pull-down driver control unit 233 outputs the inverted second reinforcing code NC_Eb ⁇ 0:5> to the data processing unit 240 .
- the driver control units 260 and 290 also operate in the same manner as the driver control unit 230 .
- the pull-up data processing unit 241 of the data processing unit 240 of FIG. 6 outputs the inverted pull-up data ⁇ UPb0:5> to the driver 250 .
- the pass gate PG 31 is turned on.
- the inverted pull-up data UPb ⁇ 0> is outputted to the driver 250 .
- the pull-down data processing unit 242 outputs the inverted pull-down data DNb ⁇ 0:5> to the driver 250 .
- NC_Eb ⁇ 0> becomes a low level (NC_E ⁇ 0> becomes a high level)
- the pass gate PG 41 is turned on.
- the inverted pull-down data DNb ⁇ 0> is outputted to the driver 250 .
- the data processing units 270 and 300 also operate in the same manner as the data processing unit 240 .
- the plurality of drivers 250 , 280 and 310 drive the inverted pull-up data UPb ⁇ 0> and the inverted pull-down data DNb ⁇ 0:5> to output them through the pad 320 .
- the number of transistors that are turned on by the first reinforcing code PC_E ⁇ 0:5> and the second reinforcing code NC_Eb ⁇ 0:5> is increased and thus the number of coupled resistors is increased, reducing the total impedance. Therefore, as compared with a case in which the plurality of drivers 250 , 280 and 310 receive the first code PC ⁇ 0:5> and the second code NC ⁇ 0:5>, a driving capability is reinforced.
- a pre-emphasis function is separately performed by the auxiliary driver 120 , but according to an embodiment of the present invention, the pre-emphasis function can be performed by using the plurality of drivers 250 , 280 and 310 shown in FIG. 2 without using a separate driver.
- the plurality of drivers 250 , 280 and 310 perform a data driving operation according to the first code PC ⁇ 0:5> and the second code NC ⁇ 0:5>.
- the circuit for controlling a driver of a semiconductor memory apparatus and the method of controlling the same according to an embodiment of the present invention may have the following effects, because a driving capability can be reinforced without a separate driver.
Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 11/641,856, filed Dec. 20, 2006, the subject matter of which application is incorporated herein by reference in its entirety.
- This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 2006-031618 filed on Apr. 6, 2006, the entire contents of which are hereby incorporated by reference.
- 1. Technical Field
- The present invention relates to a semiconductor memory apparatus, and more particularly, to a circuit for controlling a driver of a semiconductor memory apparatus.
- 2. Related Art
- Generally, a semiconductor memory apparatus includes a plurality of drivers with different impedance values so as to correspond to various data input and output impedances, and the plurality of drivers can selectively operated so as to implement various input and output impedances.
- Further, a semiconductor memory apparatus has a pre-emphasis function for lowering the impedance at the time of driving transited data, so as to improve the driving capability. Therefore, the semiconductor memory apparatus needs a separate driver to achieve the pre-emphasis function.
- A circuit for controlling a driver of a semiconductor memory apparatus according to the related art is described below.
- Ask shown in
FIG. 1 , the circuit for controlling a driver of a semiconductor memory apparatus according to the related art includes first tothird drivers impedance adjusting unit 10 that outputs a first code PC<0:5> and a second code NC<0:5> for adjusting the impedance value of each of the first tothird drivers driver control units data processing units third drivers auxiliary driver 120 that reinforces the driving capabilities of the first tothird drivers code processing unit 110 that outputs the auxiliary code to theauxiliary driver 120 according to a driving reinforcing enable signal PE; and apad 130 that is connected in common to output terminals of the first tothird drivers auxiliary driver 120 and outputs data to an external device. - Each of the first to
third drivers auxiliary driver 120 includes a pull-up driver having a plurality of PMOS transistors and a pull-down driver having a plurality of NMOS transistors. In each of the plurality of PMOS transistors, the source is connected in common to a power supply terminal VDDQ, and the drain is connected to a resistor. In each of the plurality of NMOS transistors, the drain is connected in common to a ground terminal, and the source is connected to a resistor. The number of drivers depends on the circuit design, andFIG. 1 shows an exemplary circuit using three drivers and one auxiliary driver. - The operation of the circuit apparatus for controlling a driver of a semiconductor memory apparatus according to the related art with the above-described structure is herein described.
- The
impedance adjusting unit 10 outputs a first code PC<0:5> and a second code NC<0:5> for adjusting the impedance of each driver, such that the impedance value of each driver is matched with a prescribed value. - The
driver control units data processing units driver control unit 20 outputs the first code PC<0:5> and the second code NC<0:5> to thedata processing unit 30, but when the signal stinf<0> is disabled at a logic low level, thedriver control unit 20 does not output the first code PC<0:5> and the second code NC<0:5> to thedata processing unit 30. - The
data processing units third drivers third drivers - Accordingly, the first to
third drivers - When a pre-emphasis function needs to be performed according to the data transition, the driving reinforcing enable signal PE becomes enabled and the auxiliary
code processing unit 110 outputs the prescribed auxiliary code. - As a result, the
auxiliary driver 120 reinforces the driving capability. - That is, the first to
third drivers auxiliary driver 120 are connected to each other, and internal resistors thereof are connected in parallel to one another. Therefore, when theauxiliary driver 120 operates, the total impedance value of all of the drivers is reduced, thereby reinforcing the driving capability. - However, the circuit for controlling a driver of a semiconductor memory apparatus according to the related art has the following problems.
- First, since capacitance exists in each driver due to a connection node between a transistor and a resistor, as the number of drivers increases, the capacitance increases, which deteriorates the impedance characteristics.
- Second, since a separate driver is necessary for the pre-emphasis function, the larger layout area is necessary.
- Embodiments of the present invention provide a circuit for controlling a driver of a semiconductor memory apparatus, in which impedance characteristics may be improved and layout area may be reduced.
- An embodiment of the present invention provides a circuit for controlling the driver of a semiconductor memory apparatus. The apparatus for controlling the driver of a semiconductor memory apparatus may include a driving unit having an impedance that is set according to a code value; a driving reinforcing control unit configured to output an adjustment code for a predetermined time; and a driving reinforcing unit configured to output a reinforcing code obtained by adjusting the code value using the adjustment code, wherein the reinforcing code reinforce a driving capability of the driving unit.
-
FIG. 1 is a block diagram illustrating the structure of a circuit for controlling a driver of a semiconductor memory apparatus according to the related art; -
FIG. 2 is a block diagram illustrating the structure of a circuit for controlling a driver of a semiconductor memory apparatus according to an embodiment of the present invention; -
FIG. 3 is a circuit diagram illustrating the internal structure of a driving reinforcing control unit ofFIG. 2 ; -
FIG. 4 is a circuit diagram illustrating the internal structure of a driving reinforcing unit ofFIG. 2 ; -
FIG. 5 is a circuit diagram illustrating the internal structure of a driver control unit ofFIG. 2 ; and -
FIG. 6 is a circuit diagram illustrating the internal structure of a data processing unit ofFIG. 2 . - Embodiments of an apparatus for controlling a driver of a semiconductor memory apparatus will now be described with reference to the accompanying drawings.
-
FIG. 2 is a block diagram illustrating the structure of a circuit for controlling a driver of a semiconductor memory apparatus according to an embodiment of the present invention. The circuit for controlling a driver of a semiconductor memory apparatus according to an embodiment of the present invention may be constructed such that a pre-emphasis function can be performed without a separate driver. - As shown in
FIG. 2 , the circuit for controlling a driver of a semiconductor memory apparatus according to the embodiment of the present invention may include a plurality ofdrivers impedance adjusting unit 200 that outputs a first code PC<0:5> and a second code NC<0:5> for adjusting the impedance value of each of the plurality ofdrivers reinforcing control unit 210 that outputs an adjustment code PEC<0:5> according to offset data offset<0:5> for a predetermined time corresponding to timing data TD<0:N>; a drivingreinforcing unit 220 that outputs a first reinforcing code PC_E<0:5> and a second reinforcing code NC_E<0:5> obtained by adjusting a value of the first code PC<0:5> and a value of the second code NC<0:5> using the adjustment code PEC<0:5>, so as to reinforce the driving capabilities of the plurality ofdrivers driver control units data processing units corresponding drivers pad 320 that is coupled in common to output terminals of the plurality ofdrivers - Since the plurality of
drivers driver 250 will be described. Thedriver 250 may include a pull-up driver 251 having a plurality of PMOS transistors and a pull-down driver 252 having a plurality of NMOS transistors. Here, in each of the plurality of PMOS transistors, the source is coupled in common to a power supply terminal VDDQ and the drain is coupled to a resistor. In each of the plurality of NMOS transistors, the source is coupled in common to a ground terminal and the drain is coupled to a data pull-down resistor. The number of drivers depends on the circuit design, andFIG. 2 shows an exemplary embodiment using three drivers. Further, the number of transistors and resistors forming each driver is not fixed. According to the structure shown inFIG. 2 , each of the pull-up driver 251 and the pull-down driver 252 has six transistors and six resistors. Of course, other numbers of drivers, transistors and resistors may be used. - The impedance values of the
drivers FIG. 2 , when each of the pull-up driver 251 and the pull-down driver 252 has six transistors, both the first code and the second code have six bits. -
FIG. 3 is a circuit diagram illustrating the internal structure of a driving reinforcing control unit ofFIG. 2 . As shown inFIG. 3 , the drivingreinforcing control unit 210 may include atiming control unit 211 that enables a code output enable signal CE for a predetermined time set by timing data TD<0:N>, and an adjustmentcode output unit 212 that outputs an adjustment code PEC<0:5> according to offset data offset<0:5> at an enable time of the code output enable signal CE. The timing data TD<0:N> and offset data offset<0:5> are set in a mode register that sets various operational conditions of a semiconductor memory apparatus, and may be supplied at the time of operation. Values of the timing data TD<0:N> and offset data offset<0:5> may be reset or changed. - The
timing control unit 211 may include a timing signal generator 211-1 that has a plurality of delay elements and generates timing signals obtained by delaying a DLL (Delay Locked Loop) clock DLL_CLK for a predetermined amount of time; a multiplexer 211-2 that has a plurality of switches SW that receive the timing signals outputted by the timing signal generator 211-1 and outputs one of the timing signals according to the timing data TD <0:N>; and a code output enable signal generator 211-3 that generates the code output enable signal CE using the timing signal outputted by the multiplexer 211-2. The code output enable signal generator 211-3 includes a first inverter IV11 that receives the output of the multiplexer 211-2, a first NAND gate ND11 that receives the output of the first inverter IV11 and the DLL clock DLL_CLK, and a second inverter IV12 that receives the output of the first NAND gate ND11 and outputs the code output enable signal CE. - The adjustment
code output unit 212 may include second to seventh NAND gates ND12 to ND17, each of which has a first input terminal receiving offset data offset<0:5> and a second input terminal receiving the code output enable signal CE, and third to eighth inverters IV13 to IV18 that receive the output of the respective second to seventh NAND gate ND12 to ND17 and output the adjustment codes PEC<0:5>, respectively. -
FIG. 4 is a circuit diagram illustrating the internal structure of a driving reinforcing unit ofFIG. 2 . As shown inFIG. 4 , thedriving reinforcing unit 220 may include anadder 221 that adds the adjustment code PEC<0:5> to the first code PC<0:5> and the second code NC<0:5> and outputs a first reinforcing code PC_E<0:5> and a second reinforcing code NC_EC<0:5>. -
FIG. 5 is a circuit diagram illustrating the internal structure of a driver control unit ofFIG. 2 . As shown inFIG. 5 , thedriver control unit 230 may include adata converting unit 231 that converts data so as to enable pull-up and pull-down driving, a pull-updriver control unit 232 that determines whether or not to output the first reinforcing code PC_E<0:5> according to a driver enable signal stinf<0>, and a pull-downdriver control unit 233 that determines whether or not to output the second reinforcing code NC_E<0:5> according to the driver enable signal stinf<0>. Each of thedriver control units driver control unit 230. - The
data converting unit 231 may include a first inverter IV21 that receives pull-up data UP and outputs inverted pull-up data Upb, and a second inverter IV22 that receives pull-down data DN and outputs inverted pull-down data DNb. - The pull-up
driver control unit 232 may include a third inverter IV23 that receives a driver enable signal stinf<0> and outputs an inverted driver enable signal stinfb <0>; fourth to ninth inverters IV24 to IV 29 that receive the first reinforcing codes PC_E<0:5>, respectively; and first to sixth NOR gates NR21 to NR26, each of which has a first input terminal commonly inputted with the inverted driver enable signal stinfb<0> and a second input terminal receiving the output of the respective fourth to ninth inverter IV24 to IV29, which output the first reinforcing code PC_E<0:5>. - The pull-down
driver control unit 233 may include first to sixth NAND gates ND21 to ND 26, each of which has a first input terminal commonly inputted with the driver enable signal stinfb<0>, and a second input terminal receiving a second reinforcing code NC_E<0:5>, which output an inverted second reinforcing code NC_Eb<0:5>. -
FIG. 6 is a circuit diagram illustrating the internal structure of a data processing unit ofFIG. 2 . As shown inFIG. 6 , thedata processing unit 240 may include a pull-updata processing unit 241 that outputs inverted pull-up data UPb to thedriver 250 according to the first reinforcing code PC_E<0:5>, and a pull-downdata processing unit 242 that outputs inverted pull-down data DNb to thedriver 250 according to the inverted second reinforcing code NC_Eb<0:5>. Each of thedata processing units data processing unit 240. - The pull-up
data processing unit 241 includes logic circuits that determine whether or not to output the inverted pull-up data Upb with the same number of bits as the first reinforcing code PC_E<0:5>. Since all of the logic circuits have the same structure, the structure of a logic circuit that receives the first reinforcing code PC_E<0> will be described below. The logic circuit includes a first inverter IV31 that receives the inverted pull-up data Upb, a second inverter IV32 that receives the code PC_E<0>, a pass gate PG31 that has an input terminal receiving the output of the first inverter IV31, a first control terminal receiving the output of the second inverter IV32, and a second control terminal receiving the code PC_E<0>, a transistor M31 with its gate receiving the output of the second inverter IV32, its source coupled to the output terminal of the pass gate PG31, and its drain coupled to a ground, and a third inverter IV33 whose input terminal is coupled to the source of the transistor M31. - The pull-down
data processing unit 242 may include logic circuits that determine whether or not to output the inverted pull-down data DNb with the same number of bits as the inverted second reinforcing code NC_Eb<0:5>. Since all of the logic circuits may have the same structure, the structure of a logic circuit that receives the code NC_Eb<0> is herein described. The logic circuit includes a first inverter IV41 that receives the inverted pull-down data DNb, a second inverter IV42 that receives the code NC_Eb<0>, a pass gate PG41 that has an input terminal receiving the output of the first inverter IV41, a first control terminal receiving the code NC_Eb<0>, and a second control terminal receiving the output of the second inverter IV42, a transistor M41 with its gate receiving output of the second inverter IV42, its drain coupled to the output terminal of the pass gate PG41, and its source coupled to a power supply VDD, and a third inverter IV43 whose input terminal is coupled to the drain of the transistor M41. - Hereinafter, an exemplary operation of controlling the driver of a semiconductor memory apparatus according to an embodiment of the invention that has the above-described structure will be described.
- First, the timing signal generator 211-1 in the
timing control unit 211 of the driving reinforcingcontrol unit 210 ofFIG. 3 delays a DLL clock DLL_CLK through a plurality of delay elements Delay so as to generate a timing signal. - One of the plurality of switch SW included in the multiplexer 211-2 is turned on according to timing data TD<0:5>.
- The timing signal that has passed through the switch SW of the multiplexer 211-2, having been turned on, is input to the code output enable signal generator 211-3.
- The code output enable signal generator 211-3 synchronizes the output of the multiplexer 211-2 with the DLL clock DLL_CLK and outputs a code output enable signal CE having a predetermined enable period.
- The adjustment
code output unit 212 outputs the adjustment code PEC<0:5> during a period where the voltage level of the code output enable signal CE becomes enabled at a logic high level. The code value of the adjustment code PEC<0:5> is fixed to a low level during an period where the voltage level of the code output enable signal CE becomes disabled at a logic low level. - The
adder 221 of thedriving reinforcing unit 220 ofFIG. 4 outputs the first reinforcing code PC_E<0:5> and the second reinforcing code NC_E<0:5>, which are respectively obtained by adding the adjustment code PEC<0:5> to the first code PC<0:5> and the second code NC<0:5> outputted by theimpedance adjusting unit 210, to the plurality ofdriver control units drivers - For example, if the first code PC<0:5> is “110000” and the first reinforcing code PC_E<0:5> is “110110”, an adjustment code PEC is “000110”.
- The
driver control unit 230 ofFIG. 5 outputs the inverted pull-up data UPb and the inverted pull-down data DNb, which have been inverted by thedata converting unit 231. When the stinf<0> is enabled at a logic high level, the pull-updriver control unit 232 outputs the first reinforcing code PC_E<0:5> to thedata processing unit 240, and when the stinf<0> is enabled at a logic high level, the pull-downdriver control unit 233 outputs the inverted second reinforcing code NC_Eb<0:5> to thedata processing unit 240. Thedriver control units driver control unit 230. - Then, when the first reinforcing code PC_E<0:5> is set to a logic high level, the pull-up
data processing unit 241 of thedata processing unit 240 ofFIG. 6 outputs the inverted pull-up data <UPb0:5> to thedriver 250. For example, when PC_E<0> is enabled at a logic high level, the pass gate PG31 is turned on. As a result, the inverted pull-up data UPb<0> is outputted to thedriver 250. Further, when the inverted second reinforcing code NC_Eb<0:5> is set to a logic low level, the pull-downdata processing unit 242 outputs the inverted pull-down data DNb<0:5> to thedriver 250. For example, when the NC_Eb<0> becomes a low level (NC_E<0> becomes a high level), the pass gate PG41 is turned on. The inverted pull-down data DNb<0> is outputted to thedriver 250. Thedata processing units data processing unit 240. - The plurality of
drivers pad 320. In each of the plurality ofdrivers drivers - That is, according to the related art shown in
FIG. 1 , a pre-emphasis function is separately performed by theauxiliary driver 120, but according to an embodiment of the present invention, the pre-emphasis function can be performed by using the plurality ofdrivers FIG. 2 without using a separate driver. When all of the adjustment codes PEC <0:5> are outputted to 0 by the driving reinforcingcontrol unit 210, the plurality ofdrivers - It will be apparent to those skilled in the art that various modifications and changes may be made without departing from the scope and spirit of the present invention. Therefore, it should be understood that the above embodiments are not limiting, but illustrative in all aspects. The scope of the invention is defined by the appended claims rather than by the description preceding them, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the claims.
- The circuit for controlling a driver of a semiconductor memory apparatus and the method of controlling the same according to an embodiment of the present invention may have the following effects, because a driving capability can be reinforced without a separate driver.
- First, since a separate driver performing a pre-emphasis function does not need to be provided, capacitance can be decreased. Therefore, it is possible to improve impedance characteristics.
- Second, since a separate driver does not need to be provided, a driver forming area can be decreased. Therefore, it is possible to increase a layout margin.
Claims (10)
Priority Applications (1)
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US12/364,656 US7782081B2 (en) | 2006-02-07 | 2009-02-03 | Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same |
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KR10-2006-0011594 | 2006-02-07 | ||
KR1020060011594A KR100656470B1 (en) | 2006-02-07 | 2006-02-07 | Apparatus and method for controlling driver of semiconductor memory |
KR1020060031618A KR100757926B1 (en) | 2006-02-07 | 2006-04-06 | Circuit and method for controlling sense amplifier in semiconductor memory apparatus |
KR10-2006-031618 | 2006-04-06 | ||
KR10-2006-0031618 | 2006-04-06 | ||
US11/641,856 US7489159B2 (en) | 2006-02-07 | 2006-12-20 | Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same |
US12/364,656 US7782081B2 (en) | 2006-02-07 | 2009-02-03 | Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same |
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US11/641,856 Continuation US7489159B2 (en) | 2006-02-07 | 2006-12-20 | Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same |
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US20090146684A1 true US20090146684A1 (en) | 2009-06-11 |
US7782081B2 US7782081B2 (en) | 2010-08-24 |
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US11/641,856 Active 2027-02-02 US7489159B2 (en) | 2006-02-07 | 2006-12-20 | Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same |
US12/363,947 Expired - Fee Related US7843755B2 (en) | 2006-02-07 | 2009-02-02 | Circuit and method for controlling sense amplifier of semiconductor memory apparatus |
US12/364,656 Active US7782081B2 (en) | 2006-02-07 | 2009-02-03 | Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same |
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US12/363,947 Expired - Fee Related US7843755B2 (en) | 2006-02-07 | 2009-02-02 | Circuit and method for controlling sense amplifier of semiconductor memory apparatus |
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- 2006-02-07 KR KR1020060011594A patent/KR100656470B1/en not_active IP Right Cessation
- 2006-04-06 KR KR1020060031618A patent/KR100757926B1/en not_active IP Right Cessation
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US20030146774A1 (en) * | 2002-02-07 | 2003-08-07 | International Business Machines Corporation | ASIC architechture for active-compensation of a programmable impedance I/O |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130113523A1 (en) * | 2011-11-08 | 2013-05-09 | Chang-kyu Choi | Semiconductor device |
US8604830B2 (en) * | 2011-11-08 | 2013-12-10 | Hynix Semiconductor Inc. | Semiconductor device |
Also Published As
Publication number | Publication date |
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US7843755B2 (en) | 2010-11-30 |
JP2007213786A (en) | 2007-08-23 |
KR100757926B1 (en) | 2007-09-11 |
US20070247942A1 (en) | 2007-10-25 |
US20070195604A1 (en) | 2007-08-23 |
US7486581B2 (en) | 2009-02-03 |
US20090190419A1 (en) | 2009-07-30 |
CN101017702A (en) | 2007-08-15 |
US7782081B2 (en) | 2010-08-24 |
US7489159B2 (en) | 2009-02-10 |
CN100592418C (en) | 2010-02-24 |
KR100656470B1 (en) | 2006-12-11 |
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