US20090290421A1 - Flash memory device and method of programming the same - Google Patents
Flash memory device and method of programming the same Download PDFInfo
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- US20090290421A1 US20090290421A1 US12/536,450 US53645009A US2009290421A1 US 20090290421 A1 US20090290421 A1 US 20090290421A1 US 53645009 A US53645009 A US 53645009A US 2009290421 A1 US2009290421 A1 US 2009290421A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
Definitions
- the present invention disclosed herein relates to a semiconductor memory device, and more particularly, to a flash memory device capable of reducing charge coupling that occurs between adjacent memory cells coupled to the same row, and a method of programming the same.
- a semiconductor memory device is largely classified into a volatile semiconductor memory device and a non-volatile semiconductor memory device.
- the volatile semiconductor memory device is characterized of fast reading and writing speeds, but has limitations of losing stored content when no power is applied. Contrarily, the non-volatile semiconductor memory device retains the stored content even if no power is applied. Therefore, the non-volatile memory device is used for storing content that must remain regardless of power.
- the non-volatile memory device includes a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.
- a flash EEPROM (hereinafter, referred to as a flash memory) among non-volatile semiconductor memory devices has the higher degree of integration, compared to a typical EEPROM, it is advantageous to use the flash memory for a high capacity auxiliary memory device.
- FIG. 1 shows an array structure including a conventional flash memory device.
- FIG. 2 shows a vertical sectional view including memory cells 40 , 50 , and 60 arranged in the same row of FIG. 1 .
- a memory cell array 10 may include a plurality of memory blocks including a plurality of bit lines BL 1 e , BL 1 o, BL 2 e , . . . BLmo, which are arranged in parallel.
- Each memory block may include a plurality of NAND strings corresponding to the respective bit lines BL 1 e , BL 1 o, BL 2 e , . . . BLmo.
- One memory block in the memory cell array 10 is illustrated as an example in FIG. 1 .
- Each string may have a string select transistor SST and a ground select transistor GST.
- a plurality of floating gate transistors M 0 to M 31 (hereinafter, referred to as memory cells) used for memory cells may be coupled in series between the string select transistor SST and the ground select transistor GST.
- the memory cells M 0 to M 31 included in each string may be formed in the same substrate 80 .
- the memory cells M 0 to M 31 may include adjacent floating gate transistors and shared source-drain terminals in each string.
- a plurality of word lines WL ⁇ 0 > to WL ⁇ 31 > may intersect each string.
- floating gates 41 , 51 , and 61 i.e., charge storage elements of the memory cell, may be spaced a predefined distance apart from each other.
- a control gate 70 may be formed on the floating gates 41 , 51 , and 61 of the memory cells 40 , 50 , and 60 .
- the control gate 70 may also be coupled to the corresponding word line WL ⁇ 30 >.
- an erase process may be performed to have a predetermined threshold voltage (e.g., ⁇ 3 V) in the memory cells. Then, a high voltage (e.g., 20 V) may be applied to the word line WL ⁇ 30 > for a predetermined time, which is coupled to a selected memory cell 50 . To accurately program the selected memory cell 50 , the threshold voltage of the selected memory cell 50 may increase to a higher level, but the threshold voltage of the memory cells 40 and 60 (which are not selected) must stay without change.
- a predetermined threshold voltage e.g., ⁇ 3 V
- a high voltage e.g. 20 V
- the threshold voltage of the selected memory cell 50 may increase to a higher level, but the threshold voltage of the memory cells 40 and 60 (which are not selected) must stay without change.
- the program voltage is commonly supplied to the selected memory cell 50 and unselected memory cells 40 and 60 through the control gate 70 .
- a parasitic capacitance Cx may be disposed between the adjacent floating gates 41 , 51 , and 61 . Therefore, when the program voltage is applied to the selected word line WL ⁇ 30 >, charge coupling between the selected memory cell 50 and unselected memory cells 40 and 60 occurs due to the parasitic capacitance Cx. Consequently, the threshold voltages of the selected memory cell 50 and unselected memory cells 40 and 60 arise together such that unselected memory cells 40 and 60 adjacent to the selected memory cell 50 are accidentally programmed. At this point, the size of the rising threshold voltage Vth is in proportion to the size (i.e., 2Cx) of the parasitic capacitance Cx between the selected memory 50 and adjacent memory cells 40 and 60 .
- the present invention includes a flash memory device capable of reducing charge coupling, which occurs between adjacent memory cells coupled to the same row, and a method of programming the same.
- Some embodiments of the present invention include a flash memory device comprising: a memory array intersected by a first even bit line, a first odd bit line adjacent to the first even bit line, a second even bit line, and a second odd bit line adjacent to the second even bit line, and a plurality of word lines; a page buffer circuit including a first latch coupled to an even virtual bit line and a second latch coupled to an odd virtual bit line, the even virtual bit line being coupled to the first and second even bit lines, and the odd virtual bit line being coupled to the first and second odd bit lines; and a select circuit configured to electrically couple one of the first even bit line and the second even bit line to the first latch, and to electrically couple one of the first odd bit line and the second odd bit line to the second latch.
- Some embodiments of the present invention include a method for programming a memory cell, comprising: electrically coupling a first bit line to a first latch; electrically coupling a second bit line to a second latch, the second bit line being adjacent to the first bit line; electrically decoupling a third bit line from the first latch, the third bit line being adjacent to the second bit line; and programming adjacent memory cells in a same word line associated with the first bit line and the second bit line responsive to data stored in the first latch and the second latch.
- FIG. 1 shows a view of an array structure including a conventional flash memory device
- FIG. 2 shows a vertical sectional view including memory cells arranged in the same row of FIG. 1 ;
- FIG. 3 shows a block diagram including a flash memory device according to an embodiment of the present invention
- FIG. 4 shows a block diagram including a flash memory device according to another embodiment of the present invention.
- FIG. 5 shows a flowchart including a method of programming a flash memory device according to the present invention
- FIG. 6 shows a flowchart including an LSB program operation of FIG. 5 ;
- FIG. 7 shows a flowchart including an MSB program operation of FIG. 5 ;
- FIGS. 8 and 9 show views of the result in addressing a page used for a programming method according to embodiments the present invention.
- FIG. 10 shows a view of program properties in memory cells according to page addressing of FIGS. 8 and 9 ;
- FIGS. 11 and 12 show views of the result in addressing a page used for a programming method according to embodiments the present invention.
- FIG. 13 shows a view of program properties in memory cells according to page addressing of FIGS. 11 and 12 .
- An embodiment of a flash memory device of the present invention simultaneously programs at least two adjacent memory cells (for example, memory cells of the same row respectively coupled to even bit lines and odd bit lines, which are adjacent to each other) arranged in the same row.
- a charge coupling effect is drastically reduced in memory cells adjacent to another memory cell that will be programmed. Therefore, the change of threshold voltage in the adjacent memory cells arranged in the same row where the selected memory cell is arranged significantly decreases.
- FIG. 3 shows a block diagram including a flash memory device 100 according to an embodiment of the present invention.
- the flash memory device 100 is a NAND flash memory device with a single latch structure, which may be used for storing a single bit data, or storing a multi bit data in One-NAND memory having a buffer therein.
- the flash memory device 100 may include a memory cell array 110 , a row decoder 130 (X-DEC in FIG. 3 ), a bit line select circuit 140 , a page buffer circuit 150 , and a controller 170 .
- the memory cell array 110 may include a plurality of memory blocks. Only one memory block among the plurality of memory blocks is illustrated in FIG. 3 .
- Each memory block may include a plurality of memory cells arranged on intersected regions of word lines WL 0 to WLn and bit lines BL 1 e , BL 1 o , BL 2 e, BL 2 o, and so forth.
- the memory cells may include a string structure. The string structure of the memory cell was described in detail with reference to FIG. 1 . Thus, the overlapping description will be omitted here for conciseness.
- the rows of the memory cell array 110 may be driven by the row decoder circuit 130 , and columns may be driven by a page buffer circuit 150 .
- the page buffer circuit 150 may be controlled by a controller 170 and may operate as a write driver or a sense amplifier according to an operation mode. Due to the operation characteristics, the page buffer circuit 150 may be called a sense and latch circuit.
- the page buffer circuit 150 may include a plurality of page buffers 151 , 152 , and so forth, corresponding to the respective bit lines or a pair of bit lines.
- FIG. 3 illustrates page buffers 151 and 152 corresponding to adjacent two even bit lines BL 1 e and BL 2 e, or adjacent two odd bit lines BL 1 o and BL 2 o.
- the adjacent two even bit lines BL 1 e and BL 2 e may be coupled to the page buffer 151 through an even virtual bit line VBLe.
- the adjacent two odd bit lines BL 1 o and BL 2 o may be coupled to the page buffer 152 through an odd virtual bit line VBLo.
- the even bit lines and odd bit lines are alternately arranged.
- a bit line structure coupled to each of page buffers 151 , 152 , and so forth, may vary within the scope of the present invention.
- a bit line switching operation of the bit line select circuit 140 may determine which bit line is selected among two bit lines coupled to the page buffers 151 , 152 , and so forth.
- the bit line select circuit 140 may include a plurality of switching transistors 141 to 144 coupled to the bit lines BL 1 e , BL 1 o , BL 2 e, BL 2 o, and so forth.
- the switching transistors 141 to 144 may be turned on/off according to switching control signals D 1 to D 4 generated from the controller 170 , in order to selectively activate the corresponding bit lines BL 1 e , BL 1 o , BL 2 e, and BL 2 o.
- At least two adjacent bit lines among the bit lines BL 1 e , BL 1 o , BL 2 e, and BL 2 o may be activated and the activated bit lines may be electrically coupled to the page buffers 151 and 152 .
- the switching transistors 141 and 142 , or 143 and 144 coupled to the same page buffer (or, the same virtual bit lines) may perform respectively opposite switching operations. For example, when the switching transistors 141 and 142 are turned on, the switching transistors 143 and 144 may be turned off. When the switching transistors 141 and 142 are turned off, the switching transistors 143 and 144 may be turned on.
- bit lines BL 1 e and BL 1 o when the adjacent bit lines BL 1 e and BL 1 o are electrically coupled to the corresponding page buffers 151 and 152 , other bit lines BL 2 e and BL 2 o may be electrically decoupled from the page buffers 151 and 152 by the turned-off switching transistors 143 and 144 .
- the memory cell coupled to the bit lines BL I e and BL 1 o which are electrically coupled to the page buffers 151 and 152 , may be simultaneously programmed according to the programming methods of FIGS. 5 through 7 . In this case, charge coupling that occurs between the adjacent memory cells 40 , 50 , and 60 is drastically decreased compared to transitional methods. This will be described in more detail with reference to FIGS. 8 through 13 .
- a reference number 120 represents simultaneously programmed memory cells and a page buffer corresponding to the memory cells.
- FIG. 4 shows a block diagram including a flash memory device 200 according to another embodiment of the present invention, and illustrates a NAND flash memory device 200 with a dual latch structure.
- the flash memory device 200 with a dual latch structure may be used for storing multi bit data, and the dual latch structure may be modified and changed in diverse forms. For example, one latch among two latches is included in a page buffer, and the other may be disposed outside the page buffer.
- the flash memory device 200 is identical to that of FIG. 3 except that the page buffers 251 and 152 have a dual latch structure. Therefore, operations of the bit line select circuit 140 , the controller 170 , and the page buffer 250 may be substantially identical to those of FIG. 3 .
- Like reference numbers refer to like elements throughout the drawings. Its detailed description will be omitted for conciseness.
- FIG. 5 shows a flowchart including a method of programming a flash memory device according to an embodiment of the present invention
- FIG. 5 also illustrates a multi bit programming method that can prevent the change of a threshold voltage, which is caused by charge coupling between the memory cells 40 , 50 , and 60 arranged in the same row.
- the memory cell may be programmed to have one of states 11, 01, 10, and 00.
- the states are just examples, and may be modified in various forms.
- the memory cell having a state 11 is an erased memory cell.
- the threshold voltage of the memory cell having a state 01 is higher than that of the memory cell having a state 11.
- the threshold voltage of the memory cell having a state 10 is higher than that of the memory cell having a state 01.
- the threshold voltage of the memory cell having a state 00 is higher than that of the memory cell having a state 10.
- LSB data bit one data bit (hereinafter, referred to as a Least Significant Bit, or LSB data bit) among two data bits is programmed first and then another data bit (hereinafter, referred to as a Most Significant Bit, or MSB data bit) is programmed last.
- the former is called an LSB program operation, and the latter is called an MSB program operation.
- the LSB program operation may be substantially similar to the single bit data program operation, but the MSB program operation may be substantially different from the LSB program operation.
- the programming method of the present invention may perform the LSB program on the memory cells 40 and 50 of the same row coupled to the plurality of adjacent bit lines (for example, BL 1 e and BL 1 o ) in operation S 1000 . Then, the MSB program may be performed on the memory cells 40 and 50 in operation S 2000 .
- adjacent bit lines for example, BL 1 e and BL 1 o
- adjacent bit lines may be selected for programming before performing the LSB program and MSB program operations.
- the adjacent bit lines for example, BL 1 e and BL 1 o
- the adjacent bit lines may be activated. Therefore, a voltage difference does not occur between the memory cells 40 and 50 when a program voltage is applied to adjacent memory cells 40 and 50 through the word line.
- charge coupling does not occur between the adjacent memory cells 40 and 50 coupled to the activated bit lines (for example, BL 1 e and BL 1 o ). Contrarily, charge coupling occurs between the adjacent memory cell 60 and the selected memory cell 50 coupled to physically adjacent but deactivated bit lines (for example, BL 2 e ). In this case, charge coupling for the memory cells coupled to the same row is not completely eliminated. However, when taking the arbitrarily selected memory cell 50 as a reference, charge coupling occurs on only one side of the memory cell 50 , which occurs on both sides of the memory cell 50 in traditional methods. Consequently, the change of threshold voltage in the memory cell due to charge coupling is reduced by half.
- FIG. 6 shows a flowchart including an LSB program operation S 1000 of FIG. 5 .
- FIG. 7 shows a flowchart including an MSB program operation S 2000 of FIG. 5 .
- FIGS. 6 and 7 illustrate an LSB program operation on two adjacent memory cells (hereinafter, referred to as first and second memory cells) coupled to the same row.
- LSB data when a host (not shown) requests an LSB program operation, a plurality of LSB data may be loaded into corresponding page buffers 151 and 152 , respectively, according to the control of the controller 170 in operation S 1100 .
- the LSB data may be programmed into the first and second memory cells 40 and 50 , which are adjacently arranged on the same row.
- an LSB program may be performed on the first and second memory cells 40 and 50 by using the loaded LSB data in operation S 1200 .
- the first and second memory cells 40 and 50 may be respectively coupled to the adjacently disposed and activated first and second bit lines BL 1 e and BL 1 o .
- a program verify process may be performed on one of the programmed memory cells 40 and 50 , i.e., the first memory cell 40 in operation S 1300 .
- a program verify process may be performed on the second cell 50 in operation S 1400 . In operations S 1300 and 1400 , it is determined whether the first and second memory cells 40 and 50 have a required threshold voltage or not.
- the LSB and MSB program operations for a region 120 in FIGS. 3 and 4 are described as an example. However, the example is used for understanding an embodiment of the present invention, and the number of simultaneously programmable adjacent memory cells may vary. The number of program verify operations may vary as frequently as the number of simultaneously programmable adjacent memory cells vary. The LSB program operation of the multi bit flash memory device may be applied to the single bit program operation.
- a plurality of MSB data may be loaded into the corresponding page buffer 151 and 152 .
- a first pre-read operation S 2200 and a second pre-read operation S 2300 may be performed to read states of the previously programmed data.
- the program state of the first memory cell 40 may be confirmed.
- the program state of the second memory cell 50 may be confirmed.
- the previously performed program state may be confirmed in operations S 2200 and S 2300 , and then the MSB programs for the first and second memory cells 40 and 50 may be simultaneously performed based on the program state and the MSB data loaded in the page buffers 151 and 152 in operation S 2400 .
- program verify operations may be sequentially performed on the memory cells 40 and 50 .
- MSB program method for one of states 01, 10, and 00 is described above as an example. As it is well known to those skilled in the art, the operation order of MSB 01 , MSB 10 , and MSB 00 programs may vary in diverse forms.
- FIGS. 8 through 12 show views of the result in addressing page according to a program method of an embodiment of the present invention.
- At least two memory cells coupled to the same row may have the same page address.
- a program or read operation of the NAND flash memory may be performed by a page unit, and an erase operation of the programmed data may be performed by a block unit.
- the block unit may include a plurality of pages. Therefore, adjacent memory cells having the same address may be simultaneously programmed.
- the page addressing method of FIGS. 8 and 9 may vary.
- FIG. 10 shows a view of program properties in memory cells according to page addressing of FIGS. 8 and 9 .
- parasitic capacitance Cx does not occur between the simultaneously programmed memory cells 40 and 50
- parasitic capacitance Cx occurs between memory cells 50 and 60 that are not simultaneously programmed.
- charge coupling occurs on both sides of the selected memory cell. Charge coupling that occurs during a program operation according to a program method of the present invention is reduced by half compared to transitional methods. If the number of memory cells that are simultaneously programmed among adjacent memory cells coupled to the same row increases, charge coupling occurring between the memory cells can be even more reduced.
- the number of memory cells with the same page address among memory cells coupled to the same row is not limited to two, and may be a natural number n.
- the n number of adjacent memory cells with the same page address in the same row may be programmed simultaneously, and the n number of simultaneously programmed memory cells may vary, and may correspond with at least one page buffer.
- a 1st page may correspond with page address 0 , which may include n number of adjacent memory cells, each having a LSB comprising the same page address 0 .
- a 2nd page may correspond with page address 1 , which may include the n number of adjacent memory cells, each having a MSB comprising the same page address 1 .
- FIG. 13 shows a view of program properties in memory cells according to page addressing of FIGS. 11 and 12 .
- a parasitic capacitance Cx does not occur between the simultaneously programmed memory cells 40 , 50 , and 60 .
- charge coupling which occurs between adjacent memory cells arranged in the same row during a program operation, may reduce the change of a threshold voltage. Accordingly, an additional reprogram operation is unnecessary to correct the change of a threshold voltage of adjacent memory cells, which is caused by charge coupling.
- the change of a threshold voltage, which is caused by charge coupling that occurs between adjacent memory cells arranged in the same row can be reduced and a program operation for corresponding memory cells can be performed at high speed without a program operation or an additional circuit.
- the change of a threshold voltage can be reduced without a program operation or an additional circuit.
- the change of a threshold voltage is caused by charge coupling that occurs between adjacent memory cells arranged in the same row. Consequently, an additional processor for correcting a threshold voltage in adjacent memory cells is omitted such that a program operation for a corresponding memory cell can be performed at higher speeds.
Abstract
A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.
Description
- This is a Continuation of U.S. patent application Ser. No. 11/855,978, filed on Sep. 14, 2007, now pending, which claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2006-92464, filed on Sep. 22, 2006, the entire contents of which are hereby incorporated by reference.
- The present invention disclosed herein relates to a semiconductor memory device, and more particularly, to a flash memory device capable of reducing charge coupling that occurs between adjacent memory cells coupled to the same row, and a method of programming the same.
- A semiconductor memory device is largely classified into a volatile semiconductor memory device and a non-volatile semiconductor memory device. The volatile semiconductor memory device is characterized of fast reading and writing speeds, but has limitations of losing stored content when no power is applied. Contrarily, the non-volatile semiconductor memory device retains the stored content even if no power is applied. Therefore, the non-volatile memory device is used for storing content that must remain regardless of power. The non-volatile memory device includes a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. Since a flash EEPROM (hereinafter, referred to as a flash memory) among non-volatile semiconductor memory devices has the higher degree of integration, compared to a typical EEPROM, it is advantageous to use the flash memory for a high capacity auxiliary memory device.
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FIG. 1 shows an array structure including a conventional flash memory device.FIG. 2 shows a vertical sectional view includingmemory cells FIG. 1 . - Referring to
FIGS. 1 and 2 , amemory cell array 10 may include a plurality of memory blocks including a plurality of bit lines BL1 e, BL1 o, BL2 e, . . . BLmo, which are arranged in parallel. Each memory block may include a plurality of NAND strings corresponding to the respective bit lines BL1 e, BL1 o, BL2 e, . . . BLmo. One memory block in thememory cell array 10 is illustrated as an example inFIG. 1 . - Each string may have a string select transistor SST and a ground select transistor GST. A plurality of floating gate transistors M0 to M31 (hereinafter, referred to as memory cells) used for memory cells may be coupled in series between the string select transistor SST and the ground select transistor GST. The memory cells M0 to M31 included in each string may be formed in the
same substrate 80. The memory cells M0 to M31 may include adjacent floating gate transistors and shared source-drain terminals in each string. A plurality of word lines WL<0> to WL<31> may intersect each string. - Looking at a structure of
adjacent memory cells gates - A
control gate 70 may be formed on thefloating gates memory cells control gate 70 may also be coupled to the corresponding word line WL<30>. - To program the memory cells, an erase process may be performed to have a predetermined threshold voltage (e.g., −3 V) in the memory cells. Then, a high voltage (e.g., 20 V) may be applied to the word line WL<30> for a predetermined time, which is coupled to a selected
memory cell 50. To accurately program theselected memory cell 50, the threshold voltage of theselected memory cell 50 may increase to a higher level, but the threshold voltage of thememory cells 40 and 60 (which are not selected) must stay without change. - When a program voltage is applied to the selected word line WL<30>, the program voltage is commonly supplied to the
selected memory cell 50 andunselected memory cells control gate 70. As illustrated inFIG. 2 , a parasitic capacitance Cx may be disposed between the adjacentfloating gates selected memory cell 50 andunselected memory cells selected memory cell 50 andunselected memory cells unselected memory cells memory cell 50 are accidentally programmed. At this point, the size of the rising threshold voltage Vth is in proportion to the size (i.e., 2Cx) of the parasitic capacitance Cx between theselected memory 50 andadjacent memory cells - Due to the change of a threshold voltage in the memory cell, which is caused by charge coupling, an unintended program operation occurs in the unselected memory cell. This is called program disturb. The program disturb in the flash memory device is disclosed in U.S. Pat. No. 5,867,429, entitled “HIGH DENSITY NON-VOLATILE FLASH MEMORY WITHOUT ADVERSE EFFECTS OF ELECTRIC FIELD COUPLING BETWEEN ADJACENT FLOATING GATES.” A method of reprogramming a part of memory cells after performing a program operation, which prevents the change of a threshold voltage in the memory cell due to charge coupling, is disclosed in U.S. Pat. No. 6,807,095, entitled “MULTI-STATE NONVOLATILE MEMORY CAPABLE OF REDUCING EFFECTS OF COUPLING BETWEEN STORAGE ELEMENTS.” According to the above method, the extensive threshold voltage distribution due to the charge coupling becomes less wide.
- However, an additional program operation is required for adjusting the threshold voltage distribution after performing a general program operation disclosed in U.S. Pat. No. 6,807,095. Consequently, a program time lengthens and controls become complicated. To accurately perform a program process, a new method is required to reduce the change of a threshold voltage, which occurs due to the charge coupling caused by adjacent memory cells arranged in the same row, without an additional program operation or an additional circuit.
- The present invention includes a flash memory device capable of reducing charge coupling, which occurs between adjacent memory cells coupled to the same row, and a method of programming the same.
- Some embodiments of the present invention include a flash memory device comprising: a memory array intersected by a first even bit line, a first odd bit line adjacent to the first even bit line, a second even bit line, and a second odd bit line adjacent to the second even bit line, and a plurality of word lines; a page buffer circuit including a first latch coupled to an even virtual bit line and a second latch coupled to an odd virtual bit line, the even virtual bit line being coupled to the first and second even bit lines, and the odd virtual bit line being coupled to the first and second odd bit lines; and a select circuit configured to electrically couple one of the first even bit line and the second even bit line to the first latch, and to electrically couple one of the first odd bit line and the second odd bit line to the second latch.
- Some embodiments of the present invention include a method for programming a memory cell, comprising: electrically coupling a first bit line to a first latch; electrically coupling a second bit line to a second latch, the second bit line being adjacent to the first bit line; electrically decoupling a third bit line from the first latch, the third bit line being adjacent to the second bit line; and programming adjacent memory cells in a same word line associated with the first bit line and the second bit line responsive to data stored in the first latch and the second latch.
- The accompanying figures are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the figures:
-
FIG. 1 shows a view of an array structure including a conventional flash memory device; -
FIG. 2 shows a vertical sectional view including memory cells arranged in the same row ofFIG. 1 ; -
FIG. 3 shows a block diagram including a flash memory device according to an embodiment of the present invention; -
FIG. 4 shows a block diagram including a flash memory device according to another embodiment of the present invention; -
FIG. 5 shows a flowchart including a method of programming a flash memory device according to the present invention; -
FIG. 6 shows a flowchart including an LSB program operation ofFIG. 5 ; -
FIG. 7 shows a flowchart including an MSB program operation ofFIG. 5 ; -
FIGS. 8 and 9 show views of the result in addressing a page used for a programming method according to embodiments the present invention; -
FIG. 10 shows a view of program properties in memory cells according to page addressing ofFIGS. 8 and 9 ; -
FIGS. 11 and 12 show views of the result in addressing a page used for a programming method according to embodiments the present invention; and -
FIG. 13 shows a view of program properties in memory cells according to page addressing ofFIGS. 11 and 12 . - Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Hereinafter, exemplary embodiments of the present invention will be described in conjunction with the accompanying drawings.
- An embodiment of a flash memory device of the present invention simultaneously programs at least two adjacent memory cells (for example, memory cells of the same row respectively coupled to even bit lines and odd bit lines, which are adjacent to each other) arranged in the same row. According to the above program method, a charge coupling effect is drastically reduced in memory cells adjacent to another memory cell that will be programmed. Therefore, the change of threshold voltage in the adjacent memory cells arranged in the same row where the selected memory cell is arranged significantly decreases. A structure of a flash memory device and a method of programming the same will be described in detail as follows.
-
FIG. 3 shows a block diagram including aflash memory device 100 according to an embodiment of the present invention. Theflash memory device 100 is a NAND flash memory device with a single latch structure, which may be used for storing a single bit data, or storing a multi bit data in One-NAND memory having a buffer therein. - Referring to
FIG. 3 , theflash memory device 100 may include amemory cell array 110, a row decoder 130 (X-DEC inFIG. 3 ), a bit lineselect circuit 140, apage buffer circuit 150, and acontroller 170. Thememory cell array 110 may include a plurality of memory blocks. Only one memory block among the plurality of memory blocks is illustrated inFIG. 3 . Each memory block may include a plurality of memory cells arranged on intersected regions of word lines WL0 to WLn and bit lines BL1 e, BL1 o, BL2 e, BL2 o, and so forth. The memory cells may include a string structure. The string structure of the memory cell was described in detail with reference toFIG. 1 . Thus, the overlapping description will be omitted here for conciseness. - The rows of the
memory cell array 110 may be driven by therow decoder circuit 130, and columns may be driven by apage buffer circuit 150. Thepage buffer circuit 150 may be controlled by acontroller 170 and may operate as a write driver or a sense amplifier according to an operation mode. Due to the operation characteristics, thepage buffer circuit 150 may be called a sense and latch circuit. Thepage buffer circuit 150 may include a plurality of page buffers 151, 152, and so forth, corresponding to the respective bit lines or a pair of bit lines.FIG. 3 illustrates page buffers 151 and 152 corresponding to adjacent two even bit lines BL1 e and BL2 e, or adjacent two odd bit lines BL1 o and BL2 o. - Still referring to
FIG. 3 , the adjacent two even bit lines BL1 e and BL2 e may be coupled to thepage buffer 151 through an even virtual bit line VBLe. The adjacent two odd bit lines BL1 o and BL2 o may be coupled to thepage buffer 152 through an odd virtual bit line VBLo. The even bit lines and odd bit lines are alternately arranged. A bit line structure coupled to each of page buffers 151, 152, and so forth, may vary within the scope of the present invention. A bit line switching operation of the bit lineselect circuit 140 may determine which bit line is selected among two bit lines coupled to the page buffers 151, 152, and so forth. - The bit line
select circuit 140 may include a plurality of switchingtransistors 141 to 144 coupled to the bit lines BL1 e, BL1 o, BL2 e, BL2 o, and so forth. The switchingtransistors 141 to 144 may be turned on/off according to switching control signals D1 to D4 generated from thecontroller 170, in order to selectively activate the corresponding bit lines BL1 e, BL1 o, BL2 e, and BL2 o. - At least two adjacent bit lines among the bit lines BL1 e, BL1 o, BL2 e, and BL2 o may be activated and the activated bit lines may be electrically coupled to the page buffers 151 and 152. The switching
transistors transistors transistors transistors transistors switching transistors FIGS. 5 through 7 . In this case, charge coupling that occurs between theadjacent memory cells FIGS. 8 through 13 . Referring toFIG. 3 , areference number 120 represents simultaneously programmed memory cells and a page buffer corresponding to the memory cells. -
FIG. 4 shows a block diagram including aflash memory device 200 according to another embodiment of the present invention, and illustrates a NANDflash memory device 200 with a dual latch structure. Theflash memory device 200 with a dual latch structure may be used for storing multi bit data, and the dual latch structure may be modified and changed in diverse forms. For example, one latch among two latches is included in a page buffer, and the other may be disposed outside the page buffer. - Referring to
FIG. 4 , theflash memory device 200 is identical to that ofFIG. 3 except that the page buffers 251 and 152 have a dual latch structure. Therefore, operations of the bit lineselect circuit 140, thecontroller 170, and thepage buffer 250 may be substantially identical to those ofFIG. 3 . Like reference numbers refer to like elements throughout the drawings. Its detailed description will be omitted for conciseness. -
FIG. 5 shows a flowchart including a method of programming a flash memory device according to an embodiment of the present invention,FIG. 5 also illustrates a multi bit programming method that can prevent the change of a threshold voltage, which is caused by charge coupling between thememory cells - In a case of a multi bit program where one
memory cell stores 2 bit data therein, the memory cell may be programmed to have one ofstates state 11 is an erased memory cell. The threshold voltage of the memory cell having a state 01 is higher than that of the memory cell having astate 11. The threshold voltage of the memory cell having astate 10 is higher than that of the memory cell having a state 01. The threshold voltage of the memory cell having a state 00 is higher than that of the memory cell having astate 10. In the memory cell, one data bit (hereinafter, referred to as a Least Significant Bit, or LSB data bit) among two data bits is programmed first and then another data bit (hereinafter, referred to as a Most Significant Bit, or MSB data bit) is programmed last. The former is called an LSB program operation, and the latter is called an MSB program operation. Generally, the LSB program operation may be substantially similar to the single bit data program operation, but the MSB program operation may be substantially different from the LSB program operation. - Referring to
FIG. 5 , the programming method of the present invention may perform the LSB program on thememory cells memory cells FIG. 5 , adjacent bit lines (for example, BL1 e and BL1 o) may be selected for programming before performing the LSB program and MSB program operations. In this case, the adjacent bit lines (for example, BL1 e and BL1 o) may be activated. Therefore, a voltage difference does not occur between thememory cells adjacent memory cells - According to the programming method of the present invention, charge coupling does not occur between the
adjacent memory cells adjacent memory cell 60 and the selectedmemory cell 50 coupled to physically adjacent but deactivated bit lines (for example, BL2 e). In this case, charge coupling for the memory cells coupled to the same row is not completely eliminated. However, when taking the arbitrarily selectedmemory cell 50 as a reference, charge coupling occurs on only one side of thememory cell 50, which occurs on both sides of thememory cell 50 in traditional methods. Consequently, the change of threshold voltage in the memory cell due to charge coupling is reduced by half. -
FIG. 6 shows a flowchart including an LSB program operation S1000 ofFIG. 5 .FIG. 7 shows a flowchart including an MSB program operation S2000 ofFIG. 5 .FIGS. 6 and 7 illustrate an LSB program operation on two adjacent memory cells (hereinafter, referred to as first and second memory cells) coupled to the same row. - Referring to
FIG. 6 , when a host (not shown) requests an LSB program operation, a plurality of LSB data may be loaded into corresponding page buffers 151 and 152, respectively, according to the control of thecontroller 170 in operation S1100. The LSB data may be programmed into the first andsecond memory cells - Thus, an LSB program may be performed on the first and
second memory cells second memory cells second memory cells memory cells first memory cell 40 in operation S1300. Then, a program verify process may be performed on thesecond cell 50 in operation S1400. In operations S1300 and 1400, it is determined whether the first andsecond memory cells - Next, it may be determined whether all the
memory cells memory cells memory cells - The LSB and MSB program operations for a
region 120 inFIGS. 3 and 4 are described as an example. However, the example is used for understanding an embodiment of the present invention, and the number of simultaneously programmable adjacent memory cells may vary. The number of program verify operations may vary as frequently as the number of simultaneously programmable adjacent memory cells vary. The LSB program operation of the multi bit flash memory device may be applied to the single bit program operation. - Referring to
FIG. 7 , when the host requests the MSB program operation, a plurality of MSB data may be loaded into the correspondingpage buffer first memory cell 40 may be confirmed. In the second pre-read operation, the program state of thesecond memory cell 50 may be confirmed. - The previously performed program state may be confirmed in operations S2200 and S2300, and then the MSB programs for the first and
second memory cells memory cells second memory cells memory cells memory cells memory cells - The MSB program method for one of
states 01, 10, and 00 is described above as an example. As it is well known to those skilled in the art, the operation order of MSB 01, MSB10, and MSB00 programs may vary in diverse forms. -
FIGS. 8 through 12 show views of the result in addressing page according to a program method of an embodiment of the present invention. - Referring to
FIGS. 8 and 9 , at least two memory cells coupled to the same row may have the same page address. A program or read operation of the NAND flash memory may be performed by a page unit, and an erase operation of the programmed data may be performed by a block unit. The block unit may include a plurality of pages. Therefore, adjacent memory cells having the same address may be simultaneously programmed. The page addressing method ofFIGS. 8 and 9 may vary. -
FIG. 10 shows a view of program properties in memory cells according to page addressing ofFIGS. 8 and 9 . Referring toFIGS. 8 through 10 , when at least two adjacent memory cells coupled to the same row are simultaneously programmed, parasitic capacitance Cx does not occur between the simultaneously programmedmemory cells memory cells - Referring to
FIG. 11 and 12 , the number of memory cells with the same page address among memory cells coupled to the same row is not limited to two, and may be a natural number n. The n number of adjacent memory cells with the same page address in the same row may be programmed simultaneously, and the n number of simultaneously programmed memory cells may vary, and may correspond with at least one page buffer. For example, inFIG. 11 , a 1st page may correspond withpage address 0, which may include n number of adjacent memory cells, each having a LSB comprising thesame page address 0. Similarly, a 2nd page may correspond withpage address 1, which may include the n number of adjacent memory cells, each having a MSB comprising thesame page address 1. -
FIG. 13 shows a view of program properties in memory cells according to page addressing ofFIGS. 11 and 12 . Referring toFIGS. 11 through 13 , a parasitic capacitance Cx does not occur between the simultaneously programmedmemory cells - According to various embodiments of the present invention, the change of a threshold voltage can be reduced without a program operation or an additional circuit. The change of a threshold voltage is caused by charge coupling that occurs between adjacent memory cells arranged in the same row. Consequently, an additional processor for correcting a threshold voltage in adjacent memory cells is omitted such that a program operation for a corresponding memory cell can be performed at higher speeds.
- The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Claims (13)
1. A flash memory device comprising:
an array of memory cells disposed on intersection regions of a plurality of bit lines and a plurality of word lines;
a select circuit to select a plurality of bit lines arranged adjacently; and
a page buffer circuit to program a plurality of adjacent memory cells in the same word line corresponding to the selected bit lines,
wherein Least Significant Bits (LSB) of the adjacent memory cells are simultaneously programmed, and Most Significant Bits (MSB) of the adjacent memory cells are simultaneously programmed.
2. The flash memory device of claim 1 , wherein the select circuit electrically couples a first bit line to a first latch of the page buffer circuit, and couples a second bit line to a second latch of the page buffer circuit.
3. The flash memory device of claim 2 , wherein the plurality of adjacent memory cells in the same word line associated with the first bit line and the second bit line are simultaneously programmed responsive to data stored in the first latch and the second latch.
4. The flash memory device of claim 1 , wherein the adjacent memory cells on the same word line have a same page address.
5. The flash memory device of claim 4 , wherein the LSB of the adjacent memory cells comprise a first page address, and wherein the MSB of the adjacent memory cells comprise a second page address.
6. A flash memory device comprising:
a memory array intersected by a plurality of bit lines;
a select circuit configured to electrically couple a first even bit line to a first latch, and to electrically couple a second bit line being adjacent to the first bit line to a second latch; and
a page buffer circuit to program a plurality of adjacent memory cells in a same word line associated with the first bit line and the second bit line responsive to data stored in the first latch and the second latch.
7. The flash memory device of claim 6 , wherein the adjacent memory cells in the same word line have a same page address.
8. The method of claim 6 , wherein a Least Significant Bit (LSB) of each of the adjacent memory cells are simultaneously programmed, and wherein a Most Significant Bit (MSB) of each of the adjacent memory cells are simultaneously programmed.
9. The method of claim 8 , wherein the LSB of each of the adjacent memory cells comprise a first page, and wherein the MSB of each of the adjacent memory cells comprise a second page.
10. A method for programming a memory cell, comprising:
selecting n adjacent memory cells coupled to n adjacent bit lines, each of the n adjacent memory cells having a Least Significant Bit (LSB) and a Most Significant Bit (MSB); and
simultaneously programming the selected n adjacent memory cells of a word line.
11. The method of claim 10 , wherein the n adjacent memory cells in the same word line have a same page address.
12. The method of claim 10 , wherein the LSB of each of the adjacent memory cells are simultaneously programmed, and wherein the MSB of each of the adjacent memory cells are simultaneously programmed.
13. The method of claim 12 , wherein the LSB of each of the adjacent memory cells comprise a first page, and wherein the MSB of each of the adjacent memory cells comprise a second page.
Priority Applications (1)
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US12/536,450 US20090290421A1 (en) | 2006-09-22 | 2009-08-05 | Flash memory device and method of programming the same |
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KR2006-092464 | 2006-09-22 | ||
KR1020060092464A KR100879387B1 (en) | 2006-09-22 | 2006-09-22 | Flash memory device and program method thereof |
US11/855,978 US7583540B2 (en) | 2006-09-22 | 2007-09-14 | Flash memory device and method of programming the same |
US12/536,450 US20090290421A1 (en) | 2006-09-22 | 2009-08-05 | Flash memory device and method of programming the same |
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US11/855,978 Continuation US7583540B2 (en) | 2006-09-22 | 2007-09-14 | Flash memory device and method of programming the same |
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US11/855,978 Active 2027-10-24 US7583540B2 (en) | 2006-09-22 | 2007-09-14 | Flash memory device and method of programming the same |
US12/536,450 Abandoned US20090290421A1 (en) | 2006-09-22 | 2009-08-05 | Flash memory device and method of programming the same |
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US11/855,978 Active 2027-10-24 US7583540B2 (en) | 2006-09-22 | 2007-09-14 | Flash memory device and method of programming the same |
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KR (1) | KR100879387B1 (en) |
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CN102103889A (en) * | 2009-12-22 | 2011-06-22 | 英特尔公司 | NAND programming technique |
US8441854B2 (en) | 2010-09-30 | 2013-05-14 | SK Hynix Inc. | Nonvolatile memory apparatus capable of reducing current consumption and related driving method |
US8520442B2 (en) * | 2009-12-31 | 2013-08-27 | SK Hynix Inc. | Method of operating semiconductor memory device |
CN103456364A (en) * | 2012-05-29 | 2013-12-18 | 爱思开海力士有限公司 | Semiconductor device and operating method thereof |
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KR100880320B1 (en) * | 2007-07-25 | 2009-01-28 | 주식회사 하이닉스반도체 | Flash memory device and method of programming the same |
KR100908560B1 (en) * | 2007-08-06 | 2009-07-21 | 주식회사 하이닉스반도체 | Program method of flash memory device |
US8130556B2 (en) | 2008-10-30 | 2012-03-06 | Sandisk Technologies Inc. | Pair bit line programming to improve boost voltage clamping |
KR101619249B1 (en) | 2009-11-26 | 2016-05-11 | 삼성전자주식회사 | Program method |
US8374028B2 (en) | 2011-01-19 | 2013-02-12 | Micron Technology, Inc. | Sense operation in a memory device |
US8885405B2 (en) * | 2013-01-31 | 2014-11-11 | Ememory Technology Inc. | Flash memory and associated programming method |
US8995195B2 (en) | 2013-02-12 | 2015-03-31 | Sandisk Technologies Inc. | Fast-reading NAND flash memory |
JP2015041402A (en) * | 2013-08-23 | 2015-03-02 | 株式会社東芝 | Nonvolatile semiconductor storage device and data writing method |
KR20160044923A (en) * | 2014-10-16 | 2016-04-26 | 에스케이하이닉스 주식회사 | Semiconductor memory device including a plurality of memory cells and operating method thereof |
US9589646B2 (en) * | 2014-11-26 | 2017-03-07 | Macronix International Co., Ltd. | Page buffer circuit having bias voltage application unit and operating method of same |
KR102239868B1 (en) * | 2014-11-28 | 2021-04-13 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
JP6502452B1 (en) * | 2017-10-12 | 2019-04-17 | ウィンボンド エレクトロニクス コーポレーション | Semiconductor memory device |
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Also Published As
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KR100879387B1 (en) | 2009-01-20 |
US20080074923A1 (en) | 2008-03-27 |
US7583540B2 (en) | 2009-09-01 |
KR20080027047A (en) | 2008-03-26 |
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