US20100061207A1 - Data storage device including self-test features - Google Patents
Data storage device including self-test features Download PDFInfo
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- US20100061207A1 US20100061207A1 US12/206,968 US20696808A US2010061207A1 US 20100061207 A1 US20100061207 A1 US 20100061207A1 US 20696808 A US20696808 A US 20696808A US 2010061207 A1 US2010061207 A1 US 2010061207A1
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- storage media
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/36—Monitoring, i.e. supervising the progress of recording or reproducing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2508—Magnetic discs
- G11B2220/2516—Hard disks
Definitions
- the present disclosure is generally related to a data storage device including self-test features.
- Storage devices typically include non-volatile storage media, such as magnetic discs within a hard disc drive and flash memory chips within a solid-state drive.
- Some storage systems such as a hybrid disc drive, contain a mixture of non-volatile media types.
- hybrid disc drives include non-volatile electronics, such as flash memory, that can be used in conjunction with the non-volatile rotating storage media to retain data through power loss and reset events.
- solid-state memory such as NAND flash memory
- data are erased in blocks and are read/written in pages.
- a block often contains multiple pages.
- valid data it is common for valid data to be read from the memory to another location (such as into a volatile memory buffer), modified and written to an erased data block.
- the data are written back to the same block from which they were read, where the block is erased after the data is read but before the modified data is written to the block.
- the data are written to a previously-erased block elsewhere within the storage device.
- the storage cell of the solid-state memory can deteriorate over time as it is exposed to multiple erase/write/read cycles. Further, solid-state memories and hard disc storage media may deteriorate at different rates.
- While storage systems can store data in non-volatile media for retention, in many cases it is advantageous to keep data in a volatile memory buffer, such as a dynamic random access memory (DRAM).
- a volatile memory buffer such as a dynamic random access memory (DRAM).
- data may be stored in a DRAM to improve the performance of the storage system or to reduce the wear on the storage components by reducing erases and writes.
- DRAM dynamic random access memory
- the protection of such information is valuable enough to warrant additional protection of the volatile buffer to make the information held in the buffer non-volatile. This protection generally requires the use of an internal energy source within the storage system. In a disc drive, the kinetic momentum of the rotating disc pack can be used as an energy source.
- the rotating disc pack energy source can be replaced or augmented by an auxiliary power device, such as a battery or a double-layer capacitor.
- an auxiliary power device such as a battery or a double-layer capacitor.
- solid-state drives do not include a kinetic energy source, so such drives typically contain an auxiliary power device to provide this protection. In both of these cases, however, a failure related to such auxiliary power sources can cause unexpected loss or corruption of data.
- a data storage device includes a non-volatile storage media adapted to store data and a measurement circuit adapted to measure at least one performance parameter related to the non-volatile storage media during operation.
- the data storage device further includes logic coupled to the measurement circuit and adapted to predict a failure associated with at least a portion of the non-volatile storage media when the measured performance parameter exceeds a threshold value.
- a storage device in another particular embodiment, includes one or more storage media to store data and a measurement circuit adapted to measure at least one performance parameter associated with at least one of the one or more storage media.
- the storage device further includes a control circuit coupled to the measurement circuit and to the one or more storage media.
- the control circuit is adapted to control read, write, and erase (if erasure is required) access to the one or more storage media.
- the control circuit detects a failure associated with at least one of the one or more storage media when the at least one performance parameter exceeds a threshold.
- the control circuit initiates a corrective action in response to the detected failure.
- a method in still another particular embodiment, includes measuring a performance parameter associated with at least one storage media of a storage device via a measurement circuit within the storage device when the at least one storage media is accessed. The method further includes predicting a failure when the performance parameter exceeds a threshold and preventing data loss or corruption by taking a corrective action in response to the predicted failure.
- a method in yet another particular embodiment, includes measuring a performance parameter associated with internal power supplying components of the storage system. The method further includes predicting a failure when the performance parameter exceeds a threshold and preventing data loss or corruption by taking a corrective action in response to the predicted failure.
- FIG. 1 is a block diagram of a particular illustrative embodiment of a system including a hybrid storage device that has a measurement circuit and a spindle power monitor to test the storage device;
- FIG. 2 is a block diagram of a second particular illustrative embodiment of a system including a storage device that has a device health monitor to test the storage device;
- FIG. 3 is a flow diagram of a particular illustrative embodiment of a method of performing a self-test of a storage device
- FIG. 4 is a flow diagram of a second particular illustrative embodiment of a method of performing a self-test of a storage device
- FIG. 5 is a flow diagram of a third particular illustrative embodiment of a method of performing a self-test of a storage device
- FIG. 6 is a flow diagram of a fourth particular illustrative embodiment of a method of performing a self-test of a storage device.
- FIG. 7 is a flow diagram of a fifth particular illustrative embodiment of a method of performing a self-test of a storage device.
- FIG. 1 is a block diagram of a particular illustrative embodiment of a system 100 including a hybrid storage device 102 that has a measurement circuit 124 and a power monitor 132 used to test the storage device 102 .
- the term “hybrid storage device” refers to a data storage device that includes both rotating storage media and solid-state storage media.
- the storage device 102 is adapted to communicate with a host system 104 .
- the host system 104 is typically a computer, but could be a bus expander, a processor, a personal digital assistant (PDA), another electronic device, or more generally any device capable of generating and/or relaying commands to a mass storage device.
- PDA personal digital assistant
- the storage device 102 includes recording subsystem circuitry 106 , a head-disc assembly 108 , and disc-head assembly control circuitry 120 , which includes monitoring circuitry.
- the recording subsystem circuitry 106 includes an interface circuit 112 , which includes a data buffer for temporarily buffering the data and a sequencer for directing the operation of the read/write channel 116 and the preamplifier 150 during data transfer operations.
- the interface circuit 112 is coupled to the host system 104 and to a control processor 118 , which is adapted to control operation of the storage device 102 .
- the control processor 118 includes device failure prediction logic 119 that is adapted to predict a failure associated with the storage device 102 based on one or more measured performance parameters.
- the device failure prediction logic 119 can be separate from the control processor 118 .
- the device failure prediction logic 119 can be included within the measurement circuit 124 .
- the control processor 118 is coupled to a servo circuit 122 that is adapted to control the position of one or more read/write heads 154 relative to one or more discs 156 as part of a servo loop established by the one or more read/write heads 154 .
- the one or more read/write heads 154 are mounted to a rotary actuator assembly to which a coil 152 of a voice coil motor (VCM) is attached.
- VCM voice coil motor
- a VCM includes a pair of magnetic flux paths between which the coil 152 is disposed so that the passage of current through the coil causes magnetic interaction between the coil 152 and the magnetic flux paths, resulting in the controlled rotation of the actuator assembly and the movement of the one or more heads 154 relative to the surfaces of the one or more discs 156 .
- the servo circuit 122 is used to control the application of current to the coil 152 , and hence the position of the heads 154 with respect to the tracks of the one or more discs 156 .
- the disc-head assembly control circuitry 120 includes the servo circuit 122 and includes a spindle circuit 126 that is coupled to a spindle motor 158 to control the rotation of the one or more discs 156 .
- the disc-head assembly control circuitry 120 further includes a measurement circuit 124 that is coupled to the control processor 118 and that is adapted to measure one or more electrical parameters associated with the storage device 102 .
- the disc-head assembly control circuitry 120 includes a power monitor 132 that is coupled to the spindle circuit 126 and adapted to measure the usable energy available in the back electromotive force associated with the spindle motor 158 .
- the back electromotive force represents the spindle motor 158 operating as a generator, utilizing a kinetic inertia associated with the rotation of the one or more discs 156 to generate the back EMF.
- the energy from the back EMF may be measured as a power level.
- the control processor 118 programs the data into the non-volatile memory component, such as the data flash 134 .
- the measurement circuitry 124 can record the time it took to program the data flash 134 .
- the control processor 118 can then program one bit of memory (of the data flash 134 ) at fixed periodic intervals until the power from the spindle motor 158 has been exhausted.
- the device failure prediction logic 119 can use the stored bits to determine how much power the spindle motor 158 supplied.
- the storage device 102 also includes an auxiliary power device 130 that is coupled to the spindle power monitor 132 and to the measurement circuit 124 .
- the auxiliary power device 130 can be a capacitor or a battery that is adapted to supply power to the storage device 102 under certain operating conditions.
- the auxiliary power device 130 can provide a power supply to the recording subsystem assembly 106 and to the disc-head assembly 108 to record data to the one or more discs 156 when power is turned off.
- the auxiliary power device 130 may supply power to the recording subsystem assembly 106 to record data to a data flash 134 or to a code (NOR) flash 138 when power is turned off.
- the storage device 102 includes a non-volatile solid-state storage component for data, labeled “data (NAND) flash” 134 .
- data (NAND) flash is shown in FIG. 1
- the flash memory 134 could be any non-volatile electronic storage component capable of storing data.
- the flash memory 134 could be NAND flash, NOR flash, MRAM, phase-change memory, another solid-state memory, or any combination thereof.
- the storage device 102 typically includes a dynamic random access memory (DRAM) 136 , and or other memory, or any combination thereof.
- DRAM dynamic random access memory
- the storage device 102 includes internal code storage 138 .
- the internal code storage block shown generally indicated at 138 is labeled for purposes of easy comprehension as “code (NOR) flash”, the “code (NOR) flash 138 could be any non-volatile solid-state storage component, and in some embodiments the code storage might only exist as a portion of the data storage component 134 .
- the code (NOR) flash 138 stores self-test instructions 140 , including instructions to monitor particular performance parameters associated with the storage device 102 each time data is written to, read from, and/or erased from the storage device 102 .
- the self-test instructions 140 include a sequence of data values that can be written to an erased block within the data (NAND) flash 134 , for example, while the write time is measured by the measurement circuit 124 .
- the storage device 102 frequently erases, writes and reads non-volatile electronics (NVE), such as the data (NAND) flash 134 and the code (NOR) flash 138 , to retain data through power loss and reset events.
- NVE non-volatile electronics
- erasing and writing of the NVE is typically accomplished by storing and depleting electrical charges in a “floating” gate in a NOR or NAND gate cell, many of which are included in a single NVE memory.
- NOR code
- erasing and writing are accomplished by heating and cooling chalcogenic material to switch it between amorphous and crystalline states.
- NVE non-volatile electronics
- the measurement circuit 124 measures and records a length of time to complete an erase/write/read operation for a portion of the memory, such as a block, page, segment, paragraph, etc. or for the entire memory. Not shown here, it is a common practice to perform signal conditioning, such as to normalize and/or filter the measured times.
- the device failure prediction logic 119 is adapted to compare the measured erase/write/read time to a corresponding threshold, and if the threshold is exceeded, the device failure prediction logic 119 is adapted to initiate one or more recover steps via the control processor 118 .
- the one or more recovery steps can include, but are not limited to, retrying the operation, performing additional testing on the storage, reconditioning the storage, reallocating the affected block/page, asserting an error message to the host system 104 , posting an error, and performing further testing on the flash segment.
- the device failure prediction logic 119 may be adapted to monitor programming time on a historical basis and to use trends, filtered or unfiltered, to make intelligent device failure predictions.
- the data storage device 102 includes a non-volatile storage media, such as the one or more discs 156 , the data (NAND) flash 134 , the code (NOR) flash 138 , other memory 140 , or any combination thereof.
- the non-volatile storage media is adapted to store data, including instructions executable by the control processor, user data, measurement data, other information, or any combination thereof.
- the storage device 102 includes the measurement circuit 124 that is adapted to measure at least one performance parameter related to the non-volatile storage media during operation.
- the at least one performance parameter is an erase time, a write time, a read time, or any combination thereof, that is associated with the data (NAND) flash 134 , the code (NOR) flash 138 , the other memory 142 , or any combination thereof.
- the at least one performance parameter is the usable energy available from the back electromotive force associated with the spindle motor 158 .
- the back electromotive force represents electrical energy generated by the spindle motor 158 using a kinetic inertia associated with rotation of the one or more discs 156 .
- the at least one performance parameter is a power level associated with the auxiliary power device 130 when the auxiliary power device 130 supplies power to the recording subsystem assembly 106 .
- the logic when the measured power level of the auxiliary power device 130 falls below a power threshold, the logic is adapted to predict a failure associated with the auxiliary power device 130 , which may indicate that the storage device 102 may be unable to record data to the non-volatile storage media when power is lost. In this example, the logic is adapted to take a corrective action to prevent data loss in response to the predicted failure. In still another example, when the measured back EMF from the spindle motor 158 falls below an EMF threshold, the logic is adapted to predict a failure and to take action to prevent data loss.
- the test patterns can include a pattern of all one (“1”) values, a pattern of all zero (“0”) values, a “walking ones” pattern, a “walking zeroes” pattern, a pattern containing the logical or physical storage address, a pseudorandom pattern, another pattern, or any combination thereof.
- the control processor 118 is adapted to use the self-test instructions 140 to erase and reprogram the data (NAND) flash 134 .
- the measurement circuitry 124 measures the erase/write/read time.
- the device contains voltage regulator circuitry 128 that can be controlled to provide a higher or lower voltage than normal, “margining” the voltage supply to provide additional stress factors that can ferret out weak or defective components.
- the control processor 118 uses the built-in self-test instructions 140 to run a series of erase/programming cycles against the memory using the patterns. The tests can be repeated with the voltage margined high or low. The results of the tests can be used to identify failing components and to make decision about the overall health of the storage device 102 .
- the storage device 102 can include a programmable clock that allows the data (NAND) flash 134 , the code (NOR) flash 138 , other memory, or any combination thereof to be run at faster or slower than normal clock speeds, providing additional stress on the non-volatile electronics. Further, testing may be performed using various combinations of the above stresses.
- FIG. 2 is a block diagram of a second particular illustrative embodiment of a system 200 including a data storage device 202 that has a device health monitor 216 to test the data storage device 202 .
- the data storage device 202 is a solid-state memory device that is adapted to communicate with a host system 204 via an interface 206 .
- the data storage device 202 includes a control circuit 208 that is adapted to communicate with a primary storage media 210 and with other memory 214 .
- the control circuit 208 is also coupled to an auxiliary power component 212 .
- the auxiliary power component 212 is an energy storage component, such as a battery or a capacitor, which is adapted to provide auxiliary power to the storage device 202 when power is lost.
- the control circuit 208 is also coupled to the device health monitor 216 , which monitors one or more performance parameters associated with the storage device 202 to predict a storage device failure.
- the device health monitor 216 includes a built-in self-test feature 218 , which may be used by the controller 208 to test a health associated with the primary storage media 210 or the other memory 214 .
- the built-in self-test feature 218 includes instructions executable by the control circuit 208 to erase a block of data from a selected memory, such as the primary storage media 210 , to write a new page of data to the selected memory, and to read a page of data from the selected memory.
- the built-in self-test feature 218 may also include a data sequence to be written to the selected memory.
- the device health monitor 216 also includes an auxiliary power device monitor 220 adapted to monitor a power supplied by the auxiliary power component 212 when the auxiliary power component 212 is acting as an energy source.
- the device health monitor 216 further includes one or more performance thresholds 222 .
- the device health monitor 216 may include a spindle energy power monitor 224 , when the primary storage media 210 is a rotating storage media that is rotated using a spindle motor, such as the spindle motor 158 illustrated in FIG. 1 .
- the spindle energy power monitor 224 may be omitted.
- the device health monitor 216 further includes a programming time monitor 226 that is adapted to monitor an erase time, a write time, a read time, or any combination thereof, when data are erased, written, or read to/from a selected memory, such as the primary storage media 210 or the other memory 214 .
- the device health monitor 216 includes a performance measurement log 228 that is adapted to record measurement data related to the one or more measured performance parameters.
- the device health monitor 216 includes device failure prediction logic 230 that is adapted to predict a failure associated with the storage device 202 based on at least one of the one or more measured performance parameters.
- the storage device 202 includes a control circuit 208 that is coupled to a non-volatile storage media, such as the primary storage media 210 , the other memory 214 , or any combination thereof.
- the control circuit 208 is adapted to control read/write access to the non-volatile storage media.
- the device health monitor 216 is adapted to monitor one or more performance parameters associated with the storage device 202 to predict a failure associated with the storage device 202 , when at least one of the one or more performance parameters exceeds a respective performance threshold of the one or more performance thresholds 222 .
- control circuit 208 is adapted to take corrective action to prevent data loss in response to the predicted failure.
- control circuit 208 is adapted to reallocate data from a first portion 232 of the primary storage media 210 to a second portion 234 of the primary storage media 210 in response to the predicted failure.
- control circuit 208 is adapted to prohibit access to the first or second portions 232 or 234 of the primary storage media 210 in response to the predicted failure.
- control circuit 208 disables volatile write-caching as a response to a predicted failure.
- the control circuit 208 is adapted to generate an alert and to send the alert to the host system 204 via the interface 206 in response to the predicted failure.
- the primary storage media 210 is a non-volatile, solid-state memory.
- the device health monitor 216 is adapted to utilize the built-in self-test feature 218 and the programming time monitor 226 each time the primary storage media 210 is accessed to determine a time parameter, which is compared to one of the performance thresholds 222 to predict a failure associated with at least a portion of the primary storage media 210 .
- FIG. 3 is a flow diagram of a particular illustrative embodiment of a method of performing a self-test of a storage device.
- the method starts at 300 .
- erase/write/read times of an individual block/page of a storage media are measured when an erase/write/read process is invoked.
- the erase/write/read process can be invoked by a host system, by an interrupt, by a controller of the storage device, by another process, or any combination thereof.
- the measured erase/write/read times are recorded in a performance log.
- the measured erase/write/read times are compared against erase/write/read thresholds.
- the method terminates without error at 312 .
- a corrective fault recovery action may include disabling volatile write-caching as a response to a predicted failure.
- the corrective fault recovery action may include generating an alert to a host system, reallocating data from a first portion to a second portion a storage media, prohibiting access to the a portion of the storage media, taking other data protection actions, or any combination thereof. The method terminates at 312 .
- FIG. 4 is a flow diagram of a second particular illustrative embodiment of a method of performing a self-test of a storage device.
- the method starts at 400 .
- an environmental temperature of a storage device under test is set.
- a voltage is adjusted that is applied to a solid-state storage memory component of the storage device.
- erase/write/read times of an individual block/page of a storage media are measured when an erase/write/read process is invoked.
- the erase/write/read process can be invoked by a host system, by an interrupt, by a controller of the storage device, by another process, or any combination thereof.
- the measured erase/write/read times are recorded in a performance log.
- the measured erase/write/read times are compared against erase/write thresholds.
- the method advances to 416 and the voltage that is applied to a solid-state storage memory component of the storage device is adjusted to an operating voltage level. The method terminates at 418 .
- a corrective fault recovery action may include disabling volatile write-caching as a response to a predicted failure.
- the corrective fault recovery action may include generating an alert to a host system, reallocating data from a first portion to a second portion a storage media, prohibiting access to the a portion of the storage media, taking other data protection actions, or any combination thereof.
- the voltage that is applied to a solid-state storage memory component of the storage device is adjusted to an operating voltage level. The method terminates at 418 .
- non-volatile memory devices such as the data (NAND) flash 134 and the code (NOR) flash 138 illustrated in FIG. 1 , are tested by a manufacturer prior to shipment. These tests are performed by iteratively erasing and then writing and reading the non-volatile memory devices using a plurality of test patterns. If the memory device passes its tests, the memory device is shipped to the end user for incorporation into a final product. However, it is sometimes beneficial to test the non-volatile memory device after it is installed into the final product. For storage devices, such as the hybrid storage device 102 illustrated in FIG. 1 , it is sometimes desirable to test the non-volatile memory devices after assembly is complete.
- the built-in self-test it is possible to test the non-volatile electronics, such as the flash memory, without external test equipment or with less-costly test equipment. Additionally, the built-in self-test and the measurement circuitry make it possible to periodically test the storage device during regular operation to ensure the non-volatile memory continues to work reliably.
- a manufacturer's test equipment can invoke the built-in self-tests at various temperatures as an additional stress that is not always present in the field. Further, a manufacturer's test process can use the built-in self-test, optionally in conjunction with the measurement circuitry (such as a programming time monitor), to collect data about the device performance. The data can be used as part of a statistical process control to monitor and control the quality of the final product.
- FIG. 5 is a flow diagram of a third particular illustrative embodiment of a method of performing a self-test of a storage device.
- the method starts at 500 .
- data are optionally written to a page of memory within the non-volatile storage. In general, block 502 is unnecessary if the data are known or can be determined via an error-correcting code.
- the data are read back to determine a quality value associated with the data.
- the quality value is related to the number of bits in error within the page.
- the quality value is determined by totaling the mean-square error of the sensed storage level of each individual bit cell from its optimal value.
- the non-volatile electronic storage device contains circuitry capable of converting the analog voltage of a bit cell's charge to a digital value
- this information can be used to determine a value related to the amount of error.
- the quality value is recorded in a performance log.
- the quality value is compared to a threshold. If the quality value is less than the threshold, the method terminates without error at 512 .
- the method advances to 510 and corrective action is performed to protect the data. The method terminates at 514 .
- FIG. 6 is a flow diagram of a fourth particular illustrative embodiment of a method of performing a self-test of a storage device.
- the method starts at 600 .
- an electrical load is applied to a power-supplying component of a storage device.
- a power level associated with read/write circuitry of a storage device including a storage media is measured when data is erased from or written to a portion of the storage media.
- the power level is measured from a spindle motor, an auxiliary power device, another component, or any combination thereof, using a measurement circuit.
- the power level is determined by measuring the length of time in which the spindle motor or power device remains above a threshold. This is accomplished by periodically programming a series of non-volatile locations at fixed timed intervals until power falls below a threshold.
- the measured power level is recorded in a measurement log. Proceeding to 608 , the measured power level is compared to a threshold value. In a particular example, the measured power level is compared to the threshold time value by logic, which may be part of the measurement circuit, a control circuit, a processor, or any combination thereof. At 608 , if the measured power level is less than a threshold value, the method is terminated without error at 612 . Otherwise, at 608 , if the measured power level exceeds a threshold value, the method advances to 610 and corrective fault recovery actions are performed. The he corrective fault recovery actions may include disabling volatile write-caching as a response to a predicted failure.
- the corrective fault recovery action may include generating an alert to a host system, reallocating data from a first portion to a second portion a storage media, prohibiting access to the a portion of the storage media, taking other data protection actions, or any combination thereof.
- the power level may be adjusted to a normal operating power level prior to termination. The method terminates at 612 .
- FIG. 7 is a flow diagram of a fifth particular illustrative embodiment of a method of performing a self-test of a storage device.
- the method starts at 700 .
- a performance parameter associated with at least one storage media of a storage device is measured via a measurement circuit within the storage device when the at least one storage media is accessed.
- the performance parameter comprises a read time, a write time, an erase time, or any combination thereof.
- measuring the performance parameter includes measuring the energy associated with the back electromotive force (EMF) of a spindle motor of the storage device when at least one storage media is rotating, where the back EMF is power generated from the kinetic inertia of the storage media.
- measuring the performance parameter includes measuring a power supply level associated with an auxiliary power supply when the auxiliary power supply is providing operating power to circuitry of the storage device.
- EMF back electromotive force
- a failure is predicted when the performance parameter exceeds a threshold.
- data loss is prevented by taking a corrective action in response to the predicted failure.
- circuitry of the storage device predicts the failure and prevents data loss by taking the corrective action.
- data loss is prevented by reallocating data from a memory location associated with the at least one storage media to another storage location in response to the predicted failure.
- data loss is prevented by prohibiting future write access to the at least one storage media in response to the predicted failure. The method terminates at 708 .
- the method further includes generating an alert to a host system.
- the alert may be generated by logic, by a control circuit, by the measurement circuit, or any combination thereof.
- the alert indicates an error message or annunciation associated with the at least one storage media in response to the predicted failure.
- start blocks indicated at 300 , 400 , 500 , 600 , and 700 in FIGS. 3-7 represent a trigger that initiates the particular method flow.
- the trigger may be initiated by a host system, such as the host systems 104 and 204 in FIGS. 1 and 2 , may be initiated by firmware within a storage device, may be triggered by a peripheral device (not shown), may be initiated by circuitry within the storage device, or any combination thereof.
- the measurement circuitry is incorporated within the storage device to monitor performance parameters associated with the storage device during normal operation.
- component failures may be predicted before data is lost by comparing the performance parameters to respective performance thresholds and by taking corrective action when the performance parameters deviate from the performance thresholds.
- when the power level falls below a power threshold it may be desirable to perform further testing of the storage device to isolate a problem and to provide an error message to a host system that can be used to fix the problem.
- one or more performance parameters can be measured, including the erase/write/reads times of the memory, the power supply of the auxiliary power device, the energy associated with the back electromotive force of the spindle motor, other performance parameters, or any combination thereof.
- the control circuitry of the storage device can take precautions to protect user data, such as by reallocating the user data to another portion of the storage media that is tested to have better erase/reprogram times. Further, by including the measurement circuitry and the logic to determine corrective actions within the storage device, the storage device can be made to be more reliable, since device failures can be predicted before data is lost, allowing the device to take corrective action or allowing the device to notify the user so that the user can take corrective actions to protect the user data.
Abstract
Description
- The present disclosure is generally related to a data storage device including self-test features.
- Storage devices typically include non-volatile storage media, such as magnetic discs within a hard disc drive and flash memory chips within a solid-state drive. Some storage systems, such as a hybrid disc drive, contain a mixture of non-volatile media types. In general, hybrid disc drives include non-volatile electronics, such as flash memory, that can be used in conjunction with the non-volatile rotating storage media to retain data through power loss and reset events.
- In many types of solid-state memory, such as NAND flash memory, data are erased in blocks and are read/written in pages. A block often contains multiple pages. When updating data stored in a solid-state memory, it is common for valid data to be read from the memory to another location (such as into a volatile memory buffer), modified and written to an erased data block. In some designs, the data are written back to the same block from which they were read, where the block is erased after the data is read but before the modified data is written to the block. In other designs, the data are written to a previously-erased block elsewhere within the storage device. The storage cell of the solid-state memory can deteriorate over time as it is exposed to multiple erase/write/read cycles. Further, solid-state memories and hard disc storage media may deteriorate at different rates.
- In general, storage devices and flash memory devices are tested during manufacturing to improve the quality of the finished product. Unfortunately, device failures that occur in the finished product during operation can be catastrophic to a user. While error correction and predictive failure features are sometimes included in storage devices, such features often predict failures based on the quantity of data in error. Prediction of device failure based upon a quantity of data errors may be insufficient to prevent unrecoverable loss of data.
- While storage systems can store data in non-volatile media for retention, in many cases it is advantageous to keep data in a volatile memory buffer, such as a dynamic random access memory (DRAM). For example, data may be stored in a DRAM to improve the performance of the storage system or to reduce the wear on the storage components by reducing erases and writes. However, it is generally still desirable to retain information that is stored in the DRAM upon unexpected loss of external system power. In some storage systems, the protection of such information is valuable enough to warrant additional protection of the volatile buffer to make the information held in the buffer non-volatile. This protection generally requires the use of an internal energy source within the storage system. In a disc drive, the kinetic momentum of the rotating disc pack can be used as an energy source. If the rotating disc pack has insufficient energy for the particular design, the rotating disc pack energy source can be replaced or augmented by an auxiliary power device, such as a battery or a double-layer capacitor. Generally, solid-state drives do not include a kinetic energy source, so such drives typically contain an auxiliary power device to provide this protection. In both of these cases, however, a failure related to such auxiliary power sources can cause unexpected loss or corruption of data.
- In a particular embodiment, a data storage device includes a non-volatile storage media adapted to store data and a measurement circuit adapted to measure at least one performance parameter related to the non-volatile storage media during operation. The data storage device further includes logic coupled to the measurement circuit and adapted to predict a failure associated with at least a portion of the non-volatile storage media when the measured performance parameter exceeds a threshold value.
- In another particular embodiment, a storage device includes one or more storage media to store data and a measurement circuit adapted to measure at least one performance parameter associated with at least one of the one or more storage media. The storage device further includes a control circuit coupled to the measurement circuit and to the one or more storage media. The control circuit is adapted to control read, write, and erase (if erasure is required) access to the one or more storage media. The control circuit detects a failure associated with at least one of the one or more storage media when the at least one performance parameter exceeds a threshold. The control circuit initiates a corrective action in response to the detected failure.
- In still another particular embodiment, a method is disclosed that includes measuring a performance parameter associated with at least one storage media of a storage device via a measurement circuit within the storage device when the at least one storage media is accessed. The method further includes predicting a failure when the performance parameter exceeds a threshold and preventing data loss or corruption by taking a corrective action in response to the predicted failure.
- In yet another particular embodiment, a method is disclosed that includes measuring a performance parameter associated with internal power supplying components of the storage system. The method further includes predicting a failure when the performance parameter exceeds a threshold and preventing data loss or corruption by taking a corrective action in response to the predicted failure.
-
FIG. 1 is a block diagram of a particular illustrative embodiment of a system including a hybrid storage device that has a measurement circuit and a spindle power monitor to test the storage device; -
FIG. 2 is a block diagram of a second particular illustrative embodiment of a system including a storage device that has a device health monitor to test the storage device; -
FIG. 3 is a flow diagram of a particular illustrative embodiment of a method of performing a self-test of a storage device; -
FIG. 4 is a flow diagram of a second particular illustrative embodiment of a method of performing a self-test of a storage device; -
FIG. 5 is a flow diagram of a third particular illustrative embodiment of a method of performing a self-test of a storage device; -
FIG. 6 is a flow diagram of a fourth particular illustrative embodiment of a method of performing a self-test of a storage device; and -
FIG. 7 is a flow diagram of a fifth particular illustrative embodiment of a method of performing a self-test of a storage device. -
FIG. 1 is a block diagram of a particular illustrative embodiment of asystem 100 including ahybrid storage device 102 that has ameasurement circuit 124 and apower monitor 132 used to test thestorage device 102. As used herein, the term “hybrid storage device” refers to a data storage device that includes both rotating storage media and solid-state storage media. Thestorage device 102 is adapted to communicate with ahost system 104. In a particular embodiment, thehost system 104 is typically a computer, but could be a bus expander, a processor, a personal digital assistant (PDA), another electronic device, or more generally any device capable of generating and/or relaying commands to a mass storage device. - The
storage device 102 includesrecording subsystem circuitry 106, a head-disc assembly 108, and disc-headassembly control circuitry 120, which includes monitoring circuitry. Therecording subsystem circuitry 106 includes aninterface circuit 112, which includes a data buffer for temporarily buffering the data and a sequencer for directing the operation of the read/writechannel 116 and thepreamplifier 150 during data transfer operations. Theinterface circuit 112 is coupled to thehost system 104 and to acontrol processor 118, which is adapted to control operation of thestorage device 102. In a particular embodiment, thecontrol processor 118 includes devicefailure prediction logic 119 that is adapted to predict a failure associated with thestorage device 102 based on one or more measured performance parameters. In an alternative embodiment, the devicefailure prediction logic 119 can be separate from thecontrol processor 118. In a particular example, the devicefailure prediction logic 119 can be included within themeasurement circuit 124. Thecontrol processor 118 is coupled to aservo circuit 122 that is adapted to control the position of one or more read/writeheads 154 relative to one ormore discs 156 as part of a servo loop established by the one or more read/writeheads 154. Generally, the one or more read/writeheads 154 are mounted to a rotary actuator assembly to which acoil 152 of a voice coil motor (VCM) is attached. As is known in the art, a VCM includes a pair of magnetic flux paths between which thecoil 152 is disposed so that the passage of current through the coil causes magnetic interaction between thecoil 152 and the magnetic flux paths, resulting in the controlled rotation of the actuator assembly and the movement of the one ormore heads 154 relative to the surfaces of the one ormore discs 156. Theservo circuit 122 is used to control the application of current to thecoil 152, and hence the position of theheads 154 with respect to the tracks of the one ormore discs 156. - In general, the disc-head
assembly control circuitry 120 includes theservo circuit 122 and includes aspindle circuit 126 that is coupled to aspindle motor 158 to control the rotation of the one ormore discs 156. The disc-headassembly control circuitry 120 further includes ameasurement circuit 124 that is coupled to thecontrol processor 118 and that is adapted to measure one or more electrical parameters associated with thestorage device 102. - In a particular embodiment, the disc-head
assembly control circuitry 120 includes apower monitor 132 that is coupled to thespindle circuit 126 and adapted to measure the usable energy available in the back electromotive force associated with thespindle motor 158. In a particular example, the back electromotive force (EMF) represents thespindle motor 158 operating as a generator, utilizing a kinetic inertia associated with the rotation of the one ormore discs 156 to generate the back EMF. In a particular instance, the energy from the back EMF may be measured as a power level. When power is interrupted to the storage device, thecontrol processor 118 programs the data into the non-volatile memory component, such as thedata flash 134. In a particular example, once the user's data and the firmware metadata have been stored, themeasurement circuitry 124 can record the time it took to program thedata flash 134. Thecontrol processor 118 can then program one bit of memory (of the data flash 134) at fixed periodic intervals until the power from thespindle motor 158 has been exhausted. When power is restored, the devicefailure prediction logic 119 can use the stored bits to determine how much power thespindle motor 158 supplied. - The
storage device 102 also includes anauxiliary power device 130 that is coupled to thespindle power monitor 132 and to themeasurement circuit 124. In a particular embodiment, theauxiliary power device 130 can be a capacitor or a battery that is adapted to supply power to thestorage device 102 under certain operating conditions. In a particular example, theauxiliary power device 130 can provide a power supply to therecording subsystem assembly 106 and to the disc-head assembly 108 to record data to the one ormore discs 156 when power is turned off. Further, theauxiliary power device 130 may supply power to therecording subsystem assembly 106 to record data to adata flash 134 or to a code (NOR)flash 138 when power is turned off. - Additionally, the
storage device 102 includes a non-volatile solid-state storage component for data, labeled “data (NAND) flash” 134. Although NAND flash is shown inFIG. 1 , theflash memory 134 could be any non-volatile electronic storage component capable of storing data. For example, theflash memory 134 could be NAND flash, NOR flash, MRAM, phase-change memory, another solid-state memory, or any combination thereof. Additionally, thestorage device 102 typically includes a dynamic random access memory (DRAM) 136, and or other memory, or any combination thereof. - Additionally, the
storage device 102 includesinternal code storage 138. Although the internal code storage block shown generally indicated at 138 is labeled for purposes of easy comprehension as “code (NOR) flash”, the “code (NOR)flash 138 could be any non-volatile solid-state storage component, and in some embodiments the code storage might only exist as a portion of thedata storage component 134. In a particular embodiment, the code (NOR) flash 138 stores self-test instructions 140, including instructions to monitor particular performance parameters associated with thestorage device 102 each time data is written to, read from, and/or erased from thestorage device 102. In a particular example, the self-test instructions 140 include a sequence of data values that can be written to an erased block within the data (NAND)flash 134, for example, while the write time is measured by themeasurement circuit 124. - In general, the
storage device 102 frequently erases, writes and reads non-volatile electronics (NVE), such as the data (NAND)flash 134 and the code (NOR)flash 138, to retain data through power loss and reset events. In flash components, erasing and writing of the NVE is typically accomplished by storing and depleting electrical charges in a “floating” gate in a NOR or NAND gate cell, many of which are included in a single NVE memory. In a phase-change memory, erasing and writing are accomplished by heating and cooling chalcogenic material to switch it between amorphous and crystalline states. Unfortunately, it is common for these and other NVE storage devices to degrade with usage in their ability to store data, which degradation results in changes of erase and/or write and/or read times up and to the point of failure. - During operation of the
storage device 102, themeasurement circuit 124 measures and records a length of time to complete an erase/write/read operation for a portion of the memory, such as a block, page, segment, paragraph, etc. or for the entire memory. Not shown here, it is a common practice to perform signal conditioning, such as to normalize and/or filter the measured times. The devicefailure prediction logic 119 is adapted to compare the measured erase/write/read time to a corresponding threshold, and if the threshold is exceeded, the devicefailure prediction logic 119 is adapted to initiate one or more recover steps via thecontrol processor 118. The one or more recovery steps can include, but are not limited to, retrying the operation, performing additional testing on the storage, reconditioning the storage, reallocating the affected block/page, asserting an error message to thehost system 104, posting an error, and performing further testing on the flash segment. In a particular embodiment, the devicefailure prediction logic 119 may be adapted to monitor programming time on a historical basis and to use trends, filtered or unfiltered, to make intelligent device failure predictions. - In a particular embodiment, the
data storage device 102 includes a non-volatile storage media, such as the one ormore discs 156, the data (NAND)flash 134, the code (NOR)flash 138,other memory 140, or any combination thereof. The non-volatile storage media is adapted to store data, including instructions executable by the control processor, user data, measurement data, other information, or any combination thereof. - The
storage device 102 includes themeasurement circuit 124 that is adapted to measure at least one performance parameter related to the non-volatile storage media during operation. In a particular example, the at least one performance parameter is an erase time, a write time, a read time, or any combination thereof, that is associated with the data (NAND)flash 134, the code (NOR)flash 138, theother memory 142, or any combination thereof. In another particular example, the at least one performance parameter is the usable energy available from the back electromotive force associated with thespindle motor 158. The back electromotive force represents electrical energy generated by thespindle motor 158 using a kinetic inertia associated with rotation of the one ormore discs 156. In still another particular example, the at least one performance parameter is a power level associated with theauxiliary power device 130 when theauxiliary power device 130 supplies power to therecording subsystem assembly 106. - The
storage device 102 further includes logic, such as the devicefailure prediction logic 119, that is coupled to themeasurement circuit 124 and that is adapted to predict a failure associated with at least a portion of the non-volatile storage media, when the measured performance parameter exceeds a threshold value. For example, the erase/write/read time associated with the data (NAND) flash 134 changes as the data (NAND)flash 134 deteriorates. When the (normalized and/or filtered) measured erase/write/read time associated with the data (NAND)flash 134 exceeds a corresponding threshold, the logic is adapted to predict a failure associated with the data (NAND)flash 134 and to take corrective action to prevent data loss. - In another example, when the measured power level of the
auxiliary power device 130 falls below a power threshold, the logic is adapted to predict a failure associated with theauxiliary power device 130, which may indicate that thestorage device 102 may be unable to record data to the non-volatile storage media when power is lost. In this example, the logic is adapted to take a corrective action to prevent data loss in response to the predicted failure. In still another example, when the measured back EMF from thespindle motor 158 falls below an EMF threshold, the logic is adapted to predict a failure and to take action to prevent data loss. - In a particular example, the
storage device 102 is adapted to reallocate data from a first storage location to a second storage location in response to the predicted failure. In another particular example, thestorage device 102 is adapted to prohibit access to at least a portion of the non-volatile storage media in response to the predicted failure. In another particular example, thestorage device 102 disables volatile write-caching as a response to a predicted failure. In still another particular example, thestorage device 102 is adapted to generate an alert, such as an error message, and to communicate the alert to thehost system 104 via theinterface 112. - Further, using the built-in self-test, it is possible to test the non-volatile electronics, such as the flash memory, without external test equipment. Additionally, the built-in self-test, such as the self-
test instructions 140, and themeasurement circuitry 124 make it possible to periodically test thestorage device 102 during regular operation to ensure that the non-volatile memory, such as the data (NAND)flash 134 and the code (NOR)flash 138, continues to work reliably. In a particular embodiment, the built-in self-test instructions 140 include a set of data patterns for erasing and reprogramming theflash memories control processor 118 is adapted to use the self-test instructions 140 to erase and reprogram the data (NAND)flash 134. During erase, write, and read operations, themeasurement circuitry 124 measures the erase/write/read time. - In a particular embodiment, the device contains
voltage regulator circuitry 128 that can be controlled to provide a higher or lower voltage than normal, “margining” the voltage supply to provide additional stress factors that can ferret out weak or defective components. In a particular example, thecontrol processor 118 uses the built-in self-test instructions 140 to run a series of erase/programming cycles against the memory using the patterns. The tests can be repeated with the voltage margined high or low. The results of the tests can be used to identify failing components and to make decision about the overall health of thestorage device 102. In a particular implementation, thestorage device 102 can include a programmable clock that allows the data (NAND)flash 134, the code (NOR)flash 138, other memory, or any combination thereof to be run at faster or slower than normal clock speeds, providing additional stress on the non-volatile electronics. Further, testing may be performed using various combinations of the above stresses. -
FIG. 2 is a block diagram of a second particular illustrative embodiment of asystem 200 including adata storage device 202 that has adevice health monitor 216 to test thedata storage device 202. In a particular embodiment, thedata storage device 202 is a solid-state memory device that is adapted to communicate with ahost system 204 via aninterface 206. Thedata storage device 202 includes acontrol circuit 208 that is adapted to communicate with aprimary storage media 210 and withother memory 214. Thecontrol circuit 208 is also coupled to anauxiliary power component 212. In a particular embodiment, theauxiliary power component 212 is an energy storage component, such as a battery or a capacitor, which is adapted to provide auxiliary power to thestorage device 202 when power is lost. Thecontrol circuit 208 is also coupled to thedevice health monitor 216, which monitors one or more performance parameters associated with thestorage device 202 to predict a storage device failure. - The
device health monitor 216 includes a built-in self-test feature 218, which may be used by thecontroller 208 to test a health associated with theprimary storage media 210 or theother memory 214. In a particular example, the built-in self-test feature 218 includes instructions executable by thecontrol circuit 208 to erase a block of data from a selected memory, such as theprimary storage media 210, to write a new page of data to the selected memory, and to read a page of data from the selected memory. The built-in self-test feature 218 may also include a data sequence to be written to the selected memory. Thedevice health monitor 216 also includes an auxiliary power device monitor 220 adapted to monitor a power supplied by theauxiliary power component 212 when theauxiliary power component 212 is acting as an energy source. Thedevice health monitor 216 further includes one ormore performance thresholds 222. In a particular illustrative embodiment, thedevice health monitor 216 may include a spindleenergy power monitor 224, when theprimary storage media 210 is a rotating storage media that is rotated using a spindle motor, such as thespindle motor 158 illustrated inFIG. 1 . In an alternative embodiment, where thestorage device 202 is a solid-state storage device, the spindleenergy power monitor 224 may be omitted. - The
device health monitor 216 further includes a programming time monitor 226 that is adapted to monitor an erase time, a write time, a read time, or any combination thereof, when data are erased, written, or read to/from a selected memory, such as theprimary storage media 210 or theother memory 214. In a particular embodiment, thedevice health monitor 216 includes aperformance measurement log 228 that is adapted to record measurement data related to the one or more measured performance parameters. Finally, thedevice health monitor 216 includes devicefailure prediction logic 230 that is adapted to predict a failure associated with thestorage device 202 based on at least one of the one or more measured performance parameters. - In a particular embodiment, the
storage device 202 includes acontrol circuit 208 that is coupled to a non-volatile storage media, such as theprimary storage media 210, theother memory 214, or any combination thereof. Thecontrol circuit 208 is adapted to control read/write access to the non-volatile storage media. In a particular example, thedevice health monitor 216 is adapted to monitor one or more performance parameters associated with thestorage device 202 to predict a failure associated with thestorage device 202, when at least one of the one or more performance parameters exceeds a respective performance threshold of the one ormore performance thresholds 222. - In a particular embodiment, the
control circuit 208 is adapted to take corrective action to prevent data loss in response to the predicted failure. In a particular example, thecontrol circuit 208 is adapted to reallocate data from afirst portion 232 of theprimary storage media 210 to asecond portion 234 of theprimary storage media 210 in response to the predicted failure. In another particular example, thecontrol circuit 208 is adapted to prohibit access to the first orsecond portions primary storage media 210 in response to the predicted failure. In another particular example, thecontrol circuit 208 disables volatile write-caching as a response to a predicted failure. In another particular example, thecontrol circuit 208 is adapted to generate an alert and to send the alert to thehost system 204 via theinterface 206 in response to the predicted failure. - In a particular embodiment, the
primary storage media 210 is a non-volatile, solid-state memory. Thedevice health monitor 216 is adapted to utilize the built-in self-test feature 218 and the programming time monitor 226 each time theprimary storage media 210 is accessed to determine a time parameter, which is compared to one of theperformance thresholds 222 to predict a failure associated with at least a portion of theprimary storage media 210. -
FIG. 3 is a flow diagram of a particular illustrative embodiment of a method of performing a self-test of a storage device. The method starts at 300. At 302, erase/write/read times of an individual block/page of a storage media are measured when an erase/write/read process is invoked. In a particular embodiment, the erase/write/read process can be invoked by a host system, by an interrupt, by a controller of the storage device, by another process, or any combination thereof. Moving to 304, the measured erase/write/read times are recorded in a performance log. Continuing to 306, the measured erase/write/read times are compared against erase/write/read thresholds. Advancing to 308, when the measured erase, write, or read times do not exceed corresponding erase/write/read thresholds, the method terminates without error at 312. - Returning to 308, when the measured erase/write/read times exceed corresponding erase/write/read thresholds, the method proceeds to 310 and corrective fault recovery actions are performed. In a particular example, a corrective fault recovery action may include disabling volatile write-caching as a response to a predicted failure. In another particular example, the corrective fault recovery action may include generating an alert to a host system, reallocating data from a first portion to a second portion a storage media, prohibiting access to the a portion of the storage media, taking other data protection actions, or any combination thereof. The method terminates at 312.
-
FIG. 4 is a flow diagram of a second particular illustrative embodiment of a method of performing a self-test of a storage device. The method starts at 400. At 402, optionally, an environmental temperature of a storage device under test is set. Advancing to 404, a voltage is adjusted that is applied to a solid-state storage memory component of the storage device. Continuing to 406, erase/write/read times of an individual block/page of a storage media are measured when an erase/write/read process is invoked. In a particular embodiment, the erase/write/read process can be invoked by a host system, by an interrupt, by a controller of the storage device, by another process, or any combination thereof. Moving to 408, the measured erase/write/read times are recorded in a performance log. Continuing to 410, the measured erase/write/read times are compared against erase/write thresholds. Advancing to 412, when the measured erase and write times do not exceed corresponding erase/write thresholds, the method advances to 416 and the voltage that is applied to a solid-state storage memory component of the storage device is adjusted to an operating voltage level. The method terminates at 418. - Returning to 412, when the measured erase/write/read times exceed corresponding erase/write/read thresholds, the method proceeds to 414 and corrective fault recovery actions are performed. In a particular example, a corrective fault recovery action may include disabling volatile write-caching as a response to a predicted failure. In another particular example, the corrective fault recovery action may include generating an alert to a host system, reallocating data from a first portion to a second portion a storage media, prohibiting access to the a portion of the storage media, taking other data protection actions, or any combination thereof. Continuing to 416, the voltage that is applied to a solid-state storage memory component of the storage device is adjusted to an operating voltage level. The method terminates at 418.
- In general, non-volatile memory devices, such as the data (NAND)
flash 134 and the code (NOR)flash 138 illustrated inFIG. 1 , are tested by a manufacturer prior to shipment. These tests are performed by iteratively erasing and then writing and reading the non-volatile memory devices using a plurality of test patterns. If the memory device passes its tests, the memory device is shipped to the end user for incorporation into a final product. However, it is sometimes beneficial to test the non-volatile memory device after it is installed into the final product. For storage devices, such as thehybrid storage device 102 illustrated inFIG. 1 , it is sometimes desirable to test the non-volatile memory devices after assembly is complete. Further, using the built-in self-test, it is possible to test the non-volatile electronics, such as the flash memory, without external test equipment or with less-costly test equipment. Additionally, the built-in self-test and the measurement circuitry make it possible to periodically test the storage device during regular operation to ensure the non-volatile memory continues to work reliably. - In a particular embodiment, a manufacturer's test equipment can invoke the built-in self-tests at various temperatures as an additional stress that is not always present in the field. Further, a manufacturer's test process can use the built-in self-test, optionally in conjunction with the measurement circuitry (such as a programming time monitor), to collect data about the device performance. The data can be used as part of a statistical process control to monitor and control the quality of the final product.
-
FIG. 5 is a flow diagram of a third particular illustrative embodiment of a method of performing a self-test of a storage device. The method starts at 500. At 502, data are optionally written to a page of memory within the non-volatile storage. In general, block 502 is unnecessary if the data are known or can be determined via an error-correcting code. Advancing to 504, the data are read back to determine a quality value associated with the data. In a particular embodiment, the quality value is related to the number of bits in error within the page. In another particular embodiment, the quality value is determined by totaling the mean-square error of the sensed storage level of each individual bit cell from its optimal value. For example, if the non-volatile electronic storage device contains circuitry capable of converting the analog voltage of a bit cell's charge to a digital value, this information can be used to determine a value related to the amount of error. Proceeding to 506, the quality value is recorded in a performance log. Moving to 508, the quality value is compared to a threshold. If the quality value is less than the threshold, the method terminates without error at 512. Returning to 508, if the quality value is greater than the threshold, the method advances to 510 and corrective action is performed to protect the data. The method terminates at 514. -
FIG. 6 is a flow diagram of a fourth particular illustrative embodiment of a method of performing a self-test of a storage device. The method starts at 600. At 602, an electrical load is applied to a power-supplying component of a storage device. Advancing to 604, a power level associated with read/write circuitry of a storage device including a storage media is measured when data is erased from or written to a portion of the storage media. In a particular example, the power level is measured from a spindle motor, an auxiliary power device, another component, or any combination thereof, using a measurement circuit. In a particular illustrative embodiment, the power level is determined by measuring the length of time in which the spindle motor or power device remains above a threshold. This is accomplished by periodically programming a series of non-volatile locations at fixed timed intervals until power falls below a threshold. - Continuing to 606, the measured power level is recorded in a measurement log. Proceeding to 608, the measured power level is compared to a threshold value. In a particular example, the measured power level is compared to the threshold time value by logic, which may be part of the measurement circuit, a control circuit, a processor, or any combination thereof. At 608, if the measured power level is less than a threshold value, the method is terminated without error at 612. Otherwise, at 608, if the measured power level exceeds a threshold value, the method advances to 610 and corrective fault recovery actions are performed. The he corrective fault recovery actions may include disabling volatile write-caching as a response to a predicted failure. In another particular example, the corrective fault recovery action may include generating an alert to a host system, reallocating data from a first portion to a second portion a storage media, prohibiting access to the a portion of the storage media, taking other data protection actions, or any combination thereof. In a particular embodiment, the power level may be adjusted to a normal operating power level prior to termination. The method terminates at 612.
-
FIG. 7 is a flow diagram of a fifth particular illustrative embodiment of a method of performing a self-test of a storage device. The method starts at 700. At 702, a performance parameter associated with at least one storage media of a storage device is measured via a measurement circuit within the storage device when the at least one storage media is accessed. In a particular embodiment, the performance parameter comprises a read time, a write time, an erase time, or any combination thereof. In a particular illustrative embodiment, measuring the performance parameter includes measuring the energy associated with the back electromotive force (EMF) of a spindle motor of the storage device when at least one storage media is rotating, where the back EMF is power generated from the kinetic inertia of the storage media. In another particular illustrative embodiment, measuring the performance parameter includes measuring a power supply level associated with an auxiliary power supply when the auxiliary power supply is providing operating power to circuitry of the storage device. - Continuing to 704, a failure is predicted when the performance parameter exceeds a threshold. Proceeding to 706, data loss is prevented by taking a corrective action in response to the predicted failure. In a particular embodiment, circuitry of the storage device predicts the failure and prevents data loss by taking the corrective action. In a particular example, data loss is prevented by reallocating data from a memory location associated with the at least one storage media to another storage location in response to the predicted failure. In another particular example, data loss is prevented by prohibiting future write access to the at least one storage media in response to the predicted failure. The method terminates at 708.
- In a particular embodiment, the method further includes generating an alert to a host system. The alert may be generated by logic, by a control circuit, by the measurement circuit, or any combination thereof. In general, the alert indicates an error message or annunciation associated with the at least one storage media in response to the predicted failure.
- In general, it should be understood that the “start” blocks indicated at 300, 400, 500, 600, and 700 in
FIGS. 3-7 represent a trigger that initiates the particular method flow. In general, the trigger may be initiated by a host system, such as thehost systems FIGS. 1 and 2 , may be initiated by firmware within a storage device, may be triggered by a peripheral device (not shown), may be initiated by circuitry within the storage device, or any combination thereof. - In general, the measurement circuitry is incorporated within the storage device to monitor performance parameters associated with the storage device during normal operation. By monitoring performance parameters, component failures may be predicted before data is lost by comparing the performance parameters to respective performance thresholds and by taking corrective action when the performance parameters deviate from the performance thresholds. In a particular example, when the power level falls below a power threshold, it may be desirable to perform further testing of the storage device to isolate a problem and to provide an error message to a host system that can be used to fix the problem. In general, one or more performance parameters can be measured, including the erase/write/reads times of the memory, the power supply of the auxiliary power device, the energy associated with the back electromotive force of the spindle motor, other performance parameters, or any combination thereof.
- In a particular embodiment, once a failure is predicted, the control circuitry of the storage device can take precautions to protect user data, such as by reallocating the user data to another portion of the storage media that is tested to have better erase/reprogram times. Further, by including the measurement circuitry and the logic to determine corrective actions within the storage device, the storage device can be made to be more reliable, since device failures can be predicted before data is lost, allowing the device to take corrective action or allowing the device to notify the user so that the user can take corrective actions to protect the user data.
- Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.
Claims (25)
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Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100100857A1 (en) * | 2008-10-16 | 2010-04-22 | Seagate Technology Llc | Generic non-volatile service layer |
US20110099419A1 (en) * | 2009-10-23 | 2011-04-28 | International Business Machines Corporation | Solid state drive with flash sparing |
US20120197581A1 (en) * | 2011-01-31 | 2012-08-02 | Stmicroelectronics S.R.L. | Memory device with internal measurement of functional parameters |
US20140056052A1 (en) * | 2012-08-23 | 2014-02-27 | Jung-Hyuk Lee | Resistive memory device performing selective refresh and method of refreshing resistive memory device |
US8719320B1 (en) * | 2012-03-29 | 2014-05-06 | Amazon Technologies, Inc. | Server-side, variable drive health determination |
US8806106B2 (en) | 2010-11-12 | 2014-08-12 | Seagate Technology Llc | Estimating wear of non-volatile, solid state memory |
US20150046747A1 (en) * | 2013-08-07 | 2015-02-12 | Seagate Technology Llc | Torn write mitigation |
US8972799B1 (en) * | 2012-03-29 | 2015-03-03 | Amazon Technologies, Inc. | Variable drive diagnostics |
US9037921B1 (en) * | 2012-03-29 | 2015-05-19 | Amazon Technologies, Inc. | Variable drive health determination and data placement |
US9141505B1 (en) * | 2012-09-27 | 2015-09-22 | Emc Corporation | Adaptive failure survivability in a storage system using save time and data transfer after power loss |
US9354994B2 (en) | 2014-02-18 | 2016-05-31 | International Business Machines Corporation | Preemptive relocation of failing data |
US9449643B1 (en) * | 2015-04-24 | 2016-09-20 | Seagate Technology Llc | Data storage component test deck |
US9792192B1 (en) * | 2012-03-29 | 2017-10-17 | Amazon Technologies, Inc. | Client-side, variable drive health determination |
US10055477B2 (en) * | 2012-06-26 | 2018-08-21 | Toshiba Mitsubishi-Electric Industrial Systems Corporation | Data collection apparatus and data collection program |
US20190031373A1 (en) * | 2017-07-28 | 2019-01-31 | Honeywell International Inc. | System and method for testing the functionality of an electronic flight bag |
CN111190841A (en) * | 2018-11-14 | 2020-05-22 | 三星电子株式会社 | Storage device and memory management method thereof |
US20210191652A1 (en) * | 2019-12-23 | 2021-06-24 | Micron Technology, Inc. | Linking access commands for a memory sub-system |
US11112990B1 (en) | 2016-04-27 | 2021-09-07 | Pure Storage, Inc. | Managing storage device evacuation |
US11281389B2 (en) | 2019-01-29 | 2022-03-22 | Dell Products L.P. | Method and system for inline deduplication using erasure coding |
US11301327B2 (en) * | 2020-03-06 | 2022-04-12 | Dell Products L.P. | Method and system for managing a spare persistent storage device and a spare node in a multi-node data cluster |
US11328071B2 (en) | 2019-07-31 | 2022-05-10 | Dell Products L.P. | Method and system for identifying actor of a fraudulent action during legal hold and litigation |
US11341989B2 (en) | 2020-09-30 | 2022-05-24 | Seagate Technology Llc | Read head stress reduction |
US11372730B2 (en) | 2019-07-31 | 2022-06-28 | Dell Products L.P. | Method and system for offloading a continuous health-check and reconstruction of data in a non-accelerator pool |
US11386921B2 (en) * | 2020-09-30 | 2022-07-12 | Seagate Technology Llc | Read head stress reduction |
US11418326B2 (en) | 2020-05-21 | 2022-08-16 | Dell Products L.P. | Method and system for performing secure data transactions in a data cluster |
US11416357B2 (en) | 2020-03-06 | 2022-08-16 | Dell Products L.P. | Method and system for managing a spare fault domain in a multi-fault domain data cluster |
US11442642B2 (en) | 2019-01-29 | 2022-09-13 | Dell Products L.P. | Method and system for inline deduplication using erasure coding to minimize read and write operations |
US11609820B2 (en) | 2019-07-31 | 2023-03-21 | Dell Products L.P. | Method and system for redundant distribution and reconstruction of storage metadata |
US11775193B2 (en) | 2019-08-01 | 2023-10-03 | Dell Products L.P. | System and method for indirect data classification in a storage system operations |
US11809727B1 (en) * | 2016-04-27 | 2023-11-07 | Pure Storage, Inc. | Predicting failures in a storage system that includes a plurality of storage devices |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8959284B1 (en) | 2010-06-28 | 2015-02-17 | Western Digital Technologies, Inc. | Disk drive steering write data to write cache based on workload |
US9058280B1 (en) | 2010-08-13 | 2015-06-16 | Western Digital Technologies, Inc. | Hybrid drive migrating data from disk to non-volatile semiconductor memory based on accumulated access time |
US9268499B1 (en) | 2010-08-13 | 2016-02-23 | Western Digital Technologies, Inc. | Hybrid drive migrating high workload data from disk to non-volatile semiconductor memory |
KR101190742B1 (en) * | 2010-12-06 | 2012-10-12 | 에스케이하이닉스 주식회사 | Controller for memory and storage system includint the same, method for measuring life span of memory |
JP5112566B1 (en) * | 2011-12-16 | 2013-01-09 | 株式会社東芝 | Semiconductor memory device, nonvolatile semiconductor memory inspection method, and program |
US8959281B1 (en) * | 2012-11-09 | 2015-02-17 | Western Digital Technologies, Inc. | Data management for a storage device |
US20140164323A1 (en) * | 2012-12-10 | 2014-06-12 | Transparent Io, Inc. | Synchronous/Asynchronous Storage System |
US9141176B1 (en) | 2013-07-29 | 2015-09-22 | Western Digital Technologies, Inc. | Power management for data storage device |
US9070379B2 (en) | 2013-08-28 | 2015-06-30 | Western Digital Technologies, Inc. | Data migration for data storage device |
JP6013998B2 (en) * | 2013-09-06 | 2016-10-25 | 株式会社東芝 | Data storage apparatus and data erasing method |
US8917471B1 (en) | 2013-10-29 | 2014-12-23 | Western Digital Technologies, Inc. | Power management for data storage device |
KR20160043579A (en) * | 2014-10-13 | 2016-04-22 | 삼성전자주식회사 | Use time managing method in semiconductor device and semiconductor device having use time managing part |
EP3365787B1 (en) | 2015-10-23 | 2021-07-21 | Hewlett-Packard Development Company, L.P. | Data storage device monitoring |
US20190044809A1 (en) * | 2017-08-30 | 2019-02-07 | Intel Corporation | Technologies for managing a flexible host interface of a network interface controller |
US11016669B2 (en) * | 2018-05-01 | 2021-05-25 | Qualcomm Incorporated | Persistent write data for energy-backed memory |
US20230400991A1 (en) * | 2022-06-14 | 2023-12-14 | Western Digital Technologies, Inc. | Data Storage Device and Method for Prediction-Based Improved Power-Loss Handling |
Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4637022A (en) * | 1984-12-21 | 1987-01-13 | Motorola, Inc. | Internally register-modelled, serially-bussed radio system |
US6016553A (en) * | 1997-09-05 | 2000-01-18 | Wild File, Inc. | Method, software and apparatus for saving, using and recovering data |
US6122131A (en) * | 1997-09-12 | 2000-09-19 | Quantum Corporation | Adaptively-controlled disk drive assembly |
US6289484B1 (en) * | 1999-05-19 | 2001-09-11 | Western Digital Technologies, Inc. | Disk drive employing off-line scan to collect selection-control data for subsequently deciding whether to verify after write |
US20020124137A1 (en) * | 2001-01-29 | 2002-09-05 | Ulrich Thomas R. | Enhancing disk array performance via variable parity based load balancing |
US6467054B1 (en) * | 1995-03-13 | 2002-10-15 | Compaq Computer Corporation | Self test for storage device |
US20020156975A1 (en) * | 2001-01-29 | 2002-10-24 | Staub John R. | Interface architecture |
US20020194523A1 (en) * | 2001-01-29 | 2002-12-19 | Ulrich Thomas R. | Replacing file system processors by hot swapping |
US20020194526A1 (en) * | 2001-01-29 | 2002-12-19 | Ulrich Thomas R. | Dynamic redistribution of parity groups |
US20030061546A1 (en) * | 2001-09-27 | 2003-03-27 | Kevin Collins | Storage device performance monitor |
US6574754B1 (en) * | 2000-02-14 | 2003-06-03 | International Business Machines Corporation | Self-monitoring storage device using neural networks |
US20040148543A1 (en) * | 2002-02-20 | 2004-07-29 | Hiroaki Eto | Data access control apparatus, data access control method, controller, and computer program |
US20040210796A1 (en) * | 2001-11-19 | 2004-10-21 | Kenneth Largman | Computer system capable of supporting a plurality of independent computing environments |
US6957291B2 (en) * | 2001-03-29 | 2005-10-18 | Quantum Corporation | Removable disk storage array emulating tape library having backup and archive capability |
US20060010344A1 (en) * | 2004-07-09 | 2006-01-12 | International Business Machines Corp. | System and method for predictive processor failure recovery |
US20060067192A1 (en) * | 2003-06-09 | 2006-03-30 | Fujitsu Limited | Data assurance method for optical storage media and optical storage device |
US20080151717A1 (en) * | 2006-12-25 | 2008-06-26 | Tomishige Yatsugi | Recording and reproducing apparatus |
US20080267045A1 (en) * | 2007-04-27 | 2008-10-30 | Junji Nakajima | Laser driving method and optical disc recording/reproducing device |
US7613975B2 (en) * | 2005-02-03 | 2009-11-03 | Hewlett-Packard Development Company, L.P. | Predictive diagnosis of a data read system |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6295577B1 (en) | 1998-02-24 | 2001-09-25 | Seagate Technology Llc | Disc storage system having a non-volatile cache to store write data in the event of a power failure |
US6255801B1 (en) * | 2000-05-10 | 2001-07-03 | Tyco Electronics Logistics Ag | System and method for assessing a capacity of a battery and power plant incorporating the same |
US6732234B1 (en) * | 2000-08-07 | 2004-05-04 | Broadcom Corporation | Direct access mode for a cache |
US6996668B2 (en) * | 2001-08-06 | 2006-02-07 | Seagate Technology Llc | Synchronized mirrored data in a data storage device |
KR100724833B1 (en) | 2001-09-04 | 2007-06-04 | 엘지전자 주식회사 | Method for saving the data based on power source |
US6856556B1 (en) * | 2003-04-03 | 2005-02-15 | Siliconsystems, Inc. | Storage subsystem with embedded circuit for protecting against anomalies in power signal from host |
US7725653B2 (en) * | 2006-06-29 | 2010-05-25 | Emc Corporation | Method for enabling a memory as a function of estimated power source capacity |
-
2008
- 2008-09-09 US US12/206,968 patent/US20100061207A1/en not_active Abandoned
-
2012
- 2012-03-20 US US13/424,853 patent/US9111583B2/en not_active Expired - Fee Related
Patent Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4637022A (en) * | 1984-12-21 | 1987-01-13 | Motorola, Inc. | Internally register-modelled, serially-bussed radio system |
US6467054B1 (en) * | 1995-03-13 | 2002-10-15 | Compaq Computer Corporation | Self test for storage device |
US6016553A (en) * | 1997-09-05 | 2000-01-18 | Wild File, Inc. | Method, software and apparatus for saving, using and recovering data |
US6199178B1 (en) * | 1997-09-05 | 2001-03-06 | Wild File, Inc. | Method, software and apparatus for saving, using and recovering data |
US6240527B1 (en) * | 1997-09-05 | 2001-05-29 | Roxio, Inc. | Method software and apparatus for saving using and recovering data |
US6122131A (en) * | 1997-09-12 | 2000-09-19 | Quantum Corporation | Adaptively-controlled disk drive assembly |
US6289484B1 (en) * | 1999-05-19 | 2001-09-11 | Western Digital Technologies, Inc. | Disk drive employing off-line scan to collect selection-control data for subsequently deciding whether to verify after write |
US6574754B1 (en) * | 2000-02-14 | 2003-06-03 | International Business Machines Corporation | Self-monitoring storage device using neural networks |
US20020124137A1 (en) * | 2001-01-29 | 2002-09-05 | Ulrich Thomas R. | Enhancing disk array performance via variable parity based load balancing |
US7356730B2 (en) * | 2001-01-29 | 2008-04-08 | Adaptec, Inc. | Dynamic redistribution of parity groups |
US20020166079A1 (en) * | 2001-01-29 | 2002-11-07 | Ulrich Thomas R. | Dynamic data recovery |
US20020194523A1 (en) * | 2001-01-29 | 2002-12-19 | Ulrich Thomas R. | Replacing file system processors by hot swapping |
US20020194526A1 (en) * | 2001-01-29 | 2002-12-19 | Ulrich Thomas R. | Dynamic redistribution of parity groups |
US20050144514A1 (en) * | 2001-01-29 | 2005-06-30 | Ulrich Thomas R. | Dynamic redistribution of parity groups |
US20020165942A1 (en) * | 2001-01-29 | 2002-11-07 | Ulrich Thomas R. | Data path accelerator with variable parity, variable length, and variable extent parity groups |
US6745286B2 (en) * | 2001-01-29 | 2004-06-01 | Snap Appliance, Inc. | Interface architecture |
US6990547B2 (en) * | 2001-01-29 | 2006-01-24 | Adaptec, Inc. | Replacing file system processors by hot swapping |
US6775792B2 (en) * | 2001-01-29 | 2004-08-10 | Snap Appliance, Inc. | Discrete mapping of parity blocks |
US20020156975A1 (en) * | 2001-01-29 | 2002-10-24 | Staub John R. | Interface architecture |
US6862692B2 (en) * | 2001-01-29 | 2005-03-01 | Adaptec, Inc. | Dynamic redistribution of parity groups |
US6871295B2 (en) * | 2001-01-29 | 2005-03-22 | Adaptec, Inc. | Dynamic data recovery |
US6957291B2 (en) * | 2001-03-29 | 2005-10-18 | Quantum Corporation | Removable disk storage array emulating tape library having backup and archive capability |
US20030061546A1 (en) * | 2001-09-27 | 2003-03-27 | Kevin Collins | Storage device performance monitor |
US20040210796A1 (en) * | 2001-11-19 | 2004-10-21 | Kenneth Largman | Computer system capable of supporting a plurality of independent computing environments |
US20040148543A1 (en) * | 2002-02-20 | 2004-07-29 | Hiroaki Eto | Data access control apparatus, data access control method, controller, and computer program |
US20060067192A1 (en) * | 2003-06-09 | 2006-03-30 | Fujitsu Limited | Data assurance method for optical storage media and optical storage device |
US20060010344A1 (en) * | 2004-07-09 | 2006-01-12 | International Business Machines Corp. | System and method for predictive processor failure recovery |
US7613975B2 (en) * | 2005-02-03 | 2009-11-03 | Hewlett-Packard Development Company, L.P. | Predictive diagnosis of a data read system |
US20080151717A1 (en) * | 2006-12-25 | 2008-06-26 | Tomishige Yatsugi | Recording and reproducing apparatus |
US20080267045A1 (en) * | 2007-04-27 | 2008-10-30 | Junji Nakajima | Laser driving method and optical disc recording/reproducing device |
Cited By (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7966581B2 (en) * | 2008-10-16 | 2011-06-21 | Seagate Technology Llc | Generic non-volatile service layer |
US20100100857A1 (en) * | 2008-10-16 | 2010-04-22 | Seagate Technology Llc | Generic non-volatile service layer |
US20110099419A1 (en) * | 2009-10-23 | 2011-04-28 | International Business Machines Corporation | Solid state drive with flash sparing |
US7954021B2 (en) * | 2009-10-23 | 2011-05-31 | International Business Machines Corporation | Solid state drive with flash sparing |
US8806106B2 (en) | 2010-11-12 | 2014-08-12 | Seagate Technology Llc | Estimating wear of non-volatile, solid state memory |
US10720223B2 (en) | 2011-01-31 | 2020-07-21 | Stmicroelectronics S.R.L. | Memory device with internal measurement of functional parameters |
US9646717B2 (en) * | 2011-01-31 | 2017-05-09 | Stmicroelectronics S.R.L. | Memory device with internal measurement of functional parameters |
US20120197581A1 (en) * | 2011-01-31 | 2012-08-02 | Stmicroelectronics S.R.L. | Memory device with internal measurement of functional parameters |
US8719320B1 (en) * | 2012-03-29 | 2014-05-06 | Amazon Technologies, Inc. | Server-side, variable drive health determination |
US10861117B2 (en) | 2012-03-29 | 2020-12-08 | Amazon Technologies, Inc. | Server-side, variable drive health determination |
US8972799B1 (en) * | 2012-03-29 | 2015-03-03 | Amazon Technologies, Inc. | Variable drive diagnostics |
US9037921B1 (en) * | 2012-03-29 | 2015-05-19 | Amazon Technologies, Inc. | Variable drive health determination and data placement |
US20150234716A1 (en) * | 2012-03-29 | 2015-08-20 | Amazon Technologies, Inc. | Variable drive health determination and data placement |
US10204017B2 (en) * | 2012-03-29 | 2019-02-12 | Amazon Technologies, Inc. | Variable drive health determination and data placement |
US9792192B1 (en) * | 2012-03-29 | 2017-10-17 | Amazon Technologies, Inc. | Client-side, variable drive health determination |
US9754337B2 (en) | 2012-03-29 | 2017-09-05 | Amazon Technologies, Inc. | Server-side, variable drive health determination |
US10055477B2 (en) * | 2012-06-26 | 2018-08-21 | Toshiba Mitsubishi-Electric Industrial Systems Corporation | Data collection apparatus and data collection program |
US20140056052A1 (en) * | 2012-08-23 | 2014-02-27 | Jung-Hyuk Lee | Resistive memory device performing selective refresh and method of refreshing resistive memory device |
US9141505B1 (en) * | 2012-09-27 | 2015-09-22 | Emc Corporation | Adaptive failure survivability in a storage system using save time and data transfer after power loss |
US9753828B1 (en) * | 2012-09-27 | 2017-09-05 | EMC IP Holding Company LLC | Adaptive failure survivability in a storage system utilizing save time and data transfer upon power loss |
US9448896B2 (en) * | 2013-08-07 | 2016-09-20 | Seagate Technology Llc | Torn write mitigation |
US20150046747A1 (en) * | 2013-08-07 | 2015-02-12 | Seagate Technology Llc | Torn write mitigation |
US9354994B2 (en) | 2014-02-18 | 2016-05-31 | International Business Machines Corporation | Preemptive relocation of failing data |
US10346241B2 (en) | 2014-02-18 | 2019-07-09 | International Business Machines Corporation | Preemptive relocation of failing data |
US11372710B2 (en) | 2014-02-18 | 2022-06-28 | International Business Machines Corporation | Preemptive relocation of failing data |
US9715897B2 (en) | 2015-04-24 | 2017-07-25 | Seagate Technology Llc | Data storage component test deck |
US9449643B1 (en) * | 2015-04-24 | 2016-09-20 | Seagate Technology Llc | Data storage component test deck |
US11112990B1 (en) | 2016-04-27 | 2021-09-07 | Pure Storage, Inc. | Managing storage device evacuation |
US11934681B2 (en) | 2016-04-27 | 2024-03-19 | Pure Storage, Inc. | Data migration for write groups |
US11809727B1 (en) * | 2016-04-27 | 2023-11-07 | Pure Storage, Inc. | Predicting failures in a storage system that includes a plurality of storage devices |
US20190031373A1 (en) * | 2017-07-28 | 2019-01-31 | Honeywell International Inc. | System and method for testing the functionality of an electronic flight bag |
CN111190841A (en) * | 2018-11-14 | 2020-05-22 | 三星电子株式会社 | Storage device and memory management method thereof |
US11281389B2 (en) | 2019-01-29 | 2022-03-22 | Dell Products L.P. | Method and system for inline deduplication using erasure coding |
US11442642B2 (en) | 2019-01-29 | 2022-09-13 | Dell Products L.P. | Method and system for inline deduplication using erasure coding to minimize read and write operations |
US11328071B2 (en) | 2019-07-31 | 2022-05-10 | Dell Products L.P. | Method and system for identifying actor of a fraudulent action during legal hold and litigation |
US11372730B2 (en) | 2019-07-31 | 2022-06-28 | Dell Products L.P. | Method and system for offloading a continuous health-check and reconstruction of data in a non-accelerator pool |
US11609820B2 (en) | 2019-07-31 | 2023-03-21 | Dell Products L.P. | Method and system for redundant distribution and reconstruction of storage metadata |
US11775193B2 (en) | 2019-08-01 | 2023-10-03 | Dell Products L.P. | System and method for indirect data classification in a storage system operations |
US20210191652A1 (en) * | 2019-12-23 | 2021-06-24 | Micron Technology, Inc. | Linking access commands for a memory sub-system |
US11099785B2 (en) * | 2019-12-23 | 2021-08-24 | Micron Technology, Inc. | Linking access commands for a memory sub-system |
US11301327B2 (en) * | 2020-03-06 | 2022-04-12 | Dell Products L.P. | Method and system for managing a spare persistent storage device and a spare node in a multi-node data cluster |
US11416357B2 (en) | 2020-03-06 | 2022-08-16 | Dell Products L.P. | Method and system for managing a spare fault domain in a multi-fault domain data cluster |
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US11341989B2 (en) | 2020-09-30 | 2022-05-24 | Seagate Technology Llc | Read head stress reduction |
US11386921B2 (en) * | 2020-09-30 | 2022-07-12 | Seagate Technology Llc | Read head stress reduction |
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