US20100110656A1 - Chip package and manufacturing method thereof - Google Patents

Chip package and manufacturing method thereof Download PDF

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Publication number
US20100110656A1
US20100110656A1 US12/388,771 US38877109A US2010110656A1 US 20100110656 A1 US20100110656 A1 US 20100110656A1 US 38877109 A US38877109 A US 38877109A US 2010110656 A1 US2010110656 A1 US 2010110656A1
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Prior art keywords
chip
substrate
conductive bodies
conductive
molding compound
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Abandoned
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US12/388,771
Inventor
Dongkyun Ko
Jung Lee
Jaesun An
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to US12/388,771 priority Critical patent/US20100110656A1/en
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC. reassignment ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AN, JAESUN, KO, DONGKYUN, LEE, JUNG
Priority to TW098124438A priority patent/TWI387070B/en
Priority to CN2009101713433A priority patent/CN101728364B/en
Publication of US20100110656A1 publication Critical patent/US20100110656A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01047—Silver [Ag]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0415—Small preforms other than balls, e.g. discs, cylinders or pillars
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a chip package.
  • Electro-magnetic interference is a serious and challenging problem for most electronic devices or systems. As EMI disturbances commonly interrupt, degrade or limit the effective performance of the electronic device or the whole circuit of the electronic system, it is necessary for the electronic devices or systems to have efficient EMI protection to ensure the effective and safe operation.
  • EMI protection is particularly important in small-sized, densely packaged or sensitive electronic applications operating at high frequencies.
  • Conventionally, EMI shielding solutions typically involve the use of metal plates and/or conductive gaskets, which are later attached or affixed at higher manufacturing costs.
  • the present invention provides a manufacturing method of a chip package, which offers better design flexibility with less effort.
  • the present invention is further directed to a chip package with enhanced effectiveness of EMI shielding.
  • the present invention provides a chip package including a laminate substrate, at least a chip disposed on the laminate substrate, a plurality of conductive bodies, a molding compound and a shielding layer.
  • the conductive bodies disposed on the laminate substrate are arranged around the chip.
  • the molding compound at least encapsulates the chip, a portion of the laminate substrate and the conductive bodies, but partially exposes top surfaces of the conductive bodies.
  • the shielding layer disposed over the molding compound covers not only the molding compound but also the exposed top surface of each conductive body.
  • solder materials or parts of the leadframe or printed circuit board can be used to form the conductive bodies.
  • the conductive bodies can be arranged at the boundary lines of the laminate substrate and at least a side surface of each conductive body is exposed.
  • the conductive bodies can be arranged along the boundary lines of the laminate substrate and the side surfaces of each conductive body are not exposed.
  • the chip is electrically connected to the laminate substrate of the chip package though a plurality of bumps.
  • the invention further provides a manufacturing method of a chip package.
  • a plurality of conductive bodies are formed on each substrate unit of the provided matrix substrate and arranged around the die attaching region of the substrate unit. At least a chip is disposed on the die attaching region of the substrate unit, and the chip is electrically connected to the substrate unit.
  • a marking process is performed to remove a portion of the molding compound until a top surface of each conductive body is exposed.
  • a shielding layer is formed over the molding compound to cover the molding compound and the exposed top surface of each conductive body. Then a singulation process is performed to obtain a plurality of chip packages.
  • the conductive bodies can be arranged on sawing lines of the matrix substrate and on boundary lines of each substrate unit, or arranged around boundary lines of each substrate unit with a distance apart.
  • the conductive bodies are formed from a metallic material by a spraying process, a sputtering process or a plating process, or formed from a solder material by a spraying process or a printing process.
  • the marking process comprises a laser digging process or a laser drilling process.
  • the shielding layer and the connected conductive bodies disposed on the substrate functions as an EMI shield of the chip package for the surrounding EMI radiation.
  • a complete EMI shielding is achieved through the shielding layer and the conductive bodies with flexible and variable designs. Therefore, the chip package of the present invention has better EMI shielding effectiveness and improved process windows.
  • FIGS. 1A through 1G are schematic views showing a manufacturing method of the chip package according to one preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a chip package according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of a chip package according to another embodiment of the present invention.
  • the manufacturing methods as described in the present invention can be used for fabricating various package structures and are more suitable for fabricating stacked type packages, multiple-chip packages, or high frequency device packages (including radio frequency device packages). Moreover, the manufacturing methods as described in the present invention are compatible with packaging processes utilizing build-up substrate manufacturing process or array substrate manufacturing process.
  • FIGS. 1A through 1G are schematic views showing a manufacturing method of the chip package according to the preferred embodiment of the present invention.
  • FIGS. 1A , 1 B, 1 B′ and 1 C are shown in three-dimensional schematic views, while FIGS. 1D-1G are shown in cross-sectional schematic views.
  • a matrix substrate 100 having a plurality of substrate 102 (defined by the subsequent sawing lines shown as dotted lines) is provided, while each substrate 102 includes a plurality of contacts 104 thereon.
  • the contacts 104 are arranged within the die attaching area 103 of each substrate 102 .
  • the contacts 104 function as bump pads for flip chip connecting technology.
  • the substrate 100 can be a laminate substrate, for example, a printed circuit board (PCB).
  • a plurality of conductive bodies 110 is disposed over the top surface 102 a of the substrate 102 , outside the die attaching area 103 .
  • the conductive bodies 110 are arranged around the boundary or perimeter of each substrate 102 .
  • the individual conductive bodies 110 are arranged right on the boundary lines of the substrate 102 (the dotted lines). In this case, the subsequent sawing process will cut through the conductive bodies 110 arranged along the sawing lines.
  • the individual conductive bodies 110 may be arranged along the boundary lines of the substrate 102 but are not exactly located on the boundary lines of the substrate 102 (the dotted lines), as shown in FIG. 1 B′.
  • the conductive bodies 110 may be arranged close to the boundary lines of the substrate 102 , separate by a small distance d, and d can be varied according to product requirements. However, the subsequent sawing process will not cut through the conductive bodies 110 arranged along the sawing lines.
  • the conductive body 110 can be made of a solder material, for example.
  • the conductive body 110 can be made from a conductive carrier, such as, a leadframe or a laminate printed circuit board.
  • the shape of the conductive body 110 can be polygonal blocks (shown as rectangular blocks in FIG. 1B or 1 B′). However, the conductive body 110 can be shaped as blocks, strips or even connected with one another as a ring structure, for example. In general, the sizes or the shape of conductive body 110 can be varied depending on the shielding requisites or other electrical properties of the package or even varied in accordance with the processing parameters.
  • a multi-layered substrate such as a multi-layered PCB
  • a chip 120 is disposed on each substrate 102 and within attaching area 103 .
  • a chip is provided herein, other surface mount components can be employed, and encompassed within the scope of this invention.
  • the chip 120 is electrically connected to the contacts 104 of the substrate 102 through a plurality of bumps 106 (shown in FIG. 1D ) there-between.
  • flip chip connecting technology is described herein, it is well encompassed within the scope of this invention to employ wire bonding technology (i.e. through wire connections).
  • the chip 120 should be completely separated from the conductive bodies 110 .
  • a molding process is carried out to form a molding compound 130 on the matrix substrate 100 to encapsulate the conductive bodies 110 , the chips 120 , the bumps 106 and at least a portion of the substrate 102 .
  • the molding process can be an over-molding process, for example.
  • the conductive body 110 is depicted as higher than the total height of the chip 120 and the bumps 106 , it is optional to form the conductive body 110 with a height smaller or larger than the total height of the chip 120 and the bumps 106 .
  • a marking process is performed to remove portions of the molding compound 130 over the conductive bodies 110 , so that the top surface 110 a of each conductive body 110 is at least partially exposed.
  • the top surface 110 a of the conductive body can be partially exposed or completely exposed.
  • the marking process may include a laser drilling process or a laser digging process, for example. Taking the conductive bodies arranged around the boundary of each substrate 102 as an example, the marking process may removes portions of the molding compound 130 by forming a ring-like trench within the molding compound 130 over the conductive bodies 110 , around the boundary of each substrate 102 .
  • a shielding layer 140 is formed over the molding compound 130 to cover the molding compound 130 and the exposed top surfaces 110 a of the conductive bodies 110 .
  • the shielding layer 140 can be formed by a spray coating method, a plating method, or a sputtering method, for example.
  • the singulation process is performed to obtain the individual chip packages 10 .
  • the singulation process may be a blade sawing process, for example.
  • FIG. 2 is a cross-sectional view of a chip package according to a preferred embodiment of the present invention.
  • the chip package 20 of the present embodiment includes a substrate 102 , a plurality of bumps 106 , a plurality of conductive bodies 110 , at least a chip 120 , a molding compound 130 and a shielding layer 140 .
  • the substrate 102 can be a laminated substrate, for example, a two-layered or a four-layered laminated PCB substrate.
  • the chip 120 can be a semiconductor chip, for example, a radio-frequency (RF) chip.
  • the material of the shielding layer 140 may be copper, aluminum or alloys thereof or even a solder material, for example.
  • the chips 120 are electrically connected to the substrates 102 through bumps 106 .
  • the molding compound 130 encapsulates portions of the substrates 102 , the conductive bodies 110 , and the chips 120 .
  • the shielding layer 140 is disposed over the molding compound 130 , covering the top surface of the molding compound 130 and the exposed top surfaces 110 a of the conductive bodies 110 .
  • the shielding layer 140 is electrically connected to the substrate 102 through the conductive bodies 110 .
  • the conductive body 110 can be made from a laminated PCB or a leadframe (i.e. be a chunk or a piece of a laminated PCB or a leadframe), for example. If the conductive body 110 is a piece of a laminated PCB, the shielding layer 140 can be electrically connected to the substrate 102 through vias or plated through-holes of the conductive bodies 110 , for example. If the conductive body 110 is a piece of a leadframe, the shielding layer 140 can be electrically connected to the substrate 102 through the conductive bodies 110 and the conductive bodies 110 can be fixed to the substrate 102 through conductive adhesives, such as anisotropy conductive films (ACF), for example. Alternatively, the conductive body 110 can be made of a solder material; i.e. be a solder lump, strip or a solder ring structure, for example.
  • ACF anisotropy conductive films
  • the conductive body 110 is connected to a ground vias 108 of the substrate 102 , and the shielding layer 140 is electrically grounded through the conductive body 110 and the ground via 108 .
  • the shielding layer of the present invention can be grounded within the package structure using the ground plane of the substrate. It should be noted that at least a sidewall 110 b of each conductive body 110 is aligned with the edge of the shielding layer 140 , as the sawing process cuts through the conductive bodies arranged on the sawing street lines. That is, the sidewall 110 b of each conductive body 110 is exposed.
  • the sidewall 110 b of each conductive body 110 is not exposed and is covered by the molding compound 130 .
  • the conductive bodies 110 are fully encapsulated by the molding compound 130 , except the exposed top surface 110 a .
  • the sidewall 130 b of the molding compound is aligned with an edge of the shielding layer, through the cutting of the singulation process.
  • the package structure 30 follows the manufacturing step shown in FIG. 1 B′ (rather than FIG. 1B ), and the sawing process does not cut through the conductive bodies arranged around the sawing street lines.
  • the shielding layer and the conductive bodies disposed on the substrate together function as an EMI shield, protecting the package from the EMI radiation from the surrounding radiation sources.
  • the shielding layer is formed over the whole matrix substrate and the molding compound before the singulation process, no half-cutting process is required and the process window is increased and the reliability is improved.
  • the shielding layer and the conductive bodies can efficiently shelter the chip package of the present invention from the outside EMI radiation, thus boosting the EMI shielding.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A chip package including a plurality of conductive bodies and a shielding layer for better electromagnetic interferences shielding is provided. The shielding layer over the molding compound contacts with the conductive bodies disposed on the substrate, and the shielding layer and the conductive bodies function as EMI shield. The shielding layer is electrically grounded through the conductive bodies connected to the laminate substrate and the ground plane of the substrate.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority benefit of U.S. provisional application Ser. No. 61/109,937, filed on Oct. 31, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device, and more particularly to a chip package.
  • 2. Description of Related Art
  • Electro-magnetic interference (EMI) is a serious and challenging problem for most electronic devices or systems. As EMI disturbances commonly interrupt, degrade or limit the effective performance of the electronic device or the whole circuit of the electronic system, it is necessary for the electronic devices or systems to have efficient EMI protection to ensure the effective and safe operation.
  • EMI protection is particularly important in small-sized, densely packaged or sensitive electronic applications operating at high frequencies. Conventionally, EMI shielding solutions typically involve the use of metal plates and/or conductive gaskets, which are later attached or affixed at higher manufacturing costs.
    • SUMMARY OF THE INVENTION
  • In view of the foregoing, the present invention provides a manufacturing method of a chip package, which offers better design flexibility with less effort.
  • The present invention is further directed to a chip package with enhanced effectiveness of EMI shielding.
  • The present invention provides a chip package including a laminate substrate, at least a chip disposed on the laminate substrate, a plurality of conductive bodies, a molding compound and a shielding layer. The conductive bodies disposed on the laminate substrate are arranged around the chip. The molding compound at least encapsulates the chip, a portion of the laminate substrate and the conductive bodies, but partially exposes top surfaces of the conductive bodies. The shielding layer disposed over the molding compound covers not only the molding compound but also the exposed top surface of each conductive body.
  • According to embodiments of the present invention, either solder materials or parts of the leadframe or printed circuit board can be used to form the conductive bodies.
  • According to embodiments of the present invention, the conductive bodies can be arranged at the boundary lines of the laminate substrate and at least a side surface of each conductive body is exposed.
  • According to embodiments of the present invention, the conductive bodies can be arranged along the boundary lines of the laminate substrate and the side surfaces of each conductive body are not exposed.
  • According to embodiments of the present invention, the chip is electrically connected to the laminate substrate of the chip package though a plurality of bumps.
  • The invention further provides a manufacturing method of a chip package. A plurality of conductive bodies are formed on each substrate unit of the provided matrix substrate and arranged around the die attaching region of the substrate unit. At least a chip is disposed on the die attaching region of the substrate unit, and the chip is electrically connected to the substrate unit. After forming a molding compound over the matrix substrate to encapsulate the chip, portions of the substrate units and the conductive bodies, a marking process is performed to remove a portion of the molding compound until a top surface of each conductive body is exposed. Later, a shielding layer is formed over the molding compound to cover the molding compound and the exposed top surface of each conductive body. Then a singulation process is performed to obtain a plurality of chip packages.
  • According to one embodiment of the present invention, the conductive bodies can be arranged on sawing lines of the matrix substrate and on boundary lines of each substrate unit, or arranged around boundary lines of each substrate unit with a distance apart.
  • According to one embodiment of the present invention, the conductive bodies are formed from a metallic material by a spraying process, a sputtering process or a plating process, or formed from a solder material by a spraying process or a printing process.
  • According to one embodiment of the present invention, the marking process comprises a laser digging process or a laser drilling process.
  • Based on the above, the shielding layer and the connected conductive bodies disposed on the substrate functions as an EMI shield of the chip package for the surrounding EMI radiation. According to the present invention, a complete EMI shielding is achieved through the shielding layer and the conductive bodies with flexible and variable designs. Therefore, the chip package of the present invention has better EMI shielding effectiveness and improved process windows.
  • In order to the make the aforementioned and other objects, features and advantages of the present invention comprehensible, several embodiments accompanied with figures are described in detail below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A through 1G are schematic views showing a manufacturing method of the chip package according to one preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a chip package according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of a chip package according to another embodiment of the present invention.
    •  DESCRIPTION OF EMBODIMENTS
  • Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
  • The manufacturing methods as described in the present invention can be used for fabricating various package structures and are more suitable for fabricating stacked type packages, multiple-chip packages, or high frequency device packages (including radio frequency device packages). Moreover, the manufacturing methods as described in the present invention are compatible with packaging processes utilizing build-up substrate manufacturing process or array substrate manufacturing process.
  • FIGS. 1A through 1G are schematic views showing a manufacturing method of the chip package according to the preferred embodiment of the present invention. FIGS. 1A, 1B, 1B′ and 1C are shown in three-dimensional schematic views, while FIGS. 1D-1G are shown in cross-sectional schematic views.
  • Referring to FIG. 1A, a matrix substrate 100 having a plurality of substrate 102 (defined by the subsequent sawing lines shown as dotted lines) is provided, while each substrate 102 includes a plurality of contacts 104 thereon. The contacts 104 are arranged within the die attaching area 103 of each substrate 102. The contacts 104 function as bump pads for flip chip connecting technology. The substrate 100 can be a laminate substrate, for example, a printed circuit board (PCB).
  • Referring to FIG. 1B, a plurality of conductive bodies 110 is disposed over the top surface 102 a of the substrate 102, outside the die attaching area 103. Preferably, the conductive bodies 110 are arranged around the boundary or perimeter of each substrate 102. As shown in FIG. 1B, the individual conductive bodies 110 are arranged right on the boundary lines of the substrate 102 (the dotted lines). In this case, the subsequent sawing process will cut through the conductive bodies 110 arranged along the sawing lines.
  • On the other hand, the individual conductive bodies 110 may be arranged along the boundary lines of the substrate 102 but are not exactly located on the boundary lines of the substrate 102 (the dotted lines), as shown in FIG. 1B′. The conductive bodies 110 may be arranged close to the boundary lines of the substrate 102, separate by a small distance d, and d can be varied according to product requirements. However, the subsequent sawing process will not cut through the conductive bodies 110 arranged along the sawing lines.
  • The conductive body 110 can be made of a solder material, for example. Alternatively, the conductive body 110 can be made from a conductive carrier, such as, a leadframe or a laminate printed circuit board. The shape of the conductive body 110 can be polygonal blocks (shown as rectangular blocks in FIG. 1B or 1B′). However, the conductive body 110 can be shaped as blocks, strips or even connected with one another as a ring structure, for example. In general, the sizes or the shape of conductive body 110 can be varied depending on the shielding requisites or other electrical properties of the package or even varied in accordance with the processing parameters.
  • If a multi-layered substrate, such as a multi-layered PCB, is employed, it is possible to form the conductive bodies 110 from the routing manufacturing step of the build-up substrate manufacturing process. That is, during the routing process to form the traces of the substrate, the conductive bodies can be formed by the same process as patterned metallic blocks, other than the traces.
  • Referring to FIG. 1C, at least a chip 120 is disposed on each substrate 102 and within attaching area 103. Although a chip is provided herein, other surface mount components can be employed, and encompassed within the scope of this invention. The chip 120 is electrically connected to the contacts 104 of the substrate 102 through a plurality of bumps 106 (shown in FIG. 1D) there-between. Although flip chip connecting technology is described herein, it is well encompassed within the scope of this invention to employ wire bonding technology (i.e. through wire connections). The chip 120 should be completely separated from the conductive bodies 110.
  • Referring to FIG. 1D, a molding process is carried out to form a molding compound 130 on the matrix substrate 100 to encapsulate the conductive bodies 110, the chips 120, the bumps 106 and at least a portion of the substrate 102. The molding process can be an over-molding process, for example. Although the conductive body 110 is depicted as higher than the total height of the chip 120 and the bumps 106, it is optional to form the conductive body 110 with a height smaller or larger than the total height of the chip 120 and the bumps 106.
  • Referring to FIG. 1E, a marking process is performed to remove portions of the molding compound 130 over the conductive bodies 110, so that the top surface 110 a of each conductive body 110 is at least partially exposed. The top surface 110 a of the conductive body can be partially exposed or completely exposed. The marking process may include a laser drilling process or a laser digging process, for example. Taking the conductive bodies arranged around the boundary of each substrate 102 as an example, the marking process may removes portions of the molding compound 130 by forming a ring-like trench within the molding compound 130 over the conductive bodies 110, around the boundary of each substrate 102.
  • Referring to FIG. 1F, a shielding layer 140 is formed over the molding compound 130 to cover the molding compound 130 and the exposed top surfaces 110 a of the conductive bodies 110. The shielding layer 140 can be formed by a spray coating method, a plating method, or a sputtering method, for example.
  • Finally, referring to FIG. 1G, a singulation process is performed to obtain the individual chip packages 10. The singulation process may be a blade sawing process, for example.
  • FIG. 2 is a cross-sectional view of a chip package according to a preferred embodiment of the present invention. Referring to FIG. 2, the chip package 20 of the present embodiment includes a substrate 102, a plurality of bumps 106, a plurality of conductive bodies 110, at least a chip 120, a molding compound 130 and a shielding layer 140. The substrate 102 can be a laminated substrate, for example, a two-layered or a four-layered laminated PCB substrate. The chip 120 can be a semiconductor chip, for example, a radio-frequency (RF) chip. The material of the shielding layer 140 may be copper, aluminum or alloys thereof or even a solder material, for example. The chips 120 are electrically connected to the substrates 102 through bumps 106. The molding compound 130 encapsulates portions of the substrates 102, the conductive bodies 110, and the chips 120. Besides, the shielding layer 140 is disposed over the molding compound 130, covering the top surface of the molding compound 130 and the exposed top surfaces 110 a of the conductive bodies 110. The shielding layer 140 is electrically connected to the substrate 102 through the conductive bodies 110.
  • For example, the conductive body 110 can be made from a laminated PCB or a leadframe (i.e. be a chunk or a piece of a laminated PCB or a leadframe), for example. If the conductive body 110 is a piece of a laminated PCB, the shielding layer 140 can be electrically connected to the substrate 102 through vias or plated through-holes of the conductive bodies 110, for example. If the conductive body 110 is a piece of a leadframe, the shielding layer 140 can be electrically connected to the substrate 102 through the conductive bodies 110 and the conductive bodies 110 can be fixed to the substrate 102 through conductive adhesives, such as anisotropy conductive films (ACF), for example. Alternatively, the conductive body 110 can be made of a solder material; i.e. be a solder lump, strip or a solder ring structure, for example.
  • In addition, the conductive body 110 is connected to a ground vias 108 of the substrate 102, and the shielding layer 140 is electrically grounded through the conductive body 110 and the ground via 108. Hence, taking advantage of the metal wirings or traces of the substrate surface, the shielding layer of the present invention can be grounded within the package structure using the ground plane of the substrate. It should be noted that at least a sidewall 110 b of each conductive body 110 is aligned with the edge of the shielding layer 140, as the sawing process cuts through the conductive bodies arranged on the sawing street lines. That is, the sidewall 110 b of each conductive body 110 is exposed.
  • According to another embodiment, as shown in FIG. 3, the sidewall 110 b of each conductive body 110 is not exposed and is covered by the molding compound 130. Instead, the conductive bodies 110 are fully encapsulated by the molding compound 130, except the exposed top surface 110 a. The sidewall 130 b of the molding compound is aligned with an edge of the shielding layer, through the cutting of the singulation process. Basically, the package structure 30 follows the manufacturing step shown in FIG. 1B′ (rather than FIG. 1B), and the sawing process does not cut through the conductive bodies arranged around the sawing street lines.
  • In the chip package structures of the present embodiment, the shielding layer and the conductive bodies disposed on the substrate together function as an EMI shield, protecting the package from the EMI radiation from the surrounding radiation sources.
  • Furthermore, as the shielding layer is formed over the whole matrix substrate and the molding compound before the singulation process, no half-cutting process is required and the process window is increased and the reliability is improved.
  • In summary, the shielding layer and the conductive bodies can efficiently shelter the chip package of the present invention from the outside EMI radiation, thus boosting the EMI shielding. Following the manufacturing processes disclosed in the present invention, it is possible to establish an electrical ground path within the package structure, devoid of using an extra ground plane. Accordingly, such design is compatible with the packaging of high frequency devices, particularly, radio frequency devices.
  • Although the present invention has been disclosed above by the embodiments, they are not intended to limit the present invention. Anybody skilled in the art can make some modifications and alteration without departing from the spirit and scope of the present invention. Therefore, the protecting range of the present invention falls in the appended claims.

Claims (18)

1. A chip package, comprising:
a laminate substrate;
at least a chip disposed on the laminate substrate;
a plurality of conductive bodies disposed on the laminate substrate and around the chip;
a molding compound, at least encapsulating the chip, a portion of the laminate substrate and the plurality of the conductive bodies; and
a shielding layer, disposed over the molding compound, covering the molding compound and partially covering at least a top surface of each conductive body exposed by the molding compound.
2. The chip package as claimed in claim 1, wherein at least a sidewall of each conductive body is exposed and is aligned with an edge of the shielding layer.
3. The chip package as claimed in claim 1, wherein sidewalls of the conductive bodies are covered by the molding compound and an edge of the molding compound is aligned with an edge of the shielding layer.
4. The chip package as claimed in claim 1, wherein the chip is electrically connected to the contacts through a plurality of bumps arranged underneath the chip.
5. The chip package as claimed in claim 1, wherein the conductive bodies are arranged around the chip as a ring, and the chip is separated from the conductive bodies.
6. The chip package as claimed in claim 1, wherein the chip is a radio frequency chip.
7. The chip package as claimed in claim 1, wherein the shielding layer is electrically connected to the laminate substrate via the conductive body and at least a ground via of the laminate substrate.
8. The chip package as claimed in claim 1, wherein the conductive body is made of a solder material and the conductive body is a solder block.
9. The chip package as claimed in claim 1, wherein the conductive body is a part of a printed circuit board.
10. The chip package as claimed in claim 1, wherein the conductive body is a part of a leadframe.
11. The chip package as claimed in claim 1, wherein a material of the shielding layer is a metal material.
12. A manufacturing method of a chip package, comprising:
providing a matrix substrate having a plurality of substrate units, wherein each substrate unit is defined by a plurality of sawing lines and has a die attaching region thereon;
forming a plurality of conductive bodies on each substrate unit and arranged around the die attaching region;
disposing at least a chip on the die attaching region of the substrate unit, wherein the chip is electrically connected to the substrate unit, and the plurality of conductive bodies is separated from the chip;
forming a molding compound over the matrix substrate to encapsulate the chip, portions of the substrate units and the conductive bodies;
performing a marking process to remove a portion of the molding compound until a top surface of each conductive body is exposed;
forming a shielding layer over the molding compound to cover the molding compound and the exposed top surface of each conductive body; and
performing a singulation process to obtain a plurality of chip packages.
13. The method as claimed in claim 12, wherein the conductive bodies are arranged on sawing lines of the matrix substrate and on boundary lines of each substrate unit.
14. The method as claimed in claim 12, wherein the conductive bodies are arranged around boundary lines of each substrate unit with a distance apart.
15. The method as claimed in claim 12, wherein the conductive bodies are formed from a metallic material by a spraying process, a sputtering process or a plating process.
16. The method as claimed in claim 12, wherein the conductive bodies are formed from a solder material by a spraying process or a printing process.
17. The method as claimed in claim 12, wherein the marking process comprises a laser digging process or a laser drilling process.
18. The method as claimed in claim 12, wherein the chip is electrically connected to the substrate through flip chip bonding.
US12/388,771 2008-10-31 2009-02-19 Chip package and manufacturing method thereof Abandoned US20100110656A1 (en)

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Cited By (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090194851A1 (en) * 2008-02-05 2009-08-06 Chi-Tsung Chiu Semiconductor device packages with electromagnetic interference shielding
US20100032815A1 (en) * 2008-08-08 2010-02-11 An Jaeseon Semiconductor device packages with electromagnetic interference shielding
US20100109132A1 (en) * 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US20100207257A1 (en) * 2009-02-17 2010-08-19 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method thereof
US20100207259A1 (en) * 2008-02-05 2010-08-19 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20110115066A1 (en) * 2009-11-19 2011-05-19 Seokbong Kim Semiconductor device packages with electromagnetic interference shielding
US20110115059A1 (en) * 2009-11-19 2011-05-19 Yuyong Lee Semiconductor Device Packages with Electromagnetic Interference Shielding
US7989928B2 (en) 2008-02-05 2011-08-02 Advanced Semiconductor Engineering Inc. Semiconductor device packages with electromagnetic interference shielding
US8022511B2 (en) 2008-02-05 2011-09-20 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
CN102281707A (en) * 2010-06-11 2011-12-14 株式会社村田制作所 Circuit module
US8110902B2 (en) 2009-02-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8212340B2 (en) 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US20120170162A1 (en) * 2011-01-05 2012-07-05 Siliconware Precision Industries Co., Ltd. Semiconductor package and fabrication method thereof
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8653634B2 (en) 2012-06-11 2014-02-18 Advanced Semiconductor Engineering, Inc. EMI-shielded semiconductor devices and methods of making
US8704341B2 (en) 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
US20140146495A1 (en) * 2010-12-01 2014-05-29 Apple Inc. Printed Circuit Board With Integral Radio-Frequency Shields
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8884424B2 (en) 2010-01-13 2014-11-11 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8937376B2 (en) 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US20150070849A1 (en) * 2013-09-12 2015-03-12 Taiyo Yuden Co., Ltd. Circuit module and method of producing circuit module
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US20150179481A1 (en) * 2013-12-23 2015-06-25 Stats Chippac, Ltd. Semiconductor Device and Method of Making Embedded Wafer Level Chip Scale Packages
US9070793B2 (en) 2010-08-02 2015-06-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having electromagnetic interference shielding and related methods
US9101050B2 (en) * 2013-08-13 2015-08-04 Taiyo Yuden Co., Ltd. Circuit module having electrical shield
US9129954B2 (en) 2013-03-07 2015-09-08 Advanced Semiconductor Engineering, Inc. Semiconductor package including antenna layer and manufacturing method thereof
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US9172131B2 (en) 2013-03-15 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor structure having aperture antenna
US20150348936A1 (en) * 2014-06-02 2015-12-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Electromagnetic (EM) Shielding for LC Circuits
US9236356B2 (en) 2013-07-31 2016-01-12 Advanced Semiconductor Engineering, Inc. Semiconductor package with grounding and shielding layers
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US9437576B1 (en) * 2015-03-23 2016-09-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US9490219B2 (en) * 2014-05-16 2016-11-08 Siliconware Precision Industries Co., Ltd. Semiconductor package with shielding member and method of manufacturing the same
US20170069828A1 (en) * 2015-09-09 2017-03-09 Samsung Electronics Co., Ltd. Semiconductor device
US9711462B2 (en) 2013-05-08 2017-07-18 Infineon Technologies Ag Package arrangement including external block comprising semiconductor material and electrically conductive plastic material
US9837701B2 (en) 2013-03-04 2017-12-05 Advanced Semiconductor Engineering, Inc. Semiconductor package including antenna substrate and manufacturing method thereof
US9842809B2 (en) 2015-08-10 2017-12-12 SK Hynix Inc. Semiconductor packages having EMI shielding parts and methods of fabricating the same
US20180083416A1 (en) * 2013-11-11 2018-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Method of Forming Chip Package with Waveguide for Light Coupling
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US10790239B2 (en) * 2018-09-12 2020-09-29 Samsung Electronics Co., Ltd. Semiconductor package and board for mounting the same
CN113380768A (en) * 2020-03-09 2021-09-10 南茂科技股份有限公司 Chip packaging structure and manufacturing method thereof
US11139252B2 (en) * 2018-05-11 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same

Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090000815A1 (en) 2007-06-27 2009-01-01 Rf Micro Devices, Inc. Conformal shielding employing segment buildup
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
WO2009144960A1 (en) * 2008-05-30 2009-12-03 三洋電機株式会社 Semiconductor module, semiconductor module manufacturing method and portable apparatus
US8018034B2 (en) 2009-05-01 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
US20110014746A1 (en) * 2009-07-17 2011-01-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8008121B2 (en) * 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
TWI497679B (en) * 2009-11-27 2015-08-21 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof
TWI489610B (en) 2010-01-18 2015-06-21 矽品精密工業股份有限公司 Method for making emi shielding package structure
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8284561B2 (en) 2010-08-05 2012-10-09 Advanced Semiconductor Engineering, Inc. Embedded component package structure
US9386734B2 (en) * 2010-08-05 2016-07-05 Epcos Ag Method for producing a plurality of electronic devices
CN101937855B (en) * 2010-08-10 2012-09-26 日月光半导体制造股份有限公司 Manufacture method for buried capsulation structure of component and capsulation structure thereof
US9137934B2 (en) 2010-08-18 2015-09-15 Rf Micro Devices, Inc. Compartmentalized shielding of selected components
US9210796B2 (en) * 2010-08-24 2015-12-08 Colorchip (Israel) Ltd. Light source mount
CN104934188B (en) * 2010-08-26 2018-04-10 乾坤科技股份有限公司 Electron package structure and its method for packing
TWM395907U (en) * 2010-08-27 2011-01-01 Acsip Technology Corp Structure for packaging electronic components
US8227903B2 (en) * 2010-09-15 2012-07-24 Stats Chippac Ltd Integrated circuit packaging system with encapsulant containment and method of manufacture thereof
CN102324416B (en) * 2010-09-16 2015-07-22 日月光半导体制造股份有限公司 Integrated shielding film and semiconductor packaging member of antenna
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US8279625B2 (en) 2010-12-14 2012-10-02 Apple Inc. Printed circuit board radio-frequency shielding structures
US20120187545A1 (en) * 2011-01-24 2012-07-26 Broadcom Corporation Direct through via wafer level fanout package
TWM409527U (en) * 2011-02-23 2011-08-11 Azurewave Technologies Inc Forming integrated circuit module
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9627230B2 (en) 2011-02-28 2017-04-18 Qorvo Us, Inc. Methods of forming a microshield on standard QFN package
CN102695407B (en) * 2011-03-23 2015-05-27 环旭电子股份有限公司 Miniature electromagnetic interference protection structure and manufacture method thereof
CN102709274B (en) * 2011-03-28 2016-06-29 环旭电子股份有限公司 The electromagnetic interference shielding structure of ic substrate and its manufacture method
TW201240058A (en) * 2011-03-28 2012-10-01 Universal Scient Ind Shanghai Electromagnetic interference shielding structure for integrated circuit substrate and method for fabricating the same
KR101862370B1 (en) * 2011-05-30 2018-05-29 삼성전자주식회사 Semiconductor device, a semiconductor package and a electronic device
US9179538B2 (en) 2011-06-09 2015-11-03 Apple Inc. Electromagnetic shielding structures for selectively shielding components on a substrate
TWI483374B (en) * 2011-09-27 2015-05-01 Advanced Semiconductor Eng Semiconductor package having electromagnetic interference shielding and manufacturing method thereof
CN102306645A (en) * 2011-09-29 2012-01-04 日月光半导体制造股份有限公司 Semiconductor packaging part possessing electromagnetic interference shielding membrane and manufacture method thereof
KR20130035620A (en) * 2011-09-30 2013-04-09 삼성전자주식회사 Emi shielded semiconductor package and emi shielded substrate module
KR20130041645A (en) * 2011-10-17 2013-04-25 삼성전기주식회사 Printed circuit board
US8617927B1 (en) 2011-11-29 2013-12-31 Hrl Laboratories, Llc Method of mounting electronic chips
CN103219295B (en) * 2012-01-20 2015-12-16 环旭电子股份有限公司 Conformal mask encapsulating structure and detection method
US9030841B2 (en) * 2012-02-23 2015-05-12 Apple Inc. Low profile, space efficient circuit shields
TWI459521B (en) * 2012-03-08 2014-11-01 矽品精密工業股份有限公司 Semiconductor package and fabrication method thereof
US9348936B2 (en) 2012-07-25 2016-05-24 Oracle International Corporation Heuristic caching to personalize applications
US8729679B1 (en) 2012-12-04 2014-05-20 Nxp, B.V. Shielding silicon from external RF interference
CN109712946B (en) * 2013-03-29 2021-01-19 日月光半导体制造股份有限公司 Semiconductor package
US9807890B2 (en) 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
US10079160B1 (en) 2013-06-21 2018-09-18 Hrl Laboratories, Llc Surface mount package for semiconductor devices with embedded heat spreaders
JP5756500B2 (en) * 2013-08-07 2015-07-29 太陽誘電株式会社 Circuit module
JP5517379B1 (en) * 2013-08-19 2014-06-11 太陽誘電株式会社 Circuit module
US9524942B2 (en) * 2013-12-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-substrate packaging on carrier
US9894816B2 (en) * 2014-02-04 2018-02-13 Taiyo Yuden Co., Ltd. Circuit module
FR3018630A1 (en) * 2014-03-11 2015-09-18 St Microelectronics Grenoble 2 PERFORATED ELECTRONIC HOUSING AND METHOD OF MANUFACTURE
KR102245134B1 (en) * 2014-04-18 2021-04-28 삼성전자 주식회사 Semiconductor package comprising the semiconductor chip
KR101616625B1 (en) * 2014-07-30 2016-04-28 삼성전기주식회사 Semiconductor package and method of manufacturing the same
KR101501735B1 (en) * 2014-09-23 2015-03-12 제너셈(주) EMI shielding method of the semiconductor package
KR20160040927A (en) 2014-10-06 2016-04-15 삼성전자주식회사 Semiconductor package and method for manufacturing the same
JP6443458B2 (en) * 2015-01-30 2018-12-26 株式会社村田製作所 Electronic circuit module
USD772181S1 (en) * 2015-04-02 2016-11-22 Genesis Photonics Inc. Light emitting diode package substrate
US9385083B1 (en) 2015-05-22 2016-07-05 Hrl Laboratories, Llc Wafer-level die to package and die to die interconnects suspended over integrated heat sinks
US9461001B1 (en) 2015-07-22 2016-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same
US9871016B2 (en) 2015-07-29 2018-01-16 Samsung Electronics Co., Ltd. Semiconductor package
TWI550814B (en) 2015-07-31 2016-09-21 矽品精密工業股份有限公司 Carrier body, package substrate, electronic package and method of manufacture thereof
US10026672B1 (en) 2015-10-21 2018-07-17 Hrl Laboratories, Llc Recursive metal embedded chip assembly
US9508652B1 (en) 2015-11-24 2016-11-29 Hrl Laboratories, Llc Direct IC-to-package wafer level packaging with integrated thermal heat spreaders
WO2017093281A1 (en) * 2015-11-30 2017-06-08 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic component packaged in component carrier serving as shielding cage
US9918414B2 (en) 2015-12-18 2018-03-13 Intel Corporation Electromagnetic interference shields for electronic packages and related methods
US20170287847A1 (en) * 2016-04-01 2017-10-05 Rajendra C. Dias Integrated circuit package having integrated emi shield
JP6728917B2 (en) * 2016-04-12 2020-07-22 Tdk株式会社 Method of manufacturing electronic circuit module
US9793222B1 (en) 2016-04-21 2017-10-17 Apple Inc. Substrate designed to provide EMI shielding
CN105870106A (en) * 2016-06-01 2016-08-17 爱普科斯科技（无锡）有限公司 Packaging structure of radio frequency filtration module and packaging technology of packaging structure
JP6520845B2 (en) * 2016-06-29 2019-05-29 株式会社村田製作所 Electronic component device, method of mounting electronic component device on circuit board, and mounting structure of electronic component device on circuit board
WO2018053208A1 (en) * 2016-09-15 2018-03-22 Skyworks Solutions, Inc. Through-mold features for shielding applications
KR20180032985A (en) 2016-09-23 2018-04-02 삼성전자주식회사 Integrated circuit package and method of manufacturing the same and wearable device including integrated circuit package
JP6832666B2 (en) * 2016-09-30 2021-02-24 株式会社ディスコ Manufacturing method of semiconductor package
CN106298743B (en) * 2016-10-20 2018-11-09 江苏长电科技股份有限公司 Encapsulating structure and preparation method thereof with shield effectiveness
CN106449440B (en) * 2016-10-20 2019-02-01 江苏长电科技股份有限公司 A kind of manufacturing method of the encapsulating structure with electro-magnetic screen function
CN106340506A (en) * 2016-10-20 2017-01-18 江苏长电科技股份有限公司 Semiconductor packaging structure and manufacturing method thereof
CN106531645A (en) * 2016-12-21 2017-03-22 江苏长电科技股份有限公司 Technique of packaging-prior-to-etching type mounted metal conduction three-dimensional packaging structure
CN106981430B (en) * 2016-12-21 2019-01-29 江苏长电科技股份有限公司 A kind of process of affixed metal conducting three-dimensional systematic wiring board
CN106601636B (en) * 2016-12-21 2018-11-09 江苏长电科技股份有限公司 A kind of process of the pre-packaged metal conduction three-dimension packaging structure of attachment
JP6800745B2 (en) * 2016-12-28 2020-12-16 株式会社ディスコ Semiconductor package manufacturing method
CN108735715A (en) * 2017-04-20 2018-11-02 吴明哲 Selective electromagnetic covers package body structure and its preparation method
US10978406B2 (en) * 2017-07-13 2021-04-13 Mediatek Inc. Semiconductor package including EMI shielding structure and method for forming the same
KR20190014993A (en) * 2017-08-04 2019-02-13 에스케이하이닉스 주식회사 Semiconductor package including indicating pattern
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US11211340B2 (en) 2018-11-28 2021-12-28 Shiann-Tsong Tsai Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding
US10923435B2 (en) 2018-11-28 2021-02-16 Shiann-Tsong Tsai Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance
US10896880B2 (en) 2018-11-28 2021-01-19 Shiann-Tsong Tsai Semiconductor package with in-package compartmental shielding and fabrication method thereof
TWI744572B (en) 2018-11-28 2021-11-01 蔡憲聰 Semiconductor package with in-package compartmental shielding and fabrication method thereof
US10950562B1 (en) 2018-11-30 2021-03-16 Hrl Laboratories, Llc Impedance-matched through-wafer transition using integrated heat-spreader technology
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules
JP7188643B2 (en) * 2020-05-22 2022-12-13 三菱電機株式会社 Semiconductor device, method for manufacturing semiconductor device
TWI772170B (en) * 2021-09-06 2022-07-21 先豐通訊股份有限公司 Circuit board with embedded chips and manufacturing method
TWI820772B (en) * 2022-06-29 2023-11-01 同欣電子工業股份有限公司 Package substrate and method for fabricating chip assembly

Citations (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3390226A (en) * 1964-10-19 1968-06-25 Siemens Ag Encapsulated semiconductor element
US4049682A (en) * 1976-03-01 1977-09-20 International Flavors & Fragrances Inc. Processes for preparing enol esters
US4569786A (en) * 1983-04-12 1986-02-11 Ube Industries, Ltd. Electrically conductive thermoplastic resin composition containing metal and carbon fibers
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4814205A (en) * 1983-12-02 1989-03-21 Omi International Corporation Process for rejuvenation electroless nickel solution
US5104745A (en) * 1989-07-06 1992-04-14 Gec Alsthom Sa Multifilament superconductor strand having an anti-diffusion barrier layer
US5166772A (en) * 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
US5172077A (en) * 1991-04-27 1992-12-15 Murata Manufacturing Co., Ltd. Oscillator and method of manufacturing the same
US5355016A (en) * 1993-05-03 1994-10-11 Motorola, Inc. Shielded EPROM package
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5557142A (en) * 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5600181A (en) * 1995-05-24 1997-02-04 Lockheed Martin Corporation Hermetically sealed high density multi-chip package
US5847930A (en) * 1995-10-13 1998-12-08 Hei, Inc. Edge terminals for electronic circuit modules
US5898344A (en) * 1996-03-14 1999-04-27 Tdk Corporation High-frequency module
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6079099A (en) * 1996-06-24 2000-06-27 Sumitomo Metal Industries Limited Electronic component manufacturing method
US6093972A (en) * 1997-05-19 2000-07-25 Motorola, Inc. Microelectronic package including a polymer encapsulated die
US6150193A (en) * 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US6225694B1 (en) * 1997-09-02 2001-05-01 Oki Electric Industry Co, Ltd. Semiconductor device
US6255143B1 (en) * 1999-08-04 2001-07-03 St. Assembly Test Services Pte Ltd. Flip chip thermally enhanced ball grid array
US6261680B1 (en) * 1999-12-07 2001-07-17 Hughes Electronics Corporation Electronic assembly with charge-dissipating transparent conformal coating
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US20020053724A1 (en) * 2000-09-13 2002-05-09 Siliconware Precision Industries Co., Ltd. Semiconductor package
US20020093108A1 (en) * 2001-01-15 2002-07-18 Grigorov Ilya L. Flip chip packaged semiconductor device having double stud bumps and method of forming same
US6448632B1 (en) * 2000-08-28 2002-09-10 National Semiconductor Corporation Metal coated markings on integrated circuit devices
US6455864B1 (en) * 1994-04-01 2002-09-24 Maxwell Electronic Components Group, Inc. Methods and compositions for ionizing radiation shielding
US6472743B2 (en) * 2001-02-22 2002-10-29 Siliconware Precision Industries, Co., Ltd. Semiconductor package with heat dissipating structure
US6472598B1 (en) * 1998-08-28 2002-10-29 Amkor Technology, Inc. Electromagnetic interference shield device with conductive encapsulant and dam
US6586822B1 (en) * 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6614102B1 (en) * 2001-05-04 2003-09-02 Amkor Technology, Inc. Shielded semiconductor leadframe package
US20040063242A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US6757181B1 (en) * 2000-08-22 2004-06-29 Skyworks Solutions, Inc. Molded shield structures and method for their fabrication
US20050029673A1 (en) * 2001-04-06 2005-02-10 Hitachi, Ltd. Multi-chip semiconductor device with specific chip arrangement
US20050046001A1 (en) * 2001-08-28 2005-03-03 Tessera, Inc High-frequency chip packages
US6867480B2 (en) * 2003-06-10 2005-03-15 Lsi Logic Corporation Electromagnetic interference package protection
US6900383B2 (en) * 2001-03-19 2005-05-31 Hewlett-Packard Development Company, L.P. Board-level EMI shield that adheres to and conforms with printed circuit board component and board surfaces
US6926869B2 (en) * 2000-10-09 2005-08-09 Urea Casale S.A. Apparatus for carbamate decomposition and ammonia and carbon dioxide stripping from urea solutions capable of 180 degree inversion about a horizontal axis
US6928719B2 (en) * 2001-12-07 2005-08-16 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter package
US6992400B2 (en) * 2004-01-30 2006-01-31 Nokia Corporation Encapsulated electronics device with improved heat dissipation
US7045385B2 (en) * 2003-08-20 2006-05-16 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter packages and package sheet used therein
US7081661B2 (en) * 2001-03-16 2006-07-25 Matsushita Electric Industrial Co., Ltd. High-frequency module and method for manufacturing the same
US7187060B2 (en) * 2003-03-13 2007-03-06 Sanyo Electric Co., Ltd. Semiconductor device with shield
US7186928B2 (en) * 2002-08-01 2007-03-06 Nec Corporation Electronic device including chip parts and a method for manufacturing the same
US20080042301A1 (en) * 2005-01-05 2008-02-21 Integrated System Solution Advanced Semiconductor Semiconductor device package and manufacturing method
US7446265B2 (en) * 2005-04-15 2008-11-04 Parker Hannifin Corporation Board level shielding module
US7445968B2 (en) * 2005-12-16 2008-11-04 Sige Semiconductor (U.S.), Corp. Methods for integrated circuit module packaging and integrated circuit module packages
US20090000114A1 (en) * 2007-06-27 2009-01-01 Rf Micro Devices, Inc. Heat sink formed with conformal shield
US20090075428A1 (en) * 2007-09-13 2009-03-19 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090102033A1 (en) * 2007-10-18 2009-04-23 Elmos Advanced Packaging B.V. Integrated circuit package
US7626974B2 (en) * 2003-11-24 2009-12-01 Telefonaktiebolaget Lm Ericsson (Publ) Frame synchronisation in a radio access network
US7633170B2 (en) * 2005-01-05 2009-12-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method thereof
US7643311B2 (en) * 2005-04-21 2010-01-05 Stmicroelectronics Sa Electronic circuit protection device
US7741151B2 (en) * 2008-11-06 2010-06-22 Freescale Semiconductor, Inc. Integrated circuit package formation
US7772046B2 (en) * 2008-06-04 2010-08-10 Stats Chippac, Ltd. Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference
US7829981B2 (en) * 2008-07-21 2010-11-09 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821007A (en) 1987-02-06 1989-04-11 Tektronix, Inc. Strip line circuit component and method of manufacture
US5140745A (en) 1990-07-23 1992-08-25 Mckenzie Jr Joseph A Method for forming traces on side edges of printed circuit boards and devices formed thereby
US5173764A (en) 1991-04-08 1992-12-22 Motorola, Inc. Semiconductor device having a particular lid means and encapsulant to reduce die stress
DE4340594C2 (en) * 1992-12-01 1998-04-09 Murata Manufacturing Co Method of manufacturing and adjusting the characteristics of a surface mount chip type LC filter
FI117224B (en) 1994-01-20 2006-07-31 Nec Tokin Corp Electromagnetic interference suppression piece, applied by electronic device and hybrid integrated circuit element
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
JP3541491B2 (en) 1994-06-22 2004-07-14 セイコーエプソン株式会社 Electronic components
DE4443489C2 (en) 1994-12-07 1997-08-14 Happich Gmbh Gebr Method for producing a sun visor body of a vehicle sun visor, which body is covered with decorative material blanks
US5677511A (en) * 1995-03-20 1997-10-14 National Semiconductor Corporation Overmolded PC board with ESD protection and EMI suppression
JPH08288686A (en) 1995-04-20 1996-11-01 Nec Corp Semiconductor device
DE29514398U1 (en) 1995-09-07 1995-10-19 Siemens Ag Shielding for printed circuit boards
JP3432982B2 (en) * 1995-12-13 2003-08-04 沖電気工業株式会社 Method for manufacturing surface mount semiconductor device
US5998867A (en) * 1996-02-23 1999-12-07 Honeywell Inc. Radiation enhanced chip encapsulant
US5694300A (en) * 1996-04-01 1997-12-02 Northrop Grumman Corporation Electromagnetically channelized microwave integrated circuit
US5776798A (en) * 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
JPH10284935A (en) 1997-04-09 1998-10-23 Murata Mfg Co Ltd Voltage-controlled oscillator and its production
US6566596B1 (en) * 1997-12-29 2003-05-20 Intel Corporation Magnetic and electric shielding of on-board devices
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
JP3617368B2 (en) 1999-04-02 2005-02-02 株式会社村田製作所 Mother board, sub board and manufacturing method thereof
FR2799883B1 (en) 1999-10-15 2003-05-30 Thomson Csf METHOD OF ENCAPSULATING ELECTRONIC COMPONENTS
DE10002852A1 (en) 2000-01-24 2001-08-02 Infineon Technologies Ag Shielding device and electrical component with a shielding device
US20010033478A1 (en) 2000-04-21 2001-10-25 Shielding For Electronics, Inc. EMI and RFI shielding for printed circuit boards
CN2457740Y (en) * 2001-01-09 2001-10-31 台湾沛晶股份有限公司 Structure of IC wafer
TW495943B (en) 2001-04-18 2002-07-21 Siliconware Precision Industries Co Ltd Semiconductor package article with heat sink structure and its manufacture method
US6686649B1 (en) * 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
JP3645197B2 (en) 2001-06-12 2005-05-11 日東電工株式会社 Semiconductor device and epoxy resin composition for semiconductor encapsulation used therefor
JP3865601B2 (en) 2001-06-12 2007-01-10 日東電工株式会社 Electromagnetic wave suppression sheet
US6740959B2 (en) * 2001-08-01 2004-05-25 International Business Machines Corporation EMI shielding for semiconductor chip carriers
TW550997B (en) 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
JP2003273571A (en) 2002-03-18 2003-09-26 Fujitsu Ltd High-frequency module for shielding inter-element radio wave interference
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7161252B2 (en) * 2002-07-19 2007-01-09 Matsushita Electric Industrial Co., Ltd. Module component
US6740546B2 (en) * 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
JP4178880B2 (en) * 2002-08-29 2008-11-12 松下電器産業株式会社 Module parts
US6781231B2 (en) * 2002-09-10 2004-08-24 Knowles Electronics Llc Microelectromechanical system package with environmental and interference shield
US6962869B1 (en) * 2002-10-15 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. SiOCH low k surface protection layer formation by CxHy gas plasma treatment
WO2004060034A1 (en) 2002-12-24 2004-07-15 Matsushita Electric Industrial Co., Ltd. Electronic component-built-in module
US20040150097A1 (en) * 2003-01-30 2004-08-05 International Business Machines Corporation Optimized conductive lid mounting for integrated circuit chip carriers
TWI235469B (en) * 2003-02-07 2005-07-01 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package with EMI shielding
CN1774959A (en) * 2003-04-15 2006-05-17 波零公司 Electomagnetic interference shielding for a printed circuit board
US6838776B2 (en) 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
JP4377157B2 (en) * 2003-05-20 2009-12-02 Ｎｅｃエレクトロニクス株式会社 Package for semiconductor devices
TWI236118B (en) 2003-06-18 2005-07-11 Advanced Semiconductor Eng Package structure with a heat spreader and manufacturing method thereof
US7129422B2 (en) * 2003-06-19 2006-10-31 Wavezero, Inc. EMI absorbing shielding for a printed circuit board
JP4206858B2 (en) 2003-08-04 2009-01-14 双葉電子工業株式会社 Field electron emission device
JP2005072095A (en) * 2003-08-20 2005-03-17 Alps Electric Co Ltd Electronic circuit unit and manufacturing method therefor
TWI236113B (en) * 2003-08-28 2005-07-11 Advanced Semiconductor Eng Semiconductor chip package and method for making the same
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7030469B2 (en) * 2003-09-25 2006-04-18 Freescale Semiconductor, Inc. Method of forming a semiconductor package and structure thereof
US6943423B2 (en) * 2003-10-01 2005-09-13 Optopac, Inc. Electronic package of photo-image sensors in cellular phone camera modules, and the fabrication and assembly thereof
US7276724B2 (en) 2005-01-20 2007-10-02 Nanosolar, Inc. Series interconnected optoelectronic device module assembly
US7327015B2 (en) * 2004-09-20 2008-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP4453509B2 (en) 2004-10-05 2010-04-21 パナソニック株式会社 High-frequency module with shield case and electronic equipment using this high-frequency module
US7629674B1 (en) * 2004-11-17 2009-12-08 Amkor Technology, Inc. Shielded package having shield fence
JP2006190767A (en) 2005-01-05 2006-07-20 Shinko Electric Ind Co Ltd Semiconductor device
EP1860694A1 (en) 2005-03-16 2007-11-28 Yamaha Corporation Semiconductor device, semiconductor device manufacturing method and cover frame
JP4614278B2 (en) * 2005-05-25 2011-01-19 アルプス電気株式会社 Electronic circuit unit and manufacturing method thereof
US7451539B2 (en) * 2005-08-08 2008-11-18 Rf Micro Devices, Inc. Method of making a conformal electromagnetic interference shield
US7145084B1 (en) * 2005-08-30 2006-12-05 Freescale Semiconductor, Inc. Radiation shielded module and method of shielding microelectronic device
WO2007060784A1 (en) * 2005-11-28 2007-05-31 Murata Manufacturing Co., Ltd. Circuit module and method for fabricating the same
DE102005057891B4 (en) 2005-12-02 2007-10-18 Gkss-Forschungszentrum Geesthacht Gmbh Method and device for connecting a plastic workpiece with another workpiece
US7342303B1 (en) * 2006-02-28 2008-03-11 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
DE102006019080B3 (en) * 2006-04-25 2007-08-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Housing manufacturing method for e.g. infrared sensor, involves enclosing electrical circuit along metal frame, where circuit is isolated along isolating contour that does not cut surface of substrate
US20080128890A1 (en) 2006-11-30 2008-06-05 Advanced Semiconductor Engineering, Inc. Chip package and fabricating process thereof
TWI337399B (en) * 2007-01-26 2011-02-11 Advanced Semiconductor Eng Semiconductor package for electromagnetic shielding
KR101057368B1 (en) * 2007-01-31 2011-08-18 후지쯔 세미컨덕터 가부시키가이샤 Semiconductor device and manufacturing method thereof
US7576415B2 (en) * 2007-06-15 2009-08-18 Advanced Semiconductor Engineering, Inc. EMI shielded semiconductor package
US7745910B1 (en) * 2007-07-10 2010-06-29 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
US20090035895A1 (en) * 2007-07-30 2009-02-05 Advanced Semiconductor Engineering, Inc. Chip package and chip packaging process thereof
US8022511B2 (en) * 2008-02-05 2011-09-20 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8212339B2 (en) * 2008-02-05 2012-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US7989928B2 (en) * 2008-02-05 2011-08-02 Advanced Semiconductor Engineering Inc. Semiconductor device packages with electromagnetic interference shielding
US8350367B2 (en) * 2008-02-05 2013-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8120152B2 (en) * 2008-03-14 2012-02-21 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof
US7906371B2 (en) * 2008-05-28 2011-03-15 Stats Chippac, Ltd. Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield
TWI453877B (en) 2008-11-07 2014-09-21 Advanced Semiconductor Eng Structure and process of embedded chip package
US8410584B2 (en) * 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20100110656A1 (en) 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US20100207257A1 (en) * 2009-02-17 2010-08-19 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method thereof
US8110902B2 (en) * 2009-02-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8212340B2 (en) 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8368185B2 (en) 2009-11-19 2013-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8030750B2 (en) 2009-11-19 2011-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
TWI497679B (en) 2009-11-27 2015-08-21 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof

Patent Citations (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3390226A (en) * 1964-10-19 1968-06-25 Siemens Ag Encapsulated semiconductor element
US4049682A (en) * 1976-03-01 1977-09-20 International Flavors & Fragrances Inc. Processes for preparing enol esters
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4569786A (en) * 1983-04-12 1986-02-11 Ube Industries, Ltd. Electrically conductive thermoplastic resin composition containing metal and carbon fibers
US4814205A (en) * 1983-12-02 1989-03-21 Omi International Corporation Process for rejuvenation electroless nickel solution
US5104745A (en) * 1989-07-06 1992-04-14 Gec Alsthom Sa Multifilament superconductor strand having an anti-diffusion barrier layer
US5557142A (en) * 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5166772A (en) * 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
US5172077A (en) * 1991-04-27 1992-12-15 Murata Manufacturing Co., Ltd. Oscillator and method of manufacturing the same
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5355016A (en) * 1993-05-03 1994-10-11 Motorola, Inc. Shielded EPROM package
US6455864B1 (en) * 1994-04-01 2002-09-24 Maxwell Electronic Components Group, Inc. Methods and compositions for ionizing radiation shielding
US5600181A (en) * 1995-05-24 1997-02-04 Lockheed Martin Corporation Hermetically sealed high density multi-chip package
US5847930A (en) * 1995-10-13 1998-12-08 Hei, Inc. Edge terminals for electronic circuit modules
US5898344A (en) * 1996-03-14 1999-04-27 Tdk Corporation High-frequency module
US6079099A (en) * 1996-06-24 2000-06-27 Sumitomo Metal Industries Limited Electronic component manufacturing method
US6150193A (en) * 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US6093972A (en) * 1997-05-19 2000-07-25 Motorola, Inc. Microelectronic package including a polymer encapsulated die
US6225694B1 (en) * 1997-09-02 2001-05-01 Oki Electric Industry Co, Ltd. Semiconductor device
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6472598B1 (en) * 1998-08-28 2002-10-29 Amkor Technology, Inc. Electromagnetic interference shield device with conductive encapsulant and dam
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US6255143B1 (en) * 1999-08-04 2001-07-03 St. Assembly Test Services Pte Ltd. Flip chip thermally enhanced ball grid array
US6261680B1 (en) * 1999-12-07 2001-07-17 Hughes Electronics Corporation Electronic assembly with charge-dissipating transparent conformal coating
US6757181B1 (en) * 2000-08-22 2004-06-29 Skyworks Solutions, Inc. Molded shield structures and method for their fabrication
US6448632B1 (en) * 2000-08-28 2002-09-10 National Semiconductor Corporation Metal coated markings on integrated circuit devices
US6586822B1 (en) * 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US20020053724A1 (en) * 2000-09-13 2002-05-09 Siliconware Precision Industries Co., Ltd. Semiconductor package
US6926869B2 (en) * 2000-10-09 2005-08-09 Urea Casale S.A. Apparatus for carbamate decomposition and ammonia and carbon dioxide stripping from urea solutions capable of 180 degree inversion about a horizontal axis
US20020093108A1 (en) * 2001-01-15 2002-07-18 Grigorov Ilya L. Flip chip packaged semiconductor device having double stud bumps and method of forming same
US6472743B2 (en) * 2001-02-22 2002-10-29 Siliconware Precision Industries, Co., Ltd. Semiconductor package with heat dissipating structure
US7081661B2 (en) * 2001-03-16 2006-07-25 Matsushita Electric Industrial Co., Ltd. High-frequency module and method for manufacturing the same
US6900383B2 (en) * 2001-03-19 2005-05-31 Hewlett-Packard Development Company, L.P. Board-level EMI shield that adheres to and conforms with printed circuit board component and board surfaces
US20050029673A1 (en) * 2001-04-06 2005-02-10 Hitachi, Ltd. Multi-chip semiconductor device with specific chip arrangement
US6614102B1 (en) * 2001-05-04 2003-09-02 Amkor Technology, Inc. Shielded semiconductor leadframe package
US20050046001A1 (en) * 2001-08-28 2005-03-03 Tessera, Inc High-frequency chip packages
US6928719B2 (en) * 2001-12-07 2005-08-16 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter package
US7186928B2 (en) * 2002-08-01 2007-03-06 Nec Corporation Electronic device including chip parts and a method for manufacturing the same
US20040063242A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US7187060B2 (en) * 2003-03-13 2007-03-06 Sanyo Electric Co., Ltd. Semiconductor device with shield
US6867480B2 (en) * 2003-06-10 2005-03-15 Lsi Logic Corporation Electromagnetic interference package protection
US7045385B2 (en) * 2003-08-20 2006-05-16 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter packages and package sheet used therein
US7626974B2 (en) * 2003-11-24 2009-12-01 Telefonaktiebolaget Lm Ericsson (Publ) Frame synchronisation in a radio access network
US6992400B2 (en) * 2004-01-30 2006-01-31 Nokia Corporation Encapsulated electronics device with improved heat dissipation
US20080042301A1 (en) * 2005-01-05 2008-02-21 Integrated System Solution Advanced Semiconductor Semiconductor device package and manufacturing method
US7700411B2 (en) * 2005-01-05 2010-04-20 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method
US7633170B2 (en) * 2005-01-05 2009-12-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method thereof
US7446265B2 (en) * 2005-04-15 2008-11-04 Parker Hannifin Corporation Board level shielding module
US7643311B2 (en) * 2005-04-21 2010-01-05 Stmicroelectronics Sa Electronic circuit protection device
US7445968B2 (en) * 2005-12-16 2008-11-04 Sige Semiconductor (U.S.), Corp. Methods for integrated circuit module packaging and integrated circuit module packages
US20090002969A1 (en) * 2007-06-27 2009-01-01 Rf Micro Devices, Inc. Field barrier structures within a conformal shield
US20090000815A1 (en) * 2007-06-27 2009-01-01 Rf Micro Devices, Inc. Conformal shielding employing segment buildup
US20090000114A1 (en) * 2007-06-27 2009-01-01 Rf Micro Devices, Inc. Heat sink formed with conformal shield
US20090075428A1 (en) * 2007-09-13 2009-03-19 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090102033A1 (en) * 2007-10-18 2009-04-23 Elmos Advanced Packaging B.V. Integrated circuit package
US7772046B2 (en) * 2008-06-04 2010-08-10 Stats Chippac, Ltd. Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference
US7829981B2 (en) * 2008-07-21 2010-11-09 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US7741151B2 (en) * 2008-11-06 2010-06-22 Freescale Semiconductor, Inc. Integrated circuit package formation

Cited By (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090194851A1 (en) * 2008-02-05 2009-08-06 Chi-Tsung Chiu Semiconductor device packages with electromagnetic interference shielding
US8350367B2 (en) 2008-02-05 2013-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20100207259A1 (en) * 2008-02-05 2010-08-19 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8653633B2 (en) 2008-02-05 2014-02-18 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8212339B2 (en) 2008-02-05 2012-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US7989928B2 (en) 2008-02-05 2011-08-02 Advanced Semiconductor Engineering Inc. Semiconductor device packages with electromagnetic interference shielding
US8022511B2 (en) 2008-02-05 2011-09-20 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8410584B2 (en) 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20100032815A1 (en) * 2008-08-08 2010-02-11 An Jaeseon Semiconductor device packages with electromagnetic interference shielding
US8592958B2 (en) 2008-10-31 2013-11-26 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US20100109132A1 (en) * 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8093690B2 (en) 2008-10-31 2012-01-10 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US20100207257A1 (en) * 2009-02-17 2010-08-19 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method thereof
US8110902B2 (en) 2009-02-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8212340B2 (en) 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US20110115066A1 (en) * 2009-11-19 2011-05-19 Seokbong Kim Semiconductor device packages with electromagnetic interference shielding
US8368185B2 (en) 2009-11-19 2013-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8030750B2 (en) 2009-11-19 2011-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20110115059A1 (en) * 2009-11-19 2011-05-19 Yuyong Lee Semiconductor Device Packages with Electromagnetic Interference Shielding
US9196597B2 (en) 2010-01-13 2015-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8884424B2 (en) 2010-01-13 2014-11-11 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US20110304993A1 (en) * 2010-06-11 2011-12-15 Murata Manufacturing Co., Ltd. Circuit module
US8897028B2 (en) * 2010-06-11 2014-11-25 Murata Manufacturing Co., Ltd. Circuit module
CN102281707A (en) * 2010-06-11 2011-12-14 株式会社村田制作所 Circuit module
US9070793B2 (en) 2010-08-02 2015-06-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having electromagnetic interference shielding and related methods
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9226435B2 (en) * 2010-12-01 2015-12-29 Apple Inc. Printed circuit board with integral radio-frequency shields
US20140146495A1 (en) * 2010-12-01 2014-05-29 Apple Inc. Printed Circuit Board With Integral Radio-Frequency Shields
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US20120170162A1 (en) * 2011-01-05 2012-07-05 Siliconware Precision Industries Co., Ltd. Semiconductor package and fabrication method thereof
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8937376B2 (en) 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8704341B2 (en) 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
US8653634B2 (en) 2012-06-11 2014-02-18 Advanced Semiconductor Engineering, Inc. EMI-shielded semiconductor devices and methods of making
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US9837701B2 (en) 2013-03-04 2017-12-05 Advanced Semiconductor Engineering, Inc. Semiconductor package including antenna substrate and manufacturing method thereof
US11664580B2 (en) 2013-03-04 2023-05-30 Advanced Semiconductor Engineering, Inc. Semiconductor package including antenna substrate and manufacturing method thereof
US9129954B2 (en) 2013-03-07 2015-09-08 Advanced Semiconductor Engineering, Inc. Semiconductor package including antenna layer and manufacturing method thereof
US9172131B2 (en) 2013-03-15 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor structure having aperture antenna
US9711462B2 (en) 2013-05-08 2017-07-18 Infineon Technologies Ag Package arrangement including external block comprising semiconductor material and electrically conductive plastic material
US9236356B2 (en) 2013-07-31 2016-01-12 Advanced Semiconductor Engineering, Inc. Semiconductor package with grounding and shielding layers
US9101050B2 (en) * 2013-08-13 2015-08-04 Taiyo Yuden Co., Ltd. Circuit module having electrical shield
US20150070849A1 (en) * 2013-09-12 2015-03-12 Taiyo Yuden Co., Ltd. Circuit module and method of producing circuit module
US9456488B2 (en) * 2013-09-12 2016-09-27 Taiyo Yuden Co., Ltd. Circuit module and method of producing circuit module
US20180083416A1 (en) * 2013-11-11 2018-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Method of Forming Chip Package with Waveguide for Light Coupling
US10135224B2 (en) * 2013-11-11 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method of forming chip package with waveguide for light coupling having a molding layer for a laser die
US20150179481A1 (en) * 2013-12-23 2015-06-25 Stats Chippac, Ltd. Semiconductor Device and Method of Making Embedded Wafer Level Chip Scale Packages
US10242887B2 (en) 2013-12-23 2019-03-26 STATS ChipPAC Pte. Ltd. Semiconductor device and method of making embedded wafer level chip scale packages
US9768038B2 (en) * 2013-12-23 2017-09-19 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of making embedded wafer level chip scale packages
US9490219B2 (en) * 2014-05-16 2016-11-08 Siliconware Precision Industries Co., Ltd. Semiconductor package with shielding member and method of manufacturing the same
US9754897B2 (en) * 2014-06-02 2017-09-05 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits
US20150348936A1 (en) * 2014-06-02 2015-12-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Electromagnetic (EM) Shielding for LC Circuits
US10388612B2 (en) 2014-06-02 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits
US9437576B1 (en) * 2015-03-23 2016-09-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US9553072B2 (en) 2015-03-23 2017-01-24 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
TWI562323B (en) * 2015-03-23 2016-12-11 Advanced Semiconductor Eng Semiconductor device package and method of manufacturing the same
US9842809B2 (en) 2015-08-10 2017-12-12 SK Hynix Inc. Semiconductor packages having EMI shielding parts and methods of fabricating the same
TWI710084B (en) * 2015-08-10 2020-11-11 南韓商愛思開海力士有限公司 Semiconductor packages having emi shielding parts and methods of fabricating the same
US9893020B2 (en) * 2015-09-09 2018-02-13 Samsung Electronics Co., Ltd. Semiconductor device
US20170069828A1 (en) * 2015-09-09 2017-03-09 Samsung Electronics Co., Ltd. Semiconductor device
US11139252B2 (en) * 2018-05-11 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
US10790239B2 (en) * 2018-09-12 2020-09-29 Samsung Electronics Co., Ltd. Semiconductor package and board for mounting the same
CN113380768A (en) * 2020-03-09 2021-09-10 南茂科技股份有限公司 Chip packaging structure and manufacturing method thereof

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