US20100327442A1 - Package and the Method for Making the Same, and a Stacked Package - Google Patents

Package and the Method for Making the Same, and a Stacked Package Download PDF

Info

Publication number
US20100327442A1
US20100327442A1 US12/876,907 US87690710A US2010327442A1 US 20100327442 A1 US20100327442 A1 US 20100327442A1 US 87690710 A US87690710 A US 87690710A US 2010327442 A1 US2010327442 A1 US 2010327442A1
Authority
US
United States
Prior art keywords
circuit layer
molding compound
package
disposed
dice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/876,907
Inventor
Meng-Jen Wang
Wei-Chung Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US12/876,907 priority Critical patent/US20100327442A1/en
Publication of US20100327442A1 publication Critical patent/US20100327442A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Definitions

  • the present invention relates to a package and the method for making the same, and more particularly to a package and the method for making the same, and a stacked package.
  • a conventional method for making a stacked package a plurality of die elements are formed on a wafer first, then two or more than two wafers are stacked, and a cutting process is performed so as to form a plurality of stacked package.
  • the conventional method has a disadvantage, which is that the die elements on the wafer are not tested. Therefore, the stacked packages formed as described above have the problem of high defective fraction. Especially, if more wafers are stacked, more defective fraction will occur.
  • Another conventional method is provided. First, the die elements on the wafer are cut off, and then stacked after being tested.
  • the method's disadvantage is that it is hard to align the die elements during the stacking process, which results in a shift between the corresponding upper and lower die elements.
  • the present invention is directed to a method for making a package.
  • the method comprises the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice; and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned during the reflow process, a die attach machine with high accuracy is unnecessary. That is, a die attach machine with low accuracy can achieve highly accurate placement, so the cost of the die attach machine is reduced.
  • FIGS. 1 to 10 are schematic views of a method for making a package according to the present invention.
  • FIGS. 11 to 23 are schematic views of a method for making a stacked package according to the present invention.
  • FIGS. 1 to 10 show the schematic views of the method for making the package according to the present invention.
  • a carrier 1 is provided.
  • the carrier 1 has a plurality of platforms 10 .
  • the carrier 1 is a silicon wafer, and each of the platforms 10 comprises a solder layer 11 and a pad 12 .
  • the pad 12 is disposed between the solder layer 11 and the carrier 1 , and the material of the pad 12 is preferably metal.
  • a flux 13 is formed on the platforms 10 and the carrier 1 .
  • a plurality of dice 2 are provided, and disposed on the platforms 10 , that is, on the flux 13 .
  • the dice 2 are tested and are known good dice.
  • Each of the dice 2 comprises a first surface 21 and a second surface 22 .
  • the second surface 22 faces the platforms 10 , and the second surface 22 further comprises a wettable layer 23 .
  • the first surface 21 further comprises a plurality of ball pads 24 .
  • a reflow process is performed so that the dice 2 are self-aligned on the platforms 10 . This is because that the solder layer 11 has surface tension during the reflow process, which makes the dice 2 on the solder layer 11 able to self-align.
  • the carrier 1 further has a plurality of grooves 15 disposed between the platforms 10 .
  • the grooves 15 are filled with the molding compound 14 so as to increase the combination between the molding compound 14 and the carrier 1 , as shown in FIG. 7 .
  • a circuit layer 16 is formed on the molding compound 14 , and the circuit layer 16 electrically connects the dice 2 .
  • the circuit layer 16 comprises a redistribution layer 161 , and the redistribution layer 161 connects the ball pads 24 .
  • a plurality of solder balls 17 are further formed on the circuit layer 16 . The solder balls 17 connect the redistribution layer 161 , and further electrically connect the ball pads 24 .
  • FIG. 9 the carrier 1 is removed.
  • FIG. 10 a cutting process is performed so as to form a plurality of package 3 . It should be noted that the cutting process may be performed without removing the carrier 1 , so the packages 3 may include the carrier 1 .
  • the pads 12 are formed on the carrier 1 by a photo-lithography process, and the solder layer 11 is formed on the pads 12 by electroplating, so that highly accurate placement can be achieved.
  • the dice 4 can be self-aligned during the reflow process, so a die attach machine with high accuracy is unnecessary. That is, in the embodiment, a die attach machine with low accuracy can achieve highly accurate placement, so the cost of the die attach machine is reduced.
  • FIG. 10 shows the schematic view of a package of the present invention.
  • the package 3 comprises a molding compound 14 , a platform 10 , a die 2 , a wettable layer 23 and a circuit layer 16 .
  • the molding compound 14 has a first surface 141 , a second surface 142 and an accommodating groove 143 .
  • the accommodating groove 143 penetrates the molding compound 14 .
  • the platform 10 is disposed in the accommodating groove 143 and exposed to the second surface 142 of the molding compound 14 .
  • the platform 10 comprises a solder layer 11 and a pad 12 .
  • the solder layer 11 is disposed between the pad 12 and the wettable layer 23 .
  • the material of the pad 12 is metal.
  • the die 2 is disposed in the accommodating groove 143 , and has a first surface 21 and a second surface 22 .
  • the first surface 21 of the die 2 is exposed to the first surface 141 of the molding compound 14 .
  • the first surface 21 of the die 2 further comprises a plurality of ball pads 24 .
  • the wettable layer 23 is disposed on the second surface 22 of the die 2 , and connects the solder layer 11 of the platform 10 .
  • the circuit layer 16 is disposed on the first surface 141 of the molding compound 14 , and the circuit layer 16 electrically connects the first surface 21 of the die 2 .
  • the circuit layer 16 comprises a redistribution layer 161 , and the redistribution layer 161 connects the ball pads 24 .
  • the circuit layer 16 further comprises a plurality of solder balls 17 .
  • the solder balls 17 connect the redistribution layer 161 , and further electrically connect the ball pads 24 .
  • the package 3 further comprises a carrier (not shown) disposed on the second surface 142 of the molding compound 14 .
  • FIGS. 11 to 23 show the schematic views of the method for making the stacked package according to the present invention.
  • a first carrier 4 is provided.
  • the first carrier 4 has a plurality of first platforms 40 .
  • the first carrier 4 is a silicon wafer, and each of the first platforms 40 comprises a first solder layer 41 and a first pad 42 .
  • the first pads 42 is disposed between the first solder layer 41 and the first carrier 4 .
  • a first flux 43 is formed on the first platforms 40 and the first carrier 4 .
  • a plurality of first dice 5 are provided.
  • the first dice 5 are disposed on the first platform 40 , that is, on the first flux 43 .
  • the first dice 5 are tested and are known good dice.
  • Each of the first dice 5 comprises a first surface 51 , a second surface 52 and at least one first via 55 .
  • the second surface 52 faces the first platform 40 , and the second surface 52 further comprises a first wettable layer 53 .
  • the first surface 51 further comprises a plurality of first ball pads 54 .
  • the first vias 55 comprises a conductive metal therein, and the material of the conductive metal may be the same as or different from that of the first wettable layer 53 .
  • a reflow process is performed so that the first dice 5 are self-aligned on the first platforms 40 . Afterward, the first flux 43 is removed.
  • a first molding compound 44 is formed in the gaps between the first dice 5 , and the first ball pads 54 are exposed.
  • the first carrier 4 , part of the first molding compound 44 , the first solder layer 41 , the first pad 42 and the first wettable layer 53 are removed so as to expose the first via 55 , and the first molding compound 44 has a first surface 441 and a second surface 442 .
  • a first upper circuit layer 46 and a first lower circuit layer 47 are formed on the second surface 442 and the first surface 441 of the first molding compound 44 respectively, so as to form a first package 9 A.
  • the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first vias 55 and the first ball pads 54 , so as to form a plurality of first package elements 6 A.
  • the first upper circuit layer 46 comprises a first upper redistribution layer 461
  • the first lower circuit layer 47 comprises a first lower redistribution layer 471 .
  • the first package 9 A comprises a first molding compound 44 , a plurality of first dice 5 , a first upper circuit layer 46 and a first lower circuit layer 47 .
  • the first molding compound 44 has a first surface 441 , a second surface 442 and a plurality of first accommodating grooves 443 .
  • the first accommodating grooves 443 penetrate the first molding compound 44 .
  • the first dice 5 are disposed in the first accommodating grooves 443 , and each of the first dice 5 has a first surface 51 , a second surface 52 and at least one first via 55 .
  • the first surfaces 51 of the first dice 5 are exposed to the first surface 441 of the first molding compound 44
  • the second surfaces 52 of the first dice 5 are exposed to the second surface 442 of the first molding compound 44 .
  • the first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44 .
  • the first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44 .
  • the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55 .
  • the first package 9 A further comprises a plurality of first ball pads 54 disposed on the first surfaces 51 of the first dice 5 .
  • a plurality of first solder balls 48 are further formed on the first lower circuit layer 47 , and connect the first lower redistribution layer 471 .
  • the first package elements 6 A will become a singulated package, and comprises a first molding compound 44 , a first die 5 , a first upper circuit layer 46 and a first lower circuit layer 47 .
  • the first molding compound 44 has a first surface 441 , a second surface 442 and a first accommodating groove 443 .
  • the first accommodating groove 443 penetrates the first molding compound 44 .
  • the first die 5 is disposed in the first accommodating groove 443 , and has a first surface 51 , a second surface 52 and at least one first via 55 .
  • the first surface 51 of the first die 5 is exposed to the first surface 441 of the first molding compound 44
  • the second surface 52 of the first die 5 is exposed to the second surface 442 of the first molding compound 44 .
  • the first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44 .
  • the first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44 .
  • the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55 .
  • the package further comprises a plurality of first ball pads 54 disposed on the first surface 51 of the first die 5 .
  • a plurality of first solder balls 48 are further formed on the first lower circuit layer 47 , and connect the first lower redistribution layer 471 .
  • the second package element may be a package of any type.
  • the second package element is substantially the same as the first package element 6 A, and the method for making the second package is described as below.
  • a second carrier 7 is provided.
  • the second carrier 7 has a plurality of second platforms 70 .
  • the second carrier 7 is a silicon wafer, and each of the second platforms 70 comprises a second solder layer 71 and a second pad 72 .
  • the second pad 72 is disposed between the second solder layer 71 and the second carrier 7 .
  • a second flux (not shown) is formed on the second platforms 70 and the second carrier 7 .
  • a plurality of second dice 8 are provided, and disposed on the second platforms 70 , that is, on the second flux.
  • the function or size of the second dice 8 may be the same as or different from that of the first dice 5 .
  • the second dice 8 are tested and are known good dice.
  • Each of the second dice 8 comprises a first surface 81 , a second surface 82 and at least one second via 85 .
  • the second surface 82 faces the second platforms 70 , and the second surface 82 further comprises a second wettable layer 83 .
  • the first surface 81 further comprises a plurality of second ball pads 84 .
  • the second via 85 comprises a conductive metal, and the material of the conductive metal may be the same as or different from that of the second wettable layer 83 . Afterward, a reflow process is performed so that the second dice 8 are self-aligned on the second platforms 70 . Afterward, the second flux is removed.
  • a second molding compound 74 is formed in the gaps between the second dice 8 , and the second ball pads 84 are exposed. Afterward, the second carrier 7 , part of the second molding compound 74 , the second solder layer 71 , the second pad 72 and the second wettable 83 are removed so as to expose the second via 85 , and the second molding compound 74 has a first surface 741 and a second surface 742 .
  • a second upper circuit layer 76 and a second lower circuit layer 77 are formed on the second surface 742 and the first surface 741 of the second molding compound 74 respectively, so as to form a second package 9 B.
  • the second upper circuit layer 76 is electrically connected to the second lower circuit layer 77 by the second vias 85 and the second ball pads 84 so as to form a plurality of second package elements 6 B.
  • the second upper circuit layer 76 comprises a second upper redistribution layer 761
  • the second lower circuit layer 77 comprises a second lower redistribution 771 .
  • the second package 9 B comprises a second molding compound 74 , a plurality of second dice 8 , a second upper circuit layer 76 and a second lower circuit layer 77 .
  • the second molding compound 74 has a first surface 741 , a second surface 742 and a plurality of second accommodating grooves 743 .
  • the second accommodating grooves 743 penetrate the second molding compound 74 .
  • the second dice 8 are disposed in the second accommodating grooves 743 , and each of the second dice 8 has a first surface 81 , a second surface 82 and at least one second via 85 .
  • the first surfaces 81 of the second dice 8 are exposed to the first surface 741 of the second molding compound 74
  • the second surfaces 82 of the second dice 8 are exposed to the second surface 742 of the second molding compound 74 .
  • the second upper circuit layer 76 is disposed on the second surface 742 of the second molding compound 74 .
  • the second lower circuit layer 77 is disposed on the first surface 441 of the second molding compound 74 .
  • the second upper circuit layer 76 is electrically connected to the second lower circuit layer 77 by the second via 85 .
  • the first package 9 B further comprises a plurality of second ball pads 84 disposed on the first surfaces 81 of the second dice 8 .
  • a plurality of second solder balls 78 are further formed on the second lower circuit layer 77 , and connect the second lower redistribution 771 .
  • the first package 9 A and the second package 9 B are stacked, and the first package element 6 A and the second package element 6 B are stacked, so as to form a stacked package 9 C. It is understood that other package element may be further stacked on the second package 9 B or the second package element 6 B.
  • the second lower circuit layer 77 of the second package 9 B is electrically connected to the first upper circuit layer 46 of the first package 9 A, preferably, by the second solder balls 78 .
  • a cutting process is performed so as to form a plurality of stacked package 9 .
  • FIG. 23 shows the schematic view of the stacked package after cutting process of the present invention.
  • the stacked package 9 comprises a first package element 6 A and a second package element 6 B.
  • the first package element 6 A comprises a first molding compound 44 , a first die 5 , a first upper circuit layer 46 and a first lower circuit layer 47 .
  • the first molding compound 44 has a first surface 441 , a second surface 442 and a first accommodating groove 443 .
  • the first accommodating groove 443 penetrates the first molding compound 44 .
  • the first die 5 is disposed in the first accommodating groove 443 , and has a first surface 51 , a second surface 52 and at least one first via 55 .
  • the first surface 51 of the first die 5 is exposed to the first surface 441 of the first molding compound 44
  • the second surface 52 of the first die 5 is exposed to the second surface 442 of the first molding compound 44 .
  • the first surface 51 of the first die 5 further comprises a plurality of first ball pads 54 .
  • the first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44 .
  • the first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44 .
  • the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55 .
  • the first lower circuit layer 47 further comprises a plurality of first solder balls 48 .
  • the second package element 6 B is stacked on the first package element 6 A, and electrically connected to the first upper circuit layer 46 .
  • the second package element 6 B comprises a second molding compound 74 , a second die 8 , a second upper circuit layer 76 and a second lower circuit layer 77 .
  • the second molding compound 74 has a first surface 741 , a second surface 742 and a second accommodating groove 743 .
  • the second accommodating groove 743 penetrates the second molding compound 74 .
  • the function or size of the second die 8 may be the same as or different from that of the first die 5 .
  • the second die 8 is disposed in the second accommodating 743 , and has a first surface 81 , a second surface 82 and at least one second via 85 .
  • the first surface 81 of the second die 8 is exposed to the first surface 841 of the second molding compound 84
  • the second surface 82 of the second die 8 is exposed to the second surface 842 of the second molding compound 84 .
  • the first surface 81 of the second die 8 further comprises a plurality of second ball pads 84 .
  • the first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44 .
  • the first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44 .
  • the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55 .
  • the second lower circuit layer 77 further comprises a plurality of second solder balls 78 .
  • the second lower circuit layer 77 is electrically connected to the first upper circuit layer 46 by the second solder balls 78 .
  • the dice are tested and are known good dice, and stacked with highly accurate placement, so the yield rate is raised. Moreover, dice with different sizes can be stacked in the embodiment, so the flexibility of layout is increased.

Abstract

The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This is a divisional of U.S. application Ser. No. 12/185,879, filed Aug. 5, 2008, and claims priority to Taiwanese Patent No. 096129098, filed Aug. 7, 2007, each of which is incorporated by reference herein.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a package and the method for making the same, and more particularly to a package and the method for making the same, and a stacked package.
  • 2. Description of the Related Art
  • In a conventional method for making a stacked package, a plurality of die elements are formed on a wafer first, then two or more than two wafers are stacked, and a cutting process is performed so as to form a plurality of stacked package. The conventional method has a disadvantage, which is that the die elements on the wafer are not tested. Therefore, the stacked packages formed as described above have the problem of high defective fraction. Especially, if more wafers are stacked, more defective fraction will occur.
  • In order to eliminate the above-mentioned disadvantage, another conventional method is provided. First, the die elements on the wafer are cut off, and then stacked after being tested. The method's disadvantage is that it is hard to align the die elements during the stacking process, which results in a shift between the corresponding upper and lower die elements.
  • Therefore, it is necessary to provide a package and the method for making the same, and a stacked package to solve the above problems.
    • SUMMARY OF THE INVENTION
  • The present invention is directed to a method for making a package. The method comprises the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice; and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned during the reflow process, a die attach machine with high accuracy is unnecessary. That is, a die attach machine with low accuracy can achieve highly accurate placement, so the cost of the die attach machine is reduced.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1 to 10 are schematic views of a method for making a package according to the present invention; and
  • FIGS. 11 to 23 are schematic views of a method for making a stacked package according to the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIGS. 1 to 10 show the schematic views of the method for making the package according to the present invention. First, as shown in FIG. 1, a carrier 1 is provided. The carrier 1 has a plurality of platforms 10. In the embodiment, the carrier 1 is a silicon wafer, and each of the platforms 10 comprises a solder layer 11 and a pad 12. The pad 12 is disposed between the solder layer 11 and the carrier 1, and the material of the pad 12 is preferably metal.
  • As shown in FIG. 2, a flux 13 is formed on the platforms 10 and the carrier 1.
  • As shown in FIG. 3, a plurality of dice 2 are provided, and disposed on the platforms 10, that is, on the flux 13. In the embodiment, the dice 2 are tested and are known good dice. Each of the dice 2 comprises a first surface 21 and a second surface 22. The second surface 22 faces the platforms 10, and the second surface 22 further comprises a wettable layer 23. The first surface 21 further comprises a plurality of ball pads 24.
  • As shown in FIG. 4, a reflow process is performed so that the dice 2 are self-aligned on the platforms 10. This is because that the solder layer 11 has surface tension during the reflow process, which makes the dice 2 on the solder layer 11 able to self-align.
  • As shown in FIG. 5, the flux 13 is removed. Afterward, as shown in FIG. 6, a molding compound 14 is formed in the gaps between the dice 2, and the ball pads 24 are exposed. Preferably, in another embodiment, the carrier 1 further has a plurality of grooves 15 disposed between the platforms 10. The grooves 15 are filled with the molding compound 14 so as to increase the combination between the molding compound 14 and the carrier 1, as shown in FIG. 7.
  • As shown in FIG. 8, a circuit layer 16 is formed on the molding compound 14, and the circuit layer 16 electrically connects the dice 2. In the embodiment, the circuit layer 16 comprises a redistribution layer 161, and the redistribution layer 161 connects the ball pads 24. Preferably, a plurality of solder balls 17 are further formed on the circuit layer 16. The solder balls 17 connect the redistribution layer 161, and further electrically connect the ball pads 24.
  • In FIG. 9, the carrier 1 is removed. Finally, in FIG. 10, a cutting process is performed so as to form a plurality of package 3. It should be noted that the cutting process may be performed without removing the carrier 1, so the packages 3 may include the carrier 1.
  • In the embodiment, the pads 12 are formed on the carrier 1 by a photo-lithography process, and the solder layer 11 is formed on the pads 12 by electroplating, so that highly accurate placement can be achieved. Moreover, the dice 4 can be self-aligned during the reflow process, so a die attach machine with high accuracy is unnecessary. That is, in the embodiment, a die attach machine with low accuracy can achieve highly accurate placement, so the cost of the die attach machine is reduced.
  • FIG. 10 shows the schematic view of a package of the present invention. The package 3 comprises a molding compound 14, a platform 10, a die 2, a wettable layer 23 and a circuit layer 16.
  • The molding compound 14 has a first surface 141, a second surface 142 and an accommodating groove 143. The accommodating groove 143 penetrates the molding compound 14. The platform 10 is disposed in the accommodating groove 143 and exposed to the second surface 142 of the molding compound 14. In the embodiment, the platform 10 comprises a solder layer 11 and a pad 12. The solder layer 11 is disposed between the pad 12 and the wettable layer 23. The material of the pad 12 is metal.
  • The die 2 is disposed in the accommodating groove 143, and has a first surface 21 and a second surface 22. The first surface 21 of the die 2 is exposed to the first surface 141 of the molding compound 14. Preferably, the first surface 21 of the die 2 further comprises a plurality of ball pads 24.
  • The wettable layer 23 is disposed on the second surface 22 of the die 2, and connects the solder layer 11 of the platform 10. The circuit layer 16 is disposed on the first surface 141 of the molding compound 14, and the circuit layer 16 electrically connects the first surface 21 of the die 2. In the embodiment, the circuit layer 16 comprises a redistribution layer 161, and the redistribution layer 161 connects the ball pads 24. Preferably, the circuit layer 16 further comprises a plurality of solder balls 17. The solder balls 17 connect the redistribution layer 161, and further electrically connect the ball pads 24. In another embodiment, the package 3 further comprises a carrier (not shown) disposed on the second surface 142 of the molding compound 14.
  • FIGS. 11 to 23 show the schematic views of the method for making the stacked package according to the present invention. First, as shown in FIG. 11, a first carrier 4 is provided. The first carrier 4 has a plurality of first platforms 40. In the embodiment, the first carrier 4 is a silicon wafer, and each of the first platforms 40 comprises a first solder layer 41 and a first pad 42. The first pads 42 is disposed between the first solder layer 41 and the first carrier 4.
  • As shown in FIG. 12, a first flux 43 is formed on the first platforms 40 and the first carrier 4.
  • As shown in FIG. 13, a plurality of first dice 5 are provided. The first dice 5 are disposed on the first platform 40, that is, on the first flux 43. In the embodiment, the first dice 5 are tested and are known good dice. Each of the first dice 5 comprises a first surface 51, a second surface 52 and at least one first via 55. The second surface 52 faces the first platform 40, and the second surface 52 further comprises a first wettable layer 53. The first surface 51 further comprises a plurality of first ball pads 54. The first vias 55 comprises a conductive metal therein, and the material of the conductive metal may be the same as or different from that of the first wettable layer 53.
  • As shown in FIG. 14, a reflow process is performed so that the first dice 5 are self-aligned on the first platforms 40. Afterward, the first flux 43 is removed.
  • As shown in FIG. 15, a first molding compound 44 is formed in the gaps between the first dice 5, and the first ball pads 54 are exposed.
  • As shown in FIG. 16, the first carrier 4, part of the first molding compound 44, the first solder layer 41, the first pad 42 and the first wettable layer 53 are removed so as to expose the first via 55, and the first molding compound 44 has a first surface 441 and a second surface 442.
  • As shown in FIG. 17, a first upper circuit layer 46 and a first lower circuit layer 47 are formed on the second surface 442 and the first surface 441 of the first molding compound 44 respectively, so as to form a first package 9A. In the first package 9A, the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first vias 55 and the first ball pads 54, so as to form a plurality of first package elements 6A. In the embodiment, the first upper circuit layer 46 comprises a first upper redistribution layer 461, and the first lower circuit layer 47 comprises a first lower redistribution layer 471.
  • The first package 9A comprises a first molding compound 44, a plurality of first dice 5, a first upper circuit layer 46 and a first lower circuit layer 47. The first molding compound 44 has a first surface 441, a second surface 442 and a plurality of first accommodating grooves 443. The first accommodating grooves 443 penetrate the first molding compound 44. The first dice 5 are disposed in the first accommodating grooves 443, and each of the first dice 5 has a first surface 51, a second surface 52 and at least one first via 55. The first surfaces 51 of the first dice 5 are exposed to the first surface 441 of the first molding compound 44, and the second surfaces 52 of the first dice 5 are exposed to the second surface 442 of the first molding compound 44.
  • The first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44. The first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44. The first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55. Preferably, the first package 9A further comprises a plurality of first ball pads 54 disposed on the first surfaces 51 of the first dice 5. Preferably, a plurality of first solder balls 48 are further formed on the first lower circuit layer 47, and connect the first lower redistribution layer 471.
  • In other embodiment, if the first package 9A undergoes a cutting process, the first package elements 6A will become a singulated package, and comprises a first molding compound 44, a first die 5, a first upper circuit layer 46 and a first lower circuit layer 47. The first molding compound 44 has a first surface 441, a second surface 442 and a first accommodating groove 443. The first accommodating groove 443 penetrates the first molding compound 44. The first die 5 is disposed in the first accommodating groove 443, and has a first surface 51, a second surface 52 and at least one first via 55. The first surface 51 of the first die 5 is exposed to the first surface 441 of the first molding compound 44, and the second surface 52 of the first die 5 is exposed to the second surface 442 of the first molding compound 44.
  • The first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44. The first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44. The first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55. Preferably, the package further comprises a plurality of first ball pads 54 disposed on the first surface 51 of the first die 5. Preferably, a plurality of first solder balls 48 are further formed on the first lower circuit layer 47, and connect the first lower redistribution layer 471.
  • Afterward, a second package element is provided. The second package element may be a package of any type. In the embodiment, the second package element is substantially the same as the first package element 6A, and the method for making the second package is described as below.
  • First, as shown in FIG. 18, a second carrier 7 is provided. The second carrier 7 has a plurality of second platforms 70. In the embodiment, the second carrier 7 is a silicon wafer, and each of the second platforms 70 comprises a second solder layer 71 and a second pad 72. The second pad 72 is disposed between the second solder layer 71 and the second carrier 7.
  • Afterward, a second flux (not shown) is formed on the second platforms 70 and the second carrier 7.
  • As shown in FIG. 19, a plurality of second dice 8 are provided, and disposed on the second platforms 70, that is, on the second flux. The function or size of the second dice 8 may be the same as or different from that of the first dice 5. In the embodiment, the second dice 8 are tested and are known good dice. Each of the second dice 8 comprises a first surface 81, a second surface 82 and at least one second via 85. The second surface 82 faces the second platforms 70, and the second surface 82 further comprises a second wettable layer 83. The first surface 81 further comprises a plurality of second ball pads 84. The second via 85 comprises a conductive metal, and the material of the conductive metal may be the same as or different from that of the second wettable layer 83. Afterward, a reflow process is performed so that the second dice 8 are self-aligned on the second platforms 70. Afterward, the second flux is removed.
  • As shown in FIG. 20, a second molding compound 74 is formed in the gaps between the second dice 8, and the second ball pads 84 are exposed. Afterward, the second carrier 7, part of the second molding compound 74, the second solder layer 71, the second pad 72 and the second wettable 83 are removed so as to expose the second via 85, and the second molding compound 74 has a first surface 741 and a second surface 742.
  • As shown in FIG. 21, a second upper circuit layer 76 and a second lower circuit layer 77 are formed on the second surface 742 and the first surface 741 of the second molding compound 74 respectively, so as to form a second package 9B. In the second package 9B, the second upper circuit layer 76 is electrically connected to the second lower circuit layer 77 by the second vias 85 and the second ball pads 84 so as to form a plurality of second package elements 6B. In the embodiment, the second upper circuit layer 76 comprises a second upper redistribution layer 761, the second lower circuit layer 77 comprises a second lower redistribution 771.
  • The second package 9B comprises a second molding compound 74, a plurality of second dice 8, a second upper circuit layer 76 and a second lower circuit layer 77. The second molding compound 74 has a first surface 741, a second surface 742 and a plurality of second accommodating grooves 743. The second accommodating grooves 743 penetrate the second molding compound 74. The second dice 8 are disposed in the second accommodating grooves 743, and each of the second dice 8 has a first surface 81, a second surface 82 and at least one second via 85. The first surfaces 81 of the second dice 8 are exposed to the first surface 741 of the second molding compound 74, and the second surfaces 82 of the second dice 8 are exposed to the second surface 742 of the second molding compound 74.
  • The second upper circuit layer 76 is disposed on the second surface 742 of the second molding compound 74. The second lower circuit layer 77 is disposed on the first surface 441 of the second molding compound 74. The second upper circuit layer 76 is electrically connected to the second lower circuit layer 77 by the second via 85. Preferably, the first package 9B further comprises a plurality of second ball pads 84 disposed on the first surfaces 81 of the second dice 8. Preferably, a plurality of second solder balls 78 are further formed on the second lower circuit layer 77, and connect the second lower redistribution 771.
  • As shown in FIG. 22, the first package 9A and the second package 9B are stacked, and the first package element 6A and the second package element 6B are stacked, so as to form a stacked package 9C. It is understood that other package element may be further stacked on the second package 9B or the second package element 6B. In the stacked package 9C, the second lower circuit layer 77 of the second package 9B is electrically connected to the first upper circuit layer 46 of the first package 9A, preferably, by the second solder balls 78. Afterward, as shown in FIG. 23, a cutting process is performed so as to form a plurality of stacked package 9.
  • FIG. 23 shows the schematic view of the stacked package after cutting process of the present invention. The stacked package 9 comprises a first package element 6A and a second package element 6B.
  • The first package element 6A comprises a first molding compound 44, a first die 5, a first upper circuit layer 46 and a first lower circuit layer 47.
  • The first molding compound 44 has a first surface 441, a second surface 442 and a first accommodating groove 443. The first accommodating groove 443 penetrates the first molding compound 44. The first die 5 is disposed in the first accommodating groove 443, and has a first surface 51, a second surface 52 and at least one first via 55. The first surface 51 of the first die 5 is exposed to the first surface 441 of the first molding compound 44, and the second surface 52 of the first die 5 is exposed to the second surface 442 of the first molding compound 44. Preferably, the first surface 51 of the first die 5 further comprises a plurality of first ball pads 54.
  • The first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44. The first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44. The first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55. Preferably, the first lower circuit layer 47 further comprises a plurality of first solder balls 48.
  • The second package element 6B is stacked on the first package element 6A, and electrically connected to the first upper circuit layer 46.
  • The second package element 6B comprises a second molding compound 74, a second die 8, a second upper circuit layer 76 and a second lower circuit layer 77.
  • The second molding compound 74 has a first surface 741, a second surface 742 and a second accommodating groove 743. The second accommodating groove 743 penetrates the second molding compound 74. The function or size of the second die 8 may be the same as or different from that of the first die 5. The second die 8 is disposed in the second accommodating 743, and has a first surface 81, a second surface 82 and at least one second via 85. The first surface 81 of the second die 8 is exposed to the first surface 841 of the second molding compound 84, and the second surface 82 of the second die 8 is exposed to the second surface 842 of the second molding compound 84. Preferably, the first surface 81 of the second die 8 further comprises a plurality of second ball pads 84.
  • The first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44. The first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44. The first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55. Preferably, the second lower circuit layer 77 further comprises a plurality of second solder balls 78. The second lower circuit layer 77 is electrically connected to the first upper circuit layer 46 by the second solder balls 78.
  • In the embodiment, the dice are tested and are known good dice, and stacked with highly accurate placement, so the yield rate is raised. Moreover, dice with different sizes can be stacked in the embodiment, so the flexibility of layout is increased.
  • While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined in the appended claims.

Claims (16)

1. A stacked package, comprising:
a first package element, comprising:
a first molding compound, having a first surface, a second surface and a first accommodating groove, wherein the first accommodating groove penetrates the first molding compound;
a first die, disposed in the first accommodating groove and having a first surface, a second surface and at least one first via, wherein the first surface of the first die is exposed to the first surface of the first molding compound, the second surface of the first die is exposed to the second surface of the first molding compound;
a first upper circuit layer, disposed on the second surface of the first molding compound; and
a first lower circuit layer, disposed on the first surface of the first molding compound, and the first upper circuit layer electrically connected to the first lower circuit layer by the first via; and
a second package element, stacked on the first package element, and electrically connected to the first upper circuit layer.
2. The stacked package as claimed in claim 1, wherein the first die further comprises a plurality of first ball pads disposed on the first surface of the first die.
3. The stacked package as claimed in claim 1, further comprising a plurality of first solder balls disposed on the first lower circuit layer.
4. The stacked package as claimed in claim 1, wherein the second package element comprises:
a second molding compound, having a first surface, a second surface and a second accommodating groove, wherein the second accommodating groove penetrates the second molding compound;
a second die, disposed in the second accommodating groove and having a first surface, a second surface and at least one second via, wherein the first surface of the second die is exposed to the first surface of the second molding compound, and the second surface of the second die is exposed to the second surface of the second molding compound;
a second upper circuit layer, disposed on the second surface of the second molding compound; and
a second lower circuit layer, disposed on the first surface of the second molding compound, and the second upper circuit layer electrically connected to the second lower circuit layer by the second via, and the second lower circuit layer electrically connected to the first upper circuit layer.
5. The stacked package as claimed in claim 4, wherein the second die further comprises a plurality of second ball pads disposed on the first surface of the second die.
6. The stacked package as claimed in claim 4, further comprising a plurality of second solder balls disposed on the second lower circuit layer and connecting the first upper circuit layer.
7. The stacked package as claimed in claim 1, wherein the first upper circuit layer comprises a first upper redistribution layer and the first lower circuit layer comprises a first lower redistribution layer.
8. The stacked package as claimed in claim 4, wherein the second upper circuit layer comprises a second upper redistribution layer and the second lower circuit layer comprises a second lower redistribution layer.
9. A package, comprising:
a first molding compound, having a first surface, a second surface and a plurality of first accommodating grooves, wherein the first accommodating grooves penetrate the first molding compound;
a plurality of first dice, disposed in the first accommodating grooves, each of the first dice having a first surface, a second surface and at least one first via, wherein the first surfaces of the first dice are exposed to the first surface of the first molding compound, the second surfaces of the first dice are exposed to the second surface of the first molding compound;
a first upper circuit layer, disposed on the second surface of the first molding compound; and
a first lower circuit layer, disposed on the first surface of the first molding compound, and the first upper circuit layer electrically connected to the first lower circuit layer by the first via.
10. The package as claimed in claim 9, further comprising a plurality of first ball pads disposed on the first surfaces of the first dice.
11. The package as claimed in claim 9, further comprising a plurality of first solder balls disposed on the first lower circuit layer.
12. The stacked package as claimed in claim 9, wherein the first upper circuit layer comprises a first upper redistribution layer and the first lower circuit layer comprises a first lower redistribution layer.
13. A package, comprising:
a molding compound, having a first surface, a second surface and a accommodating groove, wherein the accommodating groove penetrates the molding compound;
a die, disposed in the accommodating groove, having a first surface, a second surface and at least one via, wherein the first surface of the die is exposed to the first surface of the molding compound, and the second surface of the die is exposed to the second surface of the molding compound;
an upper circuit layer, disposed on the second surface of the molding compound; and
a lower circuit layer, disposed on the first surface of the molding compound, and the upper circuit layer electrically connected to the lower circuit layer by the via.
14. The package as claimed in claim 13, further comprising a plurality of ball pads disposed on the first surface of the die.
15. The package as claimed in claim 13, further comprising a plurality of solder balls disposed on the lower circuit layer.
16. The package as claimed in claim 13, wherein the upper circuit layer comprises an upper redistribution layer and the lower circuit layer comprises a lower redistribution layer.
US12/876,907 2007-08-07 2010-09-07 Package and the Method for Making the Same, and a Stacked Package Abandoned US20100327442A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/876,907 US20100327442A1 (en) 2007-08-07 2010-09-07 Package and the Method for Making the Same, and a Stacked Package

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW096129098A TWI345296B (en) 2007-08-07 2007-08-07 Package having a self-aligned die and the method for making the same, and a stacked package and the method for making the same
TW096129098 2007-08-07
US12/185,879 US7811858B2 (en) 2007-08-07 2008-08-05 Package and the method for making the same, and a stacked package
US12/876,907 US20100327442A1 (en) 2007-08-07 2010-09-07 Package and the Method for Making the Same, and a Stacked Package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/185,879 Division US7811858B2 (en) 2007-08-07 2008-08-05 Package and the method for making the same, and a stacked package

Publications (1)

Publication Number Publication Date
US20100327442A1 true US20100327442A1 (en) 2010-12-30

Family

ID=40345711

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/185,879 Active 2028-09-16 US7811858B2 (en) 2007-08-07 2008-08-05 Package and the method for making the same, and a stacked package
US12/876,907 Abandoned US20100327442A1 (en) 2007-08-07 2010-09-07 Package and the Method for Making the Same, and a Stacked Package

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/185,879 Active 2028-09-16 US7811858B2 (en) 2007-08-07 2008-08-05 Package and the method for making the same, and a stacked package

Country Status (2)

Country Link
US (2) US7811858B2 (en)
TW (1) TWI345296B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150179618A1 (en) * 2013-12-19 2015-06-25 SK Hynix Inc. Package-on-package modules, electronic systems including the same, and memory cards including the same

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI393223B (en) * 2009-03-03 2013-04-11 Advanced Semiconductor Eng Semiconductor package structure and manufacturing method thereof
KR101088822B1 (en) * 2009-08-10 2011-12-01 주식회사 하이닉스반도체 Semiconductor package
TWI392069B (en) 2009-11-24 2013-04-01 Advanced Semiconductor Eng Package structure and packaging process thereof
TWI446420B (en) * 2010-08-27 2014-07-21 Advanced Semiconductor Eng Releasing carrier method for semiconductor process
TWI445152B (en) 2010-08-30 2014-07-11 Advanced Semiconductor Eng Semiconductor structure and method for manufacturing the same
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
TWI434387B (en) 2010-10-11 2014-04-11 Advanced Semiconductor Eng Semiconductor element having a via and package having a semiconductor element with a via and method for making the same
TWI527174B (en) 2010-11-19 2016-03-21 日月光半導體製造股份有限公司 Package having semiconductor device
TWI445155B (en) 2011-01-06 2014-07-11 Advanced Semiconductor Eng Stacked semiconductor package and method for making the same
US8853819B2 (en) 2011-01-07 2014-10-07 Advanced Semiconductor Engineering, Inc. Semiconductor structure with passive element network and manufacturing method thereof
TWI476865B (en) * 2011-05-25 2015-03-11 Advanced Semiconductor Eng Method for making stacked semiconductor package
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
FR2985367A1 (en) * 2011-12-29 2013-07-05 3D Plus METHOD FOR THE COLLECTIVE MANUFACTURE OF 3D ELECTRONIC MODULES COMPRISING ONLY VALID PCBS
US8975157B2 (en) 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US8937387B2 (en) 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US8952542B2 (en) 2012-11-14 2015-02-10 Advanced Semiconductor Engineering, Inc. Method for dicing a semiconductor wafer having through silicon vias and resultant structures
US9406552B2 (en) 2012-12-20 2016-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process
US8841751B2 (en) 2013-01-23 2014-09-23 Advanced Semiconductor Engineering, Inc. Through silicon vias for semiconductor devices and manufacturing method thereof
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US9089268B2 (en) 2013-03-13 2015-07-28 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US9173583B2 (en) 2013-03-15 2015-11-03 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US8987734B2 (en) 2013-03-15 2015-03-24 Advanced Semiconductor Engineering, Inc. Semiconductor wafer, semiconductor process and semiconductor package
CN112786462B (en) * 2020-12-25 2023-08-22 上海易卜半导体有限公司 Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5352629A (en) * 1993-01-19 1994-10-04 General Electric Company Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules
US5478778A (en) * 1991-08-30 1995-12-26 Nec Corporation Method of manufacturing a compact optical semiconductor module capable of being readily assembled with a high precision
US6084308A (en) * 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6391737B1 (en) * 2000-06-29 2002-05-21 Vanguard International Semiconductor Corp. Method of simultaneously forming patterns on a die of an alignment mark and other dies
US6982487B2 (en) * 2003-03-25 2006-01-03 Samsung Electronics Co., Ltd. Wafer level package and multi-package stack
US20060046352A1 (en) * 2004-08-25 2006-03-02 Low Al L Substrate grooves to reduce underfill fillet bridging
US7160755B2 (en) * 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
US20070015315A1 (en) * 2005-07-13 2007-01-18 Akinori Shiraishi Semiconductor device and manufacturing method thereof
US20070155048A1 (en) * 2005-12-29 2007-07-05 Micron Technology, Inc. Methods for packaging microelectronic devices and microelectronic devices formed using such methods
US20080023435A1 (en) * 2005-07-05 2008-01-31 Enboa Wu Method for self-assembling microstructures

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5478778A (en) * 1991-08-30 1995-12-26 Nec Corporation Method of manufacturing a compact optical semiconductor module capable of being readily assembled with a high precision
US5352629A (en) * 1993-01-19 1994-10-04 General Electric Company Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules
US6084308A (en) * 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6391737B1 (en) * 2000-06-29 2002-05-21 Vanguard International Semiconductor Corp. Method of simultaneously forming patterns on a die of an alignment mark and other dies
US6982487B2 (en) * 2003-03-25 2006-01-03 Samsung Electronics Co., Ltd. Wafer level package and multi-package stack
US20060046352A1 (en) * 2004-08-25 2006-03-02 Low Al L Substrate grooves to reduce underfill fillet bridging
US7160755B2 (en) * 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
US20080023435A1 (en) * 2005-07-05 2008-01-31 Enboa Wu Method for self-assembling microstructures
US20070015315A1 (en) * 2005-07-13 2007-01-18 Akinori Shiraishi Semiconductor device and manufacturing method thereof
US20070155048A1 (en) * 2005-12-29 2007-07-05 Micron Technology, Inc. Methods for packaging microelectronic devices and microelectronic devices formed using such methods

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150179618A1 (en) * 2013-12-19 2015-06-25 SK Hynix Inc. Package-on-package modules, electronic systems including the same, and memory cards including the same
US9601469B2 (en) * 2013-12-19 2017-03-21 SK Hynix Inc. Package-on-package modules, electronic systems including the same, and memory cards including the same

Also Published As

Publication number Publication date
TW200908279A (en) 2009-02-16
TWI345296B (en) 2011-07-11
US7811858B2 (en) 2010-10-12
US20090039526A1 (en) 2009-02-12

Similar Documents

Publication Publication Date Title
US7811858B2 (en) Package and the method for making the same, and a stacked package
US11670577B2 (en) Chip package with redistribution structure having multiple chips
US20210057383A1 (en) Sawing Underfill in Packaging Processes
US9985001B2 (en) 3DIC package and methods of forming the same
US9123643B2 (en) Chip-on-wafer structures and methods for forming the same
US7145228B2 (en) Microelectronic devices
US7768125B2 (en) Multi-chip package system
US7585750B2 (en) Semiconductor package having through-hole via on saw streets formed with partial saw
US6852607B2 (en) Wafer level package having a side package
US20060019467A1 (en) Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby
US10832999B2 (en) Packaging methods for semiconductor devices comprising forming trenches in separation regions between adjacent packaging substrates
JP2009010312A (en) Stack package and manufacturing method therefor
US20120104626A1 (en) Process of forming an electronic device including a plurality of singulated die
US9040350B2 (en) Packaging and function tests for package-on-package and system-in-package structures
US11824045B2 (en) Semiconductor package and method of manufacturing the semiconductor package
US20230411261A1 (en) Exposed bonding pad of chip package and manufacturing method thereof
US7648902B2 (en) Manufacturing method of redistribution circuit structure
KR101013556B1 (en) Method for fabricating stack package
US20230108516A1 (en) Semiconductor device
US20080251937A1 (en) Stackable semiconductor device and manufacturing method thereof
KR20090098068A (en) Method of fabricating wafer level package

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION