US20110004718A1 - System, method, and computer program product for ordering a plurality of write commands associated with a storage device - Google Patents

System, method, and computer program product for ordering a plurality of write commands associated with a storage device Download PDF

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Publication number
US20110004718A1
US20110004718A1 US12/497,327 US49732709A US2011004718A1 US 20110004718 A1 US20110004718 A1 US 20110004718A1 US 49732709 A US49732709 A US 49732709A US 2011004718 A1 US2011004718 A1 US 2011004718A1
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Prior art keywords
storage device
write commands
order
commands
write
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US12/497,327
Inventor
Ross John Stenfort
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Seagate Technology LLC
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SandForce Inc
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Priority to US12/497,327 priority Critical patent/US20110004718A1/en
Assigned to SANDFORCE, INC. reassignment SANDFORCE, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STENFORT, ROSS JOHN
Priority to US13/379,607 priority patent/US8930606B2/en
Priority to JP2012519610A priority patent/JP5957634B2/en
Priority to PCT/US2010/040855 priority patent/WO2011003050A2/en
Priority to TW99121910A priority patent/TWI470436B/en
Priority to KR1020127002875A priority patent/KR101712504B1/en
Priority to CN201080030032.6A priority patent/CN102473087B/en
Priority to KR1020167011543A priority patent/KR101718128B1/en
Publication of US20110004718A1 publication Critical patent/US20110004718A1/en
Assigned to LSI CORPORATION reassignment LSI CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SANDFORCE, INC.
Assigned to AGERE SYSTEMS LLC, LSI CORPORATION reassignment AGERE SYSTEMS LLC TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS INCLUDED IN SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Assignors: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Priority to US14/576,078 priority patent/US9582195B2/en
Assigned to SEAGATE TECHNOLOGY LLC reassignment SEAGATE TECHNOLOGY LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LSI CORPORATION
Priority to US15/409,190 priority patent/US10019200B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
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    • G06F3/0689—Disk arrays, e.g. RAID, JBOD
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1097—Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Definitions

  • the present invention relates to storage devices, and more particularly to ordering write commands associated with such storage devices.
  • Storage systems may include many devices including storage device and other devices connected to and/or in communication with the storage devices. These devices in communication with the storage devices often need to access commands and/or data associated with the storage devices. In many different types of storage systems, commands are queued and the commands are executed in a random order.
  • Serial ATA computer bus is one storage-interface for connecting host bus adapters to storage devices such as hard disk drives and optical drives, etc.
  • SATA Serial ATA
  • commands are queued and the order that the commands are executed is random.
  • a device connected to a SATA drive does not have any knowledge as to the order the write commands will be executed.
  • the device attached to a SATA drive may not pre-fetch write data unless it has enough resources to pre-fetch write data for all of the commands.
  • Pre-fetching for all commands is very costly because pre-fetching all commands requires the use of a large portion of memory. Additionally, this pre-fetching may not add performance because the command being executed may not necessarily be the command for which data has been pre-fetched. There is thus a need for addressing these and/or other issues associated with the prior art.
  • a system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device.
  • a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order.
  • FIG. 1 shows a method for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment.
  • FIG. 2 shows a system for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment.
  • FIG. 3 shows a method for ordering a plurality of write commands associated with a storage device, in accordance with another embodiment.
  • FIG. 4 illustrates an exemplary system in which the various architecture and/or functionality of the various previous embodiments may be implemented.
  • FIG. 1 shows a method 100 for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment. As shown, a plurality of write commands associated with a storage device to be sent to a device are identified. See operation 102 .
  • a storage device refers to any device capable of storing data.
  • the storage device may include, but is not limited to, a Serial ATA (SATA) drive, a Serial Attached SCSI (SAS) drive, a Fibre Channel (FC) drive, or a Universal Serial Bus (USB) drive, and/or any other storage device.
  • the storage device may include a Peripheral Component Interconnect (PCI) or PCI Express based plug in card configured to appear as a storage device, or a PCI or PCI Express interface configured to appear as a storage device.
  • PCI or PCI Express interface may be used to access the storage device.
  • the write commands may be sent to any type of device capable of receiving commands.
  • the device may include a host system, an SAS/SATA bridge (e.g. an SAS to SATA bridge, etc.), a USB/SATA bridge (e.g. a USB to SATA bridge, etc.), an FC/SATA bridge (e.g. an FC to SATA bridge, etc.), a PCI or PCI Express based plug in card (e.g. configured to appear as a storage device, etc.), a PCI or PCI Express interface, an interface used to access at least one storage device or system, or any device capable of having a plurality of commands outstanding at one time.
  • an SAS/SATA bridge e.g. an SAS to SATA bridge, etc.
  • a USB/SATA bridge e.g. a USB to SATA bridge, etc.
  • an FC/SATA bridge e.g. an FC to SATA bridge, etc.
  • PCI or PCI Express based plug in card e.g. configured to appear as a
  • an order of the plurality of write commands is determined, the determined order being known by the device. See operation 104 .
  • the determined order may be a predetermined order known by the device.
  • the order may be determined based on an order in which the write commands are identified (e.g. a first come first served based approach, etc.). For example, as commands are generated and/or received, the commands may be queued. As another option, the order may include a predetermined order known by the device.
  • the order may include any order known by the device.
  • a controller may inform the device of the order.
  • the order may be determined by the storage device in real time or near real time.
  • the plurality of write commands are ordered in the determined order. See operation 106 .
  • the storage device may order the plurality of write commands in the determined order.
  • the device may be permitted to pre-fetch data associated with the plurality of write commands.
  • the device may be permitted to pre-fetch the data before an associated write command is executed. This may be accomplished because the device knows the order of the write commands.
  • read commands associated with the storage device may also be identified.
  • the plurality of read commands associated with the storage device may be ordered randomly or in a determined order.
  • the read commands may be intermixed with the write commands, where the write commands maintain their determined order relative to one another.
  • FIG. 2 shows a system 200 for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment.
  • the present system 200 may be implemented to carry out the method 100 of FIG. 2 .
  • the system 200 may be implemented in any desired environment. It should also be noted that the aforementioned definitions may apply during the present description.
  • the system 200 includes a storage device 202 .
  • one or more devices 204 are in communication with and/or connected to the storage device 202 . This communication and/or connection may be accomplished utilizing any type of bus, etc.
  • the storage device 202 may represent any number of storage devices.
  • the storage device 202 may represent a SATA drive, an SAS drive, an FC drive, a USB drive, a PCI or PCI Express based plug in card configured to appear as a storage device, and/or any other storage device.
  • the one or more devices 204 may include any device capable of receiving commands.
  • the devices 204 may include an SAS/SATA bridge, a USB/SATA bridge, an FC/SATA bridge, a PCI or PCI Express based plug in card, an expander, and initiator, and/or any other device.
  • the storage device 202 may identify write commands associated with the storage device 202 to be sent to one or more of the devices 204 .
  • the storage device 202 may then determine an order. In various embodiments, this determination may be made in real time or near real time, or may be a predetermined order.
  • the storage device 202 may then order the write commands in a determined order, where the determined order is known by the devices 204 .
  • the storage device 202 may order the write commands by placing the write commands in a queue in the order.
  • the storage device 202 may order the write commands by assigning an order to the write commands.
  • the identifying, determining, and ordering may be performed based on a mode of the storage device 202 .
  • a mode may indicate that a particular ordering is to be performed and/or utilized.
  • the identifying, determining, and ordering may be performed as a standard function.
  • a plurality of read commands associated with the storage device 202 may also be identified.
  • the plurality of read commands associated with the storage device 202 may be ordered randomly. Further, the plurality of read commands ordered randomly may be intermixed with the plurality of write commands in the determined order.
  • the devices 204 may be permitted to pre-fetch data associated with the write commands.
  • the devices 204 may be permitted to pre-fetch the data before an associated write command is executed. This may be accomplished because the devices 204 know the order of the write commands.
  • a device e.g. a host/bridge, etc.
  • a SATA drive may not know the order of the write commands.
  • the drive can not pre-fetch write data unless it has enough resources to pre-fetch write data for all the commands.
  • pre-fetching for all commands may be very costly since this costs a large portion of memory.
  • a hard disk drive may reorder the commands to reduce the number of rotations of the media needed to fetch all the data.
  • a solid-state drive (SSD) may reorder the commands based on the internal architectures to optimize for the drive.
  • the host/bridge attached to the drive that needs to fetch write data may be a bottle neck.
  • the drive may order the commands in a deterministic fashion which is known by the host and/or bridge. In one embodiment, this may be implemented as a first come first served approach. Thus, the host will know the order of the write commands and it may pre-fetch write data before the command is executed. In various embodiments, the drive may always perform this ordering, or the ordering may be based on a mode. As an option, there may be more than one mode.
  • ordering may be implemented for any protocol or mode within a protocol that does not have a deterministic technique of ordering the commands relative to one another. It should be noted that the order of the read commands may or may not be deterministic relative to the order of the write commands.
  • a memory controller e.g. an SSD controller, etc. may pass information about the order of write commands to the device attached to the drive to allow for efficient pre-fetching.
  • FIG. 3 shows a method 300 for ordering a plurality of write commands associated with a storage device, in accordance with another embodiment.
  • the present method 300 may be implemented in the context of the functionality and architecture of FIGS. 1-2 .
  • the method 300 may be carried out in any desired environment. Again, the aforementioned definitions may apply during the present description.
  • a command is identified. See operation 302 . If a command is identified, it is determined whether the command is a read command. See operation 304 .
  • the read command is queued in a random order. See operation 306 . If the command is not a read command, it is determined if the command is a write command. See operation 308 .
  • the command is queued in an order known to a receiving device. See operation 310 .
  • the write command may be queued in an order and then the receiving device may be informed as to the order.
  • the write command may be queued in a predetermined order already known by the receiving device.
  • a SATA drive may execute write commands in the same order that a host, bridge, or attached device sends the commands.
  • the host, bridge, or attached device may then pre-fetch data based on knowing the order the write commands will be executed. Thus, all available write data storage may be used for the next data.
  • an SSD controller may pass information about the order of write commands to the device attached to allow for efficient pre-fetching.
  • FIG. 4 illustrates an exemplary system 400 in which the various architecture and/or functionality of the various previous embodiments may be implemented.
  • a system 400 is provided including at least one host processor 401 which is connected to a communication bus 402 .
  • the system 400 also includes a main memory 404 .
  • Control logic (software) and data are stored in the main memory 404 which may take the form of random access memory (RAM).
  • RAM random access memory
  • the system 400 also includes a graphics processor 406 and a display 408 , i.e. a computer monitor.
  • the graphics processor 406 may include a plurality of shader modules, a rasterization module, etc. Each of the foregoing modules may even be situated on a single semiconductor platform to form a graphics processing unit (GPU).
  • GPU graphics processing unit
  • a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional central processing unit (CPU) and bus implementation. Of course, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.
  • CPU central processing unit
  • the system 400 may also include a secondary storage 410 .
  • the secondary storage 410 includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, etc.
  • the removable storage drive reads from and/or writes to a removable storage unit in a well known manner.
  • Computer programs, or computer control logic algorithms may be stored in the main memory 404 and/or the secondary storage 410 . Such computer programs, when executed, enable the system 400 to perform various functions. Memory 404 , storage 410 and/or any other storage are possible examples of computer-readable media.
  • the architecture and/or functionality of the various previous figures may be implemented in the context of the host processor graphics processor 406 , an integrated circuit (not shown) that is capable of at least a portion of the capabilities of both the host processor 401 and the graphics processor 406 , a chipset (i.e. a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any other integrated circuit for that matter.
  • an integrated circuit not shown
  • a chipset i.e. a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.
  • the architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system.
  • the system 400 may take the form of a desktop computer, lap-top computer, and/or any other type of logic.
  • the system 400 may take the form of various other devices including, but not limited to, a personal digital assistant (PDA) device, a mobile phone device, a television, etc.
  • PDA personal digital assistant
  • system 400 may be coupled to a network [e.g. a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, etc.] for communication purposes.
  • a network e.g. a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, etc.

Abstract

A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order.

Description

    FIELD OF THE INVENTION
  • The present invention relates to storage devices, and more particularly to ordering write commands associated with such storage devices.
    • BACKGROUND
  • Storage systems may include many devices including storage device and other devices connected to and/or in communication with the storage devices. These devices in communication with the storage devices often need to access commands and/or data associated with the storage devices. In many different types of storage systems, commands are queued and the commands are executed in a random order.
  • The Serial ATA (SATA) computer bus is one storage-interface for connecting host bus adapters to storage devices such as hard disk drives and optical drives, etc. Currently, in SATA systems and other comparable systems, commands are queued and the order that the commands are executed is random. A device connected to a SATA drive does not have any knowledge as to the order the write commands will be executed.
  • Thus, the device attached to a SATA drive may not pre-fetch write data unless it has enough resources to pre-fetch write data for all of the commands. Pre-fetching for all commands is very costly because pre-fetching all commands requires the use of a large portion of memory. Additionally, this pre-fetching may not add performance because the command being executed may not necessarily be the command for which data has been pre-fetched. There is thus a need for addressing these and/or other issues associated with the prior art.
    • SUMMARY
  • A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a method for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment.
  • FIG. 2 shows a system for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment.
  • FIG. 3 shows a method for ordering a plurality of write commands associated with a storage device, in accordance with another embodiment.
  • FIG. 4 illustrates an exemplary system in which the various architecture and/or functionality of the various previous embodiments may be implemented.
    •  DETAILED DESCRIPTION
  • FIG. 1 shows a method 100 for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment. As shown, a plurality of write commands associated with a storage device to be sent to a device are identified. See operation 102.
  • In the context of the present description, a storage device refers to any device capable of storing data. For example, in various embodiments, the storage device may include, but is not limited to, a Serial ATA (SATA) drive, a Serial Attached SCSI (SAS) drive, a Fibre Channel (FC) drive, or a Universal Serial Bus (USB) drive, and/or any other storage device. Additionally, in various embodiments, the storage device may include a Peripheral Component Interconnect (PCI) or PCI Express based plug in card configured to appear as a storage device, or a PCI or PCI Express interface configured to appear as a storage device. In one embodiment, a PCI or PCI Express interface may be used to access the storage device.
  • Further, the write commands may be sent to any type of device capable of receiving commands. For example, in various embodiments, the device may include a host system, an SAS/SATA bridge (e.g. an SAS to SATA bridge, etc.), a USB/SATA bridge (e.g. a USB to SATA bridge, etc.), an FC/SATA bridge (e.g. an FC to SATA bridge, etc.), a PCI or PCI Express based plug in card (e.g. configured to appear as a storage device, etc.), a PCI or PCI Express interface, an interface used to access at least one storage device or system, or any device capable of having a plurality of commands outstanding at one time.
  • In addition to identifying the write commands associated with the storage device, an order of the plurality of write commands is determined, the determined order being known by the device. See operation 104. In one embodiment, the determined order may be a predetermined order known by the device.
  • As an option, the order may be determined based on an order in which the write commands are identified (e.g. a first come first served based approach, etc.). For example, as commands are generated and/or received, the commands may be queued. As another option, the order may include a predetermined order known by the device.
  • Of course, the order may include any order known by the device. In one embodiment, a controller may inform the device of the order. In this case, the order may be determined by the storage device in real time or near real time.
  • Further, the plurality of write commands are ordered in the determined order. See operation 106. In this case, the storage device may order the plurality of write commands in the determined order.
  • In this way, the device may be permitted to pre-fetch data associated with the plurality of write commands. In this case, the device may be permitted to pre-fetch the data before an associated write command is executed. This may be accomplished because the device knows the order of the write commands.
  • In one embodiment, read commands associated with the storage device may also be identified. In this case, the plurality of read commands associated with the storage device may be ordered randomly or in a determined order. In either case, the read commands may be intermixed with the write commands, where the write commands maintain their determined order relative to one another.
  • More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing framework may or may not be implemented, per the desires of the user. It should be strongly noted that the following information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of the following features may be optionally incorporated with or without the exclusion of other features described.
  • FIG. 2 shows a system 200 for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment. As an option, the present system 200 may be implemented to carry out the method 100 of FIG. 2. Of course, however, the system 200 may be implemented in any desired environment. It should also be noted that the aforementioned definitions may apply during the present description.
  • As shown, the system 200 includes a storage device 202. As shown further, one or more devices 204 are in communication with and/or connected to the storage device 202. This communication and/or connection may be accomplished utilizing any type of bus, etc.
  • In this case, the storage device 202 may represent any number of storage devices. For example, in various embodiments, the storage device 202 may represent a SATA drive, an SAS drive, an FC drive, a USB drive, a PCI or PCI Express based plug in card configured to appear as a storage device, and/or any other storage device.
  • Furthermore, the one or more devices 204 may include any device capable of receiving commands. For example, in various embodiments, the devices 204 may include an SAS/SATA bridge, a USB/SATA bridge, an FC/SATA bridge, a PCI or PCI Express based plug in card, an expander, and initiator, and/or any other device.
  • In operation, the storage device 202 may identify write commands associated with the storage device 202 to be sent to one or more of the devices 204. The storage device 202 may then determine an order. In various embodiments, this determination may be made in real time or near real time, or may be a predetermined order.
  • The storage device 202 may then order the write commands in a determined order, where the determined order is known by the devices 204. In one embodiment, the storage device 202 may order the write commands by placing the write commands in a queue in the order. In another embodiment, the storage device 202 may order the write commands by assigning an order to the write commands.
  • In one embodiment, the identifying, determining, and ordering may be performed based on a mode of the storage device 202. For example, a mode may indicate that a particular ordering is to be performed and/or utilized. In another embodiment, the identifying, determining, and ordering may be performed as a standard function.
  • In one embodiment, a plurality of read commands associated with the storage device 202 may also be identified. In this case, the plurality of read commands associated with the storage device 202 may be ordered randomly. Further, the plurality of read commands ordered randomly may be intermixed with the plurality of write commands in the determined order.
  • In this way, the devices 204 may be permitted to pre-fetch data associated with the write commands. In this case, the devices 204 may be permitted to pre-fetch the data before an associated write command is executed. This may be accomplished because the devices 204 know the order of the write commands.
  • For example, in some systems, a device (e.g. a host/bridge, etc.) attached to a SATA drive may not know the order of the write commands. Thus, the drive can not pre-fetch write data unless it has enough resources to pre-fetch write data for all the commands. However, pre-fetching for all commands may be very costly since this costs a large portion of memory.
  • As an option, a hard disk drive (HDD) may reorder the commands to reduce the number of rotations of the media needed to fetch all the data. Additionally, a solid-state drive (SSD) may reorder the commands based on the internal architectures to optimize for the drive. However, in some cases, the host/bridge attached to the drive that needs to fetch write data may be a bottle neck.
  • Thus, the drive may order the commands in a deterministic fashion which is known by the host and/or bridge. In one embodiment, this may be implemented as a first come first served approach. Thus, the host will know the order of the write commands and it may pre-fetch write data before the command is executed. In various embodiments, the drive may always perform this ordering, or the ordering may be based on a mode. As an option, there may be more than one mode.
  • Additionally, the ordering may be implemented for any protocol or mode within a protocol that does not have a deterministic technique of ordering the commands relative to one another. It should be noted that the order of the read commands may or may not be deterministic relative to the order of the write commands.
  • For example, many read and write commands may be received. The read commands may be ordered randomly and the write commands may be ordered deterministically. The read and write commands may be intermixed, where the relative order of the write commands to one another is maintained. It should also be noted that, in one embodiment, a memory controller (e.g. an SSD controller, etc.) may pass information about the order of write commands to the device attached to the drive to allow for efficient pre-fetching.
  • FIG. 3 shows a method 300 for ordering a plurality of write commands associated with a storage device, in accordance with another embodiment. As an option, the present method 300 may be implemented in the context of the functionality and architecture of FIGS. 1-2. Of course, however, the method 300 may be carried out in any desired environment. Again, the aforementioned definitions may apply during the present description.
  • As shown, it is determined whether a command is identified. See operation 302. If a command is identified, it is determined whether the command is a read command. See operation 304.
  • If the command is a read command, the read command is queued in a random order. See operation 306. If the command is not a read command, it is determined if the command is a write command. See operation 308.
  • If the command is a write command, the command is queued in an order known to a receiving device. See operation 310. For example, in one embodiment, the write command may be queued in an order and then the receiving device may be informed as to the order. In another embodiment, the write command may be queued in a predetermined order already known by the receiving device.
  • It is then determined whether a command to pre-fetch data is received from a receiving device. See operation 312. If a command to pre-fetch data is received, the data is sent. See operation 314.
  • In one embodiment, a SATA drive may execute write commands in the same order that a host, bridge, or attached device sends the commands. The host, bridge, or attached device may then pre-fetch data based on knowing the order the write commands will be executed. Thus, all available write data storage may be used for the next data.
  • In this way, performance may be greatly increased since the write data may be pre-fetched before the device is ready for the write data. In one embodiment, an SSD controller may pass information about the order of write commands to the device attached to allow for efficient pre-fetching.
  • FIG. 4 illustrates an exemplary system 400 in which the various architecture and/or functionality of the various previous embodiments may be implemented. As shown, a system 400 is provided including at least one host processor 401 which is connected to a communication bus 402. The system 400 also includes a main memory 404. Control logic (software) and data are stored in the main memory 404 which may take the form of random access memory (RAM).
  • The system 400 also includes a graphics processor 406 and a display 408, i.e. a computer monitor. In one embodiment, the graphics processor 406 may include a plurality of shader modules, a rasterization module, etc. Each of the foregoing modules may even be situated on a single semiconductor platform to form a graphics processing unit (GPU).
  • In the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional central processing unit (CPU) and bus implementation. Of course, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.
  • The system 400 may also include a secondary storage 410. The secondary storage 410 includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, etc. The removable storage drive reads from and/or writes to a removable storage unit in a well known manner.
  • Computer programs, or computer control logic algorithms, may be stored in the main memory 404 and/or the secondary storage 410. Such computer programs, when executed, enable the system 400 to perform various functions. Memory 404, storage 410 and/or any other storage are possible examples of computer-readable media.
  • In one embodiment, the architecture and/or functionality of the various previous figures may be implemented in the context of the host processor graphics processor 406, an integrated circuit (not shown) that is capable of at least a portion of the capabilities of both the host processor 401 and the graphics processor 406, a chipset (i.e. a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any other integrated circuit for that matter.
  • Still yet, the architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the system 400 may take the form of a desktop computer, lap-top computer, and/or any other type of logic. Still yet, the system 400 may take the form of various other devices including, but not limited to, a personal digital assistant (PDA) device, a mobile phone device, a television, etc.
  • Further, while not shown, the system 400 may be coupled to a network [e.g. a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, etc.] for communication purposes.
  • While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (24)

1. A method, comprising:
identifying a plurality of write commands associated with a storage device to be sent to a device;
determining an order of the plurality of write commands, the determined order being known by the device; and
ordering the plurality of write commands in the determined order.
2. The method of claim 1, wherein the determined order is a predetermined order known by the device.
3. The method of claim 1, wherein the order is determined based on an order in which the plurality of write commands are identified.
4. The method of claim 1, further comprising permitting the device to pre-fetch data associated with the plurality of write commands.
5. The method of claim 4, wherein the device is permitted to pre-fetch the data before an associated write command is executed.
6. The method of claim 1, wherein the identifying, determining, and ordering are performed based on a mode of the storage device.
7. The method of claim 1, wherein the storage device orders the plurality of write commands in the determined order.
8. The method of claim 1, wherein the device includes a host system.
9. The method of claim 1, wherein the device includes an SAS/SATA bridge.
10. The method of claim 1, wherein the device includes a USB/SATA bridge.
11. The method of claim 1, wherein the device includes an FC/SATA bridge.
12. The method of claim 1, wherein the device includes one of a PCI or PCI Express based plug in card.
13. The method of claim 1, wherein the device includes one of a PCI or PCI Express interface.
14. The method of claim 1, wherein the device includes an interface used to access at least one storage device or system.
15. The method of claim 1, wherein the device includes a device capable of having a plurality of commands outstanding at one time.
16. The method of claim 1, further comprising identifying a plurality of read commands associated with the storage device.
17. The method of claim 16, wherein the plurality of read commands associated with the storage device are ordered randomly.
18. The method of claim 17, wherein the plurality of read commands ordered randomly are intermixed with the plurality of write commands in the determined order.
19. The method of claim 1, wherein the storage device includes one of a Serial ATA (SATA) drive, a Serial Attached SCSI (SAS) drive, a Fibre Channel (FC) drive, or a Universal Serial Bus (USB) drive.
20. The method of claim 1, wherein the storage device includes one of a PCI or PCI Express based plug in card configured to appear as a storage device.
21. The method of claim 1, wherein the storage device includes one of a PCI or PCI Express interface configured to appear as a storage device.
22. The method of claim 1, wherein a PCI or PCI Express interface is used to access the storage device.
23. A computer program product embodied on a computer readable medium, comprising:
computer code for identifying a plurality of write commands associated with a storage device to be sent to a device;
computer code for determining an order of the plurality of write commands, the determined order being known by the device; and
computer code for ordering the plurality of write commands in the determined order.
24. An apparatus, comprising:
a storage device for identifying a plurality of write commands associated with the storage device to be sent to a device, and for ordering the plurality of write commands in a determined order, the determined order being known by the device.
US12/497,327 2009-07-02 2009-07-02 System, method, and computer program product for ordering a plurality of write commands associated with a storage device Abandoned US20110004718A1 (en)

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US12/497,327 US20110004718A1 (en) 2009-07-02 2009-07-02 System, method, and computer program product for ordering a plurality of write commands associated with a storage device
KR1020167011543A KR101718128B1 (en) 2009-07-02 2010-07-02 Ordering a plurality of write commands associated with a storage device
CN201080030032.6A CN102473087B (en) 2009-07-02 2010-07-02 It pair is ranked up with the associated multiple write orders of storage device
JP2012519610A JP5957634B2 (en) 2009-07-02 2010-07-02 Ordering multiple write commands associated with a storage device
PCT/US2010/040855 WO2011003050A2 (en) 2009-07-02 2010-07-02 Ordering a plurality of write commands associated with a storage device
TW99121910A TWI470436B (en) 2009-07-02 2010-07-02 System, method, and computer program product for ordering a plurality of write commands associated with a storage device
KR1020127002875A KR101712504B1 (en) 2009-07-02 2010-07-02 Ordering a plurality of write commands associated with a storage device
US13/379,607 US8930606B2 (en) 2009-07-02 2010-07-02 Ordering a plurality of write commands associated with a storage device
US14/576,078 US9582195B2 (en) 2009-07-02 2014-12-18 Ordering a plurality of write commands associated with a storage device
US15/409,190 US10019200B2 (en) 2009-07-02 2017-01-18 Ordering a plurality of write commands associated with a storage device

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US14/576,078 Active 2029-12-15 US9582195B2 (en) 2009-07-02 2014-12-18 Ordering a plurality of write commands associated with a storage device
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100251009A1 (en) * 2009-03-27 2010-09-30 Ross John Stenfort System, method, and computer program product for converting logical block address de-allocation information in a first format to a second format
US20100250830A1 (en) * 2009-03-27 2010-09-30 Ross John Stenfort System, method, and computer program product for hardening data stored on a solid state disk
US8930606B2 (en) 2009-07-02 2015-01-06 Lsi Corporation Ordering a plurality of write commands associated with a storage device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8671258B2 (en) 2009-03-27 2014-03-11 Lsi Corporation Storage system logical block address de-allocation management
US9792074B2 (en) 2009-07-06 2017-10-17 Seagate Technology Llc System, method, and computer program product for interfacing one or more storage devices with a plurality of bridge chips
JP5920496B2 (en) 2014-02-18 2016-05-18 住友化学株式会社 Laminated porous film and non-aqueous electrolyte secondary battery
WO2017131724A1 (en) * 2016-01-29 2017-08-03 Hewlett Packard Enterprise Development Lp Host devices and non-volatile memory subsystem controllers
CN106339326A (en) * 2016-08-26 2017-01-18 记忆科技(深圳)有限公司 Method for improving sequential read performance of solid state disk (SSD)
US10466904B2 (en) * 2017-03-24 2019-11-05 Western Digital Technologies, Inc. System and method for processing and arbitrating submission and completion queues
KR102549545B1 (en) 2018-03-22 2023-06-29 삼성전자주식회사 Storage device and method of operating the storage device
CN114995882B (en) * 2022-07-19 2022-11-04 沐曦集成电路(上海)有限公司 Heterogeneous structure system systematic processing method
TWI822386B (en) * 2022-10-11 2023-11-11 慧榮科技股份有限公司 Bridge control chip and associated signal processing method

Citations (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347648A (en) * 1990-06-29 1994-09-13 Digital Equipment Corporation Ensuring write ordering under writeback cache error conditions
US5485595A (en) * 1993-03-26 1996-01-16 Cirrus Logic, Inc. Flash memory mass storage architecture incorporating wear leveling technique without using cam cells
US5544356A (en) * 1990-12-31 1996-08-06 Intel Corporation Block-erasable non-volatile semiconductor memory which tracks and stores the total number of write/erase cycles for each block
US5568423A (en) * 1995-04-14 1996-10-22 Unisys Corporation Flash memory wear leveling system providing immediate direct access to microprocessor
US5568626A (en) * 1990-02-27 1996-10-22 Nec Corporation Method and system for rewriting data in a non-volatile memory a predetermined large number of times
US5621687A (en) * 1995-05-31 1997-04-15 Intel Corporation Programmable erasure and programming time for a flash memory
US5666532A (en) * 1994-07-26 1997-09-09 Novell, Inc. Computer method and apparatus for asynchronous ordered operations
US5819307A (en) * 1994-10-20 1998-10-06 Fujitsu Limited Control method in which frequency of data erasures is limited
US5835935A (en) * 1995-09-13 1998-11-10 Lexar Media, Inc. Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory
US5881229A (en) * 1995-04-26 1999-03-09 Shiva Corporation Method and product for enchancing performance of computer networks including shared storage objects
US5956473A (en) * 1996-11-25 1999-09-21 Macronix International Co., Ltd. Method and system for managing a flash memory mass storage system
US5963970A (en) * 1996-12-20 1999-10-05 Intel Corporation Method and apparatus for tracking erase cycles utilizing active and inactive wear bar blocks having first and second count fields
US6000006A (en) * 1997-08-25 1999-12-07 Bit Microsystems, Inc. Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage
US6088701A (en) * 1997-11-14 2000-07-11 3Dfx Interactive, Incorporated Command data transport to a graphics processing device from a CPU performing write reordering operations
US6154808A (en) * 1997-10-31 2000-11-28 Fujitsu Limited Method and apparatus for controlling data erase operations of a non-volatile memory device
US6230233B1 (en) * 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
US6405295B1 (en) * 1999-09-07 2002-06-11 Oki Electric Industry, Co., Ltd. Data storage apparatus for efficient utilization of limited cycle memory material
US20020184476A1 (en) * 2001-03-23 2002-12-05 International Business Machines Corporation Instructions for ordering execution in pipelined processes
US6539453B1 (en) * 1998-12-22 2003-03-25 Gemplus Storage system including means for management of a memory with anti-attrition, and process of anti-attrition management of a memory
US6694402B1 (en) * 1998-09-04 2004-02-17 Hyperstone Ag Access control for a memory having a limited erasure frequency
US6732221B2 (en) * 2001-06-01 2004-05-04 M-Systems Flash Disk Pioneers Ltd Wear leveling of static areas in flash memory
US6831865B2 (en) * 2002-10-28 2004-12-14 Sandisk Corporation Maintaining erase counts in non-volatile storage systems
US6914853B2 (en) * 2001-09-27 2005-07-05 Intel Corporation Mechanism for efficient wearout counters in destructive readout memory
US6925523B2 (en) * 2003-03-03 2005-08-02 Agilent Technologies, Inc. Managing monotonically increasing counter values to minimize impact on non-volatile storage
US6948026B2 (en) * 2001-08-24 2005-09-20 Micron Technology, Inc. Erase block management
US6973531B1 (en) * 2002-10-28 2005-12-06 Sandisk Corporation Tracking the most frequently erased blocks in non-volatile memory systems
US6985992B1 (en) * 2002-10-28 2006-01-10 Sandisk Corporation Wear-leveling in non-volatile storage systems
US7000063B2 (en) * 2001-10-05 2006-02-14 Matrix Semiconductor, Inc. Write-many memory device and method for limiting a number of writes to the write-many memory device
US7032087B1 (en) * 2003-10-28 2006-04-18 Sandisk Corporation Erase count differential table within a non-volatile memory system
US7035967B2 (en) * 2002-10-28 2006-04-25 Sandisk Corporation Maintaining an average erase count in a non-volatile storage system
US7096313B1 (en) * 2002-10-28 2006-08-22 Sandisk Corporation Tracking the least frequently erased blocks in non-volatile memory systems
US7103732B1 (en) * 2002-10-28 2006-09-05 Sandisk Corporation Method and apparatus for managing an erase count block
US20060212655A1 (en) * 2003-06-20 2006-09-21 Jeddeloh Joseph M Posted write buffers and method of posting write requests in memory modules
US7120729B2 (en) * 2002-10-28 2006-10-10 Sandisk Corporation Automated wear leveling in non-volatile storage systems
US20060265549A1 (en) * 2001-12-11 2006-11-23 Claude Chapel Storage device cache memory management
US20070273699A1 (en) * 2006-05-24 2007-11-29 Nobuo Sasaki Multi-graphics processor system, graphics processor and data transfer method
US20080151405A1 (en) * 2005-03-22 2008-06-26 Seagate Technology Llc System and method for drive-side guarantee of quality of service and for extending the lifetime of storage devices
US20080307147A1 (en) * 2005-02-24 2008-12-11 International Business Machines Corporation Computer system bus bridge
US20090006787A1 (en) * 2007-06-27 2009-01-01 Jorge Campello De Souza Storage device with write barrier sensitive write commands and write barrier insensitive commands
US20090164698A1 (en) * 2007-12-24 2009-06-25 Yung-Li Ji Nonvolatile storage device with NCQ supported and writing method for a nonvolatile storage device
US20090193279A1 (en) * 2008-01-30 2009-07-30 Sandbridge Technologies, Inc. Method for enabling multi-processor synchronization
US20090235021A1 (en) * 2006-06-20 2009-09-17 Microsoft Corporation Efficiently synchronizing with separated disk caches
US20100211744A1 (en) * 2009-02-19 2010-08-19 Qualcomm Incorporated Methods and aparatus for low intrusion snoop invalidation
US20100241812A1 (en) * 2007-10-18 2010-09-23 Nxp B.V. Data processing system with a plurality of processors, cache circuits and a shared memory

Family Cites Families (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150470A (en) 1989-12-20 1992-09-22 International Business Machines Corporation Data processing system with instruction queue having tags indicating outstanding data status
JPH03230216A (en) 1990-02-06 1991-10-14 Fujitsu Ltd Processing system for writing processing part to storage device
GB2256735B (en) 1991-06-12 1995-06-21 Intel Corp Non-volatile disk cache
JPH06236284A (en) 1991-10-21 1994-08-23 Intel Corp Method for preservation and restoration of computer-system processing state and computer system
US5675816A (en) 1992-05-26 1997-10-07 Fujitsu Limited Magnetic disk subsystem with failsafe battery charging and power shut down
JP3122702B2 (en) * 1993-10-26 2001-01-09 富士通株式会社 Disk device write-back control method
US6728851B1 (en) 1995-07-31 2004-04-27 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US5909591A (en) 1996-06-18 1999-06-01 Lucent Technologies Inc. System and method for identifying individual modules in a modular system
US6463522B1 (en) 1997-12-16 2002-10-08 Intel Corporation Memory system for ordering load and store instructions in a processor that performs multithread execution
JPH11265262A (en) * 1998-03-18 1999-09-28 Hitachi Ltd High speed write cache disk device
JP3745552B2 (en) * 1999-02-26 2006-02-15 富士通株式会社 Information storage device
JP2001014111A (en) * 1999-06-29 2001-01-19 Hitachi Ltd Control method for rotary type storage device
US20080071973A1 (en) 2000-01-06 2008-03-20 Chow David Q Electronic data flash card with various flash memory cells
JP2001265534A (en) * 2000-03-17 2001-09-28 Hitachi Ltd Access control method and disk device using the same
US7239641B1 (en) 2001-04-24 2007-07-03 Brocade Communications Systems, Inc. Quality of service using virtual channel translation
JP2002342038A (en) * 2001-05-16 2002-11-29 Hitachi Ltd Disk device controlling execution order of commands
JP3823040B2 (en) 2001-10-12 2006-09-20 インターナショナル・ビジネス・マシーンズ・コーポレーション Data storage device, data processing device, method for optimizing execution order of write request, data processing method, and hard disk drive
US6745303B2 (en) * 2002-01-03 2004-06-01 Hitachi, Ltd. Data synchronization of multiple remote storage
US20040081179A1 (en) 2002-10-23 2004-04-29 Gregorcyk Arthur J. Method and system for selecting between serial storage buses using data signals of the buses
US7069399B2 (en) 2003-01-15 2006-06-27 Via Technologies Inc. Method and related apparatus for reordering access requests used to access main memory of a data processing system
US7076605B1 (en) 2003-04-25 2006-07-11 Network Appliance, Inc. Method and apparatus for writing data to a storage device
JP3973597B2 (en) 2003-05-14 2007-09-12 株式会社ソニー・コンピュータエンタテインメント Prefetch instruction control method, prefetch instruction control device, cache memory control device, object code generation method and device
US7386579B2 (en) 2003-11-12 2008-06-10 Siemens Product Life Cycle Management Software Inc. System, method, and computer program product for storing test results in a database
JP2005215729A (en) * 2004-01-27 2005-08-11 Hitachi Global Storage Technologies Netherlands Bv Data transmission control method and storage device
US20060004935A1 (en) 2004-06-30 2006-01-05 Pak-Lung Seto Multi-protocol bridge
US8607016B2 (en) 2004-07-21 2013-12-10 Sandisk Technologies Inc. FAT analysis for optimized sequential cluster management
US7526604B1 (en) * 2004-08-09 2009-04-28 Nvidia Corporation Command queueing speculative write prefetch
US7403130B2 (en) 2004-08-20 2008-07-22 Cooper Technologies Company Removing an automatic circuit recloser from service prior to battery failure
JP2006139548A (en) * 2004-11-12 2006-06-01 Hitachi Global Storage Technologies Netherlands Bv Media drive and command execution method thereof
JP2006172032A (en) * 2004-12-15 2006-06-29 Hitachi Global Storage Technologies Netherlands Bv Data storage device and buffer control method thereof
JP5030387B2 (en) 2005-03-08 2012-09-19 エイチジーエスティーネザーランドビーブイ Data storage device
JP4679943B2 (en) 2005-03-23 2011-05-11 ヒタチグローバルストレージテクノロジーズネザーランドビーブイ Data storage device and data rewrite processing method in nonvolatile memory thereof
US7711897B1 (en) 2005-06-10 2010-05-04 American Megatrends, Inc. Method, system, apparatus, and computer-readable medium for improving disk array performance
US7984084B2 (en) 2005-08-03 2011-07-19 SanDisk Technologies, Inc. Non-volatile memory with scheduled reclaim operations
US7694026B2 (en) 2006-03-31 2010-04-06 Intel Corporation Methods and arrangements to handle non-queued commands for data storage devices
US7826349B2 (en) 2006-05-30 2010-11-02 Intel Corporation Connection management mechanism
US7814245B2 (en) * 2006-10-05 2010-10-12 Lsi Corporation Apparatus and methods for improved SATA device interaction without a SAS expander
US7761642B2 (en) * 2006-12-22 2010-07-20 Lsi Corporation Serial advanced technology attachment (SATA) and serial attached small computer system interface (SCSI) (SAS) bridging
US7661006B2 (en) 2007-01-09 2010-02-09 International Business Machines Corporation Method and apparatus for self-healing symmetric multi-processor system interconnects
TWI360114B (en) 2007-02-16 2012-03-11 Mediatek Inc Buffer management method and optical disc drive
US20080229045A1 (en) 2007-03-16 2008-09-18 Lsi Logic Corporation Storage system provisioning architecture
US7653775B2 (en) 2007-04-09 2010-01-26 Lsi Logic Corporation Enhancing performance of SATA disk drives in SAS domains
US7996599B2 (en) 2007-04-25 2011-08-09 Apple Inc. Command resequencing in memory operations
JP4400650B2 (en) 2007-05-23 2010-01-20 セイコーエプソン株式会社 Data transfer control device and electronic device
US20080294813A1 (en) 2007-05-24 2008-11-27 Sergey Anatolievich Gorobets Managing Housekeeping Operations in Flash Memory
TWI373772B (en) 2007-10-04 2012-10-01 Phison Electronics Corp Wear leveling method and controller using the same
US7827320B1 (en) 2008-03-28 2010-11-02 Western Digital Technologies, Inc. Serial ATA device implementing intra-command processing by detecting XRDY primitive while in the XRDY state
US20100017650A1 (en) 2008-07-19 2010-01-21 Nanostar Corporation, U.S.A Non-volatile memory data storage system with reliability management
US20100250830A1 (en) 2009-03-27 2010-09-30 Ross John Stenfort System, method, and computer program product for hardening data stored on a solid state disk
US8090905B2 (en) 2009-03-27 2012-01-03 Sandforce, Inc. System, method, and computer program product for converting logical block address de-allocation information in a first format to a second format
US8671258B2 (en) 2009-03-27 2014-03-11 Lsi Corporation Storage system logical block address de-allocation management
CN104077174B (en) 2009-03-27 2018-05-01 希捷科技有限公司 Method and system for the data write for providing storage system logic block address
US8230159B2 (en) 2009-03-27 2012-07-24 Lsi Corporation System, method, and computer program product for sending logical block address de-allocation status information
US20110004718A1 (en) 2009-07-02 2011-01-06 Ross John Stenfort System, method, and computer program product for ordering a plurality of write commands associated with a storage device
US9792074B2 (en) 2009-07-06 2017-10-17 Seagate Technology Llc System, method, and computer program product for interfacing one or more storage devices with a plurality of bridge chips
US8291131B2 (en) 2009-07-06 2012-10-16 Micron Technology, Inc. Data transfer management
US8140712B2 (en) 2009-07-17 2012-03-20 Sandforce, Inc. System, method, and computer program product for inserting a gap in information sent from a drive to a host device
US8516166B2 (en) 2009-07-20 2013-08-20 Lsi Corporation System, method, and computer program product for reducing a rate of data transfer to at least a portion of memory
US20110022765A1 (en) 2009-07-23 2011-01-27 Ross John Stenfort System, method, and computer program product for maintaining a direct connection between an initiator and a drive
US20110041039A1 (en) 2009-08-11 2011-02-17 Eliyahou Harari Controller and Method for Interfacing Between a Host Controller in a Host and a Flash Memory Device
US8108737B2 (en) 2009-10-05 2012-01-31 Sandforce, Inc. System, method, and computer program product for sending failure information from a serial ATA (SATA) solid state drive (SSD) to a host device

Patent Citations (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568626A (en) * 1990-02-27 1996-10-22 Nec Corporation Method and system for rewriting data in a non-volatile memory a predetermined large number of times
US5347648A (en) * 1990-06-29 1994-09-13 Digital Equipment Corporation Ensuring write ordering under writeback cache error conditions
US5544356A (en) * 1990-12-31 1996-08-06 Intel Corporation Block-erasable non-volatile semiconductor memory which tracks and stores the total number of write/erase cycles for each block
US6230233B1 (en) * 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
US5485595A (en) * 1993-03-26 1996-01-16 Cirrus Logic, Inc. Flash memory mass storage architecture incorporating wear leveling technique without using cam cells
US5666532A (en) * 1994-07-26 1997-09-09 Novell, Inc. Computer method and apparatus for asynchronous ordered operations
US5819307A (en) * 1994-10-20 1998-10-06 Fujitsu Limited Control method in which frequency of data erasures is limited
US5568423A (en) * 1995-04-14 1996-10-22 Unisys Corporation Flash memory wear leveling system providing immediate direct access to microprocessor
US5881229A (en) * 1995-04-26 1999-03-09 Shiva Corporation Method and product for enchancing performance of computer networks including shared storage objects
US5621687A (en) * 1995-05-31 1997-04-15 Intel Corporation Programmable erasure and programming time for a flash memory
US5835935A (en) * 1995-09-13 1998-11-10 Lexar Media, Inc. Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory
US5956473A (en) * 1996-11-25 1999-09-21 Macronix International Co., Ltd. Method and system for managing a flash memory mass storage system
US5963970A (en) * 1996-12-20 1999-10-05 Intel Corporation Method and apparatus for tracking erase cycles utilizing active and inactive wear bar blocks having first and second count fields
US6000006A (en) * 1997-08-25 1999-12-07 Bit Microsystems, Inc. Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage
US6154808A (en) * 1997-10-31 2000-11-28 Fujitsu Limited Method and apparatus for controlling data erase operations of a non-volatile memory device
US6088701A (en) * 1997-11-14 2000-07-11 3Dfx Interactive, Incorporated Command data transport to a graphics processing device from a CPU performing write reordering operations
US6694402B1 (en) * 1998-09-04 2004-02-17 Hyperstone Ag Access control for a memory having a limited erasure frequency
US6539453B1 (en) * 1998-12-22 2003-03-25 Gemplus Storage system including means for management of a memory with anti-attrition, and process of anti-attrition management of a memory
US6405295B1 (en) * 1999-09-07 2002-06-11 Oki Electric Industry, Co., Ltd. Data storage apparatus for efficient utilization of limited cycle memory material
US20020184476A1 (en) * 2001-03-23 2002-12-05 International Business Machines Corporation Instructions for ordering execution in pipelined processes
US6732221B2 (en) * 2001-06-01 2004-05-04 M-Systems Flash Disk Pioneers Ltd Wear leveling of static areas in flash memory
US6948026B2 (en) * 2001-08-24 2005-09-20 Micron Technology, Inc. Erase block management
US6914853B2 (en) * 2001-09-27 2005-07-05 Intel Corporation Mechanism for efficient wearout counters in destructive readout memory
US7000063B2 (en) * 2001-10-05 2006-02-14 Matrix Semiconductor, Inc. Write-many memory device and method for limiting a number of writes to the write-many memory device
US20060265549A1 (en) * 2001-12-11 2006-11-23 Claude Chapel Storage device cache memory management
US6831865B2 (en) * 2002-10-28 2004-12-14 Sandisk Corporation Maintaining erase counts in non-volatile storage systems
US6973531B1 (en) * 2002-10-28 2005-12-06 Sandisk Corporation Tracking the most frequently erased blocks in non-volatile memory systems
US6985992B1 (en) * 2002-10-28 2006-01-10 Sandisk Corporation Wear-leveling in non-volatile storage systems
US7035967B2 (en) * 2002-10-28 2006-04-25 Sandisk Corporation Maintaining an average erase count in a non-volatile storage system
US7096313B1 (en) * 2002-10-28 2006-08-22 Sandisk Corporation Tracking the least frequently erased blocks in non-volatile memory systems
US7103732B1 (en) * 2002-10-28 2006-09-05 Sandisk Corporation Method and apparatus for managing an erase count block
US7120729B2 (en) * 2002-10-28 2006-10-10 Sandisk Corporation Automated wear leveling in non-volatile storage systems
US6925523B2 (en) * 2003-03-03 2005-08-02 Agilent Technologies, Inc. Managing monotonically increasing counter values to minimize impact on non-volatile storage
US20060212655A1 (en) * 2003-06-20 2006-09-21 Jeddeloh Joseph M Posted write buffers and method of posting write requests in memory modules
US7032087B1 (en) * 2003-10-28 2006-04-18 Sandisk Corporation Erase count differential table within a non-volatile memory system
US20080307147A1 (en) * 2005-02-24 2008-12-11 International Business Machines Corporation Computer system bus bridge
US20080151405A1 (en) * 2005-03-22 2008-06-26 Seagate Technology Llc System and method for drive-side guarantee of quality of service and for extending the lifetime of storage devices
US20070273699A1 (en) * 2006-05-24 2007-11-29 Nobuo Sasaki Multi-graphics processor system, graphics processor and data transfer method
US20090235021A1 (en) * 2006-06-20 2009-09-17 Microsoft Corporation Efficiently synchronizing with separated disk caches
US20090006787A1 (en) * 2007-06-27 2009-01-01 Jorge Campello De Souza Storage device with write barrier sensitive write commands and write barrier insensitive commands
US20100241812A1 (en) * 2007-10-18 2010-09-23 Nxp B.V. Data processing system with a plurality of processors, cache circuits and a shared memory
US20090164698A1 (en) * 2007-12-24 2009-06-25 Yung-Li Ji Nonvolatile storage device with NCQ supported and writing method for a nonvolatile storage device
US20090193279A1 (en) * 2008-01-30 2009-07-30 Sandbridge Technologies, Inc. Method for enabling multi-processor synchronization
US20100211744A1 (en) * 2009-02-19 2010-08-19 Qualcomm Incorporated Methods and aparatus for low intrusion snoop invalidation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100251009A1 (en) * 2009-03-27 2010-09-30 Ross John Stenfort System, method, and computer program product for converting logical block address de-allocation information in a first format to a second format
US20100250830A1 (en) * 2009-03-27 2010-09-30 Ross John Stenfort System, method, and computer program product for hardening data stored on a solid state disk
US8090905B2 (en) 2009-03-27 2012-01-03 Sandforce, Inc. System, method, and computer program product for converting logical block address de-allocation information in a first format to a second format
US8930606B2 (en) 2009-07-02 2015-01-06 Lsi Corporation Ordering a plurality of write commands associated with a storage device

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