US20110024821A1 - Push-pull fpga cell - Google Patents
Push-pull fpga cell Download PDFInfo
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- US20110024821A1 US20110024821A1 US12/903,493 US90349310A US2011024821A1 US 20110024821 A1 US20110024821 A1 US 20110024821A1 US 90349310 A US90349310 A US 90349310A US 2011024821 A1 US2011024821 A1 US 2011024821A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
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Abstract
A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.
Description
- This application is a continuation of co-pending U.S. patent application Ser. No. 12/334,059, filed Dec. 12, 2008, the entirety of which is incorporated by reference herein.
- 1. Field of the Invention
- The present invention relates to non-volatile memory cells. More particularly, the present invention relates to push-pull non-volatile memory cells and to arrays of such memory cells.
- 2. The Prior Art
- Push-pull non-volatile memory cells are known in the art.
FIG. 1 is a schematic diagram shows an illustrative prior-art push-pull non-volatile memory cell. The memory cell includes a p-channel non-volatile memory transistor connected in series with an n-channel non-volatile transistor. The p-channel non-volatile memory transistor and the n-channel non-volatile transistor may be fabricated as floating-gate flash transistors or may be fabricated using other known non-volatile transistor technologies. - The memory cell shown in
FIG. 1 may be used to drive a switch transistor such as the n-channel transistor shown with its gate coupled to the common drain connections of the p-channel non-volatile memory transistor and the n-channel non-volatile transistor. Such a memory cell arrangement may be used to form programmable circuit connections in a programmable integrated circuit such as a field programmable gate array (FPGA) integrated circuit. - The memory cell shown in
FIG. 1 may be programmed into one of two states. In the first state, the n-channel non-volatile transistor is turned on and the p-channel non-volatile transistor is turned off. In this state, the gate of the n-channel switch transistor is grounded, turning it off. In the second state, the p-channel non-volatile transistor is turned on and the re-channel non-volatile transistor is turned off. In this state, the gate of the n-channel switch transistor is at approximately VDD, turning it on. - In the case of flash non-volatile memory transistors, the p-channel non-volatile transistor is programmed by placing a negative voltage, such as −4v, on the source of the p-channel non-volatile transistor, placing a positive voltage such as 8.5v on its gate, while its bulk is biased at a voltage such as 1.2v. The gate and source of the p-channel non-volatile transistor are biased at 0v during this procedure.
- The n-channel flash non-volatile transistor is programmed by placing a voltage such as 8.5v, on its gate, and placing a voltage such as 4.5v on its source. The gate of the p-channel non-volatile transistor is biased at a voltage such as −3.3v and its source is biased at a voltage such as 0v during this procedure.
-
FIG. 1 is a schematic diagram of an illustrative prior-art push-pull non-volatile memory cell. -
FIG. 2 is a schematic diagram of an illustrative push-pull non-volatile memory cell according to one aspect of the present invention. -
FIG. 3 is a schematic diagram of a portion of an illustrative array of push-pull non-volatile memory cells according to one aspect of the present invention. -
FIG. 4 is a schematic diagram of an illustrative push-pull non-volatile memory cell according to one aspect of the present invention. -
FIG. 5 is a schematic diagram of a portion of an illustrative array of push-pull non-volatile memory cells according to one aspect of the present invention. - Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.
- Referring now to
FIG. 2 , a schematic diagram shows an illustrative push-pull non-volatileflash memory cell 10 according to one aspect of the present invention.Memory cell 10 includes a p-channel flash transistor 12 connected in series with an n-channel flash transistor 14. An n-channel switch transistor 16 has its gate connected to the common drain connections of the p-channel flash transistor 12 and the n-channel flash transistor 14. The n-channel switch transistor may be used to make programmable connections between circuit nodes coupled to its source and drain to form programmable circuits as is known in the art. An additional n-channel assist transistor 18 has its drain connected to the common drain connections of the p-channel flash transistor 12 and the n-channel flash transistor 14 and its source connected to ground. The p-channel non-volatile memory transistor and the n-channel non-volatile transistor are disclosed in the specific example herein as employing flash technology, but persons of ordinary skill in the art will appreciate that they may be fabricated as floating-gate flash transistors or may be fabricated using other known non-volatile transistor technologies. - To program p-
channel flash transistor 12, a voltage such as 8.5v is applied to its control gate, a negative voltage such as −4v is applied to its source, and a voltage such as 1.2 v is applied to the n-well in which p-channel flash transistor 12 is formed. Ground potential (0v) is applied to the control gate of n-channel flash transistor 14 and to the gate of n-channel assist transistor 18. The drain of n-channel flash transistor 14 may be left floating. The p-channel flash transistor is programmed using band-to-band (BTB) programming. - To program n-
channel flash transistor 14, a voltage such as 8.5v is applied to its control gate, and a voltage such as 4.5v is applied to its source. Ground potential (0v) is applied to the source of the p-channel flash transistor 12 and a negative voltage such as −3.3v is applied to its control gate. A voltage such as 3.3v is applied to the gate of n-channel assist transistor 18. The n-channel flash transistor 14 is programmed using hot carrier injection (HCl) programming. The n-channel assist transistor 18 in thememory cell 10 is employed to pass HCl programming current for programming the n-channel flash transistor 14 in the cell. The programming voltages suggested forprogramming transistors memory transistors - Referring now to
FIG. 3 , a schematic diagram shows aportion 20 of an illustrative array of push-pull non-volatile memory cells according to one aspect of the present invention. Theportion 20 of the array shown inFIG. 3 includes memory cells 10-1 and 10-2 in a first row of the array, and memory cells 10-3 and 10-4 in a second row of the array. Memory cells 10-1 and 10-3 are in a first column of the array and memory cells 10-2 and 10-4 are in a second column of the array. - The control gates of p-channel flash transistors 12-1 and 12-2 in memory cells 10-1 and 10-2 in the first row of the array are connected together to a p-
channel row line 22. The control gates of n-channel flash transistors 14-1 and 14-2 in memory cells 10-1 and 10-2 are connected together to an n-channel row line 24. The gates of n-channel assist transistors 18-1 and 18-2 in memory cells 10-1 and 10-2 are connected to arow line 26. The control gates of p-channel flash transistors 12-3 and 12-4 in memory cells 10-3 and 10-4 in the second row of the array are connected together to a p-channel row line 28. The control gates of n-channel flash transistors 14-3 and 14-4 in memory cells 10-3 and 10-4 are connected together to an n-channel row line 30. The gates of n-channel assist transistors 18-3 and 18-4 in memory cells 10-3 and 10-4 are connected to arow line 32. - The sources of p-channel flash transistors 12-1 and 12-3 in memory cells 10-1 and 10-3 in the first column of the array are connected together to a p-
channel column line 34. The sources of n-channel flash transistors 14-1 and 14-3 in memory cells 10-1 and 10-3 are connected together to an n-channel column line 36. The sources of p-channel flash transistors 12-2 and 12-4 in memory cells 10-2 and 10-4 in the second column of the array are connected together to a p-channel column line 38. The sources of n-channel flash transistors 14-2 and 14-3 in memory cells 10-2 and 10-4 are connected together to an n-channel column line 40. - When programming the p-channel flash transistors in the array, the p-channel row lines containing cells that are unselected are driven to 0v. The p-channel and n-channel column lines containing cells that are unselected are driven to a voltage that will minimize gate disturb of the memory cells on the unselected column lines, such as about 2-5 volts. When programming the n-channel flash transistors in the array, the n-channel row lines containing cells that are unselected are driven to 0v. The p-channel and n-channel column lines containing cells that are unselected are driven to a voltage that will minimize gate disturb of the memory cells on the unselected column lines, such as about 2-5 volts.
- To simultaneously erase both the p-channel and n-channel flash transistors in all of memory cells 10-1 through 10-4, a negative voltage such as −8.5 volts is applied to all of
row lines channel column lines - The erase mechanism of the memory cells of the present invention is Fowler-Nordheim tunneling (FN). Because of this, the p-channel and n-
channel flash transistors - The memory cell of
FIG. 2 has the advantage that an independent read of the status of the n-channel and p-channel transistors transistors channel transistors channel transistors - Referring now to
FIG. 4 , a schematic diagram shows an illustrative push-pullnon-volatile memory cell 50 according to another aspect of the present invention.Memory cell 50 is almost identical tomemory cell 10 ofFIG. 2 and includes a p-channel flash transistor 12 connected in series with an n-channel flash transistor 14. An n-channel switch transistor 16 has its gate connected to the common drain connections of the p-channel flash transistor 12 and the n-channel flash transistor 14. An additional n-channel assist transistor 18 has its drain connected to the common drain connections of the p-channel flash transistor 12 and the n-channel flash transistor 14 and its source connected to ground. The difference betweenmemory cell 10 ofFIG. 2 andmemory cell 50 ofFIG. 4 is that p-channel flash transistor 12 and the n-channel flash transistor 14 inmemory cell 50 ofFIG. 4 share a common floating gate. - One advantage of the
memory cell 50 ofFIG. 4 is that only the n-channel flash transistor 14 needs to be erased and programmed since it shares its floating gate with the p-channel flash transistor 12. Thus the programming circuitry that needs to be provided is less complicated since it only has to be used to provide the voltages necessary to program there-channel flash transistor 14. - Referring now to
FIG. 5 , a schematic diagram shows aportion 60 of an illustrative array of push-pull non-volatile memory cells according to another aspect of the present invention. Theportion 60 of the array shown inFIG. 5 uses the memory cell depicted inFIG. 4 in which the p-channel and n-channel flash transistors share a common floating gate. - The
portion 60 of the memory cell array shown inFIG. 5 includes memory cells 50-1 and 50-2 in a first row of the array, and memory cells 50-3 and 50-4 in a second row of the array. Memory cells 50-1 and 50-3 are in a first column of the array and memory cells 50-2 and 50-4 are in a second column of the array. - The control gates of p-channel flash transistors 12-1 and 12-2 in memory cells 50-1 and 50-2 in the first row of the array are connected together to a
row line 22. The control gates of n-channel flash transistors 14-1 and 14-2 in memory cells 10-1 and 10-2 are also connected together to p-channel row line 22. Separate row lines for the control gates of each of the p-channel and n-channel flash transistors seen in the embodiment ofFIG. 3 are not used. The gates of n-channel assist transistors 18-1 and 18-2 in memory cells 10-1 and 10-2 are connected to arow line 26. The control gates of p-channel flash transistors 12-3 and 12-4 and n-channel flash transistors 14-3 and 14-4 in memory cells 10-3 and 10-4 in the second row of the array are connected together to arow line 28. The gates of n-channel assist transistors 18-3 and 18-4 in memory cells 10-3 and 10-4 are connected to arow line 32. The row lines are connected to row-access circuitry as is known in the art. - The sources of p-channel flash transistors 12-1 and 12-3 in memory cells 10-1 and 10-3 in the first column of the array are connected together to a p-
channel column line 34. The sources of n-channel flash transistors 14-1 and 14-3 in memory cells 10-1 and 10-3 are connected together to an n-channel column line 36. The sources of p-channel flash transistors 12-2 and 12-4 in memory cells 10-2 and 10-4 in the second column of the array are connected together to a p-channel column line 38. The sources of n-channel flash transistors 14-2 and 14-3 in memory cells 10-2 and 10-4 are connected together to an n-channel column line 40. - To program memory cells in the array of
FIG. 5 , the p-channel column lines channel column lines lines row lines row lines - In order to simultaneously erase all of the memory cells in
array 50, all of the column lines 34, 36, 38, and 40 are allowed to float. A voltage such as 7v is applied to the wells containing the n-channel and p-channel flash transistors. A negative voltage such as −8.5v is applied to the control gates of the n-channel and p-channel flash transistors onrow lines row lines - During normal operation, 0v is applied to the gates of the n-channel assist transistors 18-1 through 18-4 to turn them off. A voltage such as 3.3v is applied to p-
channel column lines channel column lines row lines - While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.
Claims (1)
1. A flash memory cell including:
a p-channel flash transistor having a source, a drain, a floating gate, and a control gate;
an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate;
a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain; and
an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.
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US12/903,493 US20110024821A1 (en) | 2008-12-12 | 2010-10-13 | Push-pull fpga cell |
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US12/334,059 US7839681B2 (en) | 2008-12-12 | 2008-12-12 | Push-pull FPGA cell |
US12/903,493 US20110024821A1 (en) | 2008-12-12 | 2010-10-13 | Push-pull fpga cell |
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US12/334,059 Continuation US7839681B2 (en) | 2008-12-12 | 2008-12-12 | Push-pull FPGA cell |
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US12/334,059 Active 2029-06-04 US7839681B2 (en) | 2008-12-12 | 2008-12-12 | Push-pull FPGA cell |
US12/903,493 Abandoned US20110024821A1 (en) | 2008-12-12 | 2010-10-13 | Push-pull fpga cell |
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US20100157688A1 (en) * | 2008-12-23 | 2010-06-24 | Actel Corporation | Push-pull memory cell configured for simultaneous programming of n-channel and p-channel non-volatile transistors |
US20100208520A1 (en) * | 2009-02-13 | 2010-08-19 | Actel Corporation | Array and control method for flash based fpga cell |
US20110001116A1 (en) * | 2009-07-02 | 2011-01-06 | Actel Corporation | Back to back resistive random access memory cells |
US20140332048A1 (en) * | 2013-05-08 | 2014-11-13 | Vern Green Power Solutions, Llc | Thermoelectric device |
US10128852B2 (en) | 2015-12-17 | 2018-11-13 | Microsemi SoC Corporation | Low leakage ReRAM FPGA configuration cell |
US10147485B2 (en) | 2016-09-29 | 2018-12-04 | Microsemi Soc Corp. | Circuits and methods for preventing over-programming of ReRAM-based memory cells |
US10522224B2 (en) | 2017-08-11 | 2019-12-31 | Microsemi Soc Corp. | Circuitry and methods for programming resistive random access memory devices |
US10546633B2 (en) | 2016-12-09 | 2020-01-28 | Microsemi Soc Corp. | Resistive random access memory cell |
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US9947677B1 (en) * | 2017-02-21 | 2018-04-17 | International Business Machines Corporation | High-density EEPROM arrays having parallel-connected common-floating-gate NFET and PFET as memory cell |
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