US20110073833A1 - Resistance memory element and method of manufacturing the same - Google Patents
Resistance memory element and method of manufacturing the same Download PDFInfo
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- US20110073833A1 US20110073833A1 US12/960,605 US96060510A US2011073833A1 US 20110073833 A1 US20110073833 A1 US 20110073833A1 US 96060510 A US96060510 A US 96060510A US 2011073833 A1 US2011073833 A1 US 2011073833A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/028—Formation of the switching material, e.g. layer deposition by conversion of electrode material, e.g. oxidation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
Definitions
- the present invention relates to a resistance memory element, more specifically, a resistance memory element memorizing a plurality of resistance states of different resistance values, and a method of manufacturing the same.
- RRAM Resistive Random Access Memory
- the RRAM uses a resistance memory element which has a plurality of resistance states of different resistance values, which are changed by electric stimulations applied from the outside and whose high resistance state and low resistance state are corresponded to, e.g., information “0” and “1” to be used as a memory element.
- the RRAM highly potentially has high speed, large capacities, low electric power consumption, etc. and is considered prospective.
- the resistance memory element has a resistance memory material whose resistance states are changed by the application of voltages sandwiched between a pair of electrodes.
- a resistance memory material oxide materials containing transition metals are known.
- RRAM uses the resistance memory element whose high resistance state and low resistance state are reversibly changed by application of voltages, but its operational mechanism has not be cleared.
- the inventors of the present application have an idea as one operational mechanism of the resistance memory element that the filament-shaped property changed (current path) formed in the resistance memory material would contribute.
- This filament-shaped current path would be formed in a part where an electric field is locally concentrated, and the structure of the conventional resistance memory element, which is similar to the parallel plate capacitor, has found difficult to control the position and the density of the filament-shaped current path. This would be a barrier to further improving the density.
- a resistance memory element comprising: a pair of electrodes, and an insulating film sandwiched between the pair of electrodes, wherein at least one of the pair of electrodes has a plurality of cylindrical electrodes of a cylindrical structure of carbon in a region thereof, which is in contact with the insulating film.
- a semiconductor memory device comprising: a memory cell transistor; and a resistance memory element including: a pair of electrodes one of which is connected to the memory cell transistor; an insulating film sandwiched between the pair of electrodes, wherein at least one of the pair of electrodes has a plurality of cylindrical electrodes of a cylindrical structure of carbon in a region thereof, which is in contact with the insulating film.
- a method of manufacturing a resistance memory element comprising the steps of: forming a lower electrode over a substrate; forming an insulating film on the lower electrode; forming a plurality of cylindrical electrodes of a cylindrical structure of carbon on the insulating film; and forming an upper electrode electrically connected to the plurality of cylindrical electrodes on the plurality of cylindrical electrodes.
- a method of manufacturing a resistance memory element comprising the steps of: forming a lower electrode over a substrate; forming a plurality of cylindrical electrodes of a cylindrical structure of carbon electrically connected to the lower electrode on the lower electrode; forming an insulating film on the plurality of cylindrical electrodes; and forming an upper electrode on the insulating film.
- FIG. 1 is a diagrammatic sectional view showing the structure of the resistance memory element according to a first embodiment of the present invention
- FIG. 2 is a graph showing the current-voltage characteristics of the resistance memory element according to the first embodiment of the present invention
- FIGS. 3A-3F are sectional views showing the method of manufacturing the resistance memory element according to the first embodiment of the present invention.
- FIG. 4 is a diagrammatic sectional view showing the structure the resistance memory element according to a second embodiment of the present invention.
- FIGS. 5A-5E are sectional views showing the method of manufacturing the resistance memory element according to the second embodiment of the present invention.
- FIG. 6 is a diagrammatic sectional view showing the structure of the resistance memory element according to a third embodiment of the present invention.
- FIGS. 7A-7F are sectional views showing the method of manufacturing the resistance memory element according to the third embodiment of the present invention.
- FIG. 8 is a diagrammatic sectional view showing the structure of the nonvolatile semiconductor memory according to a fourth embodiment of the present invention.
- the resistance memory element and the method of manufacturing the same according to a first embodiment of the present invention will be explained with reference to FIGS. 1 to 3F .
- FIG. 1 is a diagrammatic sectional view showing the structure of the resistance memory element according to the present embodiment.
- FIG. 2 is a graph showing the current-voltage characteristics of the resistance memory element according to the present embodiment.
- FIGS. 3A-3F are sectional views showing the method of manufacturing the resistance memory element according to the present embodiment.
- a lower electrode 12 is formed.
- a resistance memory layer 14 of a resistance memory material is formed on the substrate 10 with the lower electrode 12 and the resistance memory layer 14 formed on.
- an insulating film 16 with an opening 18 formed down to the resistance memory layer 14 is formed on the substrate 10 with the lower electrode 12 and the resistance memory layer 14 formed on.
- a catalyst metal layer 20 containing a plurality of catalytic metal isles 20 a is formed on the resistance memory layer 14 in the opening 18 .
- carbon nanotubes 22 are formed on the catalytic metal isles 20 a .
- a plurality of cylindrical electrodes 24 of the catalytic metal isles 20 a and the carbon nanotubes 22 are formed in the opening 18 with the cylindrical electrodes 24 formed in.
- an insulating film 26 is buried with the upper parts of the cylindrical electrodes 24 exposed. Over the insulating films 16 , 26 , an upper electrode 18 electrically connected to the cylindrical electrodes 24 is formed.
- the cylindrical electrodes 24 of the catalytic metal isles 20 a and the carbon nanotubes 22 are formed between the resistance memory layer 14 and the upper electrode 18 .
- the cylindrical electrodes 14 are thus formed, whereby the position and the density of the filament-shaped current path to be formed in the resistance memory layer 14 is defined by the positions and the density of the cylindrical electrodes 14 .
- the positions and the density of the cylindrical electrode 24 are suitably controlled, whereby the position and the density of the filament-shaped current path can be controlled.
- the write current flows, concentrated in the location where the cylindrical electrode 24 are formed, which allows the writing to be made with lower operation voltages.
- the positions and the density of the cylindrical electrodes 24 can be controlled by the density of the catalytic metal layer 20 for forming the carbon nanotubes 22 and the formation probability (activation ratio) of the carbon nanotubes 22 on the catalytic metal layer 20 .
- the density of the catalytic metal layer 20 and the activation ratio of the carbon nanotubes 22 on the catalytic metal layer 20 can be controlled by conditions for forming the catalytic metal layer 20 and the carbon nanotubes 22 .
- FIG. 2 is a graph showing the current-voltage characteristics of the resistance memory element according to the present embodiment.
- the resistance memory element according to the present embodiment has the RRAM characteristic that the high resistance state and the low resistance state are switched by the application of voltages. That is, an about ⁇ 0.4 V write voltage is applied to the resistance memory element in the low resistance state of about 10.OMEGA., whereby the resistance memory element can be transited (reset) to the high resistance state of an about 160.OMEGA.. An about 0.6 V write voltage is applied to the resistance memory element in the high resistance state of about 160.OMEGA., whereby the resistance memory element can be transited (set) to the low resistance state of about 10.OMEGA..
- a 100 nm-thickness copper (Cu) film 12 a for example, a 5 nm-thickness tantalum (Ta) film 12 b , for example, and a 30 nm-thickness titanium oxide (TiO 2 ) film 14 a , for example, are deposited by, e.g., sputtering method or evaporation method ( FIG. 3A ).
- the substrate includes a semiconductor substrate itself, such as a silicon substrate or others, and also the semiconductor substrate with elements, MOS transistors, etc., interconnections, etc. formed on.
- the TiO 2 film 14 a , the Ta film 12 b and the Cu film 12 a are patterned to form the lower electrode 12 of the Cu film 12 a and the Ta film 12 b , and the resistance memory layer 14 of the TiO 2 film 14 a.
- a 350 nm-thickness silicon oxide (SiO 2 ) film is deposited by, e.g., CVD method.
- SiO 2 silicon oxide
- the insulating film 16 may be dry etched with, e.g., a fluorine-based etching gas. From the viewpoint of decreasing the etching damage to the resistance memory layer 14 , both the dry etching and the wet etching with, e.g., a hydrofluoric acid-based aqueous solution may be used.
- the catalytic metal layer 20 of a plurality of catalytic metal isles 20 a formed isolated from each other is formed ( FIG. 3C ).
- the catalytic metal layer 20 may be formed by depositing Cobalt (Co) corresponding to, e.g., a 1 nm-thickness by, e.g., sputtering method or evaporation method. After the Co deposition, annealing of a temperature as high as, e.g., about 400° C. is made to aggregate the deposited Co, and the catalytic metal isles 20 a of particulate Co are formed isolated from each other.
- Co Cobalt
- the catalytic metal layer 20 can be formed selectively in the opening 18 by lift-off method using the photoresist film used in forming the opening 18 in the insulating film 16 .
- the density of the catalytic metal layer 20 can be controlled by conditions (temperature and processing period of time) of the annealing.
- the metal material forming the catalytic metal layer 20 can be, other than Co, iron (Fe), nickel (Ni) or an alloy containing these metals.
- the catalytic metal layer 20 may be formed by blowing particles of a catalytic metal other than by using the aggregation of the thin film.
- the catalytic metal layer 20 may be formed as a particulate catalyst by laser ablation method or others with the density being controlled. At this time, the density can be controlled by the deposition period of time.
- the carbon nanotubes 22 are grown.
- the carbon nanotubes 22 are grown by thermal CVD method, e.g., under the conditions of the reaction gas of a mixed gas of acetylene and hydrogen, the acetylene flow rate of 80 sccm, the hydrogen flow rate of 20 sccm, the film forming chamber pressure of 200 Pa and the substrate temperature of 900° C.
- the carbon nanotubes 22 are grown by thermal filament CVD method, wherein the gas dissociation is made by a thermal filament, e.g., under the conditions of the reaction gas of a mixed gas of acetylene and hydrogen, the acetylene flow rate of 80 sccm, the hydrogen flow rate of 20 sccm, the film forming chamber pressure of 1000 Pa, the substrate temperature of 600° C. and the thermal filament temperature of 1800° C.
- the carbon nanotubes 22 may be grown by DC plasma thermal filament CVD method, in which a DC plasma and a thermal filament are combined, e.g., under the conditions of the reaction gas of a mixed gas of acetylene and hydrogen, the acetylene flow rate of 80 sccm, the hydrogen flow rate of 20 sccm, the film forming chamber pressure of 1000 Pa, the substrate temperature of 600° C. and the thermal filament temperature of 1800° C.
- a DC plasma and a thermal filament are combined, e.g., under the conditions of the reaction gas of a mixed gas of acetylene and hydrogen, the acetylene flow rate of 80 sccm, the hydrogen flow rate of 20 sccm, the film forming chamber pressure of 1000 Pa, the substrate temperature of 600° C. and the thermal filament temperature of 1800° C.
- 1400 V DC current is applied to the substrate 10 with the film forming chamber being the ground potential.
- the DC current is applied between the chamber and the substrate 10 , whereby the carbon nanotubes oriented vertically (along the normal direction of the substrate) can be formed.
- the carbon nanotubes are not essentially grown as described above but may be grown by, e.g., RF plasma CVD method.
- the activation ratio of the carbon nanotubes 22 can be controlled by the ratio of acetylene and hydrogen or the growth temperature.
- a plurality of cylindrical electrodes 24 of the catalytic metal isles 20 a and the carbon nanotubes 22 are formed.
- a 500 nm-thickness SiO 2 film for example, is deposited by, e.g., CVD method.
- the insulating film 26 of the SiO 2 film is formed ( FIG. 3D ).
- the opening 18 with the cylindrical electrodes 24 formed in is filled with the insulating film 26 .
- the insulating films 26 , 16 are polished by, e.g., chemical mechanical polishing (CMP) method until the upper ends of the cylindrical electrodes 24 are exposed ( FIG. 3E ).
- CMP chemical mechanical polishing
- a 10 nm-thickness titanium (Ti) film 28 for example, and a 100 nm-thickness Cu film 28 , for example, are deposited by, e.g., sputtering method or evaporation method.
- the Cu film 28 b and the Ti film 28 a are patterned by photolithography and ion milling to form the upper electrodes 28 of the Ti film 28 a and the Cu film 28 b , electrically connected to the cylindrical electrodes 24 ( FIG. 3F ).
- the cylindrical electrodes of the carbon nanotubes are provided in the region of the upper electrode, which is contact with the resistance memory layer, which permits the position and the density of the filament-shaped current path which contributes to the resistance states of the resistance memory element to be controlled by the positions and the density of the cylindrical electrodes.
- the resistance memory element and the method of manufacturing the same according to a second embodiment of the present invention will be explained with reference to FIGS. 4 to 5E .
- the same members as those of the resistance memory element according to the first embodiment shown in FIGS. 1 to 3F are represented by the same reference numbers not to repeat or to simplify their explanation.
- FIG. 4 is a diagrammatic sectional view showing the structure of the resistance memory element according to the present embodiment.
- FIGS. 5A-5E are sectional views showing the method of manufacturing the resistance memory element according to the present embodiment.
- a lower electrode 12 is formed. Over the substrate 10 with the lower electrode 12 formed on, an insulating film 16 with an opening 18 down to the lower electrode 12 formed in is formed. On the lower electrode 12 in the opening 18 , a resistance memory layer 14 is formed. On the resistance memory layer 14 , a catalytic metal layer 20 containing a plurality of catalytic metal isles 20 a is formed. On the catalytic metal isles 20 a , carbon nanotubes 22 are formed. Thus, a plurality of cylindrical electrodes 24 of the catalytic metal isles 20 a and a plurality of cylindrical electrodes 24 are formed. In the opening 18 with the cylindrical electrodes 24 formed in, an insulating film 26 is buried with the upper parts of the cylindrical electrodes 24 exposed. Over the insulating films 16 , 26 , an upper electrode 28 electrically connected to the cylindrical electrodes 24 is formed.
- the resistance memory element according to the present embodiment is the same as the resistance memory element according to the first embodiment except that the resistance memory layer 14 is formed selectively on the lower electrode 12 in the opening 18 .
- the cylindrical electrodes 24 of the carbon nanotubes 22 are formed between the resistance memory layer 14 and the upper electrode 28 , and the position and the density of the filament-shaped current path to be formed in the resistance memory layer 14 can be controlled by the positions and the density of the cylindrical electrodes 24 .
- a 100 nm-thickness Cu film 12 a for example, and a 5 nm-thickness Ta film 12 b , for example, are deposited by, e.g., sputtering method or evaporation method ( FIG. 5A ).
- the Ta film 12 b and the Cu film 12 a are patterned to form the lower electrode 12 of the Cu film 12 a and the Ta film 12 b.
- a 350 nm-thickness SiO 2 film for example, is deposited by, e.g., CVD method.
- the insulating film 16 of the SiO 2 film is formed ( FIG. 5B ).
- the opening 18 down to the lower electrode 12 is formed in the insulating film 16 .
- a Ti film 14 b , and the catalytic metal layer 20 of a plurality of catalytic metal isles 20 a formed isolated from each other is formed ( FIG. 5C ).
- the Ti film 14 b may be formed by depositing Ti in, e.g., a 2 nm-thickness by, e.g., sputtering method or evaporation method.
- the catalytic metal layer 20 is formed by, as in the first embodiment, depositing Co in, e.g., a 1 nm-thickness by, e.g., sputtering method or evaporation method and annealing the same.
- the Ti film 14 b and the catalytic metal layer 20 can be formed selectively in the opening 18 by lift-off using the photoresist film used in forming the opening 18 in the insulating film 16 .
- the film formed on the lower electrode 12 (Ti film 14 b ) is formed of a metal material whose oxide is the resistance memory material, e.g., Ti, Ni or others.
- the carbon nanotubes 22 are grown.
- the Ti film 14 b is oxidized by oxygen, etc. residing in the film forming chamber to be TiO x (0 ⁇ x ⁇ 2) film.
- the resistance memory layer 14 of TiO x is formed.
- oxygen gas may be positively fed into the reaction chamber so as to oxidize the Ti film 14 b .
- the step of oxidizing the Ti film 14 b may be made separately from the step of forming the carbon nanotubes 22 .
- a plurality of cylindrical electrodes 24 of the catalytic metal isles 20 a and the carbon nanotubes 22 is formed ( FIG. 5D ).
- the insulating film 26 and the upper electrode 28 are formed, and the resistance memory element according to the present embodiment is completed ( FIG. 5E ).
- the resistance memory element including the resistance memory layer sandwiched between the lower electrode and the upper electrode includes the cylindrical electrodes of the carbon nanotubes in the region of the upper electrode, which is in contact with the resistance memory layer, which permits the position and the density of the filament-shaped current path which contributes to the resistance states of the resistance memory element to be controlled by the positions and the density of the cylindrical electrodes.
- the resistance memory element and the method of manufacturing the same according to a third embodiment of the present invention will be explained with reference to FIGS. 6 to 7F .
- the same members of the present embodiment as those of the resistance memory element according to the first and the second embodiments shown in FIGS. 1 to 5E are represented by the same reference numbers not to repeat or to simplify their explanation.
- FIG. 6 is a diagrammatic sectional view showing the structure of the resistance memory element according to the present embodiment.
- FIGS. 7A-7F are sectional views showing the method of manufacturing the resistance memory element according to the present embodiment.
- a lower electrode 12 is formed over a substrate 10 .
- an insulating film 16 with an opening 18 formed down to the lower electrode 12 is formed.
- a catalytic metal layer 20 containing a plurality of catalytic metal isles 20 a is formed on the lower electrode 12 in the opening 18 .
- carbon nanotubes 22 are formed on the catalytic metal isles 20 a .
- a plurality of cylindrical electrodes 24 of the catalytic metal isles 20 a and the carbon nanotubes 22 are formed in the opening 18 with the cylindrical electrodes 24 formed in, an insulating film 26 is buried with the upper parts of the cylindrical electrodes 24 exposed.
- a resistance memory layer 14 which is in contact with the cylindrical electrodes 24 is formed.
- an upper electrode 28 is formed on the insulating films 16 , 26 .
- the cylindrical electrodes 24 of the catalytic metal isles 20 a and the carbon nanotubes 22 are formed between the lower electrode 12 and the resistance memory layer 14 .
- the position and the density of the filament-shaped current path to be formed in the resistance memory layer 14 is defined by the positions and the density of the cylindrical electrode 24 . Accordingly, the positions and the density of the cylindrical electrodes 24 are suitably controlled, whereby the position and the density of the filament-shaped current path can be controlled.
- a 100 nm-thickness Cu film 12 a for example, and a 5 nm-thickness Ta film 12 b , for example, are deposited by, e.g., sputtering method or evaporation method ( FIG. 7A ).
- the Ta film 12 b and the Cu film 12 a are patterned by photolithography and ion milling to form the lower electrode 12 of the Cu film 12 a and the Ta film 12 b.
- a 350 nm-thickness SiO 2 film for example, is deposited by, e.g., CVD method.
- the insulating film 16 of the SiO 2 film is formed ( FIG. 7B ).
- the opening 18 down to the lower electrode 12 is formed in the insulating film 16 .
- the catalytic metal layer 20 of a plurality of catalytic metal isles 20 a formed isolated from each other is formed ( FIG. 7C ).
- the catalytic metal layer 20 is formed by, as in the first embodiment, depositing Co in, e.g., a 1 nm-thickness by, e.g., sputtering method or evaporation method and annealing the same.
- the catalytic metal layer 20 can be formed selectively in the opening 18 by lift-off using the photoresist film used in forming the opening 18 in the insulating film 16 .
- the carbon nanotubes 22 are grown.
- a plurality of cylindrical electrodes 24 of the catalytic metal isles 20 a and the carbon nanotubes 22 are formed in the opening 18 .
- a 500 nm-thickness SiO 2 film for example, is deposited on the entire surface by, e.g., CVD method.
- the insulating film 26 of the SiO 2 film is formed ( FIG. 7D ).
- the insulating film 26 is buried.
- the insulating films 26 , 16 are polished by, e.g., CMP method until the upper ends of the cylindrical electrodes 24 are exposed ( FIG. 7E ).
- a 30 nm-thickness TiO 2 film for example, a 10 nm-thickness Ti film, for example, and a 100 nm-thickness Cu film, for example, are deposited by, e.g., sputtering method or evaporation method.
- the Cu film, the Ti film and the TiO 2 film are patterned by photolithography and ion milling to form the resistance memory layer 14 of the TiO 2 film and the upper electrode 28 of the Ti film and the Cu film, and the resistance memory element according to the present embodiment is completed ( FIG. 7F ).
- the resistance memory element including the resistance memory layer sandwiched between the lower electrode and the upper electrode includes the cylindrical electrodes of the carbon nanotubes in the region of the lower electrode, which is in contact with the resistance memory layer, whereby the position and the density of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes.
- the nonvolatile semiconductor memory device according to a fourth embodiment of the present invention will be explained with reference to FIG. 8 .
- FIG. 8 is a diagrammatic sectional view showing the structure of the nonvolatile semiconductor memory device according to the present embodiment.
- a device isolation film 32 for defining an active region is formed in a silicon substrate 30 .
- a memory cell transistor including a gate electrode 34 and source/drain regions 36 , 38 are formed in the active region defined by the device isolation film 32 .
- an inter-layer insulating film 40 is formed over the silicon substrate 30 with the memory cell transistor formed on.
- an inter-layer insulating film 40 is formed in the inter-layer insulating film 40 .
- a contact plug 42 connected to the source/drain region is buried.
- a source line 44 electrically connected to the source/drain region 36 via the contact plugs 42 is formed on the inter-layer insulating film 40 .
- an inter-layer insulating film 46 is formed over the inter-layer insulating film 40 with the source line 44 formed on.
- an inter-layer insulating film 46 is formed in the inter-layer insulating films 46 , 40 .
- a contact plug 48 connected to the source/drain region 38 is buried.
- a lower electrode 52 electrically connected to the source/drain region 38 via the contact plug 48 is formed.
- a resistance memory layer 54 is formed on the lower electrodes 52 .
- an inter-layer insulating film 60 with an opening 62 formed down to the resistance memory layer 54 is formed on the inter-layer insulating film 46 with the lower electrodes 52 and the resistance memory layer 54 formed on.
- an inter-layer insulating film 60 with an opening 62 formed down to the resistance memory layer 54 is formed in the opening 62 .
- a plurality of cylindrical electrodes 56 is formed in the gaps among the cylindrical electrodes 56 in the openings 62 .
- an upper electrode 58 connected to the cylindrical electrodes 56 is formed.
- the resistance memory element according to the first embodiment including the lower electrode 52 connected to the contact plug 48 , the resistance memory layer 54 formed on the lower electrode 52 , the cylindrical electrodes 56 formed on the resistance memory layer 54 , and the upper electrodes 58 connected to the cylindrical electrodes 56 are formed.
- an inter-layer insulating film 66 is formed over the inter-layer insulating film 60 with the upper electrode 58 formed on.
- a contact plug 68 connected to the upper electrode 58 is buried.
- a bit line 70 connected to the upper electrodes 68 of the resistance memory element 50 is formed.
- the nonvolatile semiconductor memory device comprising memory cells each including the memory cell transistor and the resistance memory element 50 is constituted.
- the resistance memory element of the nonvolatile semiconductor memory using the resistance memory element As the resistance memory element of the nonvolatile semiconductor memory using the resistance memory element, the resistance memory element according to the first embodiment is used, which facilitates the downsizing of the resistance memory element, and resultantly the nonvolatile semiconductor memory can be highly integrated.
- the nonvolatile semiconductor memory device using the resistance memory element which includes the resistance memory layer sandwiched between the lower electrode and the upper electrode and memorizes a plurality of resistance states includes the cylindrical electrodes of carbon nanotubes in the region of the upper electrode of the resistance memory element, which is in contact with the resistance memory layer, whereby the position and the density of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrode.
- the integration and high operation speed of the nonvolatile semiconductor memory can be improved.
- the cylindrical electrode 24 is formed of carbon nanotubes 22 , but in place of the carbon nanotubes 22 , other cylindrical structures may be used.
- the cylindrical structure of carbon atoms for example, carbon nanofiber is known in addition to carbon nanotube, and in place of carbon nanotube, carbon nanofiber may be used.
- the catalytic metal used in growing the cylindrical structure of carbon atoms Fe, Ni, etc. other than Co can be used.
- the resistance memory material forming the resistance memory element TiO 2 is used, but the resistance memory material is not limited to TiO 2 .
- the resistance memory materials applicable to the present invention are TiO x , NiO x , YO x , CeO x , MgO x , ZnO x , ZrO x , HfO x , WO x , NbO x , TaO x , CrO x , MnO x , AlO x , VO N , SiO x , etc.
- Oxide materials containing a plurality of metals or semiconductors such as Pr 1-x Ca x MnO 3 , La 1-x Ca x MnO 3 , SrTiO 3 , YBa 2 Cu 3 O y , LaNiO, etc., can be also used. These resistance memory materials may be used singly or in layer structures.
- the lower electrode is formed of the layer film of Cu film and Ta film
- the upper electrode is formed of the layer film of Ti film and Cu film.
- the constituent materials of the electrodes are not limited to them.
- the electrode materials applicable to the present invention are, e.g., Ir, W, Ni, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Ti, Si, TaN, TiN, Ru, ITO, NiO, IrO, SrRuO, CoSi 2 , WSi 2 , NiSi, MoSi 2 , TiSi 2 , Al—Si, Al—Cu, Al—Si—Cu, etc.
- the electrode material is selected suitably for the compatibility with the resistance memory material, etc.
- the resistance memory element of the nonvolatile semiconductor memory device As the resistance memory element of the nonvolatile semiconductor memory device, the resistance memory element according to the first embodiment is used, but the resistance memory element according to the second or the third embodiment may be used.
- the cylindrical electrodes are provided between the resistance memory layer and the upper electrode, and in the third embodiment, the cylindrical electrodes are provided between the lower electrode and the resistance memory layer.
- the cylindrical electrodes may be provided between the resistance memory layer and the upper electrode and between the lower electrode and the resistance memory layer.
- the resistance memory element according to the present invention is applied to RRAM, but the resistance memory element according to the present invention is applicable to nonvolatile semiconductor memory device other than RRAM.
- the resistance memory element according to the present invention is applicable to a read only memory (ROM).
- ROM read only memory
- the resistance memory element whose resistance state is unreversibly changed by once writing may be used.
- a resistance memory element which initially has the high resistance state, has the insulating film broken by the application of a prescribed voltage and has the low resistance state, and hereafter retains the low resistance state is applicable.
- Such resistance memory element may not be formed of the special resistance memory materials as used in RRAM and can be formed of the general insulating materials and semiconductor materials, e.g., silicon oxide film, silicon nitride film, etc.
Abstract
A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes.
Description
- This application is a divisional of application Ser. No. 12/174,868, filed Jul. 17, 2008, which is a Continuation of International Application No. PCT/JP2006/300588, with an international filing date of Jan. 18, 2006, which designating the United States of America, the entire contents of which are incorporated herein by reference.
- The present invention relates to a resistance memory element, more specifically, a resistance memory element memorizing a plurality of resistance states of different resistance values, and a method of manufacturing the same.
- Recently, as a new memory device, a semiconductor memory device called Resistive Random Access Memory (RRAM) is noted. The RRAM uses a resistance memory element which has a plurality of resistance states of different resistance values, which are changed by electric stimulations applied from the outside and whose high resistance state and low resistance state are corresponded to, e.g., information “0” and “1” to be used as a memory element. The RRAM highly potentially has high speed, large capacities, low electric power consumption, etc. and is considered prospective.
- The resistance memory element has a resistance memory material whose resistance states are changed by the application of voltages sandwiched between a pair of electrodes. As the typical resistance memory material, oxide materials containing transition metals are known.
- The related arts are disclosed in, e.g., Japanese published unexamined patent application No. 2003-008105, Japanese published unexamined patent application No. 2004-301548, Japanese published unexamined patent application No. 2005-039228, and S. Q. Liu (“Electrical-pulse-induced reversible resistance change effect in magnetoresistive film”, Appl. Phys. Lett., vol. 76, p. 2749, 2000).
- RRAM uses the resistance memory element whose high resistance state and low resistance state are reversibly changed by application of voltages, but its operational mechanism has not be cleared. The inventors of the present application have an idea as one operational mechanism of the resistance memory element that the filament-shaped property changed (current path) formed in the resistance memory material would contribute.
- This filament-shaped current path would be formed in a part where an electric field is locally concentrated, and the structure of the conventional resistance memory element, which is similar to the parallel plate capacitor, has found difficult to control the position and the density of the filament-shaped current path. This would be a barrier to further improving the density.
- According to one aspect of an embodiment, there is provided a resistance memory element comprising: a pair of electrodes, and an insulating film sandwiched between the pair of electrodes, wherein at least one of the pair of electrodes has a plurality of cylindrical electrodes of a cylindrical structure of carbon in a region thereof, which is in contact with the insulating film.
- According to another aspect of an embodiment, there is provided a semiconductor memory device comprising: a memory cell transistor; and a resistance memory element including: a pair of electrodes one of which is connected to the memory cell transistor; an insulating film sandwiched between the pair of electrodes, wherein at least one of the pair of electrodes has a plurality of cylindrical electrodes of a cylindrical structure of carbon in a region thereof, which is in contact with the insulating film.
- According to further another aspect of an embodiment, there is provided a method of manufacturing a resistance memory element comprising the steps of: forming a lower electrode over a substrate; forming an insulating film on the lower electrode; forming a plurality of cylindrical electrodes of a cylindrical structure of carbon on the insulating film; and forming an upper electrode electrically connected to the plurality of cylindrical electrodes on the plurality of cylindrical electrodes.
- According to further another aspect of an embodiment, there is provided a method of manufacturing a resistance memory element comprising the steps of: forming a lower electrode over a substrate; forming a plurality of cylindrical electrodes of a cylindrical structure of carbon electrically connected to the lower electrode on the lower electrode; forming an insulating film on the plurality of cylindrical electrodes; and forming an upper electrode on the insulating film.
-
FIG. 1 is a diagrammatic sectional view showing the structure of the resistance memory element according to a first embodiment of the present invention; -
FIG. 2 is a graph showing the current-voltage characteristics of the resistance memory element according to the first embodiment of the present invention; -
FIGS. 3A-3F are sectional views showing the method of manufacturing the resistance memory element according to the first embodiment of the present invention; -
FIG. 4 is a diagrammatic sectional view showing the structure the resistance memory element according to a second embodiment of the present invention; -
FIGS. 5A-5E are sectional views showing the method of manufacturing the resistance memory element according to the second embodiment of the present invention; -
FIG. 6 is a diagrammatic sectional view showing the structure of the resistance memory element according to a third embodiment of the present invention; -
FIGS. 7A-7F are sectional views showing the method of manufacturing the resistance memory element according to the third embodiment of the present invention; -
FIG. 8 is a diagrammatic sectional view showing the structure of the nonvolatile semiconductor memory according to a fourth embodiment of the present invention. - The resistance memory element and the method of manufacturing the same according to a first embodiment of the present invention will be explained with reference to
FIGS. 1 to 3F . -
FIG. 1 is a diagrammatic sectional view showing the structure of the resistance memory element according to the present embodiment.FIG. 2 is a graph showing the current-voltage characteristics of the resistance memory element according to the present embodiment.FIGS. 3A-3F are sectional views showing the method of manufacturing the resistance memory element according to the present embodiment. - First, the structure of the resistance memory element according to the present embodiment will be explained with reference to
FIG. 1 . - Over a
substrate 10, alower electrode 12 is formed. On thelower electrode 12, aresistance memory layer 14 of a resistance memory material is formed. On thesubstrate 10 with thelower electrode 12 and theresistance memory layer 14 formed on, aninsulating film 16 with anopening 18 formed down to theresistance memory layer 14 is formed. On theresistance memory layer 14 in theopening 18, acatalyst metal layer 20 containing a plurality ofcatalytic metal isles 20 a is formed. On the catalytic metal isles 20 a,carbon nanotubes 22 are formed. Thus, a plurality ofcylindrical electrodes 24 of the catalytic metal isles 20 a and thecarbon nanotubes 22 are formed. In theopening 18 with thecylindrical electrodes 24 formed in, aninsulating film 26 is buried with the upper parts of thecylindrical electrodes 24 exposed. Over theinsulating films upper electrode 18 electrically connected to thecylindrical electrodes 24 is formed. - As described above, in the resistance memory element according to the present embodiment, the
cylindrical electrodes 24 of thecatalytic metal isles 20 a and thecarbon nanotubes 22 are formed between theresistance memory layer 14 and theupper electrode 18. Thecylindrical electrodes 14 are thus formed, whereby the position and the density of the filament-shaped current path to be formed in theresistance memory layer 14 is defined by the positions and the density of thecylindrical electrodes 14. The positions and the density of thecylindrical electrode 24 are suitably controlled, whereby the position and the density of the filament-shaped current path can be controlled. The write current flows, concentrated in the location where thecylindrical electrode 24 are formed, which allows the writing to be made with lower operation voltages. - The positions and the density of the
cylindrical electrodes 24 can be controlled by the density of thecatalytic metal layer 20 for forming thecarbon nanotubes 22 and the formation probability (activation ratio) of thecarbon nanotubes 22 on thecatalytic metal layer 20. The density of thecatalytic metal layer 20 and the activation ratio of thecarbon nanotubes 22 on thecatalytic metal layer 20 can be controlled by conditions for forming thecatalytic metal layer 20 and thecarbon nanotubes 22. -
FIG. 2 is a graph showing the current-voltage characteristics of the resistance memory element according to the present embodiment. As shown inFIG. 2 , the resistance memory element according to the present embodiment has the RRAM characteristic that the high resistance state and the low resistance state are switched by the application of voltages. That is, an about −0.4 V write voltage is applied to the resistance memory element in the low resistance state of about 10.OMEGA., whereby the resistance memory element can be transited (reset) to the high resistance state of an about 160.OMEGA.. An about 0.6 V write voltage is applied to the resistance memory element in the high resistance state of about 160.OMEGA., whereby the resistance memory element can be transited (set) to the low resistance state of about 10.OMEGA.. - Next, the method of manufacturing the resistance memory element according to the present embodiment will be explained with reference to
FIGS. 3A to 3F . - First, on the
substrate 10, a 100 nm-thickness copper (Cu)film 12 a, for example, a 5 nm-thickness tantalum (Ta)film 12 b, for example, and a 30 nm-thickness titanium oxide (TiO2)film 14 a, for example, are deposited by, e.g., sputtering method or evaporation method (FIG. 3A ). In the specification of the present application, the substrate includes a semiconductor substrate itself, such as a silicon substrate or others, and also the semiconductor substrate with elements, MOS transistors, etc., interconnections, etc. formed on. - Then, by photolithography and ion milling, the TiO2 film 14 a, the
Ta film 12 b and theCu film 12 a are patterned to form thelower electrode 12 of theCu film 12 a and theTa film 12 b, and theresistance memory layer 14 of the TiO2 film 14 a. - The, over the
substrate 10 with thelower electrode 12 and theresistance memory layer 14 formed on, a 350 nm-thickness silicon oxide (SiO2) film, for example, is deposited by, e.g., CVD method. Thus, the insulatingfilm 16 of the SiO2 film is formed (FIG. 3B ). - Then, by photolithography and dry etching, the
opening 18 down to theresistance memory layer 14 is formed in the insulatingfilm 16. The insulatingfilm 16 may be dry etched with, e.g., a fluorine-based etching gas. From the viewpoint of decreasing the etching damage to theresistance memory layer 14, both the dry etching and the wet etching with, e.g., a hydrofluoric acid-based aqueous solution may be used. - Then, on the
resistance memory layer 14 in theopening 18, thecatalytic metal layer 20 of a plurality ofcatalytic metal isles 20 a formed isolated from each other is formed (FIG. 3C ). Thecatalytic metal layer 20 may be formed by depositing Cobalt (Co) corresponding to, e.g., a 1 nm-thickness by, e.g., sputtering method or evaporation method. After the Co deposition, annealing of a temperature as high as, e.g., about 400° C. is made to aggregate the deposited Co, and thecatalytic metal isles 20 a of particulate Co are formed isolated from each other. Thecatalytic metal layer 20 can be formed selectively in theopening 18 by lift-off method using the photoresist film used in forming theopening 18 in the insulatingfilm 16. The density of thecatalytic metal layer 20 can be controlled by conditions (temperature and processing period of time) of the annealing. - The metal material forming the
catalytic metal layer 20 can be, other than Co, iron (Fe), nickel (Ni) or an alloy containing these metals. Thecatalytic metal layer 20 may be formed by blowing particles of a catalytic metal other than by using the aggregation of the thin film. For example, thecatalytic metal layer 20 may be formed as a particulate catalyst by laser ablation method or others with the density being controlled. At this time, the density can be controlled by the deposition period of time. - Then, on the
catalytic metal layer 20, thecarbon nanotubes 22 are grown. Thecarbon nanotubes 22 are grown by thermal CVD method, e.g., under the conditions of the reaction gas of a mixed gas of acetylene and hydrogen, the acetylene flow rate of 80 sccm, the hydrogen flow rate of 20 sccm, the film forming chamber pressure of 200 Pa and the substrate temperature of 900° C. - Otherwise, the
carbon nanotubes 22 are grown by thermal filament CVD method, wherein the gas dissociation is made by a thermal filament, e.g., under the conditions of the reaction gas of a mixed gas of acetylene and hydrogen, the acetylene flow rate of 80 sccm, the hydrogen flow rate of 20 sccm, the film forming chamber pressure of 1000 Pa, the substrate temperature of 600° C. and the thermal filament temperature of 1800° C. - Otherwise, the
carbon nanotubes 22 may be grown by DC plasma thermal filament CVD method, in which a DC plasma and a thermal filament are combined, e.g., under the conditions of the reaction gas of a mixed gas of acetylene and hydrogen, the acetylene flow rate of 80 sccm, the hydrogen flow rate of 20 sccm, the film forming chamber pressure of 1000 Pa, the substrate temperature of 600° C. and the thermal filament temperature of 1800° C. - To vertically orient the
carbon nanotubes 22, 1400 V DC current is applied to thesubstrate 10 with the film forming chamber being the ground potential. The DC current is applied between the chamber and thesubstrate 10, whereby the carbon nanotubes oriented vertically (along the normal direction of the substrate) can be formed. - The carbon nanotubes are not essentially grown as described above but may be grown by, e.g., RF plasma CVD method.
- The activation ratio of the
carbon nanotubes 22 can be controlled by the ratio of acetylene and hydrogen or the growth temperature. - Thus, in the
opening 18, a plurality ofcylindrical electrodes 24 of thecatalytic metal isles 20 a and thecarbon nanotubes 22 are formed. - Next, over the entire surface, a 500 nm-thickness SiO2 film, for example, is deposited by, e.g., CVD method. Thus, the insulating
film 26 of the SiO2 film is formed (FIG. 3D ). Thus, theopening 18 with thecylindrical electrodes 24 formed in is filled with the insulatingfilm 26. - Next, the insulating
films cylindrical electrodes 24 are exposed (FIG. 3E ). - Next, over the entire surface, a 10 nm-thickness titanium (Ti)
film 28, for example, and a 100 nm-thickness Cu film 28, for example, are deposited by, e.g., sputtering method or evaporation method. - Then, the Cu film 28 b and the
Ti film 28 a are patterned by photolithography and ion milling to form theupper electrodes 28 of theTi film 28 a and the Cu film 28 b, electrically connected to the cylindrical electrodes 24 (FIG. 3F ). - As described above, according to the present embodiment, in the resistance memory element including the resistance memory layer sandwiched between the lower electrode and the upper electrode, the cylindrical electrodes of the carbon nanotubes are provided in the region of the upper electrode, which is contact with the resistance memory layer, which permits the position and the density of the filament-shaped current path which contributes to the resistance states of the resistance memory element to be controlled by the positions and the density of the cylindrical electrodes.
- The resistance memory element and the method of manufacturing the same according to a second embodiment of the present invention will be explained with reference to
FIGS. 4 to 5E . The same members as those of the resistance memory element according to the first embodiment shown inFIGS. 1 to 3F are represented by the same reference numbers not to repeat or to simplify their explanation. -
FIG. 4 is a diagrammatic sectional view showing the structure of the resistance memory element according to the present embodiment.FIGS. 5A-5E are sectional views showing the method of manufacturing the resistance memory element according to the present embodiment. - First, the structure of the resistance memory element according to the present embodiment will be explained with reference to
FIG. 4 . - Over a
substrate 10, alower electrode 12 is formed. Over thesubstrate 10 with thelower electrode 12 formed on, an insulatingfilm 16 with anopening 18 down to thelower electrode 12 formed in is formed. On thelower electrode 12 in theopening 18, aresistance memory layer 14 is formed. On theresistance memory layer 14, acatalytic metal layer 20 containing a plurality ofcatalytic metal isles 20 a is formed. On thecatalytic metal isles 20 a,carbon nanotubes 22 are formed. Thus, a plurality ofcylindrical electrodes 24 of thecatalytic metal isles 20 a and a plurality ofcylindrical electrodes 24 are formed. In theopening 18 with thecylindrical electrodes 24 formed in, an insulatingfilm 26 is buried with the upper parts of thecylindrical electrodes 24 exposed. Over the insulatingfilms upper electrode 28 electrically connected to thecylindrical electrodes 24 is formed. - As described above, the resistance memory element according to the present embodiment is the same as the resistance memory element according to the first embodiment except that the
resistance memory layer 14 is formed selectively on thelower electrode 12 in theopening 18. In the resistance memory element according to the present embodiment as well, thecylindrical electrodes 24 of thecarbon nanotubes 22 are formed between theresistance memory layer 14 and theupper electrode 28, and the position and the density of the filament-shaped current path to be formed in theresistance memory layer 14 can be controlled by the positions and the density of thecylindrical electrodes 24. - Then, the method of manufacturing the resistance memory element according to the present embodiment will be explained with reference to
FIGS. 5A to 5E . - First, on the
substrate 10, a 100 nm-thickness Cu film 12 a, for example, and a 5 nm-thickness Ta film 12 b, for example, are deposited by, e.g., sputtering method or evaporation method (FIG. 5A ). - Next, by photolithography and ion milling, the
Ta film 12 b and theCu film 12 a are patterned to form thelower electrode 12 of theCu film 12 a and theTa film 12 b. - Next, over the
substrate 10 with thelower electrode 12 formed on, a 350 nm-thickness SiO2 film, for example, is deposited by, e.g., CVD method. Thus, the insulatingfilm 16 of the SiO2 film is formed (FIG. 5B ). - Then, by photolithography and dry etching, the
opening 18 down to thelower electrode 12 is formed in the insulatingfilm 16. - Next, on the
lower electrode 12 in theopening 18, aTi film 14 b, and thecatalytic metal layer 20 of a plurality ofcatalytic metal isles 20 a formed isolated from each other is formed (FIG. 5C ). TheTi film 14 b may be formed by depositing Ti in, e.g., a 2 nm-thickness by, e.g., sputtering method or evaporation method. Thecatalytic metal layer 20 is formed by, as in the first embodiment, depositing Co in, e.g., a 1 nm-thickness by, e.g., sputtering method or evaporation method and annealing the same. TheTi film 14 b and thecatalytic metal layer 20 can be formed selectively in theopening 18 by lift-off using the photoresist film used in forming theopening 18 in the insulatingfilm 16. - Here, the film formed on the lower electrode 12 (
Ti film 14 b) is formed of a metal material whose oxide is the resistance memory material, e.g., Ti, Ni or others. - Then, as in the first embodiment, on the
catalytic metal layer 20, thecarbon nanotubes 22 are grown. When thecarbon nanotubes 22 are formed, theTi film 14 b is oxidized by oxygen, etc. residing in the film forming chamber to be TiOx (0<x≦2) film. Thus, theresistance memory layer 14 of TiOx is formed. - When the
carbon nanotubes 22 are formed, in place of using the oxygen residing in the film forming chamber, oxygen gas may be positively fed into the reaction chamber so as to oxidize theTi film 14 b. The step of oxidizing theTi film 14 b may be made separately from the step of forming thecarbon nanotubes 22. - Thus, in the
opening 18, a plurality ofcylindrical electrodes 24 of thecatalytic metal isles 20 a and thecarbon nanotubes 22 is formed (FIG. 5D ). - Then, in the same way as in the method of manufacturing the resistance memory element according to the first embodiment shown in, e.g.,
FIGS. 3D to 3F , the insulatingfilm 26 and theupper electrode 28 are formed, and the resistance memory element according to the present embodiment is completed (FIG. 5E ). - As described above, according to the present embodiment, the resistance memory element including the resistance memory layer sandwiched between the lower electrode and the upper electrode includes the cylindrical electrodes of the carbon nanotubes in the region of the upper electrode, which is in contact with the resistance memory layer, which permits the position and the density of the filament-shaped current path which contributes to the resistance states of the resistance memory element to be controlled by the positions and the density of the cylindrical electrodes.
- The resistance memory element and the method of manufacturing the same according to a third embodiment of the present invention will be explained with reference to
FIGS. 6 to 7F . The same members of the present embodiment as those of the resistance memory element according to the first and the second embodiments shown inFIGS. 1 to 5E are represented by the same reference numbers not to repeat or to simplify their explanation. -
FIG. 6 is a diagrammatic sectional view showing the structure of the resistance memory element according to the present embodiment.FIGS. 7A-7F are sectional views showing the method of manufacturing the resistance memory element according to the present embodiment. - First, the structure of the resistance memory element according to the present embodiment will be explained with reference to
FIG. 6 . - Over a
substrate 10, alower electrode 12 is formed. Over thesubstrate 10 with thelower electrode 12 formed on, an insulatingfilm 16 with anopening 18 formed down to thelower electrode 12 is formed. On thelower electrode 12 in theopening 18, acatalytic metal layer 20 containing a plurality ofcatalytic metal isles 20 a is formed. On thecatalytic metal isles 20 a,carbon nanotubes 22 are formed. Thus, a plurality ofcylindrical electrodes 24 of thecatalytic metal isles 20 a and thecarbon nanotubes 22 are formed. In theopening 18 with thecylindrical electrodes 24 formed in, an insulatingfilm 26 is buried with the upper parts of thecylindrical electrodes 24 exposed. Over the insulatingfilms resistance memory layer 14 which is in contact with thecylindrical electrodes 24 is formed. On theresistance memory layer 14, anupper electrode 28 is formed. - As described above, in the resistance memory element according to the present embodiment, the
cylindrical electrodes 24 of thecatalytic metal isles 20 a and thecarbon nanotubes 22 are formed between thelower electrode 12 and theresistance memory layer 14. With thecylindrical electrodes 24 formed between thelower electrode 12 and theresistance memory layer 14 as well, the position and the density of the filament-shaped current path to be formed in theresistance memory layer 14 is defined by the positions and the density of thecylindrical electrode 24. Accordingly, the positions and the density of thecylindrical electrodes 24 are suitably controlled, whereby the position and the density of the filament-shaped current path can be controlled. - Then, the method of manufacturing the resistance memory element according to the present embodiment will be explained with reference to
FIGS. 7A-7F . - First, over the
substrate 10, a 100 nm-thickness Cu film 12 a, for example, and a 5 nm-thickness Ta film 12 b, for example, are deposited by, e.g., sputtering method or evaporation method (FIG. 7A ). - Next, the
Ta film 12 b and theCu film 12 a are patterned by photolithography and ion milling to form thelower electrode 12 of theCu film 12 a and theTa film 12 b. - Next, over the
substrate 10 with thelower electrode 12 formed on, a 350 nm-thickness SiO2 film, for example, is deposited by, e.g., CVD method. Thus, the insulatingfilm 16 of the SiO2 film is formed (FIG. 7B ). - Then, by photolithography and dry etching, the
opening 18 down to thelower electrode 12 is formed in the insulatingfilm 16. - Next, on the
lower electrode 12 in theopening 18, thecatalytic metal layer 20 of a plurality ofcatalytic metal isles 20 a formed isolated from each other is formed (FIG. 7C ). Thecatalytic metal layer 20 is formed by, as in the first embodiment, depositing Co in, e.g., a 1 nm-thickness by, e.g., sputtering method or evaporation method and annealing the same. Thecatalytic metal layer 20 can be formed selectively in theopening 18 by lift-off using the photoresist film used in forming theopening 18 in the insulatingfilm 16. - Then, as in the first embodiment, on the
catalytic metal layer 20, thecarbon nanotubes 22 are grown. Thus, a plurality ofcylindrical electrodes 24 of thecatalytic metal isles 20 a and thecarbon nanotubes 22 are formed in theopening 18. - Next, a 500 nm-thickness SiO2 film, for example, is deposited on the entire surface by, e.g., CVD method. Thus, the insulating
film 26 of the SiO2 film is formed (FIG. 7D ). Thus, in theopening 18 with thecylindrical electrodes 24 formed in, the insulatingfilm 26 is buried. - Then, the insulating
films cylindrical electrodes 24 are exposed (FIG. 7E ). - Next, over the entire surface, a 30 nm-thickness TiO2 film, for example, a 10 nm-thickness Ti film, for example, and a 100 nm-thickness Cu film, for example, are deposited by, e.g., sputtering method or evaporation method.
- Then, the Cu film, the Ti film and the TiO2 film are patterned by photolithography and ion milling to form the
resistance memory layer 14 of the TiO2 film and theupper electrode 28 of the Ti film and the Cu film, and the resistance memory element according to the present embodiment is completed (FIG. 7F ). - As described above, according to the present embodiment, the resistance memory element including the resistance memory layer sandwiched between the lower electrode and the upper electrode includes the cylindrical electrodes of the carbon nanotubes in the region of the lower electrode, which is in contact with the resistance memory layer, whereby the position and the density of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes.
- The nonvolatile semiconductor memory device according to a fourth embodiment of the present invention will be explained with reference to
FIG. 8 . -
FIG. 8 is a diagrammatic sectional view showing the structure of the nonvolatile semiconductor memory device according to the present embodiment. - In a
silicon substrate 30, adevice isolation film 32 for defining an active region is formed. In the active region defined by thedevice isolation film 32, a memory cell transistor including agate electrode 34 and source/drain regions - Over the
silicon substrate 30 with the memory cell transistor formed on, an inter-layerinsulating film 40 is formed. In the inter-layer insulatingfilm 40, acontact plug 42 connected to the source/drain region is buried. On theinter-layer insulating film 40, asource line 44 electrically connected to the source/drain region 36 via the contact plugs 42 is formed. - Over the inter-layer insulating
film 40 with thesource line 44 formed on, an inter-layerinsulating film 46 is formed. In the inter-layer insulatingfilms contact plug 48 connected to the source/drain region 38 is buried. - Over the inter-layer insulating
film 46, alower electrode 52 electrically connected to the source/drain region 38 via thecontact plug 48 is formed. On thelower electrodes 52, aresistance memory layer 54 is formed. On theinter-layer insulating film 46 with thelower electrodes 52 and theresistance memory layer 54 formed on, an inter-layerinsulating film 60 with anopening 62 formed down to theresistance memory layer 54 is formed. In theopening 62, a plurality ofcylindrical electrodes 56 is formed. In the gaps among thecylindrical electrodes 56 in theopenings 62, an insulatingfilm 64 is buried. - Over the inter-layer insulating
film 60 and the insulatingfilm 64, anupper electrode 58 connected to thecylindrical electrodes 56 is formed. Thus, the resistance memory element according to the first embodiment including thelower electrode 52 connected to thecontact plug 48, theresistance memory layer 54 formed on thelower electrode 52, thecylindrical electrodes 56 formed on theresistance memory layer 54, and theupper electrodes 58 connected to thecylindrical electrodes 56 are formed. - Over the inter-layer insulating
film 60 with theupper electrode 58 formed on, an inter-layerinsulating film 66 is formed. In the inter-layer insulatingfilm 66, acontact plug 68 connected to theupper electrode 58 is buried. Over the inter-layer insulatingfilm 66, abit line 70 connected to theupper electrodes 68 of theresistance memory element 50 is formed. - Thus, the nonvolatile semiconductor memory device comprising memory cells each including the memory cell transistor and the
resistance memory element 50 is constituted. - As the resistance memory element of the nonvolatile semiconductor memory using the resistance memory element, the resistance memory element according to the first embodiment is used, which facilitates the downsizing of the resistance memory element, and resultantly the nonvolatile semiconductor memory can be highly integrated.
- As described above, according to the present embodiment, the nonvolatile semiconductor memory device using the resistance memory element which includes the resistance memory layer sandwiched between the lower electrode and the upper electrode and memorizes a plurality of resistance states includes the cylindrical electrodes of carbon nanotubes in the region of the upper electrode of the resistance memory element, which is in contact with the resistance memory layer, whereby the position and the density of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrode. Thus, the integration and high operation speed of the nonvolatile semiconductor memory can be improved.
- The present invention is not limited to the above-described embodiments and can cover other various modifications.
- For example, in the above-described embodiments, the
cylindrical electrode 24 is formed ofcarbon nanotubes 22, but in place of thecarbon nanotubes 22, other cylindrical structures may be used. As the cylindrical structure of carbon atoms, for example, carbon nanofiber is known in addition to carbon nanotube, and in place of carbon nanotube, carbon nanofiber may be used. As the catalytic metal used in growing the cylindrical structure of carbon atoms, Fe, Ni, etc. other than Co can be used. - In the above-described embodiments, as the resistance memory material forming the resistance memory element, TiO2 is used, but the resistance memory material is not limited to TiO2. As the resistance memory materials applicable to the present invention are TiOx, NiOx, YOx, CeOx, MgOx, ZnOx, ZrOx, HfOx, WOx, NbOx, TaOx, CrOx, MnOx, AlOx, VON, SiOx, etc. Oxide materials containing a plurality of metals or semiconductors, such as Pr1-xCaxMnO3, La1-xCaxMnO3, SrTiO3, YBa2Cu3Oy, LaNiO, etc., can be also used. These resistance memory materials may be used singly or in layer structures.
- In the above-described embodiments, the lower electrode is formed of the layer film of Cu film and Ta film, and the upper electrode is formed of the layer film of Ti film and Cu film. However, the constituent materials of the electrodes are not limited to them. As the electrode materials applicable to the present invention are, e.g., Ir, W, Ni, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Ti, Si, TaN, TiN, Ru, ITO, NiO, IrO, SrRuO, CoSi2, WSi2, NiSi, MoSi2, TiSi2, Al—Si, Al—Cu, Al—Si—Cu, etc. Preferably, the electrode material is selected suitably for the compatibility with the resistance memory material, etc.
- In the above-described fourth embodiment, as the resistance memory element of the nonvolatile semiconductor memory device, the resistance memory element according to the first embodiment is used, but the resistance memory element according to the second or the third embodiment may be used.
- In the first, the second and the fourth embodiments, the cylindrical electrodes are provided between the resistance memory layer and the upper electrode, and in the third embodiment, the cylindrical electrodes are provided between the lower electrode and the resistance memory layer. However, the cylindrical electrodes may be provided between the resistance memory layer and the upper electrode and between the lower electrode and the resistance memory layer.
- In the first to the fourth embodiments, the resistance memory element according to the present invention is applied to RRAM, but the resistance memory element according to the present invention is applicable to nonvolatile semiconductor memory device other than RRAM. For example, the resistance memory element according to the present invention is applicable to a read only memory (ROM). For ROM, the resistance memory element whose resistance state is unreversibly changed by once writing may be used. For example, a resistance memory element which initially has the high resistance state, has the insulating film broken by the application of a prescribed voltage and has the low resistance state, and hereafter retains the low resistance state is applicable. Such resistance memory element may not be formed of the special resistance memory materials as used in RRAM and can be formed of the general insulating materials and semiconductor materials, e.g., silicon oxide film, silicon nitride film, etc.
Claims (8)
1. A resistance memory element comprising:
a pair of electrodes, and an insulating film sandwiched between the pair of electrodes, wherein
at least one of the pair of electrodes has a plurality of cylindrical electrodes of a cylindrical structure of carbon in a region thereof, which is in contact with the insulating film.
2. The resistance memory element according to claim 1 , wherein
the cylindrical structure is a carbon nanotube.
3. The resistance memory element according to claim 1 , wherein
the insulating film is formed of a resistance memory material whose high resistance state and low resistance state are switched by application of a voltage.
4. The resistance memory element according to claim 3 , wherein
the resistance memory material is titanium oxide, nickel oxide, Pr1-xCaxMnO3 or La1-xCaxMnO3.
5. A semiconductor memory device comprising:
a memory cell transistor; and
a resistance memory element including:
a pair of electrodes one of which is connected to the memory cell transistor;
an insulating film sandwiched between the pair of electrodes, wherein
at least one of the pair of electrodes has a plurality of cylindrical electrodes of a cylindrical structure of carbon in a region thereof, which is in contact with the insulating film.
6. The semiconductor device according to claim 5 , wherein
the cylindrical structure is a carbon nanotube.
7. The semiconductor device according to claim 5 , wherein
the insulating film is formed of a resistance memory material whose high resistance state and low resistance state are switched by application of a voltage.
8. The semiconductor device according to claim 7 , wherein
the resistance memory material is titanium oxide, nickel oxide, Pr1-xCaxMnO3 or La1-xCaxMnO3.
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US12/960,605 US20110073833A1 (en) | 2006-01-18 | 2010-12-06 | Resistance memory element and method of manufacturing the same |
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PCT/JP2006/300588 WO2007083362A1 (en) | 2006-01-18 | 2006-01-18 | Resistive storage element and method for manufacturing same |
US12/174,868 US7867814B2 (en) | 2006-01-18 | 2008-07-17 | Resistance memory element and method of manufacturing the same |
US12/960,605 US20110073833A1 (en) | 2006-01-18 | 2010-12-06 | Resistance memory element and method of manufacturing the same |
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US7867814B2 (en) | 2011-01-11 |
US20080296551A1 (en) | 2008-12-04 |
JPWO2007083362A1 (en) | 2009-06-11 |
JP4911037B2 (en) | 2012-04-04 |
WO2007083362A1 (en) | 2007-07-26 |
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