US20110174362A1 - Manufacture of thin film solar cells with high conversion efficiency - Google Patents
Manufacture of thin film solar cells with high conversion efficiency Download PDFInfo
- Publication number
- US20110174362A1 US20110174362A1 US12/980,135 US98013510A US2011174362A1 US 20110174362 A1 US20110174362 A1 US 20110174362A1 US 98013510 A US98013510 A US 98013510A US 2011174362 A1 US2011174362 A1 US 2011174362A1
- Authority
- US
- United States
- Prior art keywords
- layer
- amorphous silicon
- substrate
- junction
- type amorphous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000006243 chemical reaction Methods 0.000 title description 28
- 238000004519 manufacturing process Methods 0.000 title description 23
- 239000010409 thin film Substances 0.000 title description 18
- 239000010410 layer Substances 0.000 claims abstract description 1084
- 239000000758 substrate Substances 0.000 claims abstract description 217
- 230000004888 barrier function Effects 0.000 claims abstract description 107
- 239000011247 coating layer Substances 0.000 claims abstract 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 190
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 98
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 73
- 239000000463 material Substances 0.000 claims description 70
- 229910052710 silicon Inorganic materials 0.000 claims description 66
- 239000010703 silicon Substances 0.000 claims description 66
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 65
- 239000002019 doping agent Substances 0.000 claims description 65
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 59
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 52
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 51
- 229910052799 carbon Inorganic materials 0.000 claims description 51
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 38
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 37
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 37
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 35
- 239000011521 glass Substances 0.000 claims description 34
- 229910001887 tin oxide Inorganic materials 0.000 claims description 34
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 33
- 229910052742 iron Inorganic materials 0.000 claims description 31
- 229910052709 silver Inorganic materials 0.000 claims description 23
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 21
- 239000004332 silver Substances 0.000 claims description 21
- 239000010955 niobium Substances 0.000 claims description 16
- 229910052758 niobium Inorganic materials 0.000 claims description 14
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 14
- 229910052763 palladium Inorganic materials 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000002131 composite material Substances 0.000 claims description 10
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 229910052731 fluorine Inorganic materials 0.000 claims description 9
- 239000011737 fluorine Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000000956 alloy Substances 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 6
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims 3
- 229910052906 cristobalite Inorganic materials 0.000 claims 3
- 239000000377 silicon dioxide Substances 0.000 claims 3
- 229910052682 stishovite Inorganic materials 0.000 claims 3
- 229910052905 tridymite Inorganic materials 0.000 claims 3
- 238000000034 method Methods 0.000 abstract description 98
- 210000004027 cell Anatomy 0.000 description 119
- 239000007789 gas Substances 0.000 description 94
- 239000010408 film Substances 0.000 description 87
- 230000008569 process Effects 0.000 description 77
- 239000006117 anti-reflective coating Substances 0.000 description 53
- 238000000151 deposition Methods 0.000 description 53
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 39
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 38
- 230000008021 deposition Effects 0.000 description 37
- 239000000203 mixture Substances 0.000 description 36
- 229910000077 silane Inorganic materials 0.000 description 34
- 238000012545 processing Methods 0.000 description 30
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 27
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 26
- 239000001257 hydrogen Substances 0.000 description 26
- 229910052739 hydrogen Inorganic materials 0.000 description 26
- 239000011787 zinc oxide Substances 0.000 description 19
- 229910052782 aluminium Inorganic materials 0.000 description 18
- 239000012159 carrier gas Substances 0.000 description 17
- 238000005240 physical vapour deposition Methods 0.000 description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 16
- 238000005137 deposition process Methods 0.000 description 15
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 13
- 229910052796 boron Inorganic materials 0.000 description 13
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 13
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 12
- 210000004692 intercellular junction Anatomy 0.000 description 12
- 230000003287 optical effect Effects 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 10
- 239000001301 oxygen Substances 0.000 description 10
- 229910052760 oxygen Inorganic materials 0.000 description 10
- 230000005855 radiation Effects 0.000 description 10
- 239000000243 solution Substances 0.000 description 10
- 230000001965 increasing effect Effects 0.000 description 9
- 230000031700 light absorption Effects 0.000 description 9
- 239000000126 substance Substances 0.000 description 9
- 238000010521 absorption reaction Methods 0.000 description 8
- 229910052786 argon Inorganic materials 0.000 description 8
- 239000011651 chromium Substances 0.000 description 8
- 150000002431 hydrogen Chemical class 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- 238000010790 dilution Methods 0.000 description 7
- 239000012895 dilution Substances 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 238000012546 transfer Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- -1 C4H10 Chemical compound 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 5
- 125000004432 carbon atom Chemical group C* 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000002834 transmittance Methods 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910021431 alpha silicon carbide Inorganic materials 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 239000011261 inert gas Substances 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000011734 sodium Substances 0.000 description 4
- WXRGABKACDFXMG-UHFFFAOYSA-N trimethylborane Chemical compound CB(C)C WXRGABKACDFXMG-UHFFFAOYSA-N 0.000 description 4
- 229910015900 BF3 Inorganic materials 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 239000006096 absorbing agent Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 3
- 238000000149 argon plasma sintering Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000000356 contaminant Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000011541 reaction mixture Substances 0.000 description 3
- 239000005361 soda-lime glass Substances 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000004630 atomic force microscopy Methods 0.000 description 2
- 230000008033 biological extinction Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000012864 cross contamination Methods 0.000 description 2
- 238000013036 cure process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920000307 polymer substrate Polymers 0.000 description 2
- 238000002203 pretreatment Methods 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000005049 silicon tetrachloride Substances 0.000 description 2
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000010944 silver (metal) Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 230000001502 supplementing effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910016909 AlxOy Inorganic materials 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 240000005373 Panax quinquefolius Species 0.000 description 1
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- XNRNVYYTHRPBDD-UHFFFAOYSA-N [Si][Ag] Chemical compound [Si][Ag] XNRNVYYTHRPBDD-UHFFFAOYSA-N 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 150000001343 alkyl silanes Chemical class 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- UORVGPXVDQYIDP-BJUDXGSMSA-N borane Chemical compound [10BH3] UORVGPXVDQYIDP-BJUDXGSMSA-N 0.000 description 1
- 229910000085 borane Inorganic materials 0.000 description 1
- 150000001639 boron compounds Chemical class 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005108 dry cleaning Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005816 glass manufacturing process Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000013080 microcrystalline material Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 150000003018 phosphorus compounds Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229940071182 stannate Drugs 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- QHGNHLZPVBIIPX-UHFFFAOYSA-N tin(ii) oxide Chemical class [Sn]=O QHGNHLZPVBIIPX-UHFFFAOYSA-N 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- LALRXNPLTWZJIJ-UHFFFAOYSA-N triethylborane Chemical compound CCB(CC)CC LALRXNPLTWZJIJ-UHFFFAOYSA-N 0.000 description 1
- UORVGPXVDQYIDP-UHFFFAOYSA-N trihydridoboron Substances B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67236—Apparatus for manufacturing or treating in a plurality of work-stations the substrates being processed being not semiconductor wafers, e.g. leadframes or chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
- H01L21/67736—Loading to or unloading from a conveyor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
- H01L31/03921—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/054—Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means
- H01L31/056—Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
- H01L31/076—Multiple junction or tandem solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/52—PV systems with concentrators
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
A method and apparatus for forming solar cells is provided. In one embodiment, a photovoltaic device includes a antireflection coating layer disposed on a first surface of a substrate, a barrier layer disposed on a second surface of the substrate, a first transparent conductive oxide layer disposed on the barrier layer, a conductive contact layer disposed on the first transparent conductive oxide layer, a first p-i-n junction formed on the conductive contact layer, and a second transparent conductive oxide layer formed on the first p-i-n junction.
Description
- This application claims benefit of U.S. Provisional Patent Application Ser. No. 61/295,991 [Attorney Docket #: APPM 14633L], filed Jan. 18, 2010, which is incorporated by reference herein.
- 1. Field of the Invention
- Embodiments of the present invention generally relate to solar cells and methods for forming the same. More particularly, embodiments of the present invention relate to methods for manufacturing thin-film solar cells with high conversion efficiency.
- 2. Description of the Related Art
- Solar cells convert solar radiation and other light into usable electrical energy. The energy conversion occurs as the result of the photovoltaic effect. Solar cells may be formed from crystalline material or from amorphous or microcrystalline materials. Generally, there are two major types of solar cells that are produced in large quantities today, which are crystalline silicon solar cells and thin film solar cells. Crystalline silicon solar cells typically use either mono-crystalline substrates (i.e., single-crystal substrates of pure silicon) or a multi-crystalline silicon substrates (i.e., poly-crystalline or polysilicon). Additional film layers are deposited onto the silicon substrates to improve capture of light, form the electrical circuits, and protect the devices. Suitable substrates include glass, metal, and polymer substrates. It has been found that the properties of thin-film solar cells degrade over time upon exposure to light, which can cause the device stability to be less than desired. Typical solar cell properties that may degrade are the fill factor (FF), short circuit current, and open circuit voltage (Voc).
- Thin film silicon solar cells have gained a significant market share due to low-cost, large-area deposition of the amorphous-microcrystalline silicon absorber layers. Thin-film solar cells use thin layers of materials deposited on suitable substrates to form one or more p-n junctions. Generally, different material layers perform different functions formed in the solar cells. In some instances, some material layers may server as a light absorber layer that may have high light-trapping effect to absorb light in the absorber layer to generate high current. In contrast, some material layers are configured to reflect and scatter light to the solar cells formed on the substrate so as to assist light retaining in the solar cell for a longer time for current generation. However, absorption loss may often occurs when light transmitting through these reflective material layers, thereby adversely reducing overall electrical performance and conversion efficiency of the solar cell junctions formed on the substrate. To expand the economic uses of solar cells, efficiency must be improved. Solar cell efficiency relates to the proportion of incident radiation converted into useful electricity. To be useful for more applications, solar cell efficiency must be improved beyond the current best performance of approximately 15%. With energy costs rising, there is a need for improved thin film solar cells and methods and apparatuses for forming the same in a factory environment.
- Embodiments of the invention provide methods of forming solar cells. In one embodiment, a photovoltaic device includes a ARC layer disposed on a first surface of a substrate, a barrier layer disposed on a second surface of the substrate, a first TCO layer disposed on the barrier layer, a conductive contact layer disposed on the first TCO layer, a first p-i-n junction formed on the conductive contact layer, and a second TCO layer formed on the first p-i-n junction.
- Embodiments of the invention may further provide a photovoltaic device, comprising a substrate having a first surface and a second surface, a barrier layer disposed on the first surface of the substrate, a first transparent conductive oxide layer disposed on the barrier layer, a conductive contact layer disposed on the first transparent conductive oxide layer, wherein the conductive contact layer comprises a tin oxide layer, a titanium oxide layer, a tantalum layer, a tantalum oxide layer, a niobium doped tin oxide layer, or a niobium doped titanium oxide layer, a first p-i-n junction formed on the conductive contact layer, and a second transparent conductive oxide layer formed over the first p-i-n junction.
- Embodiments of the invention may further provide a photovoltaic device, comprising a substrate having a first surface and a second surface, wherein the substrate comprises a glass material having an iron concentration less than about 0.03% by weight, a barrier layer disposed on the first surface of the substrate, a first transparent conductive oxide layer disposed on the barrier layer, a first p-i-n junction comprising a p-type amorphous silicon layer formed over the first transparent conductive oxide layer, an intrinsic type amorphous silicon layer formed over the p-type amorphous silicon layer, and an n-type microcrystalline silicon carbide layer formed over the intrinsic type amorphous silicon layer, a conductive contact layer disposed between the first transparent conductive oxide layer and the p-type amorphous silicon layer, wherein the index of refraction of the material in the conductive contact layer is between the index of refraction of the material in the first transparent conductive oxide layer and the index of refraction of the material in the p-type amorphous silicon layer, and the electrical sheet resistance of the combination of the formed first transparent conductive oxide layer and the formed conductive contact layer is less than about 10 Ohms per square, a second p-i-n junction comprising a p-type microcrystalline silicon layer disposed over the n-type microcrystalline silicon carbide layer, an intrinsic type microcrystalline silicon layer formed over the p-type microcrystalline silicon layer, and an n-type amorphous silicon layer formed over the intrinsic type microcrystalline silicon layer, a conductive index matching layer disposed on the n-type amorphous silicon layer, and a second transparent conductive oxide layer formed over the conductive index matching layer.
- Embodiments of the invention may further provide a photovoltaic device, comprising a substrate having a first surface and a second surface, a barrier layer disposed on the second surface of the substrate, a first transparent conductive oxide layer disposed on the barrier layer, a conductive contact layer disposed on the first transparent conductive oxide layer, a first p-i-n junction formed on the conductive contact layer, wherein the first p-i-n junction further comprises a p-type amorphous silicon layer, an intrinsic type amorphous silicon layer, and a n-type microcrystalline silicon carbide layer, a second transparent conductive oxide layer formed over the first p-i-n junction, and a metal back electrode formed on the second transparent conductive oxide layer, wherein the metal back electrode comprises silver and palladium.
- Embodiments of the invention may further provide a method of forming a solar cell device, comprising forming a first transparent conductive oxide layer over a first surface of a substrate, wherein the first transparent conductive oxide layer comprises tin and oxygen, and the substrate comprises a glass material having an iron concentration less than about 0.03% by weight, forming a conductive contact layer disposed on the first transparent conductive oxide layer, wherein the resistivity of the first transparent conductive oxide layer and conductive contact layer is less than about 10 Ohms per square, and forming a first p-i-n junction on the conductive contact layer, wherein forming the first p-i-n junction comprises forming a p-doped amorphous silicon layer on the conductive contact layer, forming an intrinsic type amorphous silicon layer over the p-type amorphous silicon layer, and forming a an n-type microcrystalline silicon layer on the conductive contact layer.
- Embodiments of the invention may further provide a method of forming a solar cell device, comprising forming a first transparent conductive oxide layer over a first surface of a substrate, wherein the first transparent conductive oxide layer comprises tin and oxygen, forming a conductive contact layer disposed on the first transparent conductive oxide layer, forming a first p-i-n junction over the conductive contact layer, wherein forming the first p-i-n junction comprises forming a p-doped amorphous silicon layer on the conductive contact layer, forming an intrinsic type amorphous silicon layer over the p-type amorphous silicon layer, wherein forming the intrinsic type amorphous silicon layer comprises providing a gas mixture to the surface of the substrate in a processing chamber, wherein the gas mixture includes a ratio of a hydrogen gas to a silane gas less than 6, controlling a substrate temperature between about 220 degrees Celsius and about 250 degrees Celsius, and controlling a process pressure in the processing chamber at between about 1 Torr and about 2 Torr, forming an n-type microcrystalline silicon layer on the intrinsic type amorphous silicon layer, forming a second p-i-n junction over the first p-i-n junction, wherein forming the second p-i-n junction comprises forming a p-doped microcrystalline silicon layer over the n-type microcrystalline silicon layer, forming an intrinsic type microcrystalline silicon layer over the p-type microcrystalline silicon layer, and forming an n-type on the intrinsic type microcrystalline silicon layer, forming a conductive index matching layer over the first p-i-n junction, and forming a second transparent conductive oxide layer on the conductive index matching layer.
- Embodiments of the invention may further provide a method of forming a solar cell device, comprising forming a first transparent conductive oxide layer disposed over a first surface of a substrate, forming a conductive contact layer disposed on the first transparent conductive oxide layer, wherein the conductive contact layer is a niobium doped titanium oxide layer formed in a physical vapor deposition chamber, forming a first p-i-n junction on the conductive contact layer, wherein forming the first p-i-n junction comprises forming a p-doped amorphous silicon layer on the conductive contact layer, forming an intrinsic type amorphous silicon layer over the p-type amorphous silicon layer, forming an n-type microcrystalline silicon layer on the intrinsic type amorphous silicon layer, and forming a second transparent conductive oxide layer over the n-type microcrystalline silicon layer.
- In another embodiment, a method of forming a solar cell device includes forming a ARC layer on a first surface of a substrate, forming a barrier layer on a second surface of a substrate, forming a first TCO layer disposed on the barrier layer, forming a conductive contact layer disposed on the first TCO layer, wherein the conductive contact layer is a niobium doped titanium oxide layer formed in a PVD chamber, forming a first p-i-n junction on the conductive contact layer, forming a conductive index matching layer on the first p-i-n junction, and forming a second TCO layer on the conductive index matching layer.
- In yet another embodiment, an automated and integrated system for forming a solar cell includes a first deposition chamber that is adapted to deposit a conductive contact layer on a first TCO layer on a first surface of the substrate, wherein an ARC layer is formed on a second surface of the substrate, and wherein a barrier layer is formed between the first surface of the substrate and the first TCO layer, a second deposition chamber that is adapted to deposit a p-type silicon containing layer and an interface barrier layer on the conductive contact layer, a third deposition chamber that is adapted to deposit an intrinsic type silicon-containing layer and, n-type microcrystalline silicon carbide layer or a conductive index matching layer on intrinsic type silicon-containing layer, and an automated conveyor device that is adapted to transfer the substrate between the first deposition chamber, second deposition chamber and third deposition chamber.
- So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
-
FIG. 1 is schematic side-view of a single junction thin-film solar cell according to one embodiment of the invention; -
FIG. 2 is a schematic side-view of a tandem junction thin-film solar cell according to one embodiment of the invention; -
FIG. 3 is a magnified view of an antireflective coating (ARC) layer disposed on a first surface of a substrate according to one embodiment of the invention; -
FIG. 4 is a magnified view of a barrier layer disposed on a surface of a second surface of a substrate according to one embodiment of the invention; -
FIG. 5 is a magnified view of a back metal electrode formed in a solar cell disposed on a substrate according to one embodiment of the invention; -
FIG. 6 is a process flow diagram of a method for manufacturing a solar cell on a substrate according to one embodiment of the invention; -
FIG. 7 is a cross-sectional view of an apparatus according to one embodiment of the invention; -
FIG. 8 is a plan view of an apparatus according to another embodiment of the invention; and -
FIG. 9 is a plan view of a portion of a production line having apparatuses ofFIGS. 7 and 8 incorporated therein according to one embodiment of the invention. - To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
- It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
- Thin-film solar cells are generally formed from numerous types of films, or layers, put together in many different ways. Most films used in such devices incorporate a semiconductor element that may comprise silicon, germanium, carbon, boron, phosphorous, nitrogen, oxygen, hydrogen and the like. Characteristics of the different films include degrees of crystallinity, dopant type, dopant concentration, film refractive index, film extinction coefficient, film transparency, film absorption, and conductivity. Typically, most of these films can be formed by use of a chemical vapor deposition process, which may include some degree of ionization or plasma formation.
- Charge generation during a photovoltaic process is generally provided by a bulk semiconductor layer, such as a silicon containing layer. The bulk layer is also sometimes called an intrinsic layer to distinguish it from the various doped layers present in the solar cell. The intrinsic layer may have any desired degree of crystallinity, which will influence its light-absorbing characteristics. For example, an amorphous intrinsic layer, such as amorphous silicon, will generally absorb light at different wavelengths from intrinsic layers having different degrees of crystallinity, such as microcrystalline silicon. For this reason, most solar cells will use both types of layers to yield the broadest possible absorption characteristics to increase cell conversion efficiency. In some instances, an intrinsic layer may be used as a buffer layer between two dissimilar layer types to provide a smoother transition in optical or electrical properties between the two layers.
-
FIG. 1 is a schematic side-view of a single-junction thin-filmsolar cell 100 formed on asubstrate 102 having afirst surface 152 oriented toward light orsolar radiation 101.Solar cell 100 comprises thesubstrate 102, such as a glass substrate, polymer substrate, metal substrate, or other suitable substrate, with thin films formed on asecond surface 154 thereover. In one configuration, thesubstrate 102 is a glass material that is between about 2.6 mm and about 4 mm thick, such as about 3.2 mm thick. In one embodiment, thesubstrate 102 includes a glass material having relatively low concentration of iron (Fe) element doped therein. It is believed that the lower amount of iron elements doped in the glass substrate will reduce light absorption when light is transmitted through thesubstrate 102 to thesolar cell 100 formed thereon. It is believed that less light will be absorbed in a low iron glass at the longer wavelengths of light, such as wavelength between about 800 nm to about 1100 nm, versus conventional glass materials that are typically used in solar applications, such as soda lime glass. Therefore, a low iron glass containing substrate can be useful when it is used in combination with a solar cell that contains crystalline silicon containing layers (e.g., microcrystalline silicon), since they tend to absorb light within these wavelengths versus amorphous silicon containing layers. In one embodiment, the iron concentration in thesubstrate 102, such as a glass substrate, is controlled to a level between about 0.01 percent by weight and about 0.03 percent by weight, such as less than about 0.02 percent by weight. In another embodiment, the iron concentration in aglass type substrate 102 is controlled to a level less than about 0.03 percent by weight. In another embodiment, the iron concentration in aglass type substrate 102 is controlled to a level less than about 70 ppm. In yet another embodiment, the iron concentration in aglass type substrate 102 is controlled to a level less than about 7 ppm. In one example, in a tandem type solar cell device (solar cell 200 inFIG. 2 ), the use of a low iron glass substrate that has a reduced absorption in the longer received wavelengths is used to increase the amount of current generated in the microcrystalline containing secondp-i-n junction 136, and thus the tandem junction type thin-film solar cell, or solar cell. - An anti-reflective coating (ARC)
layer 103 is formed on thefirst surface 152 of thesubstrate 102. In one embodiment, theARC layer 103 is disposed on thefirst surface 152 of thesubstrate 102 to reduce light loss whensolar radiation 101 passing through thesubstrate 102. TheARC layer 103 is selected to have a refractive index between the refractive index of air and the refractive index of thesubstrate 102. In one embodiment, as the refractive index of air is about 1.0 and the refractive index of thesubstrate 102, such as a glass substrate (e.g., low iron glass) is typically between about 1.4 and about 1.5, the refractive index of theARC layer 103 is tuned and selected at between about 1.1 and 1.4, such as about 1.2. It is believed that by selecting an ARC layer with a refractive index between about 1.1 and 1.4, theARC layer 103 may assist light to smoothly transmit and pass through from the air through thesubstrate 102 to the film layers formed thereon, which is described below. When light is transmitted from air through thesubstrate 102, dramatic refractive index change may result in reflection of light back into the air and away from thesolar cells 100 formed on thesubstrate 102. Accordingly, by selectingproper ARC layer 103 materials that tend to act as a buffer layer between air and thesubstrate 102, the amount of light lost to reflection from the substrate surface can be reduced and/or controlled. Details relating to the selection and properties of theARC layer 103 will be further described below with referenced toFIG. 3 . - The
solar cell 100 is formed on thesecond surface 154 of thesubstrate 102 opposite to the position where theARC layer 103 is formed on thesubstrate 102. Thesolar cell 100 includes anoptional barrier layer 104 formed on thesecond surface 154 of thesubstrate 102. Subsequently, a first transparent conductive oxide (TCO)layer 106 is formed on theoptional barrier layer 104. In the embodiment wherein theoptional barrier layer 104 is not present, thefirst TCO layer 106 is directly formed on thesecond surface 154 of thesubstrate 102. A firstp-i-n junction 116 is then formed on thefirst TCO layer 106. An optionalconductive contact layer 108 may be formed between thefirst TCO layer 106 and the firstp-i-n junction 116. In one embodiment wherein the optionalconductive contact layer 108 is not present, the firstp-i-n junction 116 may be directly formed on thefirst TCO layer 106. Subsequently, a conductiveindex matching layer 118, asecond TCO layer 120 and theback metal electrode 122 are then consecutively formed on the firstp-i-n junction 116. - In one embodiment, the
optional barrier layer 104 may be pre-fabricated on and come with thesubstrate 102 from a glass supplier. Theoptional barrier layer 104, in one part, has a similar function as theARC layer 103 described above in that it can increase the amount of light that makes it to the firstp-i-n junction 116 by reducing light absorption and reflection within or at the interface with thesubstrate 102 and the first transparent conductive oxide (TCO)layer 106. Theoptional barrier layer 104, in another part, is configured to have a low contact resistance and a high adhesion to thesubstrate 102 and the subsequently to-be-formed first transparent conductive oxide (TCO)layer 106. In one embodiment, theoptional barrier layer 104 is selected from a material that has high film transparency, high film conductivity and high electron mobility, which will improve the solar cell efficiency by reducing the absorption and the series resistance between the interconnected solar cells, which are typically formed by use of a scribing process, on thesubstrate 102. Furthermore, theoptional barrier layer 104 may also have certain degree of surface roughness in order to improve light scattering so as to improve light absorption within thesolar cell 100. Details relating to the film properties and structure of theoptional barrier layer 104 will be described below with referenced toFIG. 4 . - The
first TCO layer 106 and thesecond TCO layer 120 may each comprise tin oxide, zinc oxide, indium tin oxide, cadmium stannate, combinations thereof, or other suitable materials. It is understood that the TCO materials may also include additional dopants and components. For example, tin oxide (SnO2) may further include iron (Fe), magnesium (Mg), or other suitable dopants. In the embodiment wherein the SnO2 TCO layer is utilized, it is believed that the SnO2 TCO layer may increase the amount of light that makes it to the firstp-i-n junction 116 by reducing light absorption and reflection within or at the interface with thesubstrate 102 and the first transparent conductive oxide (TCO)layer 106. In one embodiment, a fluorinated tin oxide (SnO2:F)TCO layer 106 is used, since it is relatively inexpensive to form on the substrate and it is easily textured to improve light trapping. In one embodiment, the grain size of a formed tin oxide (SnO2) layer is between about 600 nm to 800 nm in size. In another embodiment, the grain size of a formed tin oxide (SnO2) layer is about three to five times the thickness of theTCO layer 106, or approximately 900 nm to 1500 nm in size, where, for example, theTCO layer 106 is between about 300 nm and about 600 nm thick. - In another example, the TCO material may be a zinc oxide that may further include dopants, such as aluminum, aluminum oxide, gallium, boron, and other suitable dopants. For example, the TCO materials may have zinc oxide comprising 5 atomic % or less of dopants, such as comprising 3 atomic % or less aluminum oxide dopants, such as between about 0.25 atomic percent and 3 atomic % aluminum oxide dopants formed therein. In one embodiment, the first and the
second TCO layer second TCO layer second TCO layer 120 may assist in the reflection of light back to the active regions (e.g., first p-i-n junction 116) of the formed solar cell formed on thesubstrate 102, thereby increasing current generation in these active region(s) of the solar cell device. In one embodiment, thefirst TCO layer 106 may be controlled to have about 1 percent by atomic weight of aluminum oxide doped in about 99 percent by atomic weight of zinc oxide. Thesecond TCO layer 120 may be controlled to have about 2 percent by atomic weight of aluminum oxide doped in about 98 percent by atomic weight of zinc oxide. In a PVD process, the oxygen gas supplied in a gas mixture (e.g., gas mixture including oxygen and argon gas) may be controlled at between about 1.5 percent and about 5 percent by volume to create the AZO layer with a desired concentration ratio of oxygen dopants formed therein. In certain instances, thesubstrate 102 may be provided by the glass manufacturers with thefirst TCO layer 106 already provided thereon. Typically, the TCO layer(s) 106, 120 may be formed using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. An example of a deposition process that may be used to form the TCO layers 106 and/or 120 are further described in the commonly assigned U.S. patent application Ser. No. 12/481,175 [Attorney Docket Number APPM 14329], filed Jun. 9, 2009, U.S. Provisional Patent Application Ser. No. 61/186,633 [Attorney Docket #: APPM 14441L02], filed Jun. 12, 2009, U.S. Provisional Patent Application Ser. No. 61/186,636 [Attorney Docket #: APPM 14442L02], filed Jun. 12, 2009, and U.S. Provisional Patent Application Ser. No. 61/244,386 [Attorney Docket #: APPM 14441L03], filed Sep. 21, 2009, which are all incorporated by reference herein in their entirety. - To improve light absorption by enhancing light trapping within the first
p-i-n junction 116, the substrate and/or one or more of thin films formed thereover may be optionally textured by wet, plasma, ion, and/or mechanical processes. For example, in the embodiment wherein thefirst TCO layer 106 is textured and the subsequent thin films deposited thereover will generally follow the topography of the surface below it. In one example, thesubstrate 102, theoptional barrier layer 104, theTCO layer 106, and/or the optionalconductive contact layer 108 are textured by mechanical, dry etching process, wet chemical etching or other similar means to achieve an average surface roughness of at least about 30 nm. In one embodiment, the average surface roughness is between about 70 nm and about 90 nm. The roughness of the textured surface can be measured and characterized using a scanning electron microscopy (SEM) and atomic force microscopy (AFM). In some embodiments, it is desirable to use afirst TCO layer 106 layer that comprises a tin oxide, or doped tin oxide material, versus a zinc oxide containing TCO layer, due to the added material cost, hardware cost and hardware complexity often required to form a good quality zinc oxide layer on thesubstrate 102 that also has a uniform and desirable roughness after texturing to optimally capture the incident light when the solar cell is in use. - Subsequently, in one embodiment, the
conductive contact layer 108 may be formed on thefirst TCO layer 106. Theconductive contact layer 108 provides a good contact interface between the first transparent conductive oxide (TCO)layer 106 and subsequent to-be-formed firstp-i-n junction 116. Theconductive contact layer 108 is formed to have a high film transparency to help reduce light loss traveling from the first transparent conductive oxide layer (TCO) 106 to the firstp-i-n junction 116. Furthermore, theconductive contact layer 108 also assist reducing contact resistance between theTCO layer 106 and the firstp-i-n junction 116, which will improve the current flow between the first transparent conductive oxide layer (TCO) 106 and the firstp-i-n junction 116, and thus improve the conversion efficiency to thesolar cell 100. It should be noted that reducing the conductivity of the layers in the front contact layer stack (e.g.,optional barrier layer 104,TCO layer 106 and the conductive contact layer 108) too far can adversely affect the ability of the formed front contact layer stack to transmit the infrared (IR) wavelengths of light to the active regions of the solar cell device due to the unwanted absorption of these wavelengths of light in the stack. Therefore, while a low conductivity front contact layer stack has electrical conductivity benefits, due to optical absorption changes in the high conductivity materials can greatly affect the efficiency of a solar cell by reducing the amount of IR radiation that makes it to the active layers that are able to absorb these wavelengths, such as microcrystalline layers in a tandem junction solar call. Therefore, in one embodiment, the sheet resistance of a stack of layers comprising theTCO layer 106 and theconductive contact layer 108 is between about 8 Ohms per square (Ω/□) and about 15 Ohms per square (Ω/□). In one embodiment, the sheet resistance of a stack of layers comprising theTCO layer 106 and theconductive contact layer 108 is between about 8 Ohms per square (Ω/□) and about 10 Ohms per square (Ω/□). In yet another embodiment, the sheet resistance of a stack of layers comprising theTCO layer 106 and theconductive contact layer 108 is less than about 15 Ohms per square (Ω/□). - It should also be noted that the use of low iron
glass type substrates 102, while improving optical transmission, will generally adversely affect the apparent conductivity of the front contact structure of the solar cell by reducing the amount of generated current that can flow through the parallel conductive path formed through the more resistive substrate material. The reduction in conductivity of a low iron glass versus a soda lime glass is generally due to the removal of sodium (Na), iron (Fe) and other elements from the substrate material during the glass substrate formation process, thus also making low iron glass generally harder to form and more expensive. In one example, it is believed that the same front contact layer configuration that is able to achieve a sheet resistance of about 10 Ohms per square (Ω/□) on a soda lime glass substrate would only achieve a greater than about 14 Ohms per square sheet resistance on a low iron concentration glass substrate, due to the difference in resistivity of the substrate material. In one embodiment, it is desirable to form a front contact structure on a low ironglass type substrate 102 that has a measured sheet resistance between about 8 Ohms per square (Ω/□) and about 15 Ohms per square (Ω/□). In one embodiment, it is desirable to form a front contact structure on a low ironglass type substrate 102 that has a measured sheet resistance of between about 8 Ohms per square (Ω/□) and about 10 Ohms per square (Ω/□). In another embodiment, it is desirable to form a front contact structure on a low ironglass type substrate 102 that has a measured sheet resistance of less than about 15 Ohms per square (Ω/□). In one example, the sheet resistance of the desired combination of formed layers is measured using a four point probe that is placed in contact with the exposed surface of theconductive contact layer 108. - In one embodiment, a front contact structure having desirable optical and conductivity properties is formed by doping the
optional barrier layer 104,TCO layer 106 and/or theconductive contact layer 108 with a conductive dopant material (e.g., indium, aluminum). In one example, theoptional barrier layer 104 and/orTCO layer 106 comprise a tin oxide (SnO2) layer that is doped with less than about 10% by weight of indium. In another example, theoptional barrier layer 104 and/orTCO layer 106 comprise a tin oxide (SnO2) layer that is doped with less than about 10% by weight of iron (Fe). - In one embodiment, the
conductive contact layer 108 may be a titanium layer, titanium oxide layer, tantalum, tantalum oxide, aluminum, aluminum oxide, and doped titanium, doped tantalum or doped aluminum containing layers, such as niobium doped titanium oxide layer, niobium doped titanium oxide layer, aluminum doped titanium oxide or tantalum oxide layer. In one example, theconductive contact layer 108 is a niobium doped titanium oxide layer may have a formula NbxTiyOz where x has a range between 0.01 and 0.1 and y has a range of between 0.9 and 0.99 and z is about 2. In one embodiment, theconductive contact layer 108 is a niobium doped titanium oxide layer having a niobium dopant concentration less than 1 percent by weight formed in the titanium oxide layer. In one embodiment, theconductive contact layer 108 may have a thickness between about 200 Å and about 700 Å. - In one embodiment, the
conductive contact layer 108 may provide good electrical contact between the first transparentconductive oxide layer 106 and subsequent to-be-formedsolar cell junctions 116. Theconductive contact layer 108 is formed to have a high film transparency to help reduce light loss traveling from the first transparentconductive layer 106 to the subsequent to-be-formed firstp-i-n junction 116. In one embodiment, theconductive contact layer 108 may have a film conductivity between about 2×10−4 ohm-cm and about 2×10−3 ohm-cm. - Additionally, the optical and electrical film properties of the
conductive contact layer 108 may be adjusted or tuned to have a different optical characteristic so as to match and/or provide improved optical properties between the adjacent layers. For example, the refractive indices of the first transparentconductive layer 106 and the adjacent film layers in the firstp-i-n junction 116 often have significant difference, as the first transparentconductive layer 106 is often fabricated from a conductive material and the film layers in the firstp-i-n junction 116 are often fabricated from one or more semiconductor containing layers, such as a silicon based material. In order to reduce and compensate for the refractive index difference between these layers and provide a smooth optical transition theconductive contact layer 108 formed there between is formed to serve as a refractive index matching layer (e.g., a buffer layer) to reduce the amount of light reflection from the interface between the first transparentconductive layer 106 and the firstp-i-n junction 116, due to the refractive index difference between these layers. Accordingly, theconductive contact layer 108 is generally tuned and adjusted to have a refractive index somewhere between the refractive index of the first transparentconductive layer 106 and the layers utilized to form firstp-i-n junction 116. In one embodiment, the refractive index of theconductive contact layer 108 is controlled at between about 2.0 and about 2.8, such as about 2.3, as the refractive index of the transparentconductive layer 106 is often about 1.8 to 2.1 and the dielectric layer, such as a silicon based layer, is often about 3.6 to 3.8. - Furthermore, the
conductive contact layer 108 may have a high electron mobility so as to help carry the generated electron/hole pairs to the adjacent layers in the formed solar cell device. In one embodiment, theconductive contact layer 108 may formed so that electrons moving through the formed layer has an electron mobility between about 20 V-s/cm2 and about 90 V-s/cm2. - The first
p-i-n junction 116 may comprise a p-typeamorphous silicon layer 110, an intrinsic typeamorphous silicon layer 112 formed over the p-typeamorphous silicon layer 110, and an n-type microcrystalline silicon basedlayer 114 formed over the intrinsic typeamorphous silicon layer 112. In one embodiment, the p-type dopants of p-typeamorphous silicon layer 110 may comprise a group III element, such as boron or aluminum. In one embodiment, boron is used as the p-type dopant. Examples of boron-containing sources include trimethylboron (TMB (or B(CH3)3)), diborane (B2H6), BF3, B(C2H5)3, and similar compounds. In one example, TMB is used as the p-type dopant. The n-type dopants of an n-type microcrystalline silicon basedlayer 114 may each comprise a group V element, such as phosphorus, arsenic, or antimony. In one embodiment, phosphorus is used as the n-type dopant. In certain embodiment wherein the intrinsic typeamorphous silicon layer 112 is formed as a film layer having low optical bandgap, an optionalinterface barrier layer 111 may be formed between the p-typeamorphous silicon layer 110 and the intrinsic typeamorphous silicon layer 112 to prevent dopant diffusion occurring during the subsequent thermal processes. Details and examples of an optionalinterface barrier layer 111 and the low film bandgap intrinsic typeamorphous silicon layer 112 are disclosed in U.S. application Ser. No. 12/582,323 (Attorney Docket's Number 14466) filed on Oct. 20, 2009, which is incorporated by reference herein in its entirety. Also, further details of the optionalinterface barrier layer 111 are also further discussed below. In certain embodiments, the p-typeamorphous silicon layer 110 may be formed to a thickness between about 60 Å and about 300 Å. In certain embodiments, the optionalinterface barrier layer 111 may be formed to a thickness between about 1 Å and about 200 Å. In certain embodiments, the intrinsic typeamorphous silicon layer 112 may be formed to a thickness between about 1,500 Å and about 3,500 Å. In certain embodiments, the n-type microcrystalline silicon basedlayer 114 may be formed to a thickness between about 100 Å and about 400 Å. Typically, the layers in the firstp-i-n junction 116 are formed using a CVD or PVD process. An example of a deposition process that may be used to form the firstp-i-n junction 116 is further described in the U.S. patent application Ser. No. 11/671,988 [Attorney Docket Number APPM 11709.P1], filed Feb. 6, 2007, which is incorporated herein by reference in its entirety. - Subsequently, in one embodiment, a conductive
index matching layer 118 is formed on the firstp-i-n junction 116. The conductiveindex matching layer 118 is configured to increase light reflection back to the firstp-i-n junction 116 so as to increase current generation in thejunction 116. Similarly, the conductiveindex matching layer 118 is selected from a material having a refractive index between the refractive index of the adjacent layer found in the firstp-i-n junction 116, such as an n-type microcrystalline silicon basedlayer 114, and thesecond TCO layer 120. As the refractive index of the n-type microcrystalline silicon basedlayer 114 is generally around 3 and the refractive index of thesecond TCO layer 120 is around 1.9, and thus the refractive index of the conductiveindex matching layer 118 is configured to be between about 1.4 and about 1.8 to increase light reflection back to the firstp-i-n junction 116. In one embodiment, the conductiveindex matching layer 118 is a silicon containing material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or other suitable silicon containing materials, or similar materials. In yet another embodiment, the conductiveindex matching layer 118 may also be configured as transparent conductive oxide layer such as an indium tin oxide (ITO) layer, zinc oxide containing layer, or tin oxide containing layer, as needed. In another embodiment, the conductiveindex matching layer 118 is not a continuous film layer. For example, the conductiveindex matching layer 118 may be formed as a non-continuous film layer, such as a thin layer of particles, or islands, that create an uneven surface so as to assist in the reflection and scattering light back to the firstp-i-n junction 116. Additionally, the conductiveindex matching layer 118 may also have a good adhesion to the underlying n-type microcrystalline silicon basedlayer 114 to provide a good interface there between. Furthermore, the conductiveindex matching layer 118 also has a high film transparency with low light absorption so as to reduce light loss while transmitting through the conductivematching index layer 118 to thesecond TCO layer 120. In one embodiment, the conductivematching index layer 118 may have a film thickness between about 50 Å and about 2000 Å, such as about 200 Å. - In one embodiment, subsequently, the
second TCO layer 120 is formed over theconductive matching layer 118, and comprises an indium tin oxide (ITO) layer, zinc oxide containing layer, or tin oxide containing layer. In one example, thesecond TCO layer 120 is formed so that it has a sheet resistance of about 2 to 20 Ohms per square and a thickness between about 50 and 300 nm. After thesecond TCO layer 120, theback metal electrode 122 is disposed on thesecond TCO layer 120. Theback metal electrode 122 is typically comprises a metal material that is conductive to assist in the transmission of the current generated by the firstp-i-n junction 116. In one embodiment, the metal backelectrode 122 may comprise two layers that have a high conductivity and also assist in reflecting light back to the firstp-i-n junction 116. Details of the structures and film properties of theback metal electrode 122 will be further described below with referenced toFIG. 5 . -
FIG. 2 is a schematic side-view of a tandem junction type thin-film solar cell, orsolar cell 200, according to one embodiment of the invention. Similar to the structure of the single junction thin-filmsolar cell 100 depicted inFIG. 1 , a secondp-i-n junction 136 may be disposed between the firstp-i-n junction 116 and the conductiveindex matching layer 118 to assist in the absorption of light in a broader spectrum. In addition, a wavelength selective reflector (WSR)layer 150 may be optionally disposed between the firstp-i-n junction 116 and the secondp-i-n junction 136. In one embodiment, theWSR layer 150 actively serves as an intermediate reflector having a desired refractive index, or ranges of refractive indexes, to reflect light received from the light incident side of thesolar cell 200. In one embodiment, theWSR layer 150 disposed between the firstp-i-n junction 116 and the secondp-i-n junction 136 is configured to have film properties that improve light scattering and current generation in thesolar cell 200. Additionally, theWSR layer 150 also provides a good p-n tunnel junction that has a high electrical conductivity and a tailored bandgap range that affect its transmissive and reflective properties to improve the formed solar cell's light conversion efficiency. TheWSR layer 150 also serves as a junction layer that boosts the absorption of the short to mid wavelengths of light (e.g., 280 nm to 800 nm) in the firstp-i-n junction 116 and improves short-circuit current, resulting in improved quantum and conversion efficiency. TheWSR layer 150 further has high film transmittance for mid to long wavelengths of light (e.g., 500 nm to 1100 nm) to facilitate the transmission of light to the layers formed in thejunction 116. Further, it is generally desirable for theWSR layer 150 to absorb as little light as possible while reflecting desirable wavelengths of light (e.g., shorter wavelengths) back to the layers in the firstp-i-n junction 116 and transmitting desirable wavelengths of light (e.g., longer wavelengths) to the layers in the secondp-i-n junction 136. Additionally, theWSR layer 150 can be formed with a desirable bandgap and have a high electrical conductivity so as to efficiently conduct the generated current and allow electrons to flow from the firstp-i-n junction 116 to the secondp-i-n junction 136, and avoid blocking the generated current. TheWSR layer 150 is desired to reflect shorter wavelength light back to the firstp-i-n junction 116 while allowing substantially all of the longer wavelengths of light to pass to secondp-i-n junction 136. By forming theWSR layer 150 that has a high film transmittance of desired wavelengths, a low film light absorption, desirable band gap properties (e.g., wide band gap range), and a high electrical conductivity the overall solar cell conversion efficiency may be improved. - In one embodiment, the
WSR layer 150 may be a microcrystalline silicon layer having n-type or p-type dopants disposed within theWSR layer 150. In an exemplary embodiment, theWSR layer 150 is an n-type crystalline silicon alloy having n-type dopants disposed within theWSR layer 150. Different dopants disposed within theWSR layer 150 may also influence the WSR layer film optical and electrical properties, such as bandgap, crystalline fraction, conductivity, transparency, film refractive index, extinction coefficient, and the like. In some instances, one or more dopants may be doped into various regions of theWSR layer 150 to efficiently control and adjust the film bandgap, work function(s), conductivity, transparency and so on. In one embodiment, theWSR layer 150 is controlled to have a refractive index between about 1.4 and about 4, a bandgap of at least about 2 eV, and a conductivity greater than about 0.3 S/cm. In one embodiment, theWSR layer 150 may comprise an n-type doped silicon alloy layer, such as silicon oxide (SiOX, SiO2), silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or the like. In an exemplary embodiment, theWSR layer 150 is an n-type SiON or SiC layer. Further details and examples of the WSR layers are disclosed in U.S. application Ser. No. 12/208,478 (Attorney Docket's Number 13551) filed on Sep. 11, 2008 by Sheng et al., U.S. Application Ser. No. 61/139,390 (Attorney Docket's Number 13551L) filed on Dec. 19, 2008 by Sheng et al., U.S. application Ser. No. 12/481,175 (Attorney Docket's Number 14329) filed on Jun. 9, 2009 by Sheng et al and U.S. Application Ser. No. 61/227,844 (Attorney Docket's Number 14139L) filed on Jul. 23, 2009 by Yang et al., which are all herein incorporated by reference in their entirety. - The second
p-i-n junction 136 is formed over the firstp-i-n junction 116, or theWSR layer 150, can include a p-typemicrocrystalline silicon layer 130, an intrinsicmicrocrystalline silicon layer 132, and an n-typeamorphous silicon layer 134. In certain embodiments, the p-typemicrocrystalline silicon layer 130 may be formed to a thickness between about 100 Å and about 400 Å. In certain embodiments, the intrinsic typemicrocrystalline silicon layer 132 may be formed to a thickness between about 10,000 Å and about 30,000 Å. In certain embodiments, the n-typeamorphous silicon layer 134 may be formed to a thickness between about 100 Å and about 500 Å. Typically, the layers in the secondp-i-n junction 136 are formed using a CVD or PVD process. An example of a deposition process that may be used to form the secondp-i-n junction 136 is further described in the U.S. patent application Ser. No. 11/671,988 [Attorney Docket Number APPM 11709.P1], filed Feb. 6, 2007, which is incorporated herein by reference in its entirety. - In operation,
solar radiation 101 is primarily absorbed by theintrinsic layers p-i-n junctions type layers type layer intrinsic layer type layers type layers p-i-n junction 116 comprises an intrinsic typeamorphous silicon layer 112 and the secondp-i-n junction 136 comprises an intrinsic typemicrocrystalline silicon layer 132 since amorphous silicon and microcrystalline silicon absorb different wavelengths of thesolar radiation 101. Therefore, the formedsolar cell 200 is more efficient, since it captures a larger portion of the solar radiation spectrum. Theintrinsic layer solar radiation 101 first strikes the intrinsic typeamorphous silicon layer 112 and then strikes the intrinsic typemicrocrystalline silicon layer 132 since amorphous silicon has a larger bandgap than microcrystalline silicon. In a case where aWSR layer 150 is present, the solar radiation that is not absorbed by the firstp-i-n junction 116 and is transmitted through theWSR layer 150 will continue on to the secondp-i-n junction 136. -
FIG. 3 depicts a magnified view of the antireflective coating (ARC)layer 103 disposed on thefirst surface 152 of thesubstrate 102 according to one embodiment of the invention. As discussed above, theARC layer 103 is selected to have a refractive index between the refractive index of air and the refractive index of thesubstrate 102. In one embodiment, theARC layer 103 is selected to have a refractive index between about 1.1 and 1.4. In one embodiment, theARC layer 103 may be fabricated by a spray coating technique to spray a chemical solution on thefirst surface 152 of thesubstrate 102. Subsequently, a baking process is performed to dry out and cure the chemical solution sprayed on thefirst surface 152 of thesubstrate 102. The cured and/or dried out chemical is then formed a thin layer ofARC layer 103 with desired film composition on thesubstrate 102. In one embodiment, the temperature of the cure/drying process is controlled at a relatively low temperature, such as lower than 200 degrees Celsius, to drive out the excess moisture and water contained in the chemical solution. In one embodiment, the temperature of the cure/drying process is controlled at about less 100 degrees Celsius. - In one embodiment, the chemical solution, which is sprayed on the
first surface 152 of thesubstrate 102, includes silane, fluorine (F) and carbon (C) that are dissolved in an aqueous solution. It is believed that the addition of fluorine (F) in the chemical solution may affect the transmittance of theresultant ARC layer 103 formed on thesubstrate 102. Accordingly, by actively controlling the concentration of the different elements in the chemical solution, such as the fluorine or carbon elements, the transmittance and film refractive index may be adjusted to form adesirable ARC layer 103. In one embodiment, the chemical solution used to form theARC layer 103 may include between about 40 percent by volume and about 79 percent by volume of silane, between about 20 percent by volume and about 59 percent by volume of fluorine, and about less than 1 percent by volume of carbon dissolved in water. It is noted that the water described herein may include any forms of water, including D.I. water, steamed water, pure water, of any suitable water. In one example, the fluorine concentration in the chemical solution is achieved by adding a solution containing hydrofluoric acid (HF) and the carbon and silicon concentration is achieved by adding a solution containing alkylsilane. - After the
ARC layer 103 is formed on thesubstrate 102, the surface of theARC layer 103 may be polished or surface finished to provide a film surface with desired film roughness. It is believed that a surface with a desirable roughness may assist in trapping light that can be delivered through thesubstrate 102 to the solar cell junctions formed thereon. In one embodiment, the surface of theARC layer 103 may be CMP polishing with a polishing fluid including CeO2 or Al2O3. Alternatively, the surface of theARC layer 103 may be mechanically abraded and/or polished by any suitable manner available in the art. In one embodiment, theARC layer 103 is surface finished to have an average film roughness of about 50 Ra. - In another embodiment, the
ARC layer 103 may be formed on thefirst surface 152 of thesubstrate 102 by a PVD, CVD, or other suitable deposition techniques. Accordingly, theARC layer 103 may comprise an inorganic film layer having a desired film transmittance and refractive index that can assist in the transmission of light through thesubstrate 102 to thesolar cell junctions substrate 102. In one embodiment, theARC layer 103 may contain a titanium oxide (TiO2) layer, a tin oxide layer (SnO2), silicon oxide (SiO2) or combinations thereof, which are formed on thefirst surface 152 of thesubstrate 102. In another embodiment, theARC layer 103 may be a composite layer having one or more layers formed on thefirst surface 152 of thesubstrate 102. In one embodiment, theARC layer 103 may be a film stack include afirst layer 302 formed on asecond layer 304, which is formed on thesubstrate 102, as shown inFIG. 3 . In one embodiment, thefirst layer 302 may be a silicon oxide layer (SiO2) and thesecond layer 304 is a titanium oxide (TiO2) layer or a tin oxide layer (SnO2) or vise versa. In one embodiment, thefirst layer 302 formed in theARC layer 103 is a silicon oxide layer (SiO2) and thesecond layer 304 is a titanium oxide (TiO2) layer. In another embodiment, theARC layer 103 may include a film stack containing repeated silicon oxide (SiO2) and titanium oxide (TiO2) layers. For example, theARC layer 103 may include a film stack having a first pair of a first silicon oxide (SiO2) layer and a first titanium oxide (TiO2) layer and a second pair having a second silicon oxide layer (SiO2) and a second titanium oxide (TiO2) layer consecutively formed on thesubstrate 102. It is noted that the first layer of silicon oxide layer (SiO2) and the second layer of titanium oxide (TiO2) layer may be repeatedly formed as many times as needed. - In one embodiment, the
first layer 302 is a silicon oxide layer (SiO2) that has a thickness of about 20 nm and thesecond layer 304 is a titanium oxide (TiO2) layer that has a thickness of about 10 nm fabricated by a PVD process. In another embodiment, the overall thickness of theARC layer 103 may be controlled at between about 30 nm and about 3000 nm, such as about 50 nm and about 1000 nm. As discussed above, theARC layer 103 utilizing this composite film stack may have a refractive index between about 1.1 and 1.4. -
FIG. 4 depicts a magnified view of thebarrier layer 104 disposed on thesecond surface 154 of thesubstrate 102 according to one embodiment of the invention. As discussed above, thebarrier layer 104 may provide similar functions as theARC layer 103, since it is generally intended to improve the transmission of light to thejunctions barrier layer 104 is configured to have good adhesion between thesubstrate 102 and the first transparent conductive oxide (TCO)layer 106, have a good electrical conductivity, and also act as a barrier to prevent any contaminants (e.g., sodium (Na)) found in thesubstrate 102 from diffusing into theTCO layer 106 andjunctions barrier layer 104 is selected from a material that has high film transparency, high light scattering, high film conductivity, high electrical mobility and sufficient barrier properties (e.g., density) to inhibit the movement of mobile contaminants. - In one embodiment, the
barrier layer 104 may be a titanium oxide (TiO2) layer, a tin oxide layer (SnO2), aluminum oxide layer (Al2O3), or combinations thereof. In another embodiment, thebarrier layer 104 may be a silicon containing layer, such as silicon oxide layer, silicon nitride layer, silicon oxynitride layer or the combinations thereof. Different dopants, such as iron (Fe), chromium (Cr), aluminum (Al) or other suitable elements, may be doped into thebarrier layer 104 to improve the films transparency and conductivity. In one embodiment, thebarrier layer 104 is a tin oxide layer (SnO2), an iron doped a tin oxide layer (SnO2:Fe), a titanium oxide layer (TiO2), an iron doped titanium oxide layer (TiO2:Fe), an aluminum oxide layer (AlxOy) or any other suitable materials. In an exemplary embodiment depicted inFIG. 4 , thebarrier layer 104 may be a composite film having afirst layer 404 formed on asecond layer 402. In one embodiment, thefirst layer 404 may be a titanium oxide (TiO2) layer and thesecond layer 402 may be a tin oxide layer (SnO2). In another embodiment, thefirst layer 404 may be a silicon oxide (SiO2) layer and thesecond layer 402 may be a tin oxide layer (SnO2). In yet embodiment, thefirst layer 404 may be a tin oxide (SnO2) layer and thesecond layer 402 may be a titanium oxide (TiO2) layer. In yet another embodiment, thefirst layer 404 may be a silicon oxide layer (SiO2) and thesecond layer 402 may be a silicon oxynitride (SiON) layer, or silicon oxide layer. Thebarrier layer 104 may have a thickness between about 100 Å and about 600 Å, such as between about 200 Å and about 400 Å. -
FIG. 5 depicts a magnified view of theback metal electrode 122 disposed on thesecond TCO layer 120, according to one embodiment of the invention.FIG. 5 only depicts theback metal electrode 122 and thesecond TCO layer 120 formed in thesolar cells back metal electrode 122 assists in the reflection of light back to thesolar cell junctions back metal electrode 122 may include, but not limited to, a material selected from the group consisting of Al, Ag, Ti, Cr, Au, Cu, Pt, alloys thereof, or combinations thereof. In one particular embodiment, theback metal electrode 122 may be a silver (Ag) layer having different doped formed therein. Suitable dopants that may be doped into the silver layer includes silicon (Si), palladium (Pd), or other suitable elements. The dopants, such as silicon or palladium, may have a concentration controlled between about 0.1 weight percent and about 10 weight percent, such as between 0.15 weight percent and about 7 weight percent in the formed silver (Ag) containing layer. In one embodiment, the doped silver (Ag) layer may be formed by a PVD process that uses a silver target having a desired concentration of a dopant material disposed therein. In this case, the target used in the PVD process may be selected from a silver based target having a concentration of silicon (Si) of between about 0.1 weight percent and about 10 weight percent. Similarly, in the embodiment wherein theback metal electrode 122 is configured to form as a palladium doped silver layer (Ag:Pd), the target utilized in the PVD process may be selected from a silver based target having a palladium element doped therein with a concentration between about 0.1 weight percent and about 10 weight percent. It is believed that aback metal electrode 122 formed from a silver palladium alloy (Ag:Pd) will be highly reflective at wavelengths between 500 and 1100 nm, such as 0%, while also supplying improved adhesive properties versus pure silver and the other silver silicon alloys. In one example, a palladium doped silver layer (Ag:Pd) that has a concentration between about 0.25 and about 7 weight percent is able to achieve a reflectivity of 90%. - In one embodiment, the
back metal electrode 122 may be in form of a composite layer having afirst layer 502 and asecond layer 504 disposed on thefirst layer 502, as shown inFIG. 5 . Anadditional interface layer 501 may be disposed between thefirst layer 502 of theback metal electrode 122 and thesecond TCO layer 120 to improve interface adhesion so that the subsequently formedfirst layer 502 of theback metal electrode 122 will reliably adhere to thesecond TCO layer 120. In one embodiment, theadditional interface layer 501 may be a thin chromium (Cr) layer having a thickness controlled at less than 50 Å, such as about less than 20 Å. In one embodiment, as depicted inFIG. 5 , theback metal electrode 122 includes thefirst layer 502 fabricated from a silicon (Si) or palladium (Pd) doped silver (Ag) layer and the silicon or palladium dopant concentration is controlled to about 0.25 weight percent and have a thickness between about 300 Å and about 2500 Å, such as less than 1500 Å. Thesecond layer 504 is fabricated from a nickel vanadium (NiV) alloy having a thickness between about 300 Å and about 2500 Å, such as less than 1500 Å. Other films, materials, substrates, and/or packaging may be provided overback metal electrode 122 to complete the solar cell device. The formed solar cells may be interconnected to form solar cells, or solar cell modules, which in turn can be connected to form solar cell arrays, which are typically formed by use of a scribing process. An example of a process of forming interconnected solar cells on a substrate is further described in the U.S. patent application Ser. No. 12/483,948 [Attorney Docket Number APPM 14174], filed Jun. 12, 2009, which is incorporated herein by reference in its entirety. - Referring back to
FIGS. 1 and 2 , prior to the deposition of the p-typeamorphous silicon layer 110, a heavily doped heavily doped or degenerately doped amorphous silicon layer (e.g., reference numeral 109) may be formed on theconductive contact layer 108. It is believed that degenerate doping improves charge collection by providing low-resistance contact, or Ohmic type contact. Degenerate doping is also believed to improve conductivity of the amorphous silicon layer. Details description and examples of the heavily doped heavily doped or degenerately doped amorphous silicon layer ormicrocrystalline silicon layer 109 is disclosed in U.S. application Ser. No. 12/481,175 (Attorney Docket's Number 14329) filed on Jun. 9, 2009 by Sheng et al., which is herein incorporated by reference in its entirety. The charge collection attributes oflayer 109 is generally provided by the use of doped semiconductor layers, such as silicon layers doped with p-type or n-type dopants. P-type dopants are generally Group III elements, such as boron or aluminum. N-type dopants are generally Group V elements, such as phosphorus, arsenic, or antimony. In most embodiments, boron is used as the p-type dopant and phosphorus as the n-type dopant. These dopants may be added to the p-type and n-type layers - Dopants will generally be provided as dilute gas mixtures in an inert gas. For example, dopants may be provided at molar or volume concentrations of about 0.5% in a carrier gas. If a dopant is provided at a volume concentration of 0.5% in a carrier gas flowing at 1.0 sccm/L, the resultant dopant flow rate will be 0.005 sccm/L. Dopants may be provided to a reaction chamber at flow rates between about 0.0002 sccm/L and about 0.1 sccm/L depending on the degree of doping desired.
- In one embodiment, the
layer 109 is a degeneratively-doped p-type amorphous silicon layer (e.g., heavily doped p-type amorphous silicon, p++ layer). The degenerately (e.g., heavily) doped p++-type amorphous silicon layer may have a Group III element doping concentration that is higher than the p-typeamorphous silicon layer 110. The degenerately doped p++-type amorphous silicon layer has a doping concentration equivalent to a layer formed using TMB and silane at a flow rate ratio by volume between about 2:1 and about 6:1 at a pressure of between about 2 and about 2.5 Torr, where the TMB precursor comprises 0.5% molar or volume concentration of TMB. The degenerately (e.g., heavily) doped p++-type amorphous silicon layer is formed at a plasma power between about 45 milliwatts/cm2 (2400 Watts) and about 91 milliwatts/cm2 (4800 Watts). In one example, the degenerately doped p++-type amorphous silicon layer may be formed by providing silane at a flow rate of between about 2.1 sccm/L (e.g., 6000 sccm) about 3.1 sccm/L (e.g., 9000 sccm), hydrogen gas at a flow rate so that the hydrogen gas to silane gas mixture ratio is about 6.0, a doping precursor at a TMB gas (e.g., 0.5% molar or volume concentration of TMB) to silane gas mixture flow rate ratio by volume of 6:1, while the substrate support temperature is maintained at about 200° C., the plasma power is controlled between about 57 milliwatts/cm2 (3287 Watts) and the chamber pressure is maintained at about 2.5 Torr for about 2-10 seconds to form about a 10-50 Å film, such as a 20 Å film. In one embodiment, the heavily doped amorphous silicon layer has a Group III element dopant concentration formed in the amorphous silicon layer between about 1020 atoms/cm3 and about 1021 atoms/cm3. - In one embodiment, the degeneratively-doped p++-type amorphous silicon layer may be formed as a heavily doped p-type amorphous silicon carbide layer. The carbon elements may be provided by supplying a carbon containing gas into the gas mixture while forming the heavily doped p++-type amorphous silicon carbide layer. In one embodiment, the addition of methane or other carbon containing compounds, such as CH4, C3H8, C4H10, or C2H2, can be used to form the heavily doped p-type amorphous
silicon carbide layer 109 that absorbs less light than other silicon containing materials. It is believed the addition of carbon to the degeneratively-doped p++-type amorphous silicon layer will improve the transparency of the film so that less light will be absorbed during use, thereby improving the conversion efficiency of the solar cell. In one embodiment, the carbon concentration in the heavily doped p++-type amorphous silicon carbide layer is controlled to a concentration between about 1 atomic percent and about 50 atomic percent. In one embodiment, the heavily doped p++-type amorphous silicon carbide layer has a thickness between about 20 Å and about 300 Å, such as between about 10 Å and about 200 Å, for example between about 20 Å and about 100 Å. - In one embodiment, the heavily doped p++-type layer is a heavily doped p-type amorphous silicon layer and the p-type
amorphous silicon layer 110, subsequently formed thereon, may be configured as a p-type amorphous silicon layer or a p-type amorphous silicon carbide layer. In another embodiment wherein the heavily doped p++-type layer is formed as a heavily doped amorphous silicon carbide layer, the p-typeamorphous silicon layer 110 subsequently formed thereon may be configured as a p-type amorphous silicon carbide layer. Details description and examples of the heavily doped heavily doped or degenerately doped amorphous silicon layer ormicrocrystalline silicon layer 109 is disclosed in U.S. application Ser. No. 12/481,175 (Attorney Docket's Number 14329) filed on Jun. 9, 2009 by Sheng et al., which is incorporated by reference in its entirety. - After the degeneratively-doped doped p++-type amorphous silicon layer is formed on the
conductive contact layer 108, the p-typeamorphous silicon layer 110 may be deposited by providing a gas mixture of hydrogen gas to silane gas in a ratio of about 20:1 or less. Silane gas may be provided at a flow rate between about 1 sccm/L and about 10 sccm/L. Hydrogen gas may be provided at a flow rate between about 5 sccm/L and 60 sccm/L. Trimethylboron may be provided at a flow rate between about 0.005 sccm/L and about 0.05 sccm/L. If trimethylboron is provided in a 0.5% molar or volume concentration in a carrier gas, then the dopant/carrier gas mixture may be provided at a flow rate between about 1 sccm/L and about 10 sccm/L. Additionally, a carbon containing gas may be supplied in the gas mixture to deposit p-typeamorphous silicon layer 110 as well to form p-typeamorphous silicon layer 110 as a carbon doped p-type amorphous silicon layer. Suitable examples of carbon containing gas include CH4, C3H8, C4H10, or C2H2, or any suitable carbon containing gas. Carbon containing gas may be provided at a flow rate between about 0.001 sccm/L and about 5 sccm/L. Applying RF power between about 15 mWatts/cm2 and about 200 mWatts/cm2 at a chamber pressure between about 0.1 Torr and 20 Torr, for example between about 1 Torr and about 4 Torr, will deposit a p-typeamorphous silicon layer 110 at about 100 Å/min or more. In one embodiment, the p-typeamorphous silicon layer 110 may have a thickness between about 60 Å and about 300 Å. In one example, the p-typeamorphous silicon layer 110 has a Group III element dopant concentration of between about 1018 atoms/cm3 and about 1020 atoms/cm3. - After the p-type
amorphous silicon layer 110 is formed on thesubstrate 102, the barrier layer, such as theinterface barrier layer 111 depicted inFIGS. 1 and 2 , may be formed on the p-typeamorphous silicon layer 110. It is noted that theinterface barrier layer 111 may be formed within the same chamber in which the p-typeamorphous silicon layer 110 is formed. It is noted that theinterface barrier layer 111 may also be formed within the same chamber in which the subsequent intrinsic typeamorphous silicon layer 112 is formed. Alternatively, theinterface barrier layer 111 may be formed in any suitable deposition chamber, such as a separate stand-alone CVD or PVD deposition chamber, as needed. - In one embodiment, the
interface barrier layer 111 has a dopant, such as carbon, nitrogen, or other suitable elements, disposed therein. In one embodiment, theinterface barrier layer 111 is formed as a carbon containing silicon containing layer. For example, theinterface barrier layer 111 is formed as a carbon doped amorphous silicon layer, such as a silicon carbide layer (SiC). Theinterface barrier layer 111 serves as a cap layer and/or barrier layer that prevents the dopants, such as boron, in the underlying p-typeamorphous silicon layer 110 from diffusing into the nearby adjacent layers during the subsequent deposition processes, thereby reducing the likelihood of contaminating or damaging the film layers and the solar cell devices formed on thesubstrate 102. It is believed that the carbon element formed in theinterface barrier layer 111 can efficiently strengthen the silicon bonding microstructures with stronger silicon-carbon (Si—C) bonds formed therein, thereby providing a robust bonding network and thus preventing impurities and dopants from diffusion to the adjacent film layers. Boron diffusion is believed to be aided by certain defects, such as dangling bonds formed in amorphous silicon, or interstitials in crystalline silicon layers. Accordingly, carbon element formed in theinterface barrier layer 111 may act as trap sties to capture boron elements so as to slow down or eliminate the boron diffusion. - Furthermore, the
interface barrier layer 111 can be a carbon rich film that is stable enough to withstand the high temperature or plasma processing environments used to form or alter portions of the solar cell in the subsequent process steps. The carbon richinterface barrier layer 111 also provides manufacture flexibility to offset minor structure changes from the underlying p-type layer 110 so that the addition of theinterface barrier layer 111 in the solar cell structure will only produces negligible series resistance increase. Details and examples of the optionalinterface barrier layer 111 and the low film bandgap intrinsic typeamorphous silicon layer 112 are disclosed in U.S. application Ser. No. 12/582,323 (Attorney Docket's Number 14466) filed on Oct. 20, 2009 by Sheng et al. which is herein incorporated by reference in its entirety. In one embodiment, theinterface barrier layer 111 may be deposited by providing a gas mixture includes at least a carbon containing gas and a silicon containing gas. Suitable examples of carbon containing gas include CH4, C3H8, C4H10, or C2H2, or any suitable carbon containing gas. Suitable examples of the silicon containing gas include silane (SiH4), disilane (Si2H6), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), combinations thereof and the like. In an exemplary embodiment, the carbon containing gas used to deposit theinterface barrier layer 111 is CH4 and the silicon containing gas used to deposit the barrier layer is SiH4. The CH4 gas supplied in the gas mixture has a ratio to silane gas of about 0.5:1 or less. Silane gas may be provided at a flow rate between about 1 sccm/L and about 10 sccm/L. The RF power is applied between about 15 mWatts/cm2 and about 200 mWatts/cm2 to the processing chamber. The chamber pressure is maintained between about 0.1 Torr and 20 Torr, such as between about 1 Torr and about 4 Torr. In one embodiment, thebarrier layer 111 is formed to have a thickness between about 1 Å and about 200 Å, such as about 10 Å and about 25 Å, for example, about 20 Å. - In one embodiment, in which the
interface barrier layer 111 and the p-typeamorphous silicon layer 110 are formed in the same chamber, the gas mixture supplied to the processing chamber may be varied to deposit different layers on the substrate during the different deposition process steps. For example, in one embodiment, the gas mixture supplied to deposit the p-typeamorphous silicon layer 110 may include at least a silicon containing gas, a carbon containing gas, and a Group III containing gas while the gas mixture supplied to deposit theinterface barrier layer 111 may include at least a silicon containing gas and a carbon containing gas. - In one embodiment, during the deposition of the p-type
amorphous silicon layer 110 and theinterface barrier layer 111 in the same chamber, the gas mixture supplied to the processing chamber may initially include the silicon containing gas, Group III containing gas, and the carbon containing gas. After the p-typeamorphous silicon layer 110 has reached a desired thickness on thesubstrate 102, the Group III containing gas supplied in the gas mixture may subsequently turned off to deposit theinterface barrier layer 111 on the substrate without breaking vacuum. The gas species supplied in the gas mixture may be smoothly switched and transitioned to deposit the p-typeamorphous silicon layer 110 and theinterface barrier layer 111 can have a graded interface. In this example, the material layers can be deposited on thesubstrate 102 in a single chamber without having to be transferred between different chambers. It is noted that the gas flow rate may be varied as need to deposit each of the layers. - After the
interface barrier layer 111 is formed on thesubstrate 102, the intrinsic type amorphous layer 112 (FIGS. 1-2 ) is then formed on theinterface barrier layer 111. The intrinsic typeamorphous silicon layer 112 is formed under a process condition having a relatively high temperature, a relatively low pressure, and a relatively low hydrogen dilution ratio (e.g., low H2/SiH4 ratio). The relatively high temperature, relatively low pressure, relatively low hydrogen dilution ratio (e.g., low H2/SiH4 ratio) process condition described herein results in an intrinsic typeamorphous silicon layer 112 having relatively lower film bandgap that absorbs a broader light spectrum and improves the solar cell's conversion efficiency. It is believed that the relatively high temperature used during the deposition process may assist in producing smaller bandgap films that have a low defect density and high current generation, which may advantageously improve the overall conversion efficiency of the solar cell junction. In one embodiment, it is believed that the processes described herein can be used to reduce the band gap of theamorphous silicon layer 112 to between about 1.70 eV and about 1.75 eV versus more conventionally formed amorphous silicon layers that typically have a band gap of about 1.78 eV. Preferably, the band gap of the formedamorphous silicon layer 112 is between about 1.70 eV and about 1.72 eV. Therefore, using the deposition techniques described herein, the formed amorphous silicon layer can deliver about a 5% reduction in the effective band gap as measured using the Tauc method. In one embodiment, the deposition temperature is controlled at a range greater than 200 degrees Celsius, such as between about 220 degrees Celsius and about 300 degrees Celsius, for example, between about 220 degrees Celsius and about 250 degrees Celsius. In certain circumstances, the use of a high temperature deposition process could cause dopants in the p-typeamorphous silicon layer 110 to diffuse into the intrinsic typeamorphous silicon layer 112 or adjacent film layers during the subsequent deposition process(es). Accordingly, by adding theinterface barrier layer 111 disposed between the p-typeamorphous silicon layer 110 and the intrinsic typeamorphous silicon layer 112, theinterface barrier layer 111 can be used to suppress the dopant diffusion into the intrinsic typeamorphous silicon layer 112, thereby maintaining the purity and desired properties of the intrinsic typeamorphous silicon layer 112. - Furthermore, the relatively low deposition pressure used to form the intrinsic type
amorphous silicon layer 112, such as less than 2.5 Torr, may also assist in depositing a layer that has good optoelectronic and microstructural properties and having less cluster phase hydrogen formed in the resultant amorphous silicon film, leading to a smaller bandgap and improved electrical properties in the formed film layer. It is believed that higher cluster phase hydrogen formed in the resultant film may increase the crystallinity of the resultant film, thereby reducing the likelihood of forming the resultant film as an amorphous silicon layer. In one embodiment, the process pressure controlled during the deposition is less than about 2.5 Torr, such as about less than 2 Torr, such as about 0.1 Torr and about 1.8 Torr, for example, about 1 Torr and about 1.5 Torr. An RF power between about 15 milliWatts/cm2 and about 250 milliWatts/cm2 may be provided to the processing chamber. - Additionally, the relatively low hydrogen dilution supplied in the gas mixture for depositing the intrinsic type
amorphous silicon layer 112 may also assist in depositing an intrinsic typeamorphous silicon layer 112 that has a smaller bandgap. It is believed that lower hydrogen gas flow during the deposition process will reduce the hydrogen content in the formed intrinsic type amorphous silicon layer, thereby reducing the chance of forming crystalline regions in theamorphous silicon layer 112, thus tending to produce an amorphous film, instead of microcrystalline silicon film. A smaller bandgap amorphous silicon layer may be produced by the positioning of hydrogen atoms in amorphous silicon states of the intrinsic typeamorphous silicon layer 112. The amorphous silicon layers may assist obtaining light at a longer wavelength, thereby increasing current generation in the junction cells. In one embodiment, the hydrogen to silane ratio (H2/SiH4) supplied in the gas mixture is controlled to a level of about less than 10, such as less than 6, for example between about 2 and about 5. Alternatively, silane gas supplied in the gas mixture may be controlled at a flow rate between about 1 sccm/L and about 10 sccm/L. Hydrogen gas may be controlled at a flow rate between about 2 sccm/L and 100 sccm/L. An optional carrier gas, or inert gas, such as Ar and He or the like, may also be supplied into the gas mixture if necessary. In the embodiment wherein the carrier gas or inert gas is supplied into the processing chamber, the gas flow rate of the carrier gas or inert gas may be controlled at between about 2 sccm/L and about 100 sccm/L. - Accordingly, by providing a relatively high deposition temperature, relatively low deposition pressure, and a low hydrogen dilution ratio during the deposition process, an intrinsic
amorphous silicon film 112 with low film bandgap can be obtained. Furthermore, by adding theinterface barrier layer 111 between the p-typeamorphous silicon layer 110 and the intrinsic typeamorphous silicon layer 112, theinterface barrier layer 111 can be used to prevent the dopants contained in the p-typeamorphous silicon layer 110 from diffusing into the adjacent and/or upper intrinsic typeamorphous silicon layer 112, thereby forming an intrinsic typeamorphous silicon layer 112 that has a desirable purity, electrical properties and optical properties. Therefore, the high temperature process used to form the intrinsic type amorphous silicon layer will not damage or destroy the film properties or device performance of a formed solar cell, which would normally be found in conventionally formed devices. By use of the aforementioned intrinsic type amorphous silicon deposition process and barrier layer formation process, the formed amorphous silicon based solar cell junction can efficiently convert longer wavelengths of light, even after correcting for light induced degradation (LID) by prolonged light-soaking, thereby improving the overall device performance and solar cell device conversion efficiency. - In one embodiment, the intrinsic type
amorphous silicon layer 112 may be formed to a thickness between about 1,500 Å and about 4,500 Å, such as between about 2,000 Å and about 4,000 Å, for example about 3000 Å and about 3500 Å. It is believed that the intrinsic typeamorphous silicon layer 112 with a higher thickness, such as greater than 2800 Å, may have increase light absorption in the intrinsic typeamorphous silicon layer 112, thereby retaining light in the intrinsic typeamorphous silicon layer 112 for a longer time for higher current generation. In one embodiment, the intrinsic typeamorphous silicon layer 112 may be formed to a thickness between about 3,000 Å and about 3,500 Å. - After the intrinsic type
amorphous silicon layer 112 is formed on theinterface barrier layer 111, the n-type microcrystalline silicon layer 114 (FIGS. 1-2 ) is formed on the intrinsic typeamorphous silicon layer 112. In one embodiment, the n-typemicrocrystalline silicon layer 114 may be deposited by providing a gas mixture of hydrogen gas to silane gas in a ratio of about 100:1 or more, such as about 500:1 or less, such as between about 150:1 and about 400:1, for example about 304:1 or about 203:1. Silane gas may be provided at a flow rate between about 0.1 sccm/L and about 0.8 sccm/L, such as between about 0.32 sccm/L and about 0.45 sccm/L, for example about 0.35 sccm/L. Hydrogen gas may be provided at a flow rate between about 30 sccm/L and about 250 sccm/L, such as between about 68 sccm/L and about 143 sccm/L, for example about 71.43 sccm/L. Phosphine may be provided at a flow rate between about 0.0005 sccm/L and about 0.006 sccm/L, such as between about 0.0025 sccm/L and about 0.015 sccm/L, for example about 0.005 sccm/L. In other words, if phosphine is provided in a 0.5% molar or volume concentration in a carrier gas, then the dopant/carrier gas may be provided at a flow rate between about 0.1 sccm/L and about 5 sccm/L, such as between about 0.5 sccm/L and about 3 sccm/L, for example between about 0.9 sccm/L and about 1.088 sccm/L. Applying RF power between about 100 mW/cm2 and about 900 mW/cm2, such as about 370 mW/cm2, at a chamber pressure of between about 1 Torr and about 100 Torr, for example between about 3 Torr and about 20 Torr, such as between 4 Torr and about 12 Torr, for example about 6 Torr or about 9 Torr, will deposit an n-type microcrystalline silicon layer having a crystalline fraction between about 20 percent and about 80 percent, for example between 50 percent and about 70 percent, at a rate of about 50 Å/min or more, such as about 150 Å/min or more. - In one embodiment, one or more elements may be added to n-type
microcrystalline silicon layer 114, such as carbon atoms by supplementing the reactant gas mixture with sources of carbon to form an n-type microcrystalline silicon carbide (mc-SiC) layer. For example, carbon may be added to the film by adding a carbon source, such as methane (CH4), C3H8, C4H10, or C2H2, to the gas mixture while forming the n-typemicrocrystalline silicon layer 114. In general, most C1-C4 hydrocarbons may be used as carbon sources. In one embodiment, the n-type silicon carbide layer formed for the n-typemicrocrystalline silicon layer 114 may have between about 1 atomic % and about 50 atomic % carbon. The quantity of secondary components may be adjusted by adjusting the ratios of precursor gases in the processing chamber. The ratios may be adjusted in steps to form layered structures, or continuously to form a single layer having a graded composition. In one embodiment, the ratio of the carbon containing gas flow, such as the methane (CH4) gas flow, to silane flow rate is between about 0 and about 0.5, such as between about 0.20 and about 0.35, for example about 0.25. The ratio of methane gas to silane in the feed may be varied to adjust the amount of carbon in the deposited n-typemicrocrystalline silicon layer 114. - It is believed that the carbon atoms disposed in the n-type microcrystalline silicon layer will allow a highly conductive layer to be formed that has an adjustable bandgap and refractive index. Microcrystalline silicon carbide, for example, can develop a layer that has a crystalline fraction above 60%, a bandgap width above 2 electron volts (eV), and conductivity greater than 0.1 siemens per centimeter (S/cm). The bandgap and refractive index can be adjusted by varying the ratio of methane to silane in the reaction mixture. In one embodiment, the ratio of methane gas flow rate to silane flow rate is between about 0 and about 0.5, such as between about 0.20 and about 0.35, for example about 0.25. Moreover, it can be deposited at rates of 150-200 Å/min with thickness variation less than 10%. The adjustable refractive index allows formation of a reflective layer that is highly conductive with wide bandgap, resulting in improved current and fill factor. Details description and examples of the doped n-type
microcrystalline silicon layer 114 is disclosed in U.S. application Ser. No. 12/208,478 (Attorney Docket's Number 13551) filed on Sep. 11, 2008 by Sheng et al., U.S. Application Ser. No. 61/139,390 (Attorney Docket's Number 13551L) filed on Dec. 19, 2008 by Sheng et al., which are incorporated by reference in their entirety. - Referring now to
FIG. 2 , after the firstp-i-n junction 116, and theoptional WSR layer 150, is formed on thesubstrate 102, the secondp-i-n junction 136 is subsequently formed on the firstp-i-n junction 116 and/or theWSR layer 150. The secondp-i-n junction 136 includes the p-typemicrocrystalline silicon layer 130, the intrinsic typemicrocrystalline silicon layer 132, and the n-typeamorphous silicon layer 134. In one embodiment, the p-typemicrocrystalline silicon layer 130 may be deposited by providing a gas mixture of hydrogen gas and silane gas in ratio of hydrogen-to-silane of about 200:1 or greater, such as 1000:1 or less, for example between about 250:1 and about 800:1, and in a further example about 601:1 or about 401:1. Silane gas may be provided at a flow rate between about 0.1 sccm/L and about 0.8 sccm/L, such as between about 0.2 sccm/L and about 0.38 sccm/L. Hydrogen gas may be provided at a flow rate between about 60 sccm/L and about 500 sccm/L, such as about 143 sccm/L. TMB may be provided at a flow rate between about 0.0002 sccm/L and about 0.0016 sccm/L, such as about 0.00115 sccm/L. If TMB is provided in a 0.5% molar or volume concentration in a carrier gas, then the dopant/carrier gas mixture may be provided at a flow rate between about 0.04 sccm/L and about 0.32 sccm/L, such as about 0.23 sccm/L. It has been found that by applying an RF power between about 50 mW/cm2 and about 700 mW/cm2, such as between about 290 mW/cm2 and about 440 mW/cm2, and maintaining the chamber pressure at between about 1 Torr and about 100 Torr, preferably between about 3 Torr and about 20 Torr, more preferably between 4 Torr and about 12 Torr, such as about 7 Torr or about 9 Torr, a p-type microcrystalline layer having crystalline fraction between about 20 percent and about 80 percent, preferably between 50 percent and about 70 percent for a microcrystalline layer can be deposited at a deposition rate of about 10 Å/min or more, such as about 143 Å/min or more. - After the p-type
microcrystalline silicon layer 130 is formed on thesubstrate 102, the intrinsic typemicrocrystalline silicon layer 132 is then formed on the p-typemicrocrystalline silicon layer 130. The intrinsic typemicrocrystalline silicon layer 132 may be deposited by providing a gas mixture of silane gas and hydrogen gas in a ratio of hydrogen to silane between about 20:1 and about 200:1. Silane gas may be provided at a flow rate between about 0.5 sccm/L and about 5 sccm/L. Hydrogen gas may be provided at a flow rate between about 40 sccm/L and about 400 sccm/L. In certain embodiments, the silane flow rate may be ramped up from a first flow rate to a second flow rate during deposition. In certain embodiments, the hydrogen flow rate may be ramped down from a first flow rate to a second flow rate during deposition. Applying RF power between about 300 mW/cm2 or greater, such as about 600 mW/cm2 or greater, at a chamber pressure between about 1 Torr and about 100 Torr, for example between about 3 Torr and about 20 Torr, such as between about 4 Torr and about 12 Torr, will generally deposit an intrinsic type microcrystalline silicon layer having crystalline fraction between about 20 percent and about 80 percent, such as between 55 percent and about 75 percent, at a rate of about 200 Å/min or more, for example about 500 Å/min. In one embodiment, the deposited intrinsic type microcrystalline silicon layer has crystalline fraction between about 60 percent and about 65 percent and has a desired layer thickness, in an effort to balance out the decrease in deposition rate as the crystal fraction is increased and the lower required thickness of the formed i-layer as the crystal fraction is increased. In some embodiments, it may be advantageous to ramp the power density of the applied RF power from a first power density to a second power density during deposition. - In another embodiment, the intrinsic type
microcrystalline silicon layer 132 may be deposited in multiple steps, each formed region having a different crystal fraction. In one embodiment, for example, the ratio of hydrogen to silane may be reduced in four steps from 100:1 to 95:1 to 90:1 and then to 85:1. In one embodiment, silane gas may be provided at a flow rate between about 0.1 sccm/L and about 5 sccm/L, such as about 0.97 sccm/L. Hydrogen gas may be provided at a flow rate between about 10 sccm/L and about 200 sccm/L, such as between about 80 sccm/L and about 105 sccm/L. In an exemplary embodiment wherein the deposition has multiple steps, such as four steps, the hydrogen gas flow may start at about 97 sccm/L in the first step, and be gradually reduced to about 92 sccm/L, 88 sccm/L, and 83 sccm/L respectively in the subsequent process steps. In the mean while, the hydrogen to silane ratio is controlled at 100:1, 95:1, 90:1 and 85:1 respectively in each process step. Applying RF power between about 300 mW/cm2 or greater, such as about 490 mW/cm2 at a chamber pressure between about 1 Torr and about 100 Torr, for example between about 3 Torr and about 20 Torr, such as between about 4 Torr and about 12 Torr, such as about 9 Torr, will result in deposition of an intrinsic type microcrystalline silicon layer at a rate of about 200 Å/min or more, such as 400 Å/min. - After the intrinsic type
microcrystalline silicon layer 132 is formed on the p-typemicrocrystalline silicon layer 130, the n-typeamorphous silicon layer 134 may be formed on the intrinsic typemicrocrystalline silicon layer 132. Alternatively, the n-type silicon layer 134 may be formed from a crystalline silicon based film having a crystalline fraction between about 20% and about 100%. In one embodiment wherein the n-type layer 134 is formed as an n-type amorphous silicon layer, the n-typeamorphous silicon layer 134 may be deposited by providing a gas mixture containing a hydrogen gas to silane gas in a ratio of about 20:1 or less, such as about 5:5:1 or 7.8:1. Silane gas may be provided at a flow rate between about 0.1 sccm/L and about 10 sccm/L, such as between about 1 sccm/L and about 10 sccm/L, between about 0.1 sccm/L and 5 sccm/L, or between about 0.5 sccm/L and about 3 sccm/L, for example about 1.42 sccm/L or 5.5 sccm/L. Hydrogen gas may be provided at a flow rate between about 1 sccm/L and about 40 sccm/L, such as between about 4 sccm/L and about 40 sccm/L, or between about 1 sccm/L and about 10 sccm/L, for example about 6.42 sccm/L or 27 sccm/L. Phosphine may be provided at a flow rate between about 0.0005 sccm/L and about 0.075 sccm/L, such as between about 0.0005 sccm/L and about 0.0015 sccm/L or between about 0.015 sccm/L and about 0.03 sccm/L, for example about 0.0095 sccm/L or 0.023 sccm/L. If phosphine is provided in a 0.5% molar or volume concentration in a carrier gas, then the dopant/carrier gas mixture may be provided at a flow rate between about 0.1 sccm/L and about 15 sccm/L, such as between about 0.1 sccm/L and about 3 sccm/L, between about 2 sccm/L and about 15 sccm/L, or between about 3 sccm/L and about 6 sccm/L, for example about 1.9 sccm/L or about 4.71 sccm/L. Applying RF power between about 25 mW/cm2 and about 250 mW/cm2, such as about 60 mW/cm2 or about 80 mW/cm2, at a chamber pressure between about 0.1 Torr and about 20 Torr, preferably between about 0.5 Torr and about 4 Torr, such as about 1.5 Torr, will deposit an n-type amorphous silicon layer 134 at a rate of about 100 Å/min or more, such as about 200 Å/min or more, such as about 300 Å/min or about 600 Å/min. - In the embodiment wherein the n-
type silicon layer 134 is formed as the n-type microcrystalline silicon layer, the n-typemicrocrystalline silicon layer 134 may be formed by the process similar to or the same as the process described above utilized to form the n-typemicrocrystalline silicon layer 114 for the firstp-i-n junction 116. - In one embodiment, one or more elements may be added to n-type amorphous or
microcrystalline silicon layer 134, such as carbon atoms by supplementing the reactant gas mixture with a source of carbon to form a n-type microcrystalline/amorphous silicon carbide (mc-SiC or α-SiC) layer. For example, carbon may be added to the film by adding a carbon source, such as methane (CH4), C3H8, C4H10, or C2H2, to the gas mixture while forming the n-type microcrystalline/amorphous silicon carbide (mc-SiC or α-SiC)layer 134. In general, most C1-C4 hydrocarbons may be used as carbon sources. In one embodiment, the n-type silicon carbide layer formed for the microcrystalline/amorphous silicon carbide (mc-SiC or α-SiC)layer 134 may have between about 1 atomic % and about 50 atomic % carbon. The quantity of secondary components may be adjusted by adjusting the ratios of precursor gases in the processing chamber. The ratios may be adjusted in steps to form layered structures, or continuously to form graduated single layers. In one embodiment, the ratio of the carbon containing gas flow, such as the methane (CH4) gas flow, to silane flow rate is between about 0 and about 0.5, such as between about 0.20 and about 0.35, for example about 0.25. The ratio of methane gas to silane in the feed may be varied to adjust the amount of carbon in the deposited n-type microcrystalline/amorphous silicon carbide (mc-SiC or α-SiC)layer 134. - It should be noted that in many embodiments of the invention a pre-clean processes may be used to prepare substrates and/or reaction chambers for deposition of any of the above layers. A hydrogen or argon plasma pre-treat process may be performed to remove contaminants from the exposed surface of the substrate and/or chamber walls by supplying hydrogen gas or argon gas to the processing chamber between about 10 sccm/L and about 45 sccm/L, such as between about 15 sccm/L and about 40 sccm/L, for example about 20 sccm/L and about 36 sccm/L. In one example, the hydrogen gas may be supplied at about 21 sccm/L or the argon gas may be supplied at about 36 sccm/L. The treatment is accomplished by applying RF power between about 10 mW/cm2 and about 250 mW/cm2, such as between about 25 mW/cm2 and about 250 mW/cm2, for example about 60 mW/cm2 or about 80 mW/cm2 for hydrogen treatment and about 25 mW/cm2 for argon treatment. In many embodiments it may be advantageous to perform an argon plasma pre-treatment process prior to depositing a p-type amorphous silicon layer, and a hydrogen plasma pre-treatment process prior to depositing other types of layers.
- As discussed above, after the second
p-i-n junction 136 is formed on thesubstrate 102, the conductiveindex matching layer 118, thesecond TCO layer 120, and theback metal electrode 122 is then consecutively formed thereon to complete the manufacture of the tandem junctionsolar cell 200 as depicted inFIG. 2 . -
FIG. 6 depicts is a process flow diagram of a method for manufacturing a solar cell on a substrate according to one embodiment of the invention. Similar to the structures discussed above with referenced toFIGS. 1 and 2 , theprocess sequence 600 begins atstep 602 in which an ARC layer is formed on a surface of asubstrate 102. In one embodiment,step 602 is performed using one or more of the process steps used to form an ARC that is described above. In one embodiment, the ARC layer is formed during the glass manufacturing process, and thus step 602 includes providing a substrate, such as thesubstrate 102, having theARC layer 103 formed thereon into a solar cell production line, such as theproduction line 900 depicted below with referenced toFIG. 9 . In one embodiment, theARC layer 103 is a fluorine and carbon containing silicon based material coated on thesubstrate 102 by a sol-gel spray process. In another embodiment, theARC layer 103 is an inorganic material, such as a TiO2 layer, a composite film of SiO2 and TiO2 layer, or other suitable materials, formed by a CVD, PVD or other suitable deposition techniques. In one exemplary embodiment, theARC layer 103 is a composite film having a film stack including a first pair of SiO2 and TiO2 layer and a second pair of SiO2 and TiO2 layer consecutively formed on thefirst surface 152 of thesubstrate 102. In one embodiment, theARC layer 103 has a film refractive index at between about 1.1 and 1.4 and a thickness between about 30 nm and about 3000 nm. - In one embodiment, it is believed that the
ARC 103 layer disposed on thesubstrate 102 may improve the overall current gain (conversion efficiency) of thesolar cell substrate 102 is made from a low iron glass that has an iron concentration of between about 0.01 percent by weight and about 0.03 percent by weight. - At
step 604, thebarrier layer 104 may be formed on thesecond surface 154 of thesubstrate 102. As discussed above, thebarrier layer 104 may be formed from a material that has high film conductivity and mobility so as to reduce the resistance of thefirst TCO layer 106. In one embodiment, thebarrier layer 104 is a tin oxide layer (SnO2) or an iron doped a tin oxide layer (SnO2:Fe). In another embodiment, thebarrier layer 104 is a silicon oxynitride, silicon nitride, silicon oxide layer, or combinations thereof. In one embodiment, thebarrier layer 104 may be fabricated by a PVD chamber or a CVD chamber included in the production line of the solar cell system, such as theproduction line 900 depicted inFIG. 9 , as further discussed below. In another embodiment, thebarrier layer 104 may be pre-coated or pre-fabricated on thesubstrate 102 by a glass supplier prior to providing into the solar cell production line for processing. In one embodiment, thebarrier layer 104 has a thickness between about 200 Å and about 400 Å. In one embodiment, it is believed that thebarrier layer 104 disposed on thesubstrate 102 may improve overall current gain (conversion efficiency) of thesolar cell - At
step 606, thefirst TCO layer 106 is formed on thebarrier layer 104. Thefirst TCO layer 106 may be a ZnO2, ITO, SnO2, iron doped SnO2 layer, aluminum doped ZnO2 (AZO) layer, titanium oxide layer, doped titanium oxide layer or any other suitable materials, as discussed above. In one exemplary embodiment depicted inFIGS. 1 and 2 , thefirst TCO layer 106 is a SnO2 or an iron doped SnO2 layer. Alternatively, thefirst TCO layer 106 is an aluminum oxide doped ZnO2 (AZO) layer having an aluminum oxide dopant concentration at about 1 percent by weight and a zinc oxide material about 99 percent by weight. - At
step 608, after thefirst TCO layer 106 is disposed on thesubstrate 102, theconductive contact layer 108 is formed on thefirst TCO layer 106. As discussed above, theconductive contact layer 108 provides a good interface between thefirst TCO layer 106 and subsequent to-be-formedsolar cell junction 116. In one embodiment, theconductive contact layer 108 may be a titanium layer (Ti), tantalum layer, aluminum layer, titanium oxide layer (TiO2), tantalum oxide layer, aluminum oxide layer and doped titanium containing layer, such as niobium doped titanium oxide layer (TiO2:Nb) or aluminum doped titanium oxide layer (TiO2:Al). In one embodiment, theconductive contact layer 108 may have a thickness between about 200 Å and about 700 Å In one embodiment, it is believed that theconductive contact layer 108 disposed on thesubstrate 102 may improve overall current gain (conversion efficiency) of thesolar cell - At
step 610, after theconductive contact layer 108 is formed on thesubstrate 102, the firstp-i-n junction 116 is formed on theconductive contact layer 108. As discussed above, the firstp-i-n junction 116 includes the heavily doped p-typeamorphous silicon layer 109, the p-typeamorphous silicon layer 110, optionalinterface barrier layer 111, the intrinsic typeamorphous silicon layer 112 and the n-typemicrocrystalline silicon layer 114. As the intrinsic typeamorphous silicon layer 112 may be formed having a relatively smaller bandgap by utilizing the process conditions of relatively high deposition temperature, relatively low pressure and relatively low hydrogen dilution during the deposition process, the intrinsic typeamorphous silicon layer 112 may help to increase the overall conversion efficiency of the solar cell(s) containing the firstp-i-n junction 116 disposed on thesubstrate 102. It is believed that the relatively high temperature used during the deposition process may assist in producing low bandgap films that have a low defect density and high current generation, which may advantageously improve the overall conversion efficiency of the solar cell junction. The relatively low deposition pressure used to form the intrinsic typeamorphous silicon layer 112, such as less than 2.5 Torr, may also assist in depositing a layer that has good optoelectronic and microstructural properties and having less cluster phase hydrogen formed in the resultant film, leading to a smaller bandgap. Furthermore, the relatively low hydrogen dilution supplied in the gas mixture for depositing the intrinsic typeamorphous silicon layer 112 may also assist in depositing an intrinsic typeamorphous silicon layer 112 that has a smaller bandgap. In one embodiment, when the intrinsic typeamorphous silicon layer 112 is formed having a relatively small bandgap, theoptional interface layer 111 may be optionally formed prior to the deposition of the intrinsic type amorphous silicon layer 113, as discussed above. It is believed that by forming an intrinsic typeamorphous silicon layer 112 with a relatively smaller bandgap the conversion efficiency (or overall current gain) of thesolar cells amorphous silicon layer 112 as formed was about 1.71 eV using a hydrogen dilution ration of about 10:1 (SiH4/H2) versus a more conventionally formed amorphous silicon layer that typically has a 1.78 eV band gap, as measured using the Tauc method. - Furthermore, in one embodiment, the n-type
microcrystalline silicon layer 114 formed on the firstp-i-n junction 116 may be formed as an n-type microcrystalline silicon carbide layer. As discussed above, the carbon atoms formed in the n-type microcrystallinesilicon carbide layer 114 is a highly conductive layer that can be formed with a desirable bandgap and refractive index. Accordingly, it is believed that by utilizing n-type microcrystallinesilicon carbide layer 114 in the firstp-i-n junction 116, the overall current gain (conversion efficiency) of thesolar cell FIG. 2 , the overall current gain (conversion efficiency) of thesolar cell 200 may be improved by about 3-9 percent, such as about 7 percent. - At
step 612, an optional wavelength selective reflector (WSR)layer 150 may be formed on the firstp-i-n junction 116. Subsequently, atstep 614, the secondp-i-n junction 136 may be formed on theWSR layer 150 to form thesolar cell 200 as a tandem junction, as shown inFIG. 2 . It is noted that in the embodiment wherein the solar cell is configured to form as a single junction, such as thesolar cell 100 depicted inFIG. 1 ,step line 622, may be eliminated. In the embodiment wherein the solar cell junction is configured to form as a tandem junctionsolar cell 200, as shown inFIG. 2 , theWSR layer 150 atstep 612 and the secondp-i-n junction 136 may be sequentially and consecutively formed on the firstp-i-n junction 116. In one embodiment, theWSR layer 150 may be optional formed on the firstp-i-n junction 116. In the embodiment wherein theWSR layer 150 is not present, the secondp-i-n junction 136 may be directly formed on the firstp-i-n junction 116. In one embodiment, theWSR layer 150 is a n-type microcrystalline silicon carbide layer or silicon oxynitride layer having a thickness between about 500 Å and about 5,000 Å, such as between about 1,000 Å and about 2,000 Å, for example about 1,500 Å. - The second
p-i-n junction 136 formed atstep 614 includes the p-typemicrocrystalline silicon layer 130, the intrinsic typemicrocrystalline silicon layer 132 and the n-typeamorphous silicon layer 134. As discussed above, the n-type layer 134 may be an n-type microcrystalline silicon layer. As discussed above, the secondary dopants, such as carbon atoms or nitrogen dopants, formed in the n-type amorphous/microcrystalline silicon layer 134 may increase the conductivity of the n-type amorphous/microcrystalline silicon layer 134 having a desirable bandgap and refractive index. In one embodiment, the n-type layer 134 formed in the secondp-i-n junction 136 is formed as an n-type amorphoussilicon carbide layer 134. It is believed that by utilizing n-type amorphoussilicon carbide layer 134 in the secondp-i-n junction 136, the overall current gain (conversion efficiency) of thesolar cell 200 may be improved for about 1-3 percent. - At
step 616, the conductiveindex matching layer 118 is formed on the secondp-i-n junction 136, as depicted inFIG. 2 . In the embodiment wherein thesolar cell 100 only includes a single p-i-n junction, the conductiveindex matching layer 118 may be directly formed on the firstp-i-n junction 116 as shown inFIG. 1 . As discussed above, the conductiveindex matching layer 118 is configured to increase light reflection back to the firstp-i-n junction 116 and/or the secondp-i-n junction 136 so as to increase current generation in thejunctions index matching layer 118 is a silicon containing material, such as silicon oxide, silicon carbide, silicon oxynitride, silicon nitride, silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or other suitable silicon containing materials. In another embodiment, the conductiveindex matching layer 118 may also be configured as an indium tin oxide (ITO) layer as needed. In another embodiment, the conductiveindex matching layer 118 may not be formed as a continuous film layer. For example, the conductiveindex matching layer 118 may be formed as a non-continuous film layer, such as a thin layer of particles, to create an uneven reflection surface so as to assist reflecting and scattering light back to the firstp-i-n junction 116 and/or the secondp-i-n junction 136. In one embodiment, the particle size utilized to form the conductiveindex matching layer 118 has a diameter about 10 nm. In one embodiment, the conductivematching index layer 118 is a silicon carbide, silicon nitride, or a silicon oxynitride layer having a film thickness between about 50 Å and about 2000 Å, such as about 200 Å. - In one embodiment, the conductive
index matching layer 118 may be formed by any suitable deposition techniques, such as PVD, CVD, electroplating, electroless plating or any other suitable manners. In one embodiment, the conductiveindex matching layer 118 may be formed in a CVD chamber so that the conductiveindex matching layer 118 may be formed within the same chamber where the n-type layer type layer index matching layer 118 may be formed in-situ in a single chamber without breaking vacuum so as to reduce manufacture cost and manufacture cycle time. In another embodiment, the conductiveindex matching layer 118 may be formed in separate chambers or individually formed in different processing tools or even different production lines as needed. - At
step 618, after the conductiveindex matching layer 118 is formed on thesubstrate 102, thesecond TCO layer 120 is formed on the conductiveindex matching layer 118. Similar to the configuration of thefirst TCO layer 106, thesecond TCO layer 120 may be a ZnO2, ITO, SnO2, aluminum doped ZnO2 (AZO) layer, or any other suitable materials, as discussed above. In one exemplary embodiment depicted inFIGS. 1 and 2 , thesecond TCO layer 120 is an aluminum oxide doped ZnO2 (AZO) layer having an aluminum oxide dopant concentration at about 2 percent by weight in zinc oxide material about 98 percent by weight. In one embodiment, a dopant material (e.g., indium, aluminum) is added to thesecond TCO layer 120 during the deposition process to form a layer that has more desirable optical, conductivity and/or barrier properties. In one example, thesecond TCO layer 120 comprise a tin oxide (SnO2) layer that is doped with less than about 10% of indium. In another example, thesecond TCO layer 120 comprise a tin oxide (SnO2) layer that is doped with less than about 10% of iron (Fe). - At
step 620, theback metal electrode 122 is formed on thesecond TCO layer 120. Theback metal electrode 122 assists reflecting light back to thesolar cell junctions back metal electrode 122 may include, but not limited to, a material selected from the group consisting of Al, Ag, Ti, Cr, Au, Cu, Pt, Ni, V, alloys thereof, or combinations thereof. In one particular embodiment, theback metal electrode 122 may be a silver (Ag) layer having a silicon or palladium (Pd) dopant concentration controlled at about 0.25 weight percent. In one embodiment, theback metal electrode 122 may in form of a composite film having a first layer of the silicon doped silver (Ag) layer and a second layer of nickel (Ni) vanadium (V) alloy material disposed on the first layer of the silicon or palladium (Pd) doped silver (Ag) layer. - Furthermore, an additional interface layer, such as the
additional interface layer 501 depicted inFIG. 5 , may be disposed between theback metal electrode 122 and thesecond TCO layer 120 to improve interface adhesion. In one embodiment, the additional interface layer may be a thin chromium (Cr) layer having a thickness controlled at less than 50 Å, such as about less than 20 Å. - It is believed that by using the additional interface layer, the
back metal electrode 122 with composite structure having the silicon or palladium (Pd) doped silver (Ag) layer and the nickel (Ni) vanadium (V) alloy material disposed on the silicon doped silver (Ag) layer, the overall current gain (conversion efficiency) of thesolar cell - After formation of the
back metal electrode 122, the solar cell structure is completed on thesubstrate 102. Accordingly, by using all the materials, structures, barrier layers, interface layers, and materials as discussed above, the overall current gain (conversion efficiency) of thesolar cell -
FIG. 7 is a schematic cross-section view of one embodiment of a plasma enhanced chemical vapor deposition (PECVD) chamber, orchamber 700, in which one or more films of a thin-film solar cell, such as the solar cells ofFIGS. 1-2 may be deposited. One suitable plasma enhanced chemical vapor deposition chamber is available from Applied Materials, Inc., located in Santa Clara, Calif. It is contemplated that other deposition chambers, including those from other manufacturers, may be utilized to practice the present invention. - The
chamber 700 generally includeswalls 702, a bottom 704, and ashowerhead 710, andsubstrate support 730 which define aprocess volume 706. The process volume is accessed through avalve 708 such that the substrate, may be transferred in and out of thechamber 700. Thesubstrate support 730 includes asubstrate receiving surface 732 for supporting asubstrate 102 and stem 734 coupled to alift system 736 to raise and lower thesubstrate support 730. Ashadow ring 733 may be optionally placed over periphery of thesubstrate 102. Lift pins 738 are moveably disposed through thesubstrate support 730 to move a substrate to and from thesubstrate receiving surface 732. Thesubstrate support 730 may also include heating and/orcooling elements 739 to maintain thesubstrate support 730 at a desired temperature. Thesubstrate support 730 may also include groundingstraps 731 to provide RF grounding at the periphery of thesubstrate support 730. - The
showerhead 710 is coupled to abacking plate 712 at its periphery by asuspension 714. Theshowerhead 710 may also be coupled to thebacking plate 712, orwall 705, by one or more center supports 716 to help prevent sag and/or control the straightness/curvature of theshowerhead 710. Agas source 720 is coupled to thebacking plate 712 to provide gas through thebacking plate 712 and through theshowerhead 710 to thesubstrate receiving surface 732. Avacuum pump 709 is coupled to thechamber 700 to control theprocess volume 706 at a desired pressure. AnRF power source 722 is coupled to thebacking plate 712 and/or to theshowerhead 710 to provide a RF power to theshowerhead 710 so that an electric field is created between theshowerhead 710 and thesubstrate support 730 so that a plasma may be generated from the gases between theshowerhead 710 and thesubstrate support 730. Various RF frequencies may be used, such as a frequency between about 0.3 MHz and about 200 MHz. In one embodiment the RF power source is provided at a frequency of 13.56 MHz. - A
remote plasma source 724, such as an inductively coupled remote plasma source, may also be coupled between thegas source 720 and thebacking plate 712. Between processing substrates, a cleaning gas may be provided to theremote plasma source 724 so that a remote plasma is generated and provided to clean chamber components. The cleaning gas may be further excited by theRF power source 722 provided to the showerhead. Suitable cleaning gases include but are not limited to NF3, F2, and SF6. - The deposition methods for one or more layers, such as one or more of the layers of
FIGS. 1-5 , may include the following deposition parameters in the process chamber ofFIG. 7 or other suitable chamber. A substrate having a surface area of 10,000 cm2 or more, such as 40,000 cm2 or more, and for example 55,000 cm2 or more is provided to the chamber. It is understood that after processing the substrate may be cut to form smaller solar cells. - In one embodiment, the heating and/or
cooling elements 739 may be set to provide a substrate support temperature during deposition of about 400° C. or less, for example between about 100° C. and about 400° C., such as between about 150° C. and about 300° C., such as about 200° C. - The spacing during deposition between the top surface of a substrate disposed on the
substrate receiving surface 732 and theshowerhead 710 may be between 400 mil and about 1,200 mil, such as between 400 mil and about 800 mil. - A
controller 748 is coupled to theprocessing chamber 700. The controller 548 includes a central processing unit (CPU) 760, amemory 758, and supportcircuits 762. Thecontroller 748 is utilized to control the process sequence, regulating the gas flows from thegas source 720 into the chamber 500 and controlling power supply from theRF power source 722 and theremote plasma source 724. TheCPU 760 may be of any form of a general purpose computer processor that can be used in an industrial setting. The software routines can be stored in thememory 758, such as random access memory, read only memory, floppy or hard disk drive, or other form of digital storage. Thesupport circuits 762 are conventionally coupled to theCPU 760 and may comprise cache, clock circuits, input/output subsystems, power supplies, and the like. The software routines, when executed by theCPU 760, transform the CPU into a specific purpose computer (controller) 748 that controls the processing chamber 500 such that the processes, such as described above, are performed in accordance with the present invention. The software routines may also be stored and/or executed by a second controller (not shown) that is located remotely from theprocessing chamber 700. -
FIG. 8 is a top schematic view of one embodiment of aprocess system 800 having a plurality of process chambers 831-837, such asPECVD chamber 700 ofFIG. 7 or other suitable chambers, such as PVD chambers, plating chambers, or coating chambers capable of depositing films for solar cells depicted inFIGS. 1-2 . Theprocess system 800 includes atransfer chamber 820 coupled to aload lock chamber 810 and the process chambers 831-837. Theload lock chamber 810 allows substrates to be transferred between the ambient environment outside thesystem 800 and vacuum environment within thetransfer chamber 820 and process chambers 831-837. Theload lock chamber 810 includes one or more evacuatable regions holding one or more substrate. The evacuatable regions are pumped down during input of substrates into thesystem 800 and are vented during output of the substrates from thesystem 800. Thetransfer chamber 820 has at least onevacuum robot 822 disposed therein that is adapted to transfer substrates between theload lock chamber 810 and the process chambers 831-837. While seven process chambers are shown inFIG. 8 ; this configuration is not intended to be limiting as to the scope of the invention, since the system may have any suitable number of process chambers. - In certain embodiments of the invention, the
system 800 is configured to deposit the first or second p-i-n junction (e.g.,reference numeral 116, 136) of a multi-junction solar cell. In one embodiment, one of the process chambers 831-837 is configured to deposit the p-type layer(s) of the first and/or second p-i-n junction while the remaining process chambers 831-837 are each configured to deposit both the intrinsic type layer(s) and the n-type layer(s). The intrinsic type layer(s) and the n-type layer(s) of the p-i-n junctions may be deposited in the same chamber without any passivation process in between the deposition steps. Thus, in one configuration, a substrate enters the system through theload lock chamber 810, the substrate is then transferred by the vacuum robot into the dedicated process chamber configured to deposit the p-type layer(s). Next, after forming the p-type layer the substrate is transferred by the vacuum robot into one of the remaining process chamber configured to deposit both the intrinsic type layer(s) and the n-type layer(s). After forming the intrinsic type layer(s) and the n-type layer(s) the substrate is transferred by thevacuum robot 822 back to theload lock chamber 810. In certain embodiments, the time to process a substrate with the process chamber to form the p-type layer(s) is approximately 4 or more times faster, such as 6 or more times faster, than the time to form the intrinsic type layer(s) and the n-type layer(s) in a single chamber. Therefore, in certain embodiments of the system to deposit the first p-i-n junction, the ratio of p-chambers to i/n-chambers is 1:4 or more, such as 1:6 or more. The throughput of the system including the time to provide plasma cleaning of the process chambers may be about 10 substrates/hr or more, for example 20 substrates/hr or more. - In certain embodiments of the invention, a
system 800 is configured to deposit the p-i-n junction (e.g.,reference numerals 116, 136) solar cells. In one embodiment, one of the process chambers 831-837 is configured to deposit the p-type layer(s) while the remaining process chambers 831-837 are each configured to deposit both the intrinsic type layer(s) and the n-type layer(s) and the conductive index matching layer (e.g., reference numeral 118). The interface barrier layer (e.g., reference numeral 111) may be optionally formed with the p-type layer(s) or with the intrinsic type layer(s) and the n-type layer(s). Also, the heavily doped p-type layer (p++ layer, e.g., reference numeral 109) may be formed with the p-type layer(s) in a chamber. The intrinsic type layer(s) and the n-type layer(s) may be deposited in the same chamber. In certain embodiments, the time to process a substrate with the process chamber to form the p-type layer(s) is approximately 4 or more times faster than the time to form the intrinsic type layer(s) and the n-type layer(s) in a single chamber. Therefore, in certain embodiments of the system to deposit the p-i-n junction, the ratio of p-chambers to i/n-chambers is 1:4 or more, such as 1:6 or more. The throughput of the system including the time to provide plasma cleaning of the process chambers may be about 3 substrates/hr or more, such as 5 substrates/hr or more. - In certain embodiments, the throughput of a
system 800 that is configured for depositing the p-i-n junction comprising an intrinsic type amorphous silicon layer has a throughput that is two times larger than the throughput of asystem 800 that is used to deposit the second p-i-n junction comprising an intrinsic type microcrystalline silicon layer, due to the difference in thickness between the intrinsic type microcrystalline silicon layer(s) and the intrinsic type amorphous silicon layer(s). Therefore, asingle system 800 that is adapted to deposit the first p-i-n junction, which comprises an intrinsic type amorphous silicon layer, can be matched with two ormore systems 800 that are adapted to deposit a second p-i-n junction, which comprises an intrinsic type microcrystalline silicon layer. Once a first p-i-n junction has been formed in one system, the substrate may be exposed to the ambient environment (i.e., vacuum break) and transferred to the second system, where the second p-i-n junction is formed. A wet or dry cleaning of the substrate between the first system depositing the first p-i-n junction and the second p-i-n junction may be necessary. -
FIG. 9 illustrates one configuration of a portion of aproduction line 900 that has a plurality ofdeposition systems automation devices 902. In one configuration, as shown inFIG. 9 , theproduction line 900 comprises a plurality ofdeposition systems substrate 102. Thesystems system 800 depicted inFIG. 8 , but are generally configured to deposit different layer(s) or junction(s) on thesubstrate 102. In general, each of thedeposition systems load lock load lock 810, that are each in transferable communication with anautomation device 902. - During process sequencing, a substrate is generally transported from a
system automation device 902 to one of thesystems system 906 has a plurality ofchambers 906A-906H that are each configured to deposit or process one or more layers in the formation of a first p-i-n junction, thesystem 905 having a plurality ofchambers 905A-905H is configured to deposit the multiple layers formed in the first p-i-n junction and thesystem 904 having the plurality ofchambers 904A-904H is configure to deposit or process one or more layers in the formation of a second p-i-n junction. It is noted that the number of systems and the number of the chambers configured to deposit each layer in each of the systems may be varied to meet different process requirements and configurations. In one embodiment, it is desirable to separate or isolate the WSR layer deposition process chambers from the p-type, intrinsic or n-type layer deposition chambers to prevent the cross contamination of one or more of the layers in the formed solar cell device or subsequently formed solar cell devices. In configurations where the WSR layer comprises a carbon or an oxygen containing layer, it is generally important to prevent the cross contamination of the formed intrinsic layer(s) in the formed junctions, and/or prevent particle generation problems due to the stress in the oxygen or carbon containing deposited material layers formed on the shields or other chamber components in a processing chamber. - The
automation device 902 may generally comprise a robotic device or conveyor that is adapted to move and position a substrate. In one embodiment, a plurality ofautomation devices 902 and acontroller 748, which is connected to all of the processing chambers andautomation devices 902 in theproduction line 900, are used in combination to serially transfer a plurality of substrates so that the processing steps inprocessing sequence 600 can be performed on a plurality ofsubstrates 102. In one example, theautomation device 902 is a series of conventional substrate conveyors (e.g., roller type conveyor) and/or robotic devices (e.g., 6-axis robot, SCARA robot) that are configured to move and position the substrate within theproduction line 900 as desired. In one embodiment, one or more of theautomation devices 902 also contains one or more substrate lifting components, or drawbridge conveyors, that are used to allow substrates upstream of a desired system to be delivered past a substrate that would be blocking its movement to another desired position within theproduction line 900. In this way the movement of substrates to the various systems will not be impeded by other substrates waiting to be delivered to another system. - In one embodiment of the
production line 900, apatterning chamber 950 is in communication with one or more of theautomation devices 902, and is configured to perform a patterning process on one or more of the layers in the formed WSR layer, conductive index matching layer, barrier layer, or TCO layer. In one example, thepatterning chamber 950 is advantageously positioned to perform a patterning process on one or more of the layers by conventional means. It is also contemplated that the patterning process can also be used to etch one or more regions in one or more of the layers during the solar cell devices formation process. While the configurations of thepatterning chamber 950 generally discuss etching type patterning processes, this configuration need not be limiting as to the scope of the invention described herein. In one embodiment, thepatterning chamber 950 is used to remove one or more regions in one or more of the formed layers and/or deposit one or more material layers (e.g., dopant containing materials, metals pastes) on the one or more of the formed layers on the substrate surface. - While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. For example, the process chamber of
FIG. 7 has been shown in a horizontal position. It is understood that in other embodiments of the invention the process chamber may be in any non-horizontal position, such as vertical. Embodiments of the invention have been described in reference to the multi-process chamber cluster tool inFIGS. 8 and 9 , but in-line systems and hybrid in-line/cluster systems may also be used. Embodiments of the invention have been described in reference to a first system configured to form a first p-i-n junction and a second system configured to form a second p-i-n junction. Finally, the embodiments described herein are p-i-n configurations generally applicable to transparent substrates, such as glass, but other embodiments are contemplated in which n-i-p junctions, single or multiply stacked, are constructed on opaque substrates such as stainless steel or polymer in a reverse deposition sequence. - Embodiments of a
production line 900 that include all of the processing chambers used to perform the processing steps in theprocess sequence 600, and are interconnected by one or more substratetransferring automation devices 902, have a distinct advantages over other prior art processing configuration that require manual handling steps and/or manually performed processes, since the throughput of theproduction line 900 can be increased over these prior configurations, the chance of damaging the often fragile glass substrates during the transfer or performance of one or more of the processing steps is reduced, and the substrate-to-substrate process repeatability can be increased. Substrate handling related defects that are created during one or more of the steps in the solar cell formation process are greatly increased when one or more coatings are disposed on the two major surfaces of thesubstrate 102, such assurfaces - Thus, an apparatus and methods for forming high efficiency cell junctions in a solar cell device are provided. The method advantageously produces high conversion efficiency solar cell improved to at least about 10% even after the efficiency has degraded due to LID, for example, as compared to the about 7%-8% efficiency achieved by current conventional solar cell devices. In one embodiment, greater than 10% efficiency is achieved by selecting and forming a solar cell device that contains an ARC layer, a barrier layer, a conductive contact layer, a conductive index matching interface layer, a low bandgap intrinsic amorphous silicon layer, an n-type microcrystalline silicon carbide layer in a first p-i-n junction, an n-type amorphous silicon layer in a second p-i-n junction, a conductive index matching layer, and composite film stack in the back metal electrode. By utilizing the new film structure and new materials described herein, the conversion efficiency of the solar cell devices may be efficiently improved and increased as desired.
- While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (32)
1. A photovoltaic device, comprising:
a substrate having a first surface and a second surface;
a barrier layer disposed on the first surface of the substrate;
a first transparent conductive oxide layer disposed on the barrier layer;
a conductive contact layer disposed on the first transparent conductive oxide layer, wherein the conductive contact layer comprises a tin oxide layer, a titanium oxide layer, a tantalum layer, a tantalum oxide layer, a niobium doped tin oxide layer, or a niobium doped titanium oxide layer;
a first p-i-n junction formed on the conductive contact layer; and
a second transparent conductive oxide layer formed over the first p-i-n junction.
2. The photovoltaic device of claim 1 , further comprising:
an antireflection coating layer disposed on the second surface of the substrate, wherein the antireflection coating layer is fabricated from a silicon containing material having carbon dopants, fluorine dopants or combinations thereof formed in the silicon containing layer.
3. The photovoltaic device of claim 1 , further comprising an antireflection coating layer disposed on the second surface of the substrate, wherein the antireflection coating layer includes a film stack having a SiO2 layer and a TiO2 layer.
4. The photovoltaic device of claim 1 , wherein the first p-i-n junction further comprises:
a p-type amorphous silicon layer;
an intrinsic type amorphous silicon layer; and
a n-type microcrystalline silicon carbide layer.
5. The photovoltaic device of claim 4 , further comprising:
a heavily doped p-type amorphous silicon formed on the conductive contact layer prior to the formation of the p-type amorphous silicon layer.
6. The photovoltaic device of claim 4 , further comprising an interface barrier layer disposed between the p-type amorphous silicon layer and the intrinsic type amorphous silicon layer, wherein the interface barrier layer comprises silicon and carbon.
7. The photovoltaic device of claim 4 , wherein the index of refraction of the material in the conductive contact layer is between the index of refraction of the material in the first transparent conductive oxide layer and the index of refraction of the material in the p-type amorphous silicon layer.
8. The photovoltaic device of claim 1 , further comprising a second p-i-n junction formed between the first p-i-n junction and the second transparent conductive oxide layer, wherein the second p-i-n junction comprises:
a p-type microcrystalline silicon layer;
an intrinsic type microcrystalline silicon layer; and
an n-type amorphous silicon layer.
9. The photovoltaic device of claim 8 , further comprising a conductive index matching layer disposed between the second p-i-n junction and the second transparent conductive oxide layer, wherein the index of refraction of the material in the conductive index matching layer is less than the index of refraction of the material in the second transparent conductive oxide layer.
10. The photovoltaic device of claim 1 , further comprising:
a conductive index matching layer formed between the first p-i-n junction and the second transparent conductive oxide layer, and the conductive index matching layer comprises a material selected from a group consisting of silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), and indium tin oxide (ITO).
11. The photovoltaic device of claim 10 , wherein the conductive index matching layer having a refractive index between about 1.4 and about 1.8.
12. The photovoltaic device of claim 1 , further comprising:
a metal back electrode formed on the second transparent conductive oxide layer, wherein the metal back electrode is a composite film stack having a silicon or palladium doped silver layer disposed on the second transparent conductive oxide layer and a nickel (Ni) vanadium (V) alloy layer formed on the silicon doped silver layer.
13. The photovoltaic device of claim 1 , wherein the barrier layer is a tin oxide layer, an iron doped tin oxide layer, a titanium oxide layer, or an iron doped titanium oxide layer.
14. The photovoltaic device of claim 1 , wherein the substrate comprises a glass substrate having an iron element disposed therein that has a concentration less than about 0.03 percent by weight, and the electrical sheet resistance of the combination of the formed first transparent conductive oxide layer and the formed conductive contact layer is less than about 10 Ohms per square.
15. A photovoltaic device, comprising:
a substrate having a first surface and a second surface, wherein the substrate comprises a glass material having an iron concentration less than about 0.03% by weight;
a barrier layer disposed on the first surface of the substrate;
a first transparent conductive oxide layer disposed on the barrier layer;
a first p-i-n junction comprising:
a p-type amorphous silicon layer formed over the first transparent conductive oxide layer;
an intrinsic type amorphous silicon layer formed over the p-type amorphous silicon layer; and
an n-type microcrystalline silicon carbide layer formed over the intrinsic type amorphous silicon layer;
a conductive contact layer disposed between the first transparent conductive oxide layer and the p-type amorphous silicon layer, wherein the index of refraction of the material in the conductive contact layer is between the index of refraction of the material in the first transparent conductive oxide layer and the index of refraction of the material in the p-type amorphous silicon layer, and the electrical sheet resistance of the combination of the formed first transparent conductive oxide layer and the formed conductive contact layer is less than about 10 Ohms per square;
a second p-i-n junction comprising:
a p-type microcrystalline silicon layer disposed over the n-type microcrystalline silicon carbide layer;
an intrinsic type microcrystalline silicon layer formed over the p-type microcrystalline silicon layer; and
an n-type amorphous silicon layer formed over the intrinsic type microcrystalline silicon layer;
a conductive index matching layer disposed on the n-type amorphous silicon layer; and
a second transparent conductive oxide layer formed over the conductive index matching layer.
16. The photovoltaic device of claim 15 , wherein the p-type amorphous silicon layer further comprises:
a first p-type amorphous silicon layer formed on the conductive contact layer; and
a second p-type amorphous silicon layer, wherein the first p-type amorphous silicon layer is more heavily doped with a p-type dopant than the second p-type amorphous silicon layer.
17. The photovoltaic device of claim 16 , further comprising an interface barrier layer disposed between the p-type amorphous silicon layer and the intrinsic type amorphous silicon layer, wherein the interface barrier layer comprises silicon and carbon.
18. The photovoltaic device of claim 15 , further comprising an antireflection coating layer disposed on the second surface of the substrate, wherein the antireflection coating layer is fabricated from a material comprising silicon and carbon or fluorine.
19. The photovoltaic device of claim 15 , further comprising an antireflection coating layer disposed on the second surface of the substrate, wherein the antireflection coating layer includes a film stack having a SiO2 layer and a TiO2 layer.
20. The photovoltaic device of claim 15 , wherein the first transparent conductive oxide layer comprises a doped tin oxide, wherein the doped tin oxide comprises less than about 10% by weight of indium or iron.
21. The photovoltaic device of claim 15 , wherein the first conductive index matching layer comprises a material selected from a group consisting of silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), and indium tin oxide (ITO), and the first conductive index matching layer has a refractive index between about 1.4 and about 1.8.
22. The photovoltaic device of claim 15 , further comprising a metal back electrode formed on the second transparent conductive oxide layer, wherein the metal back electrode comprises silver and between about 0.25 and about 7 weight % of palladium.
23. The photovoltaic device of claim 15 , wherein the barrier layer is a tin oxide layer, an iron doped tin oxide layer, a titanium oxide layer, or an iron doped titanium oxide layer.
24. The photovoltaic device of claim 15 , wherein the conductive contact layer is a tin oxide layer, a titanium oxide layer, a tantalum layer, a tantalum oxide layer, a niobium doped tin oxide layer, or a niobium doped titanium oxide layer.
25. A photovoltaic device, comprising:
a substrate having a first surface and a second surface;
a barrier layer disposed on the second surface of the substrate;
a first transparent conductive oxide layer disposed on the barrier layer;
a conductive contact layer disposed on the first transparent conductive oxide layer;
a first p-i-n junction formed on the conductive contact layer, wherein the first p-i-n junction further comprises:
a p-type amorphous silicon layer;
an intrinsic type amorphous silicon layer; and
a n-type microcrystalline silicon carbide layer;
a second transparent conductive oxide layer formed over the first p-i-n junction; and
a metal back electrode formed on the second transparent conductive oxide layer, wherein the metal back electrode comprises silver and palladium.
26. The photovoltaic device of claim 25 , wherein the metal back electrode comprises between about 0.25 weight % and 7 weight % of palladium.
27. The photovoltaic device of claim 25 , further comprising:
an antireflection coating layer disposed on the first surface of the substrate, wherein the antireflection coating layer is fabricated from a silicon containing material having carbon dopants, fluorine dopants or combinations thereof formed in the silicon containing layer.
28. The photovoltaic device of claim 25 , further comprising an antireflection coating layer disposed on the first surface of the substrate, wherein the antireflection coating layer includes a film stack having a SiO2 layer and a TiO2 layer.
29. The photovoltaic device of claim 25 , wherein the substrate is a glass substrate having iron element doped therein with a concentration between about 0.01 percent by weight and about 0.03 percent by weight.
30. The photovoltaic device of claim 25 , further comprising a second p-i-n junction formed between the first p-i-n junction and the second transparent conductive oxide layer, wherein the second p-i-n junction comprises:
a p-type microcrystalline silicon layer;
an intrinsic type microcrystalline silicon layer; and
an n-type amorphous silicon layer.
31. The photovoltaic device of claim 30 , further comprising a conductive index matching layer disposed between the second p-i-n junction and the second transparent conductive oxide layer, wherein the index of refraction of the material in the conductive index matching layer is less than the index of refraction of the material in the second transparent conductive oxide layer.
32. The photovoltaic device of claim 25 , further comprising a nickel (Ni) vanadium (V) alloy layer formed on the metal back electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/980,135 US20110174362A1 (en) | 2010-01-18 | 2010-12-28 | Manufacture of thin film solar cells with high conversion efficiency |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US29599110P | 2010-01-18 | 2010-01-18 | |
US12/980,135 US20110174362A1 (en) | 2010-01-18 | 2010-12-28 | Manufacture of thin film solar cells with high conversion efficiency |
Publications (1)
Publication Number | Publication Date |
---|---|
US20110174362A1 true US20110174362A1 (en) | 2011-07-21 |
Family
ID=44276649
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/980,132 Expired - Fee Related US8252624B2 (en) | 2010-01-18 | 2010-12-28 | Method of manufacturing thin film solar cells having a high conversion efficiency |
US12/980,135 Abandoned US20110174362A1 (en) | 2010-01-18 | 2010-12-28 | Manufacture of thin film solar cells with high conversion efficiency |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/980,132 Expired - Fee Related US8252624B2 (en) | 2010-01-18 | 2010-12-28 | Method of manufacturing thin film solar cells having a high conversion efficiency |
Country Status (4)
Country | Link |
---|---|
US (2) | US8252624B2 (en) |
CN (1) | CN102714228A (en) |
TW (1) | TW201208101A (en) |
WO (1) | WO2011087878A2 (en) |
Cited By (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102655178A (en) * | 2012-04-28 | 2012-09-05 | 法国圣戈班玻璃公司 | Cover plate, manufacturing method of cover plate, solar glass and photovoltaic device |
US20120256181A1 (en) * | 2011-04-11 | 2012-10-11 | Jia-Min Shieh | Power-generating module with solar cell and method for fabricating the same |
CN103137769A (en) * | 2011-12-02 | 2013-06-05 | 杜邦太阳能有限公司 | Cascade type solar battery and manufacturing method thereof |
WO2013102576A1 (en) * | 2012-01-04 | 2013-07-11 | Tel Solar Ag | Intermediate reflection structure in thin film solar cells |
WO2013130746A1 (en) * | 2012-02-28 | 2013-09-06 | International Business Machines Corporation | Solar cell made using barrier layer between p-type and intrinsic layers |
CN103579426A (en) * | 2012-07-19 | 2014-02-12 | 华夏光股份有限公司 | Semiconductor device |
CN103594572A (en) * | 2012-08-15 | 2014-02-19 | 华夏光股份有限公司 | Alternating-current light-emitting device |
US20140174517A1 (en) * | 2012-12-21 | 2014-06-26 | Lg Electronics Inc. | Solar cell and method of manufacturing the same |
US20140273331A1 (en) * | 2013-03-13 | 2014-09-18 | Genevieve A. Solomon | Methods for wet chemistry polishing for improved low viscosity printing in solar cell fabrication |
TWI475704B (en) * | 2012-06-14 | 2015-03-01 | Nexpower Technology Corp | Thin film solar cell and manufacturing method thereof |
US20150129037A1 (en) * | 2013-11-08 | 2015-05-14 | Lg Electronics Inc. | Solar cell |
US20150295099A1 (en) * | 2012-01-13 | 2015-10-15 | Kurtis LESCHKIES | High work-function buffer layers for silicon-based photovoltaic devices |
KR101766339B1 (en) | 2012-01-11 | 2017-08-08 | 엘지전자 주식회사 | Solar cell and method for manufacturing the same |
US9831115B2 (en) | 2016-02-19 | 2017-11-28 | Sunedison Semiconductor Limited (Uen201334164H) | Process flow for manufacturing semiconductor on insulator structures in parallel |
US9853133B2 (en) * | 2014-09-04 | 2017-12-26 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity silicon-on-insulator substrate |
US9881832B2 (en) | 2015-03-17 | 2018-01-30 | Sunedison Semiconductor Limited (Uen201334164H) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof |
US9985146B2 (en) | 2014-09-19 | 2018-05-29 | Kabushiki Kaisha Toshiba | Photoelectric conversion device, and solar cell |
US10079170B2 (en) | 2014-01-23 | 2018-09-18 | Globalwafers Co., Ltd. | High resistivity SOI wafers and a method of manufacturing thereof |
US10128396B2 (en) | 2012-10-26 | 2018-11-13 | Stmicroelectronics S.R.L. | Photovoltaic cell |
US10224233B2 (en) | 2014-11-18 | 2019-03-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation |
US10269617B2 (en) | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
US10283402B2 (en) | 2015-03-03 | 2019-05-07 | Globalwafers Co., Ltd. | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
US10290533B2 (en) | 2015-03-17 | 2019-05-14 | Globalwafers Co., Ltd. | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures |
US10304722B2 (en) | 2015-06-01 | 2019-05-28 | Globalwafers Co., Ltd. | Method of manufacturing semiconductor-on-insulator |
US10319872B2 (en) | 2012-05-10 | 2019-06-11 | International Business Machines Corporation | Cost-efficient high power PECVD deposition for solar cells |
US10332782B2 (en) | 2015-06-01 | 2019-06-25 | Globalwafers Co., Ltd. | Method of manufacturing silicon germanium-on-insulator |
US10381260B2 (en) | 2014-11-18 | 2019-08-13 | GlobalWafers Co., Inc. | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers |
US10453703B2 (en) | 2016-12-28 | 2019-10-22 | Sunedison Semiconductor Limited (Uen201334164H) | Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield |
US10468295B2 (en) | 2016-12-05 | 2019-11-05 | GlobalWafers Co. Ltd. | High resistivity silicon-on-insulator structure and method of manufacture thereof |
US10468294B2 (en) | 2016-02-19 | 2019-11-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface |
US10475696B2 (en) | 2017-07-14 | 2019-11-12 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacture of a semiconductor on insulator structure |
US10483379B2 (en) | 2014-09-04 | 2019-11-19 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss |
US10483152B2 (en) | 2014-11-18 | 2019-11-19 | Globalwafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
US10529616B2 (en) | 2015-11-20 | 2020-01-07 | Globalwafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
US10546771B2 (en) | 2016-10-26 | 2020-01-28 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
US10573550B2 (en) | 2016-03-07 | 2020-02-25 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof |
US10593748B2 (en) | 2016-03-07 | 2020-03-17 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof |
US10622247B2 (en) | 2016-02-19 | 2020-04-14 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a buried high resistivity layer |
US10818540B2 (en) | 2018-06-08 | 2020-10-27 | Globalwafers Co., Ltd. | Method for transfer of a thin layer of silicon |
US11114332B2 (en) | 2016-03-07 | 2021-09-07 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof |
US11142844B2 (en) | 2016-06-08 | 2021-10-12 | Globalwafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
US11173697B2 (en) | 2018-04-27 | 2021-11-16 | Globalwafers Co., Ltd. | Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate |
EP3913681A3 (en) * | 2020-05-18 | 2022-03-16 | STMicroelectronics S.r.l. | Method of fabrication of an integrated thermoelectric converter, and integrated thermoelectric converter thus obtained |
US11696504B2 (en) | 2020-05-18 | 2023-07-04 | Stmicroelectronics S.R.L. | Method of fabrication of an integrated thermoelectric converter, and integrated thermoelectric converter thus obtained |
US11848227B2 (en) | 2016-03-07 | 2023-12-19 | Globalwafers Co., Ltd. | Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment |
Families Citing this family (248)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8251576B1 (en) * | 2009-05-30 | 2012-08-28 | Mia Sole | Cold lift-off test for strength of film stack subjected to thermal loading |
US20120012167A1 (en) * | 2010-07-13 | 2012-01-19 | International Business Machines Corporation | Solar cell employing an enhanced free hole density p-doped material and methods for forming the same |
US20120202315A1 (en) * | 2011-02-03 | 2012-08-09 | Applied Materials, Inc. | In-situ hydrogen plasma treatment of amorphous silicon intrinsic layers |
US20130019929A1 (en) * | 2011-07-19 | 2013-01-24 | International Business Machines | Reduction of light induced degradation by minimizing band offset |
US20130023129A1 (en) | 2011-07-20 | 2013-01-24 | Asm America, Inc. | Pressure transmitter for a semiconductor processing environment |
US20130019934A1 (en) * | 2011-07-22 | 2013-01-24 | Primestar Solar, Inc. | Oxygen getter layer for photovoltaic devices and methods of their manufacture |
CN103022241A (en) * | 2011-09-28 | 2013-04-03 | 吉富新能源科技(上海)有限公司 | High-performance transparent conductive glass module processing technology |
CN103022240A (en) * | 2011-09-28 | 2013-04-03 | 吉富新能源科技(上海)有限公司 | Technology for simply manufacturing antireflection layer |
US20130164882A1 (en) * | 2011-12-23 | 2013-06-27 | International Business Machines Corporation | Transparent conducting layer for solar cell applications |
US8980728B2 (en) * | 2012-01-06 | 2015-03-17 | Phostek, Inc. | Method of manufacturing a semiconductor apparatus |
US20150136210A1 (en) | 2012-05-10 | 2015-05-21 | Tel Solar Ag | Silicon-based solar cells with improved resistance to light-induced degradation |
US10714315B2 (en) | 2012-10-12 | 2020-07-14 | Asm Ip Holdings B.V. | Semiconductor reaction chamber showerhead |
JP6055270B2 (en) * | 2012-10-26 | 2016-12-27 | キヤノン株式会社 | Solid-state imaging device, manufacturing method thereof, and camera |
US9379259B2 (en) * | 2012-11-05 | 2016-06-28 | International Business Machines Corporation | Double layered transparent conductive oxide for reduced schottky barrier in photovoltaic devices |
CN103066153A (en) * | 2012-12-28 | 2013-04-24 | 福建铂阳精工设备有限公司 | Silicon-based thin-film lamination solar cell and manufacturing method thereof |
WO2014110520A1 (en) | 2013-01-11 | 2014-07-17 | Silevo, Inc. | Module fabrication of solar cells with low resistivity electrodes |
US20160376700A1 (en) | 2013-02-01 | 2016-12-29 | Asm Ip Holding B.V. | System for treatment of deposition reactor |
KR20140102782A (en) * | 2013-02-14 | 2014-08-25 | 삼성전자주식회사 | Blade for transferring wafer and wafer transferring apparatus having the same |
KR20150019132A (en) * | 2013-08-12 | 2015-02-25 | 삼성전자주식회사 | Light transmission type two sided solar cell |
DE102014111781B4 (en) * | 2013-08-19 | 2022-08-11 | Korea Atomic Energy Research Institute | Process for the electrochemical production of a silicon layer |
CN103618010A (en) * | 2013-10-21 | 2014-03-05 | 福建铂阳精工设备有限公司 | Silicon-based thin-film solar cell back electrode and manufacturing method thereof, and silicon-based thin-film solar cell |
US20160276514A1 (en) * | 2013-11-12 | 2016-09-22 | Nitto Denko Corporation | Solar energy collection systems utilizing holographic optical elements useful for building integrated photovoltaics |
CN103646978B (en) * | 2013-12-09 | 2016-04-13 | 韩帅 | Solar module |
JPWO2015115492A1 (en) * | 2014-01-30 | 2017-03-23 | 旭硝子株式会社 | Glass plate with anti-glare function for solar cells |
US11015245B2 (en) | 2014-03-19 | 2021-05-25 | Asm Ip Holding B.V. | Gas-phase reactor and system having exhaust plenum and components thereof |
TWI575765B (en) * | 2014-05-19 | 2017-03-21 | The anti - reflection spectrum of the multi - faceted solar cell increases the structure | |
US10309012B2 (en) | 2014-07-03 | 2019-06-04 | Tesla, Inc. | Wafer carrier for reducing contamination from carbon particles and outgassing |
US9690016B2 (en) * | 2014-07-11 | 2017-06-27 | Applied Materials, Inc. | Extreme ultraviolet reflective element with amorphous layers and method of manufacturing thereof |
US10941490B2 (en) | 2014-10-07 | 2021-03-09 | Asm Ip Holding B.V. | Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same |
US10276355B2 (en) | 2015-03-12 | 2019-04-30 | Asm Ip Holding B.V. | Multi-zone reactor, system including the reactor, and method of using the same |
KR20180008454A (en) * | 2015-05-14 | 2018-01-24 | 가부시키가이샤 쇼와 | A dye-sensitized solar cell having a collector electrode on a counter electrode |
US10458018B2 (en) | 2015-06-26 | 2019-10-29 | Asm Ip Holding B.V. | Structures including metal carbide material, devices including the structures, and methods of forming same |
JP6584880B2 (en) * | 2015-09-11 | 2019-10-02 | 株式会社東芝 | Semiconductor device |
US20170098722A1 (en) * | 2015-10-01 | 2017-04-06 | Lg Electronics Inc. | Solar cell |
TWI596785B (en) * | 2015-10-07 | 2017-08-21 | 財團法人工業技術研究院 | Solar cell structure and method for manufacturing the same |
CN105304740A (en) * | 2015-10-12 | 2016-02-03 | 友达光电股份有限公司 | Photovoltaic conversion module |
US10211308B2 (en) | 2015-10-21 | 2019-02-19 | Asm Ip Holding B.V. | NbMC layers |
US9761744B2 (en) | 2015-10-22 | 2017-09-12 | Tesla, Inc. | System and method for manufacturing photovoltaic structures with a metal seed layer |
US11139308B2 (en) | 2015-12-29 | 2021-10-05 | Asm Ip Holding B.V. | Atomic layer deposition of III-V compounds to form V-NAND devices |
US10529554B2 (en) | 2016-02-19 | 2020-01-07 | Asm Ip Holding B.V. | Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches |
US10367080B2 (en) | 2016-05-02 | 2019-07-30 | Asm Ip Holding B.V. | Method of forming a germanium oxynitride film |
US11453943B2 (en) | 2016-05-25 | 2022-09-27 | Asm Ip Holding B.V. | Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor |
US9859151B1 (en) | 2016-07-08 | 2018-01-02 | Asm Ip Holding B.V. | Selective film deposition method to form air gaps |
US10612137B2 (en) | 2016-07-08 | 2020-04-07 | Asm Ip Holdings B.V. | Organic reactants for atomic layer deposition |
US9812320B1 (en) | 2016-07-28 | 2017-11-07 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US9887082B1 (en) | 2016-07-28 | 2018-02-06 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
KR102532607B1 (en) | 2016-07-28 | 2023-05-15 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and method of operating the same |
CN106298988A (en) * | 2016-10-10 | 2017-01-04 | 江苏神科新能源有限公司 | A kind of heterojunction solar battery and preparation method thereof |
US11532757B2 (en) | 2016-10-27 | 2022-12-20 | Asm Ip Holding B.V. | Deposition of charge trapping layers |
US10714350B2 (en) | 2016-11-01 | 2020-07-14 | ASM IP Holdings, B.V. | Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
KR102546317B1 (en) | 2016-11-15 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Gas supply unit and substrate processing apparatus including the same |
KR20180068582A (en) | 2016-12-14 | 2018-06-22 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11447861B2 (en) | 2016-12-15 | 2022-09-20 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus and a method of forming a patterned structure |
US11581186B2 (en) | 2016-12-15 | 2023-02-14 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus |
KR20180070971A (en) | 2016-12-19 | 2018-06-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US10269558B2 (en) | 2016-12-22 | 2019-04-23 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US11390950B2 (en) | 2017-01-10 | 2022-07-19 | Asm Ip Holding B.V. | Reactor system and method to reduce residue buildup during a film deposition process |
PL233211B1 (en) * | 2017-01-25 | 2019-09-30 | Saule Spolka Z Ograniczona Odpowiedzialnoscia | Optoelectronic film and method for producing optoelectronic film |
US10468261B2 (en) | 2017-02-15 | 2019-11-05 | Asm Ip Holding B.V. | Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures |
US10529563B2 (en) | 2017-03-29 | 2020-01-07 | Asm Ip Holdings B.V. | Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures |
WO2018189752A1 (en) * | 2017-04-15 | 2018-10-18 | Indian Institute Of Science | Solar cell |
US10770286B2 (en) | 2017-05-08 | 2020-09-08 | Asm Ip Holdings B.V. | Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures |
US11306395B2 (en) | 2017-06-28 | 2022-04-19 | Asm Ip Holding B.V. | Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus |
KR20190009245A (en) | 2017-07-18 | 2019-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods for forming a semiconductor device structure and related semiconductor device structures |
US11374112B2 (en) | 2017-07-19 | 2022-06-28 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US10541333B2 (en) | 2017-07-19 | 2020-01-21 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US11018002B2 (en) | 2017-07-19 | 2021-05-25 | Asm Ip Holding B.V. | Method for selectively depositing a Group IV semiconductor and related semiconductor device structures |
US10590535B2 (en) | 2017-07-26 | 2020-03-17 | Asm Ip Holdings B.V. | Chemical treatment, deposition and/or infiltration apparatus and method for using the same |
US10692741B2 (en) | 2017-08-08 | 2020-06-23 | Asm Ip Holdings B.V. | Radiation shield |
US10770336B2 (en) | 2017-08-08 | 2020-09-08 | Asm Ip Holding B.V. | Substrate lift mechanism and reactor including same |
US11769682B2 (en) | 2017-08-09 | 2023-09-26 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US11139191B2 (en) | 2017-08-09 | 2021-10-05 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US11830730B2 (en) | 2017-08-29 | 2023-11-28 | Asm Ip Holding B.V. | Layer forming method and apparatus |
US11295980B2 (en) | 2017-08-30 | 2022-04-05 | Asm Ip Holding B.V. | Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures |
US11056344B2 (en) | 2017-08-30 | 2021-07-06 | Asm Ip Holding B.V. | Layer forming method |
KR102491945B1 (en) | 2017-08-30 | 2023-01-26 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US10672919B2 (en) * | 2017-09-19 | 2020-06-02 | Tesla, Inc. | Moisture-resistant solar cells for solar roof tiles |
US10658205B2 (en) | 2017-09-28 | 2020-05-19 | Asm Ip Holdings B.V. | Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber |
US10403504B2 (en) | 2017-10-05 | 2019-09-03 | Asm Ip Holding B.V. | Method for selectively depositing a metallic film on a substrate |
US11022879B2 (en) | 2017-11-24 | 2021-06-01 | Asm Ip Holding B.V. | Method of forming an enhanced unexposed photoresist layer |
JP7214724B2 (en) | 2017-11-27 | 2023-01-30 | エーエスエム アイピー ホールディング ビー.ブイ. | Storage device for storing wafer cassettes used in batch furnaces |
TWI791689B (en) | 2017-11-27 | 2023-02-11 | 荷蘭商Asm智慧財產控股私人有限公司 | Apparatus including a clean mini environment |
US10872771B2 (en) | 2018-01-16 | 2020-12-22 | Asm Ip Holding B. V. | Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures |
TW202325889A (en) | 2018-01-19 | 2023-07-01 | 荷蘭商Asm 智慧財產控股公司 | Deposition method |
CN111630203A (en) | 2018-01-19 | 2020-09-04 | Asm Ip私人控股有限公司 | Method for depositing gap filling layer by plasma auxiliary deposition |
US11081345B2 (en) | 2018-02-06 | 2021-08-03 | Asm Ip Holding B.V. | Method of post-deposition treatment for silicon oxide film |
JP7124098B2 (en) | 2018-02-14 | 2022-08-23 | エーエスエム・アイピー・ホールディング・ベー・フェー | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
US10896820B2 (en) | 2018-02-14 | 2021-01-19 | Asm Ip Holding B.V. | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
KR102636427B1 (en) | 2018-02-20 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing method and apparatus |
US10975470B2 (en) | 2018-02-23 | 2021-04-13 | Asm Ip Holding B.V. | Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment |
US11190128B2 (en) | 2018-02-27 | 2021-11-30 | Tesla, Inc. | Parallel-connected solar roof tile modules |
US11473195B2 (en) | 2018-03-01 | 2022-10-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus and a method for processing a substrate |
US11629406B2 (en) | 2018-03-09 | 2023-04-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate |
US11114283B2 (en) | 2018-03-16 | 2021-09-07 | Asm Ip Holding B.V. | Reactor, system including the reactor, and methods of manufacturing and using same |
KR102646467B1 (en) | 2018-03-27 | 2024-03-11 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electrode on a substrate and a semiconductor device structure including an electrode |
US11230766B2 (en) | 2018-03-29 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
WO2019188716A1 (en) * | 2018-03-29 | 2019-10-03 | 株式会社カネカ | Solar cell and manufacturing method therefor |
US11088002B2 (en) | 2018-03-29 | 2021-08-10 | Asm Ip Holding B.V. | Substrate rack and a substrate processing system and method |
KR20190128558A (en) | 2018-05-08 | 2019-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures |
KR102596988B1 (en) | 2018-05-28 | 2023-10-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of processing a substrate and a device manufactured by the same |
US11718913B2 (en) | 2018-06-04 | 2023-08-08 | Asm Ip Holding B.V. | Gas distribution system and reactor system including same |
US11270899B2 (en) | 2018-06-04 | 2022-03-08 | Asm Ip Holding B.V. | Wafer handling chamber with moisture reduction |
US11286562B2 (en) | 2018-06-08 | 2022-03-29 | Asm Ip Holding B.V. | Gas-phase chemical reactor and method of using same |
US10797133B2 (en) | 2018-06-21 | 2020-10-06 | Asm Ip Holding B.V. | Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures |
KR102568797B1 (en) | 2018-06-21 | 2023-08-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing system |
WO2020003000A1 (en) | 2018-06-27 | 2020-01-02 | Asm Ip Holding B.V. | Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material |
CN112292478A (en) | 2018-06-27 | 2021-01-29 | Asm Ip私人控股有限公司 | Cyclic deposition methods for forming metal-containing materials and films and structures containing metal-containing materials |
US10612136B2 (en) | 2018-06-29 | 2020-04-07 | ASM IP Holding, B.V. | Temperature-controlled flange and reactor system including same |
US10388513B1 (en) | 2018-07-03 | 2019-08-20 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10755922B2 (en) | 2018-07-03 | 2020-08-25 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US11053591B2 (en) | 2018-08-06 | 2021-07-06 | Asm Ip Holding B.V. | Multi-port gas injection system and reactor system including same |
US11430674B2 (en) | 2018-08-22 | 2022-08-30 | Asm Ip Holding B.V. | Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
KR20200030162A (en) | 2018-09-11 | 2020-03-20 | 에이에스엠 아이피 홀딩 비.브이. | Method for deposition of a thin film |
US11024523B2 (en) | 2018-09-11 | 2021-06-01 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
US11049751B2 (en) | 2018-09-14 | 2021-06-29 | Asm Ip Holding B.V. | Cassette supply system to store and handle cassettes and processing apparatus equipped therewith |
CN110970344A (en) | 2018-10-01 | 2020-04-07 | Asm Ip控股有限公司 | Substrate holding apparatus, system including the same, and method of using the same |
US11232963B2 (en) | 2018-10-03 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR102592699B1 (en) | 2018-10-08 | 2023-10-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same |
KR102546322B1 (en) | 2018-10-19 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
KR102605121B1 (en) | 2018-10-19 | 2023-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
USD948463S1 (en) | 2018-10-24 | 2022-04-12 | Asm Ip Holding B.V. | Susceptor for semiconductor substrate supporting apparatus |
US11087997B2 (en) | 2018-10-31 | 2021-08-10 | Asm Ip Holding B.V. | Substrate processing apparatus for processing substrates |
KR20200051105A (en) | 2018-11-02 | 2020-05-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and substrate processing apparatus including the same |
US11572620B2 (en) | 2018-11-06 | 2023-02-07 | Asm Ip Holding B.V. | Methods for selectively depositing an amorphous silicon film on a substrate |
US11031242B2 (en) | 2018-11-07 | 2021-06-08 | Asm Ip Holding B.V. | Methods for depositing a boron doped silicon germanium film |
US10847366B2 (en) | 2018-11-16 | 2020-11-24 | Asm Ip Holding B.V. | Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process |
US10818758B2 (en) | 2018-11-16 | 2020-10-27 | Asm Ip Holding B.V. | Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures |
US11217444B2 (en) | 2018-11-30 | 2022-01-04 | Asm Ip Holding B.V. | Method for forming an ultraviolet radiation responsive metal oxide-containing film |
KR102636428B1 (en) | 2018-12-04 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | A method for cleaning a substrate processing apparatus |
US20200181770A1 (en) * | 2018-12-05 | 2020-06-11 | Asm Ip Holding B.V. | Method of forming a structure including silicon nitride on titanium nitride and structure formed using the method |
US11158513B2 (en) | 2018-12-13 | 2021-10-26 | Asm Ip Holding B.V. | Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures |
JP2020096183A (en) | 2018-12-14 | 2020-06-18 | エーエスエム・アイピー・ホールディング・ベー・フェー | Method of forming device structure using selective deposition of gallium nitride, and system for the same |
TWI819180B (en) | 2019-01-17 | 2023-10-21 | 荷蘭商Asm 智慧財產控股公司 | Methods of forming a transition metal containing film on a substrate by a cyclical deposition process |
KR20200091543A (en) | 2019-01-22 | 2020-07-31 | 에이에스엠 아이피 홀딩 비.브이. | Semiconductor processing device |
CN111524788B (en) | 2019-02-01 | 2023-11-24 | Asm Ip私人控股有限公司 | Method for topologically selective film formation of silicon oxide |
TW202104632A (en) | 2019-02-20 | 2021-02-01 | 荷蘭商Asm Ip私人控股有限公司 | Cyclical deposition method and apparatus for filling a recess formed within a substrate surface |
KR102626263B1 (en) | 2019-02-20 | 2024-01-16 | 에이에스엠 아이피 홀딩 비.브이. | Cyclical deposition method including treatment step and apparatus for same |
KR20200102357A (en) | 2019-02-20 | 2020-08-31 | 에이에스엠 아이피 홀딩 비.브이. | Apparatus and methods for plug fill deposition in 3-d nand applications |
TW202044325A (en) | 2019-02-20 | 2020-12-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of filling a recess formed within a surface of a substrate, semiconductor structure formed according to the method, and semiconductor processing apparatus |
TW202100794A (en) | 2019-02-22 | 2021-01-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing apparatus and method for processing substrate |
US11742198B2 (en) | 2019-03-08 | 2023-08-29 | Asm Ip Holding B.V. | Structure including SiOCN layer and method of forming same |
KR20200108242A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer |
KR20200108243A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Structure Including SiOC Layer and Method of Forming Same |
KR20200116033A (en) | 2019-03-28 | 2020-10-08 | 에이에스엠 아이피 홀딩 비.브이. | Door opener and substrate processing apparatus provided therewith |
KR20200116855A (en) | 2019-04-01 | 2020-10-13 | 에이에스엠 아이피 홀딩 비.브이. | Method of manufacturing semiconductor device |
KR20200123380A (en) | 2019-04-19 | 2020-10-29 | 에이에스엠 아이피 홀딩 비.브이. | Layer forming method and apparatus |
KR20200125453A (en) | 2019-04-24 | 2020-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Gas-phase reactor system and method of using same |
KR20200130121A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Chemical source vessel with dip tube |
KR20200130118A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Method for Reforming Amorphous Carbon Polymer Film |
KR20200130652A (en) | 2019-05-10 | 2020-11-19 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing material onto a surface and structure formed according to the method |
JP2020188255A (en) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | Wafer boat handling device, vertical batch furnace, and method |
USD947913S1 (en) | 2019-05-17 | 2022-04-05 | Asm Ip Holding B.V. | Susceptor shaft |
USD975665S1 (en) | 2019-05-17 | 2023-01-17 | Asm Ip Holding B.V. | Susceptor shaft |
USD935572S1 (en) | 2019-05-24 | 2021-11-09 | Asm Ip Holding B.V. | Gas channel plate |
USD922229S1 (en) | 2019-06-05 | 2021-06-15 | Asm Ip Holding B.V. | Device for controlling a temperature of a gas supply unit |
KR20200141003A (en) | 2019-06-06 | 2020-12-17 | 에이에스엠 아이피 홀딩 비.브이. | Gas-phase reactor system including a gas detector |
US10858282B1 (en) * | 2019-06-07 | 2020-12-08 | Qualcomm Incorporated | Doped, low-temperature co-fired glass-ceramic (LTCC) insulating substrates, and related wiring boards and methods of manufacture |
KR20200143254A (en) | 2019-06-11 | 2020-12-23 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method |
USD944946S1 (en) | 2019-06-14 | 2022-03-01 | Asm Ip Holding B.V. | Shower plate |
USD931978S1 (en) | 2019-06-27 | 2021-09-28 | Asm Ip Holding B.V. | Showerhead vacuum transport |
KR20210005515A (en) | 2019-07-03 | 2021-01-14 | 에이에스엠 아이피 홀딩 비.브이. | Temperature control assembly for substrate processing apparatus and method of using same |
JP2021015791A (en) | 2019-07-09 | 2021-02-12 | エーエスエム アイピー ホールディング ビー.ブイ. | Plasma device and substrate processing method using coaxial waveguide |
CN112216646A (en) | 2019-07-10 | 2021-01-12 | Asm Ip私人控股有限公司 | Substrate supporting assembly and substrate processing device comprising same |
KR20210010307A (en) | 2019-07-16 | 2021-01-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210010816A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Radical assist ignition plasma system and method |
KR20210010820A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods of forming silicon germanium structures |
US11643724B2 (en) | 2019-07-18 | 2023-05-09 | Asm Ip Holding B.V. | Method of forming structures using a neutral beam |
CN112242296A (en) | 2019-07-19 | 2021-01-19 | Asm Ip私人控股有限公司 | Method of forming topologically controlled amorphous carbon polymer films |
TW202113936A (en) | 2019-07-29 | 2021-04-01 | 荷蘭商Asm Ip私人控股有限公司 | Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation |
CN112309900A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112309899A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
US11587815B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11227782B2 (en) | 2019-07-31 | 2022-01-18 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11587814B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
CN112323048B (en) | 2019-08-05 | 2024-02-09 | Asm Ip私人控股有限公司 | Liquid level sensor for chemical source container |
WO2021030236A2 (en) | 2019-08-09 | 2021-02-18 | Leading Edge Equipment Technologies, Inc. | Producing a ribbon or wafer with regions of low oxygen concentration |
USD965044S1 (en) | 2019-08-19 | 2022-09-27 | Asm Ip Holding B.V. | Susceptor shaft |
USD965524S1 (en) | 2019-08-19 | 2022-10-04 | Asm Ip Holding B.V. | Susceptor support |
JP2021031769A (en) | 2019-08-21 | 2021-03-01 | エーエスエム アイピー ホールディング ビー.ブイ. | Production apparatus of mixed gas of film deposition raw material and film deposition apparatus |
USD949319S1 (en) | 2019-08-22 | 2022-04-19 | Asm Ip Holding B.V. | Exhaust duct |
USD940837S1 (en) | 2019-08-22 | 2022-01-11 | Asm Ip Holding B.V. | Electrode |
USD979506S1 (en) | 2019-08-22 | 2023-02-28 | Asm Ip Holding B.V. | Insulator |
KR20210024423A (en) | 2019-08-22 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for forming a structure with a hole |
USD930782S1 (en) | 2019-08-22 | 2021-09-14 | Asm Ip Holding B.V. | Gas distributor |
US11286558B2 (en) | 2019-08-23 | 2022-03-29 | Asm Ip Holding B.V. | Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film |
KR20210024420A (en) | 2019-08-23 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane |
KR20210029090A (en) | 2019-09-04 | 2021-03-15 | 에이에스엠 아이피 홀딩 비.브이. | Methods for selective deposition using a sacrificial capping layer |
KR20210029663A (en) | 2019-09-05 | 2021-03-16 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11562901B2 (en) | 2019-09-25 | 2023-01-24 | Asm Ip Holding B.V. | Substrate processing method |
CN112593212B (en) | 2019-10-02 | 2023-12-22 | Asm Ip私人控股有限公司 | Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process |
TW202129060A (en) | 2019-10-08 | 2021-08-01 | 荷蘭商Asm Ip控股公司 | Substrate processing device, and substrate processing method |
KR20210043460A (en) | 2019-10-10 | 2021-04-21 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming a photoresist underlayer and structure including same |
KR20210045930A (en) | 2019-10-16 | 2021-04-27 | 에이에스엠 아이피 홀딩 비.브이. | Method of Topology-Selective Film Formation of Silicon Oxide |
US11637014B2 (en) | 2019-10-17 | 2023-04-25 | Asm Ip Holding B.V. | Methods for selective deposition of doped semiconductor material |
KR20210047808A (en) | 2019-10-21 | 2021-04-30 | 에이에스엠 아이피 홀딩 비.브이. | Apparatus and methods for selectively etching films |
CN111477704A (en) * | 2019-10-22 | 2020-07-31 | 国家电投集团西安太阳能电力有限公司 | Method for relieving PID attenuation of photovoltaic module |
US11646205B2 (en) | 2019-10-29 | 2023-05-09 | Asm Ip Holding B.V. | Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same |
KR20210054983A (en) | 2019-11-05 | 2021-05-14 | 에이에스엠 아이피 홀딩 비.브이. | Structures with doped semiconductor layers and methods and systems for forming same |
US11501968B2 (en) | 2019-11-15 | 2022-11-15 | Asm Ip Holding B.V. | Method for providing a semiconductor device with silicon filled gaps |
KR20210062561A (en) | 2019-11-20 | 2021-05-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure |
US11450529B2 (en) | 2019-11-26 | 2022-09-20 | Asm Ip Holding B.V. | Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface |
CN112951697A (en) | 2019-11-26 | 2021-06-11 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112885693A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112885692A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
JP2021090042A (en) | 2019-12-02 | 2021-06-10 | エーエスエム アイピー ホールディング ビー.ブイ. | Substrate processing apparatus and substrate processing method |
KR20210070898A (en) | 2019-12-04 | 2021-06-15 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11885013B2 (en) | 2019-12-17 | 2024-01-30 | Asm Ip Holding B.V. | Method of forming vanadium nitride layer and structure including the vanadium nitride layer |
KR20210080214A (en) | 2019-12-19 | 2021-06-30 | 에이에스엠 아이피 홀딩 비.브이. | Methods for filling a gap feature on a substrate and related semiconductor structures |
KR20210095050A (en) | 2020-01-20 | 2021-07-30 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming thin film and method of modifying surface of thin film |
TW202130846A (en) | 2020-02-03 | 2021-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming structures including a vanadium or indium layer |
TW202146882A (en) | 2020-02-04 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of verifying an article, apparatus for verifying an article, and system for verifying a reaction chamber |
US11776846B2 (en) | 2020-02-07 | 2023-10-03 | Asm Ip Holding B.V. | Methods for depositing gap filling fluids and related systems and devices |
TW202146715A (en) | 2020-02-17 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for growing phosphorous-doped silicon layer and system of the same |
KR20210116249A (en) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | lockout tagout assembly and system and method of using same |
KR20210116240A (en) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate handling device with adjustable joints |
KR20210117157A (en) | 2020-03-12 | 2021-09-28 | 에이에스엠 아이피 홀딩 비.브이. | Method for Fabricating Layer Structure Having Target Topological Profile |
KR20210124042A (en) | 2020-04-02 | 2021-10-14 | 에이에스엠 아이피 홀딩 비.브이. | Thin film forming method |
TW202146689A (en) | 2020-04-03 | 2021-12-16 | 荷蘭商Asm Ip控股公司 | Method for forming barrier layer and method for manufacturing semiconductor device |
TW202145344A (en) | 2020-04-08 | 2021-12-01 | 荷蘭商Asm Ip私人控股有限公司 | Apparatus and methods for selectively etching silcon oxide films |
US11821078B2 (en) | 2020-04-15 | 2023-11-21 | Asm Ip Holding B.V. | Method for forming precoat film and method for forming silicon-containing film |
CN113555279A (en) | 2020-04-24 | 2021-10-26 | Asm Ip私人控股有限公司 | Method of forming vanadium nitride-containing layers and structures including the same |
KR20210132605A (en) | 2020-04-24 | 2021-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Vertical batch furnace assembly comprising a cooling gas supply |
KR20210132600A (en) | 2020-04-24 | 2021-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element |
KR20210134226A (en) | 2020-04-29 | 2021-11-09 | 에이에스엠 아이피 홀딩 비.브이. | Solid source precursor vessel |
KR20210134869A (en) | 2020-05-01 | 2021-11-11 | 에이에스엠 아이피 홀딩 비.브이. | Fast FOUP swapping with a FOUP handler |
KR20210141379A (en) | 2020-05-13 | 2021-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Laser alignment fixture for a reactor system |
KR20210143653A (en) | 2020-05-19 | 2021-11-29 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210145078A (en) | 2020-05-21 | 2021-12-01 | 에이에스엠 아이피 홀딩 비.브이. | Structures including multiple carbon layers and methods of forming and using same |
TW202201602A (en) | 2020-05-29 | 2022-01-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing device |
TW202218133A (en) | 2020-06-24 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming a layer provided with silicon |
TW202217953A (en) | 2020-06-30 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing method |
KR20220010438A (en) | 2020-07-17 | 2022-01-25 | 에이에스엠 아이피 홀딩 비.브이. | Structures and methods for use in photolithography |
TW202204662A (en) | 2020-07-20 | 2022-02-01 | 荷蘭商Asm Ip私人控股有限公司 | Method and system for depositing molybdenum layers |
TW202212623A (en) | 2020-08-26 | 2022-04-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming metal silicon oxide layer and metal silicon oxynitride layer, semiconductor structure, and system |
USD990534S1 (en) | 2020-09-11 | 2023-06-27 | Asm Ip Holding B.V. | Weighted lift pin |
USD1012873S1 (en) | 2020-09-24 | 2024-01-30 | Asm Ip Holding B.V. | Electrode for semiconductor processing apparatus |
TW202229613A (en) | 2020-10-14 | 2022-08-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of depositing material on stepped structure |
TW202217037A (en) | 2020-10-22 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of depositing vanadium metal, structure, device and a deposition assembly |
TW202223136A (en) | 2020-10-28 | 2022-06-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming layer on substrate, and semiconductor processing system |
KR20220076343A (en) | 2020-11-30 | 2022-06-08 | 에이에스엠 아이피 홀딩 비.브이. | an injector configured for arrangement within a reaction chamber of a substrate processing apparatus |
US11946137B2 (en) | 2020-12-16 | 2024-04-02 | Asm Ip Holding B.V. | Runout and wobble measurement fixtures |
TW202231903A (en) | 2020-12-22 | 2022-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate |
USD1023959S1 (en) | 2021-05-11 | 2024-04-23 | Asm Ip Holding B.V. | Electrode for substrate processing apparatus |
USD980814S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas distributor for substrate processing apparatus |
USD980813S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas flow control plate for substrate processing apparatus |
USD981973S1 (en) | 2021-05-11 | 2023-03-28 | Asm Ip Holding B.V. | Reactor wall for substrate processing apparatus |
USD990441S1 (en) | 2021-09-07 | 2023-06-27 | Asm Ip Holding B.V. | Gas flow control plate |
CN115125510A (en) * | 2022-06-22 | 2022-09-30 | 中威新能源(成都)有限公司 | Chemical vapor deposition method, carrier, cell piece and heterojunction cell |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4060426A (en) * | 1974-07-02 | 1977-11-29 | Polaroid Corporation | Tin indium oxide and polyvinylcarbazole layered polarized photovoltaic cell |
US4769086A (en) * | 1987-01-13 | 1988-09-06 | Atlantic Richfield Company | Thin film solar cell with nickel back |
US5453135A (en) * | 1992-12-28 | 1995-09-26 | Canon Kabushiki Kaisha | Photoelectric conversion device with improved back reflection layer |
US5677236A (en) * | 1995-02-24 | 1997-10-14 | Mitsui Toatsu Chemicals, Inc. | Process for forming a thin microcrystalline silicon semiconductor film |
US5858120A (en) * | 1995-11-10 | 1999-01-12 | Canon Kabushiki Kaisha | Photovoltaic device |
US6180870B1 (en) * | 1996-08-28 | 2001-01-30 | Canon Kabushiki Kaisha | Photovoltaic device |
US20070169808A1 (en) * | 2006-01-26 | 2007-07-26 | Kherani Nazir P | Solar cell |
US20080105302A1 (en) * | 2006-11-02 | 2008-05-08 | Guardian Industries Corp. | Front electrode for use in photovoltaic device and method of making same |
US20080115828A1 (en) * | 2006-11-17 | 2008-05-22 | Guardian Industries Corp. | High transmission glass ground at edge portion(s) thereof for use in electronic device such as photovoltaic applications and corresponding method |
US20080173350A1 (en) * | 2007-01-18 | 2008-07-24 | Applied Materials, Inc. | Multi-junction solar cells and methods and apparatuses for forming the same |
US20080178932A1 (en) * | 2006-11-02 | 2008-07-31 | Guardian Industries Corp. | Front electrode including transparent conductive coating on patterned glass substrate for use in photovoltaic device and method of making same |
US20080236661A1 (en) * | 2007-03-30 | 2008-10-02 | Delta Electronics Inc. | Solar cell |
US20080283490A1 (en) * | 2007-05-17 | 2008-11-20 | Hsin-Chiao Luan | Protection layer for fabricating a solar cell |
US20090020154A1 (en) * | 2007-01-18 | 2009-01-22 | Shuran Sheng | Multi-junction solar cells and methods and apparatuses for forming the same |
US20090056798A1 (en) * | 2007-08-29 | 2009-03-05 | Ferro Corporation | Thick Film Pastes For Fire Through Applications In Solar Cells |
US20090104733A1 (en) * | 2007-10-22 | 2009-04-23 | Yong Kee Chae | Microcrystalline silicon deposition for thin film solar applications |
US20090304912A1 (en) * | 2008-06-06 | 2009-12-10 | Byung Sung Kwak | Method for manufacturing electrochromic devices |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3419108B2 (en) * | 1994-10-06 | 2003-06-23 | 鐘淵化学工業株式会社 | Manufacturing method of thin film solar cell |
JPH09129905A (en) * | 1995-10-27 | 1997-05-16 | Mitsubishi Heavy Ind Ltd | Amorphous semiconductor solar cell |
JP3294097B2 (en) * | 1996-02-14 | 2002-06-17 | 三菱重工業株式会社 | Amorphous semiconductor solar cell |
JPH09283777A (en) * | 1996-04-17 | 1997-10-31 | Citizen Watch Co Ltd | Manufacture of solar cell |
JPH10144942A (en) * | 1996-11-11 | 1998-05-29 | Mitsubishi Heavy Ind Ltd | Amorphous semiconductor solar cell |
JPH11150282A (en) * | 1997-11-17 | 1999-06-02 | Canon Inc | Photovoltaic element and its manufacture |
-
2010
- 2010-12-28 WO PCT/US2010/062175 patent/WO2011087878A2/en active Application Filing
- 2010-12-28 US US12/980,132 patent/US8252624B2/en not_active Expired - Fee Related
- 2010-12-28 CN CN2010800618324A patent/CN102714228A/en active Pending
- 2010-12-28 US US12/980,135 patent/US20110174362A1/en not_active Abandoned
- 2010-12-30 TW TW099146966A patent/TW201208101A/en unknown
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4060426A (en) * | 1974-07-02 | 1977-11-29 | Polaroid Corporation | Tin indium oxide and polyvinylcarbazole layered polarized photovoltaic cell |
US4769086A (en) * | 1987-01-13 | 1988-09-06 | Atlantic Richfield Company | Thin film solar cell with nickel back |
US5453135A (en) * | 1992-12-28 | 1995-09-26 | Canon Kabushiki Kaisha | Photoelectric conversion device with improved back reflection layer |
US5677236A (en) * | 1995-02-24 | 1997-10-14 | Mitsui Toatsu Chemicals, Inc. | Process for forming a thin microcrystalline silicon semiconductor film |
US5858120A (en) * | 1995-11-10 | 1999-01-12 | Canon Kabushiki Kaisha | Photovoltaic device |
US6180870B1 (en) * | 1996-08-28 | 2001-01-30 | Canon Kabushiki Kaisha | Photovoltaic device |
US20070169808A1 (en) * | 2006-01-26 | 2007-07-26 | Kherani Nazir P | Solar cell |
US20080178932A1 (en) * | 2006-11-02 | 2008-07-31 | Guardian Industries Corp. | Front electrode including transparent conductive coating on patterned glass substrate for use in photovoltaic device and method of making same |
US20080105302A1 (en) * | 2006-11-02 | 2008-05-08 | Guardian Industries Corp. | Front electrode for use in photovoltaic device and method of making same |
US20080115828A1 (en) * | 2006-11-17 | 2008-05-22 | Guardian Industries Corp. | High transmission glass ground at edge portion(s) thereof for use in electronic device such as photovoltaic applications and corresponding method |
US20080173350A1 (en) * | 2007-01-18 | 2008-07-24 | Applied Materials, Inc. | Multi-junction solar cells and methods and apparatuses for forming the same |
US20090020154A1 (en) * | 2007-01-18 | 2009-01-22 | Shuran Sheng | Multi-junction solar cells and methods and apparatuses for forming the same |
US20080236661A1 (en) * | 2007-03-30 | 2008-10-02 | Delta Electronics Inc. | Solar cell |
US20080283490A1 (en) * | 2007-05-17 | 2008-11-20 | Hsin-Chiao Luan | Protection layer for fabricating a solar cell |
US20090056798A1 (en) * | 2007-08-29 | 2009-03-05 | Ferro Corporation | Thick Film Pastes For Fire Through Applications In Solar Cells |
US20090104733A1 (en) * | 2007-10-22 | 2009-04-23 | Yong Kee Chae | Microcrystalline silicon deposition for thin film solar applications |
US20090304912A1 (en) * | 2008-06-06 | 2009-12-10 | Byung Sung Kwak | Method for manufacturing electrochromic devices |
Cited By (85)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9040333B2 (en) | 2011-04-11 | 2015-05-26 | National Applied Research Laboratories | Method for fabricating power-generating module with solar cell |
US20120256181A1 (en) * | 2011-04-11 | 2012-10-11 | Jia-Min Shieh | Power-generating module with solar cell and method for fabricating the same |
CN103137769A (en) * | 2011-12-02 | 2013-06-05 | 杜邦太阳能有限公司 | Cascade type solar battery and manufacturing method thereof |
WO2013102576A1 (en) * | 2012-01-04 | 2013-07-11 | Tel Solar Ag | Intermediate reflection structure in thin film solar cells |
KR101766339B1 (en) | 2012-01-11 | 2017-08-08 | 엘지전자 주식회사 | Solar cell and method for manufacturing the same |
US20150295099A1 (en) * | 2012-01-13 | 2015-10-15 | Kurtis LESCHKIES | High work-function buffer layers for silicon-based photovoltaic devices |
WO2013130746A1 (en) * | 2012-02-28 | 2013-09-06 | International Business Machines Corporation | Solar cell made using barrier layer between p-type and intrinsic layers |
US9537038B2 (en) | 2012-02-28 | 2017-01-03 | International Business Machines Corporation | Solar cell made using a barrier layer between P-type and intrinsic layers |
US9190549B2 (en) | 2012-02-28 | 2015-11-17 | International Business Machines Corporation | Solar cell made using a barrier layer between p-type and intrinsic layers |
CN102655178A (en) * | 2012-04-28 | 2012-09-05 | 法国圣戈班玻璃公司 | Cover plate, manufacturing method of cover plate, solar glass and photovoltaic device |
US10319872B2 (en) | 2012-05-10 | 2019-06-11 | International Business Machines Corporation | Cost-efficient high power PECVD deposition for solar cells |
US10672932B2 (en) * | 2012-05-10 | 2020-06-02 | International Business Machines Corporation | Cost-efficient high power PECVD deposition for solar cells |
US10727367B2 (en) | 2012-05-10 | 2020-07-28 | International Business Machines Corporation | Cost-efficient high power PECVD deposition for solar cells |
DE102013207490B4 (en) | 2012-05-10 | 2022-11-17 | International Business Machines Corporation | Cost-effective, high-performance PECVD deposition for solar cells |
TWI475704B (en) * | 2012-06-14 | 2015-03-01 | Nexpower Technology Corp | Thin film solar cell and manufacturing method thereof |
CN103579426A (en) * | 2012-07-19 | 2014-02-12 | 华夏光股份有限公司 | Semiconductor device |
CN103594572A (en) * | 2012-08-15 | 2014-02-19 | 华夏光股份有限公司 | Alternating-current light-emitting device |
US10128396B2 (en) | 2012-10-26 | 2018-11-13 | Stmicroelectronics S.R.L. | Photovoltaic cell |
US11257975B2 (en) | 2012-10-26 | 2022-02-22 | Stmicroelectronics S.R.L. | Photovoltaic cell |
US20140174517A1 (en) * | 2012-12-21 | 2014-06-26 | Lg Electronics Inc. | Solar cell and method of manufacturing the same |
US9437757B2 (en) | 2013-03-13 | 2016-09-06 | Sunpower Corporation | Methods for wet chemistry polishing for improved low viscosity printing in solar cell fabrication |
US20140273331A1 (en) * | 2013-03-13 | 2014-09-18 | Genevieve A. Solomon | Methods for wet chemistry polishing for improved low viscosity printing in solar cell fabrication |
US9082925B2 (en) * | 2013-03-13 | 2015-07-14 | Sunpower Corporation | Methods for wet chemistry polishing for improved low viscosity printing in solar cell fabrication |
US9799781B2 (en) * | 2013-11-08 | 2017-10-24 | Lg Electronics Inc. | Solar cell |
US10644171B2 (en) | 2013-11-08 | 2020-05-05 | Lg Electronics Inc. | Solar cell |
US20150129037A1 (en) * | 2013-11-08 | 2015-05-14 | Lg Electronics Inc. | Solar cell |
US10910257B2 (en) | 2014-01-23 | 2021-02-02 | Globalwafers Co., Ltd. | High resistivity SOI wafers and a method of manufacturing thereof |
US11081386B2 (en) | 2014-01-23 | 2021-08-03 | Globalwafers Co., Ltd. | High resistivity SOI wafers and a method of manufacturing thereof |
US10079170B2 (en) | 2014-01-23 | 2018-09-18 | Globalwafers Co., Ltd. | High resistivity SOI wafers and a method of manufacturing thereof |
US11594446B2 (en) | 2014-01-23 | 2023-02-28 | Globalwafers Co., Ltd. | High resistivity SOI wafers and a method of manufacturing thereof |
US10483379B2 (en) | 2014-09-04 | 2019-11-19 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss |
US9853133B2 (en) * | 2014-09-04 | 2017-12-26 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity silicon-on-insulator substrate |
US9985146B2 (en) | 2014-09-19 | 2018-05-29 | Kabushiki Kaisha Toshiba | Photoelectric conversion device, and solar cell |
US10483152B2 (en) | 2014-11-18 | 2019-11-19 | Globalwafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
US10224233B2 (en) | 2014-11-18 | 2019-03-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation |
US11699615B2 (en) | 2014-11-18 | 2023-07-11 | Globalwafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacture |
US10796945B2 (en) | 2014-11-18 | 2020-10-06 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He—N2 co-implantation |
US10403541B2 (en) | 2014-11-18 | 2019-09-03 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He—N2 co-implantation |
US10381261B2 (en) | 2014-11-18 | 2019-08-13 | Globalwafers Co., Ltd. | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers |
US10381260B2 (en) | 2014-11-18 | 2019-08-13 | GlobalWafers Co., Inc. | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers |
US11139198B2 (en) | 2014-11-18 | 2021-10-05 | Globalwafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
US10784146B2 (en) | 2015-03-03 | 2020-09-22 | Globalwafers Co., Ltd. | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
US10283402B2 (en) | 2015-03-03 | 2019-05-07 | Globalwafers Co., Ltd. | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
US10658227B2 (en) | 2015-03-03 | 2020-05-19 | Globalwafers Co., Ltd. | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
US9881832B2 (en) | 2015-03-17 | 2018-01-30 | Sunedison Semiconductor Limited (Uen201334164H) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof |
US10475694B2 (en) | 2015-03-17 | 2019-11-12 | Globalwafers Co., Ltd. | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof |
US10290533B2 (en) | 2015-03-17 | 2019-05-14 | Globalwafers Co., Ltd. | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures |
US10510583B2 (en) | 2015-06-01 | 2019-12-17 | Globalwafers Co., Ltd. | Method of manufacturing silicon germanium-on-insulator |
US10332782B2 (en) | 2015-06-01 | 2019-06-25 | Globalwafers Co., Ltd. | Method of manufacturing silicon germanium-on-insulator |
US10304722B2 (en) | 2015-06-01 | 2019-05-28 | Globalwafers Co., Ltd. | Method of manufacturing semiconductor-on-insulator |
US10755966B2 (en) | 2015-11-20 | 2020-08-25 | GlobaWafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
US10818539B2 (en) | 2015-11-20 | 2020-10-27 | Globalwafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
US10529616B2 (en) | 2015-11-20 | 2020-01-07 | Globalwafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
US10985049B2 (en) | 2015-11-20 | 2021-04-20 | Globalwafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
US10622247B2 (en) | 2016-02-19 | 2020-04-14 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a buried high resistivity layer |
US11508612B2 (en) | 2016-02-19 | 2022-11-22 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a buried high resistivity layer |
US10468294B2 (en) | 2016-02-19 | 2019-11-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface |
US9831115B2 (en) | 2016-02-19 | 2017-11-28 | Sunedison Semiconductor Limited (Uen201334164H) | Process flow for manufacturing semiconductor on insulator structures in parallel |
US10593748B2 (en) | 2016-03-07 | 2020-03-17 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof |
US11114332B2 (en) | 2016-03-07 | 2021-09-07 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof |
US11848227B2 (en) | 2016-03-07 | 2023-12-19 | Globalwafers Co., Ltd. | Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment |
US10573550B2 (en) | 2016-03-07 | 2020-02-25 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof |
US11655559B2 (en) | 2016-06-08 | 2023-05-23 | Globalwafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
US11655560B2 (en) | 2016-06-08 | 2023-05-23 | Globalwafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
US11142844B2 (en) | 2016-06-08 | 2021-10-12 | Globalwafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
US10475695B2 (en) | 2016-06-22 | 2019-11-12 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
US11587825B2 (en) | 2016-06-22 | 2023-02-21 | Globalwafers Co., Ltd. | Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate |
US10825718B2 (en) | 2016-06-22 | 2020-11-03 | Globalwafers Co., Ltd. | Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate |
US10269617B2 (en) | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
US11380576B2 (en) | 2016-06-22 | 2022-07-05 | Globalwafers Co., Ltd. | Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate |
US11239107B2 (en) | 2016-10-26 | 2022-02-01 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
US10546771B2 (en) | 2016-10-26 | 2020-01-28 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
US10741437B2 (en) | 2016-10-26 | 2020-08-11 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
US10832937B1 (en) | 2016-10-26 | 2020-11-10 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
US11145538B2 (en) | 2016-12-05 | 2021-10-12 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator structure and method of manufacture thereof |
US10468295B2 (en) | 2016-12-05 | 2019-11-05 | GlobalWafers Co. Ltd. | High resistivity silicon-on-insulator structure and method of manufacture thereof |
US10453703B2 (en) | 2016-12-28 | 2019-10-22 | Sunedison Semiconductor Limited (Uen201334164H) | Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield |
US10707093B2 (en) | 2016-12-28 | 2020-07-07 | Sunedison Semiconductor Limited (Uen201334164H) | Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield |
US10475696B2 (en) | 2017-07-14 | 2019-11-12 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacture of a semiconductor on insulator structure |
US10796946B2 (en) | 2017-07-14 | 2020-10-06 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacture of a semiconductor on insulator structure |
US11173697B2 (en) | 2018-04-27 | 2021-11-16 | Globalwafers Co., Ltd. | Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate |
US11443978B2 (en) | 2018-06-08 | 2022-09-13 | Globalwafers Co., Ltd. | Method for transfer of a thin layer of silicon |
US10818540B2 (en) | 2018-06-08 | 2020-10-27 | Globalwafers Co., Ltd. | Method for transfer of a thin layer of silicon |
US11696504B2 (en) | 2020-05-18 | 2023-07-04 | Stmicroelectronics S.R.L. | Method of fabrication of an integrated thermoelectric converter, and integrated thermoelectric converter thus obtained |
EP3913681A3 (en) * | 2020-05-18 | 2022-03-16 | STMicroelectronics S.r.l. | Method of fabrication of an integrated thermoelectric converter, and integrated thermoelectric converter thus obtained |
Also Published As
Publication number | Publication date |
---|---|
CN102714228A (en) | 2012-10-03 |
WO2011087878A3 (en) | 2011-11-24 |
US20110177648A1 (en) | 2011-07-21 |
TW201208101A (en) | 2012-02-16 |
US8252624B2 (en) | 2012-08-28 |
WO2011087878A2 (en) | 2011-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8252624B2 (en) | Method of manufacturing thin film solar cells having a high conversion efficiency | |
US8895842B2 (en) | High quality TCO-silicon interface contact structure for high efficiency thin film silicon solar cells | |
US7582515B2 (en) | Multi-junction solar cells and methods and apparatuses for forming the same | |
US20100269896A1 (en) | Microcrystalline silicon alloys for thin film and wafer based solar applications | |
US8203071B2 (en) | Multi-junction solar cells and methods and apparatuses for forming the same | |
US7919398B2 (en) | Microcrystalline silicon deposition for thin film solar applications | |
US20110088760A1 (en) | Methods of forming an amorphous silicon layer for thin film solar cell application | |
US20080173350A1 (en) | Multi-junction solar cells and methods and apparatuses for forming the same | |
US20080223440A1 (en) | Multi-junction solar cells and methods and apparatuses for forming the same | |
EP2187446A2 (en) | Microcrystalline silicon alloys for thin film and wafer based solar applications | |
EP2359411A2 (en) | Microcrystalline silicon alloys for thin film and wafer based solar applications | |
WO2013130179A2 (en) | Buffer layer for improving the performance and stability of surface passivation of si solar cells | |
US20130112264A1 (en) | Methods for forming a doped amorphous silicon oxide layer for solar cell devices | |
EP2439792A1 (en) | Thin-film solar cell fabrication process, deposition method for solar cell precursor layer stack, and solar cell precursor layer stack | |
US20110120536A1 (en) | Roughness control of a wavelength selective reflector layer for thin film solar applications | |
US20120107996A1 (en) | Surface treatment process performed on a transparent conductive oxide layer for solar cell applications | |
EP2426737A1 (en) | Thin-film solar fabrication process, deposition method for solar cell precursor layer stack, and solar cell precursor layer stack | |
US20120285522A1 (en) | Thin-film solar fabrication process, deposition method for tco layer, and solar cell precursor layer stack | |
EP2210273A1 (en) | Method of dynamic temperature control during microcrystalline si growth | |
WO2010117548A2 (en) | High quality tco-silicon interface contact structure for high efficiency thin film silicon solar cells | |
US20110275200A1 (en) | Methods of dynamically controlling film microstructure formed in a microcrystalline layer | |
US20110171774A1 (en) | Cleaning optimization of pecvd solar films | |
WO2012113441A1 (en) | Thin-film solar fabrication process, deposition method for a layer stack of a solar cell, and solar cell precursor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: APPLIED MATERIALS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TANNER, DAVID;LE, HEIN-MINH HUU;GU, QUANCHENG;AND OTHERS;SIGNING DATES FROM 20110127 TO 20110204;REEL/FRAME:025924/0526 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |