US20110291264A1 - Integrated circuit packaging system with posts and method of manufacture thereof - Google Patents
Integrated circuit packaging system with posts and method of manufacture thereof Download PDFInfo
- Publication number
- US20110291264A1 US20110291264A1 US12/791,865 US79186510A US2011291264A1 US 20110291264 A1 US20110291264 A1 US 20110291264A1 US 79186510 A US79186510 A US 79186510A US 2011291264 A1 US2011291264 A1 US 2011291264A1
- Authority
- US
- United States
- Prior art keywords
- underfill
- horizontal cover
- integrated circuit
- protruding connector
- post
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Definitions
- the present invention relates generally to an integrated circuit packaging system, and more particularly to a system with interconnects.
- Products must be capable of competing in world markets and attracting many consumers or buyers. It is very important for products to continue to improve in features, performance, and reliability while reducing product costs, product size, and to be available quickly for purchase by the consumers or buyers.
- the present invention provides a method of manufacture of an integrated circuit packaging system including: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer.
- the present invention provides an integrated circuit packaging system, including: an integrated circuit chip having a chip pad; a conductive post on the chip pad; and an underfill around the conductive post, the conductive post exposed from the underfill, and a non-horizontal underfill side of the underfill planar with a non-horizontal side of the integrated circuit chip.
- FIG. 1 is a bottom view of an integrated circuit packaging system in a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view of FIG. 1 taken along a line 2 - 2 of FIG. 1 .
- FIG. 3 is a top view of an integrated circuit packaging system in a second embodiment of the present invention.
- FIG. 4 is a cross-sectional view of FIG. 3 taken along a line 4 - 4 of FIG. 3 .
- FIG. 5 is a top view of a semiconductor wafer used in manufacturing of the integrated circuit packaging system of FIG. 2 .
- FIG. 6 is a cross-sectional view of FIG. 5 taken along a line 6 - 6 of FIG. 5 .
- FIG. 7 is a bottom view of a wafer frame used in manufacturing of the integrated circuit packaging system of FIG. 2 .
- FIG. 8 is a cross-sectional view of FIG. 7 taken along a line 8 - 8 of FIG. 7 .
- FIG. 9 is a top view of the structure of FIG. 7 on the structure of FIG. 5 in a mounting phase.
- FIG. 10 is a cross-sectional view of FIG. 9 taken along a line 10 - 10 of FIG. 9 in an attaching phase.
- FIG. 11 is the structure of FIG. 10 in an underfill applying phase.
- FIG. 12 is the structure of FIG. 11 in a planarizing phase.
- FIG. 13 is the structure of FIG. 12 in a singulation phase.
- FIG. 14 is a bottom view of a wafer frame used in manufacturing of the integrated circuit packaging system of FIG. 2 in a third embodiment of the present invention.
- FIG. 15 is a cross-sectional view of FIG. 14 taken along a line 15 - 15 of FIG. 14 .
- FIG. 16 is a top view of the structure of FIG. 14 on the structure of FIG. 5 in a mounting phase.
- FIG. 17 is a cross-sectional view of FIG. 16 taken along a line 17 - 17 of FIG. 16 in an attaching phase.
- FIG. 18 is the structure of FIG. 17 in an underfill applying phase.
- FIG. 19 is the structure of FIG. 18 in an etching phase.
- FIG. 20 is the structure of FIG. 19 in a singulation phase.
- FIG. 21 is a flow chart of a method of manufacture of the integrated circuit packaging system in a further embodiment of the present invention.
- horizontal is defined as a plane parallel to the plane or surface of the present invention, regardless of its orientation.
- vertical refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane, as shown in the figures.
- active side refers to a side of a die, a module, a package, or an electronic structure having active circuitry fabricated thereon or having elements for connection to the active circuitry within the die, the module, the package, or the electronic structure.
- processing includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
- Embodiments of the present invention provides methods/solutions to meet the critical for the demand by providing methods to form interconnects and underfill on wafers during wafer level processing.
- the embodiments forthcoming describe methods that result in improved interconnect joint strengths, improved coplanar interconnects, underfill uniformity, and fine pitch interconnects for the flip chip packages.
- FIG. 1 therein is shown a bottom view of an integrated circuit packaging system 100 in a first embodiment of the present invention.
- the bottom view depicts first post ends 102 , second post ends 104 , third post ends 106 , and fourth post ends 108 exposed from an underfill 112 of the integrated circuit packaging system 100 .
- the integrated circuit packaging system 100 can be a flip chip, as an example.
- the integrated circuit packaging system 100 can be formed having one of or any combination of the first post ends 102 , the second post ends 104 , the third post ends 106 , or the fourth post ends 108 exposed in any position from the underfill 112 .
- the integrated circuit packaging system 100 is shown having every row occupied with the first post ends 102 except the bottom row, as an example.
- the first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 exposed from the underfill 112 can provide electrical connectivity to circuitry within the integrated circuit packaging system 100 .
- the underfill 112 provides a hermetic seal protection around the first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 and to the contents of the integrated circuit packaging system 100 .
- the underfill 112 also provides mechanical support and electrical isolation for the first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 .
- the underfill 112 can be formed from an etchant resistant electrically insulative material capable of providing structural rigidity and characteristics similar that of an epoxy, an encapsulant, or an anisotropic conductive film (ACF).
- the underfill 112 can be used to improve the thermal dissipation characteristics of the present invention.
- the underfill 112 can be formed from a thermally conductive material to provide both improve thermal dissipation and the hermetic seal protection.
- Non-horizontal underfill sides 114 of the underfill 112 enclose an area containing the first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 forming an outline of a planar shape of the integrated circuit packaging system 100 .
- first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 are shown having a footprint shape of a circle. It is understood that the first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 can have a different footprint shapes.
- the first post ends 102 can have combination of footprint shapes that can include a rectangle, oval, or a multifaceted geometric shape.
- FIG. 2 therein is shown a cross-sectional view of FIG. 1 taken along a line 2 - 2 of FIG. 1 .
- the cross-sectional view depicts first conductive posts 202 having the first post ends 102 , second conductive posts 204 having the second post ends 104 , third conductive posts 206 having the third post ends 106 , and the fourth conductive posts 208 having the fourth post ends 108 .
- the first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 are exposed from an attachment side 210 of the underfill 112 .
- the first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 can be formed from a metal that can include a copper metal, a conductive metal, a conductive metal alloy, or any combination thereof.
- the first post ends 102 can be formed coplanar to the attachment side 210 using a planarization process, an etching process, or a combination thereof.
- the planarization process results in the first post ends 102 having planarization marks and the etching process results in etch marks.
- planarization marks are defined as a physical appearance on a surface of an element that is a result of manufacturing processes that can include grinding, sanding, polishing, or any combination thereof.
- the planarization marks are accompanied by differences between a grain structure on the surface of the element and a grain structure below the surface of the element.
- the etch marks are defined as an etched physical appearance on a surface of an element that is the result of a chemical etchant.
- the chemical etchant is an acidic, alkali, or basic chemical used to dissolve unwanted materials such as metals, semiconductor materials, or glass from a reduction-oxidation (redox) reaction.
- the etched physical appearance are from changes in microstructure and macrostructure of the surface of the element as a result of the redox reactions introduced by the chemical etchant are observable using metallography techniques to observe characteristics that can include a surface crystal structure, surface reflective, surface refractive, and surface profile characteristics.
- the second conductive posts 204 includes a raised platform 212 located centrally on the second post ends 104 .
- the second post ends 104 can optionally include a protect layer 214 .
- the protect layer 214 can be formed from a conductive metal different from the metal of the first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 .
- the protect layer 214 can cover a portion of the second conductive posts 204 over the attachment side 210 to prevent the portion of the second conductive posts 204 from exposure to the chemical etchant.
- the protect layer 214 on the second post ends 104 includes etch marks as a result of the etching process.
- the second post ends 104 can be formed without the protect layer 214 provided the second post ends 104 are formed from an etchant resistant conductive metal material.
- the second post ends 104 formed without the protect layer 214 results in the second post ends 104 having the etch marks.
- the third post ends 106 can project above the attachment side 210 and include a cavity 216 centrally located in the third post ends 106 .
- the cavity 216 is formed by surrounding sides and an inner post base 217 of the third post ends 106 that are coplanar with the attachment side 210 .
- the third post ends 106 can optionally include the protect layer 214 .
- the protect layer 214 can cover a portion of the third conductive posts 206 and the cavity 216 over the attachment side 210 to prevent the portion of the third conductive posts 206 from exposure to the chemical etchant.
- the protect layer 214 on the third post ends 106 includes etch marks as a result of the etching process.
- the third post ends 106 can be formed without the protect layer 214 provided the third post ends 106 are formed from an etchant resistant conductive metal material.
- the third post ends 106 formed without the protect layer 214 results in the third post ends 106 having the etch marks.
- the fourth post ends 108 of the fourth conductive posts 208 can be below the attachment side 210 and forms a bottom of a recess 218 of the underfill 112 .
- the fourth post ends 108 can optionally include the protect layer 214 covering the fourth conductive posts 208 .
- the protect layer 214 can cover a portion of the fourth conductive posts 208 to prevent the portion of the fourth conductive posts 208 from exposure to the chemical etchant.
- the protect layer 214 on the fourth post ends 108 includes etch marks as a result of the etching process.
- the fourth post ends 108 can be formed without the protect layer 214 provided the fourth post ends 108 are formed from an etchant resistant conductive metal material.
- the fourth post ends 108 formed without the protect layer 214 results in the fourth post ends 108 having the etch marks.
- the underfill 112 is attached to an integrated circuit chip 222 .
- the integrated circuit chip 222 is defined as an active device including a non-active side and an active side 224 having circuitry fabricated thereon.
- a side of the underfill 112 opposite the attachment side 210 is in direct contact with the active side 224 of the integrated circuit chip 222 .
- the attachment side 210 can be parallel with the active side 224 .
- Chip pads 228 formed of conductive metal or metal alloys on the active side 224 .
- the chip pads 228 are bond pads for the integrated circuit chip 222 .
- the chip pads 228 are attached to ends of the first conductive posts 202 opposite the first post ends 102 , the second conductive posts 204 opposite the second post ends 104 , the third conductive posts 206 opposite the third post ends 106 , and the fourth conductive posts 208 opposite the fourth post ends 108 using solder.
- the chip pads 228 provide connectivity between circuitry of the integrated circuit chip 222 and the first conductive posts 202 , the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 .
- the first conductive posts 202 , the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 are formed from a material that can include a copper metal, a conductive metal, a conductive metal alloy, or any combination thereof.
- the first conductive posts 202 , the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 can be structured having multiple joined layers of different material having different physical characteristic properties.
- the underfill 112 surrounds, provides structural support, and hermetically seals the active side 224 , sides of the chip pads 228 , and sides of the first conductive posts 202 , the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 .
- Non-horizontal sides 230 of the integrated circuit chip 222 can be coplanar with the non-horizontal underfill sides 114 .
- the attachment side 210 can also be formed using a planarization process, an etching process, or a combination thereof.
- the attachment side 210 can exhibit characteristics of similar to the planarization marks and the etch marks of the first post ends 102 .
- the underfill 112 provides improved joint strength from lateral and tangential forces applied to the first conductive posts 202 , the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 when integrating with a next level of integration (not shown) such as a printed circuit board or an integrated circuit packaging assembly.
- the improved joint strength is a result of the active side 224 , sides of the chip pads 228 , and the first conductive posts 202 , the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 held together by the underfill 112 .
- the first post ends 102 are formed to be coplanar with one another resulting in improved connectivity with the next level of integration.
- the combination of the improved joint strength and the improved connectivity results in the superior reliability of the integrated circuit packaging system 100 over the solder bumped packaging systems.
- the present invention provides the integrated circuit packaging system 100 with increased interconnection density capabilities.
- the underfill 112 provides additional support enabling the first conductive posts 202 , the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 to be thinner and closer together than solder bumps resulting in the increased interconnection density capabilities.
- FIG. 3 therein is shown a top view of an integrated circuit packaging system 300 in a second embodiment of the present invention.
- the top view depicts an encapsulation 302 having a rectangular shape and package sides 304 formed around a periphery of the integrated circuit packaging system 300 .
- the encapsulation 302 can optionally be omitted from the integrated circuit packaging system 300 .
- the encapsulation 302 can be formed form materials that can include an epoxy, a ceramic, a plastic, a molding compound, or any combination thereof.
- the encapsulation 302 can be used to protect the integrated circuit packaging system 300 by providing structural support, and hermetically sealing the contents of the integrated circuit packaging system 300 .
- the integrated circuit packaging system 300 can include the integrated circuit packaging system 100 , a base substrate 402 , chip interconnects 404 , discrete components 406 , the encapsulation 302 , and system connectors 408 .
- the cross-sectional view taken along the line 4 - 4 is shown intersecting the first conductive posts 202 having the first post ends 102 .
- the second conductive posts 204 of FIG. 2 , the third conductive posts 206 of FIG. 2 , and the fourth conductive posts 208 of FIG. 3 are not shown or included here.
- the base substrate 402 can include a substrate, an interposer, a circuit board, or a laminate having base conductors 410 on an inner base side 412 , on an outer base side 414 opposite the inner base side 412 , and within the base substrate 402 .
- the base conductors 410 can be formed from a conductive material and provide connectivity between, on, and within the inner base side 412 and the outer base side 414 .
- the integrated circuit packaging system 100 can be mounted over and connected to the inner base side 412 using the chip interconnects 404 .
- the chip interconnects 404 attach the first post ends 102 with the base conductors 410 and provide electrical connectivity between the first post ends 102 and the base conductors 410 of the base substrate 402 .
- the chip interconnects 404 can be formed of solder and include solder on pads, solder films, solder pastes, or any combination thereof.
- the chip interconnects 404 are oriented between the attachment side 210 and the inner base side 412 .
- the discrete components 406 can be mounted and connected to the inner base side 412 adjacent the integrated circuit packaging system 100 . Any one of the discrete components 406 is defined to be either a transistor, a resistor, a capacitor, a diode, or an inductor.
- the encapsulation 302 can cover the integrated circuit packaging system 100 , the discrete components 406 , and the inner base side 412 to provide additional protection.
- the package sides 304 can be parallel to the non-horizontal sides 230 and the non-horizontal underfill sides 114 of the underfill 112 .
- the encapsulation 302 can be omitted and the integrated circuit packaging system 300 can be protected by an enclosure (not shown) such as a cabinet, a room, a chamber, or embedded in a package subsystem.
- the system connectors 408 can be optionally attached to the base conductors 410 on the outer base side 414 .
- the system connectors 408 can include bond wires, conductive balls, conductive bumps, conductive leads, or a combination thereof.
- the system connectors 408 can provide connectivity between the integrated circuit packaging system 300 and the next level of integration.
- the system connectors 408 can be omitted to enable other means of connectivity between the next level of integration and the integrated circuit packaging system 300 .
- the present invention provides the integrated circuit packaging system 300 with a package profile height lower than a package profile height of solder bumped packaging systems.
- the first post ends 102 of the integrated circuit packaging system 100 can be attached to the inner base side 412 of the base substrate 402 using a thin solder film.
- a combination of the first post ends 102 coplanar with the attachment side 210 and the thin solder film results in the package profile height of the present invention to be lower than the package profile height of the solder bumped packaging systems.
- FIG. 5 therein is shown a top view of a semiconductor wafer 502 used in manufacturing of the integrated circuit packaging system 100 of FIG. 2 .
- the top view of the semiconductor wafer 502 is shown having a shape of an ellipse.
- the semiconductor wafer 502 is defined as a thin slice of semiconductor material used as a substrate from which miniaturized electronic circuitry is built in and over a semiconductor active side 504 of the semiconductor wafer 502 .
- Chip sites 506 are shown located on the semiconductor wafer 502 .
- the chip sites 506 are areas of the semiconductor wafer 502 having active circuitry along the semiconductor active side 504 .
- Each of the chip sites 506 can be used to form and build the miniaturized semiconductor circuitry of the integrated circuit chip 222 of FIG. 2 .
- the semiconductor wafer 502 is depicted with sixteen of the chip sites 506 .
- the semiconductor wafer 502 can have any number of the chip sites 506 .
- the semiconductor wafer 502 can have fifty-two of the chip sites 506 , as an example.
- FIG. 6 therein is shown a cross-sectional view of FIG. 5 taken along a line 6 - 6 of FIG. 5 .
- the cross-sectional view shows a wafer non-active side 602 of the semiconductor wafer 502 opposite the semiconductor active side 504 .
- Each of the chip sites 506 include the chip pads 228 exposed from the semiconductor active side 504 .
- the chip pads 228 can provide connectivity to the miniaturized semiconductor circuitry within each of the chip sites 506 .
- the chip pads 228 can include a chip pad pitch 606 and a maximum wafer pad width 618 .
- the chip pad pitch 606 is defined as the distance between centers at adjacent locations of the chip pads 228 within each of the chip sites 506 .
- the chip pad pitch 606 of the chip pads 228 within each of the chip sites 506 can be identical.
- the maximum wafer pad width 618 is defined a largest of all possible distances measurable from any first peripheral edge of one of the chip pads 228 to a second peripheral edge of the one of the chip pads 228 opposite the first peripheral edge.
- FIG. 7 therein is shown a bottom view of a wafer frame 702 used in manufacturing of the integrated circuit packaging system 100 of FIG. 2 .
- the wafer frame 702 includes a horizontal cover 704 with a connection side 706 .
- a perimeter area formed by the horizontal cover 704 can be less than a perimeter area formed by the semiconductor wafer 502 of FIG. 5 .
- the horizontal cover 704 is formed from a material that can be removed using processes that can include grinding, sanding, polishing, cutting, sawing, or any combination thereof.
- the material used to form the horizontal cover 704 can be a metal that includes copper, copper alloys, or any combination thereof.
- the bottom view of the wafer frame 702 is shown having connect sites 708 .
- the connect sites 708 are areas on the connection side 706 .
- FIG. 8 therein is shown a cross-sectional view of FIG. 7 taken along a line 8 - 8 of FIG. 7 .
- the cross-sectional view depicts the wafer frame 702 having the horizontal cover 704 with the connection side 706 and a non-connection side 802 opposite the connection side 706 .
- the protruding connectors 804 are shown perpendicular to the connection side 706 .
- the protruding connectors 804 can be oriented having any angle relative to the connection side 706 .
- the protruding connectors 804 can be oriented having an angle of ninety degrees with respect to the connection side 706 , as an example.
- the protruding connectors 804 can be formed from a material identical to the conductive metal of the first conductive posts 202 of FIG. 2 and integral to the connection side 706 .
- the protruding connectors 804 within each of the connect sites 708 can have a connector pitch 806 less than three hundred microns inclusive.
- the connector pitch 806 is defined as the distance between centers at adjacent locations of the protruding connectors 804 within each of the connect sites 708 .
- the connector pitch 806 of the protruding connectors 804 within each of the connect sites 708 can be identical.
- Attachment surfaces 808 can be formed on an end of each of the protruding connectors 804 and can be facing away from the connection side 706 .
- the attachment surfaces 808 can be formed from a material similar to the material of the protruding connectors 804 and parallel with the connection side 706 .
- the attachment surfaces 808 can have a maximum body width 810 less than one hundred fifty microns inclusive.
- the maximum body width 810 is defined a largest of all possible distances measurable from any peripheral edge of one of the attachment surfaces 808 to an edge of the one of the attachment surfaces 808 opposite the peripheral edge.
- FIG. 9 therein is shown a top view of the structure of FIG. 7 on the structure of FIG. 5 in a mounting phase.
- the top view depicts the wafer frame 702 of FIG. 7 mounted over the semiconductor wafer 502 having the semiconductor active side 504 exposed around a circumference of the wafer frame 702 during a mounting process.
- the mounting process can include mechanized fixtures (not show) that can include automated computer monitoring, alignment, and positional equipment in a clean room environment.
- FIG. 10 therein is shown a cross-sectional view of FIG. 9 taken along a line 10 - 10 of FIG. 9 in an attaching phase.
- Each of the connect sites 708 of FIG. 7 on the connection side 706 of the horizontal cover 704 are aligned over the chip sites 506 of FIG. 5 on the semiconductor active side 504 of the semiconductor wafer 502 .
- the chip pads 228 of the semiconductor wafer 502 are attached to the attachment surfaces 808 of the protruding connectors 804 using a conductive bonding material during an attaching process.
- the conductive bonding material can include a eutectic reaction layer with thermo-compression, ultra-sonic, thermo-sonic, thermo conductive applied energy.
- FIG. 11 therein is shown the structure of FIG. 10 in an underfill applying phase.
- the underfill 112 is applied between the horizontal cover 704 and the semiconductor wafer 502 using a filling process that can include a combination of dispensing equipment (not shown) with contact heating, convective heating, or infrared heating.
- the underfill 112 surrounds the protruding connectors 804 , surrounds the chip pads 228 , and covers the connection side 706 and the semiconductor active side 504 .
- a ring shaped area 1102 around the underfill 112 can expose the semiconductor active side 504 between the underfill 112 and a perimeter outline of the semiconductor wafer 502 .
- the underfill 112 is applied during wafer processing phases of manufacturing which involves a highly specialized facility than includes cleanrooms, filtered laminated air flow, controlled temperature and humidity, and specialized equipment operating with extreme precision from the front end of the line (FEOL) through the back end of the line (BEOL).
- the underfill 112 having a uniform distribution covers the connection side 706 , the semiconductor active side 504 , the chip pads 228 , the protruding connectors 804 , and attachment areas between the attachment surfaces 808 and the protruding connectors 804 .
- the uniform distribution is defined a material having the same densities, composition, and characteristics throughout the material.
- the uniform distribution of the underfill 112 provides results in improved reliability of the structure and circuitry of the integrated circuit packaging system 100 .
- FIG. 12 therein is shown the structure of FIG. 11 in a planarizing phase.
- the horizontal cover 704 of FIG. 11 is removed from above the chip sites 506 to expose the end of each of the protruding connectors 804 of FIG. 11 opposite the end with the attachment surfaces 808 using a planarization process.
- the planarization process can include grinding, sanding, polishing, cutting, sawing, or any combination thereof of the horizontal cover 704 to expose the protruding connectors 804 and the underfill 112 .
- the planarization of the protruding connectors 804 results in formation of the first conductive posts 202 with the first post ends 102 .
- the first post ends 102 are exposed from the underfill 112 and parallel to the semiconductor wafer 502 .
- the first post ends 102 are formed having the planarization marks.
- Non-horizontal planar cuts through the semiconductor wafer 502 and the underfill 112 are used to separate the chip sites 506 of FIG. 12 from one another and the ring shaped area 1102 during a singulation process.
- the singulation process includes cutting, sawing, grinding, or any combination thereof.
- the integrated circuit packaging system 1302 is similar to the integrated circuit packaging system 100 of FIG. 2 except the integrated circuit packaging system 1302 has only the first conductive posts 202 with the first post ends 102 and includes the integrated circuit chip 222 , the underfill 112 , and the chip pads 228 .
- the non-horizontal underfill sides 114 , the non-horizontal sides 230 , and the attachment side 210 are formed during the singulation process.
- FIG. 14 therein is shown a bottom view of a wafer frame used in manufacturing of the integrated circuit packaging system 100 of FIG. 2 in a third embodiment of the present invention.
- the wafer frame 1402 includes a horizontal cover 1404 with a connection side 1406 .
- a perimeter area formed by the horizontal cover 1404 can be less than a perimeter area formed by the semiconductor wafer 502 of FIG. 5 .
- the protect layer 214 of FIG. 2 can optionally be used to separate and isolate the horizontal cover 1404 from the second conductive posts 204 of FIG. 2 , from the third conductive posts 206 of FIG. 2 , and from the fourth conductive posts 208 of FIG. 2 .
- the horizontal cover 1404 formed from a material having a greater chemical etchant solubility than chemical etchant solubilities of the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 can omit the application of the protect layer 214 .
- the chemical etchant solubility is defined as the ability of an element to dissolve in the chemical etchant to form a homogeneous solution.
- the bottom view of the wafer frame 1402 is shown having connect sites 1408 .
- the connect sites 1408 are areas on the connection side 1406 used to identify specific portions of the horizontal cover 1404 within, above, and below the areas on the connection side 1406 .
- FIG. 15 therein is shown a cross-sectional view of FIG. 14 taken along a line 15 - 15 of FIG. 14 .
- the cross-sectional view taken along the line 15 - 15 is shown intersecting the first conductive posts 202 having the first post ends 102 .
- the second conductive posts 204 of FIG. 2 , the third conductive posts 206 of FIG. 2 , and the fourth conductive posts 208 of FIG. 3 are not shown.
- the cross-sectional view depicts the wafer frame 1402 having the horizontal cover 1404 with the connection side 1406 and a side 1502 opposite the connection side 1406 .
- Each of the connect sites 1408 can include protruding connectors 1504 projecting perpendicularly from the connection side 1406 .
- the protruding connectors 1504 can formed from a material identical to the material of the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 and integral to the connection side 1406 of the horizontal cover 1404 .
- the protruding connectors 1504 within each of the connect sites 1408 can have a connector pitch 1506 less than three hundred microns inclusive.
- the connector pitch 1506 is defined as the distance between centers at adjacent locations of the protruding connectors 1504 within each of the connect sites 1408 .
- the connector pitch 1506 of the protruding connectors 1504 within each of the connect sites 1408 can be identical.
- Attachment surfaces 1508 can be formed on an end of each of the protruding connectors 1504 opposite an end of the protruding connectors 1504 integral to the connection side 1406 .
- the attachment surfaces 1508 of the second post ends 104 , the third post ends 106 , and the fourth post ends 108 can be formed from a material similar to the material of the protruding connectors 1504 and parallel with the connection side 1406 .
- the protect layer 214 of FIG. 2 can cover the ends of the protruding connectors 1504 integral to the connection side 1406 and is between the protruding connectors 1504 and the connection side 1406 of the horizontal cover 1404 .
- the protect layer 214 (not shown) is within the horizontal cover.
- the protect layer 214 can be formed on or in the horizontal cover 1404 .
- the protect layer 214 could optionally be omitted if the material of the protruding connectors 1504 is a chemical insoluble material.
- the chemical insoluble material is defined as a material capable being exposed to the chemical etchant without any loss or change to the material.
- the protect layer 214 can be formed on or in the connection side 1406 of the horizontal cover 1404 .
- the connection side 1406 can be formed having indentations molded to shapes of the second post ends 104 and the third post ends 106 .
- the indentations in the connection side 1406 can be covered with the protect layer 214 and used to form the second conductive posts 204 and the third conductive posts 206 , respectively.
- the connection side 1406 can also protruded portions molded to a shape of the recess 218 of FIG. 2 and covered with the protect layer 214 to form the fourth conductive posts 208 .
- the protect layer 214 can be formed on the protruding connectors 1504 .
- the protruding connectors 1504 can be formed having an end shaped identically to the second post ends 104 , the third post ends 106 , and the fourth post ends 108 .
- the end shaped identically to the second post ends 104 , the third post ends 106 , and the fourth post ends 108 can be covered with the protect layer 214 , joined to the connection side 1406 of the horizontal cover 1040 with the attachment surfaces 1508 coplanar and facing away from the connection side 1406 .
- the protruding connectors 1504 can be used to form the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 , respectively.
- the protect layer 214 can be formed as a part of the protruding connectors 1504 .
- the protruding connectors 1504 can be formed having multiple layers of different material that can include a material identical to the material of the protect layer 214 .
- the material layered on the protruding connectors 1504 can be formed to be identical to the second post ends 104 , the third post ends 106 , and the fourth post ends 108 and used to form the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 from the protruding connectors 1504 , respectively.
- each of the protruding connectors 1504 used to form the second conductive posts 204 of FIG. 2 , the third conductive posts 206 of FIG. 2 , and the fourth conductive posts 208 of FIG. 2 are identical to the second conductive posts 204 , the third conductive posts 206 , and the fourth conductive posts 208 respectively.
- each of the protruding connectors 1504 having the protect layer 214 of FIG. 2 can be identical to dimensions of the second conductive posts 204 of FIG. 2 , the third conductive posts 206 of FIG. 2 , or the fourth conductive posts 208 of FIG. 2 with the protect layer 214 .
- Portions of the connection side 1406 integral to the second post ends 104 of FIG. 2 , the third post ends 106 of FIG. 2 , and the fourth post ends 108 of FIG. 2 can extend away from or retract in the connection side 1406 , thus enabling ends of all of the protruding connectors 1504 to be coplanar.
- the attachment surfaces 1508 can have a maximum body width 1510 one hundred fifty microns inclusive.
- the maximum body width 1510 is defined a largest of all possible distances measurable from any peripheral edge of one of the attachment surfaces 1508 to an edge of the one of the attachment surfaces 1508 opposite the peripheral edge.
- FIG. 16 therein is shown a top view of the structure of FIG. 14 on the structure of FIG. 5 in a mounting phase.
- the top view depicts the wafer frame 1402 of FIG. 14 mounted over the semiconductor wafer 502 having the semiconductor active side 504 exposed around a circumference of the wafer frame 1402 during a mounting process.
- the mounting process can include mechanized fixtures (not show) that can include automated computer monitoring, alignment, and positional equipment in a clean room environment.
- FIG. 17 therein is shown a cross-sectional view of FIG. 16 taken along a line 17 - 17 of FIG. 16 in an attaching phase.
- Each of the connect sites 1408 of FIG. 14 on the connection side 1406 of the horizontal cover 1404 are aligned over the chip sites 506 of FIG. 5 on the semiconductor active side 504 of the semiconductor wafer 502 .
- the chip pads 228 of the semiconductor wafer 502 are attached to the attachment surfaces 1508 of the protruding connectors 1504 using a conductive bonding material during an attaching process.
- the conductive bonding material can include a eutectic reaction layer with thermo-compression, ultra-sonic, thermo-sonic, thermo conductive applied energy.
- FIG. 18 therein is shown the structure of FIG. 17 in an underfill applying phase.
- the underfill 112 is applied between the horizontal cover 1404 and the semiconductor wafer 502 using a filling process that can include a combination of dispensing equipment (not shown) with contact heating, convective heating, or infrared heating.
- the underfill 112 surrounds the protruding connectors 1504 , surrounds the chip pads 228 , and covers the connection side 1406 and an area of the semiconductor active side 504 facing the connection side 1406 .
- a ring shaped area 1802 around the underfill 112 can expose the semiconductor active side 504 between the underfill 112 and a perimeter outline of the semiconductor wafer 502 .
- FIG. 19 therein is shown the structure of FIG. 18 in an etching phase.
- the horizontal cover 1404 of FIG. 18 is removed from above the chip sites 506 to expose the end of each of the protruding connectors 1504 of FIG. 18 opposite the end with the attachment surfaces 1508 using an etching process.
- the etching process can form the first post ends 102 , the second post ends 104 of FIG. 2 , the third post ends 106 of FIG. 2 , and the fourth post ends 108 of FIG. 2 from the protruding connectors 804 . Only the first post ends 102 are depicted in the figure. The first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 are exposed from the underfill 112 .
- the first post ends 102 are parallel to the semiconductor wafer 502 .
- the first post ends 102 , the second post ends 104 , the third post ends 106 , and the fourth post ends 108 are formed having the etch marks.
- Non-horizontal planar cuts through the semiconductor wafer 502 and the underfill 112 are used to separate the chip sites 506 of FIG. 19 from one another and the ring shaped area 1802 during a singulation process.
- the singulation process includes cutting, sawing, grinding, or any combination thereof.
- the integrated circuit package 2002 can be identical to the integrated circuit packaging system 100 of FIG. 2 and include the integrated circuit chip 222 , the first conductive posts 202 , the second conductive posts 204 of FIG. 2 , the third conductive posts 206 of FIG. 2 , and the fourth conductive posts 208 .
- the non-horizontal underfill sides 114 , the non-horizontal sides 230 , and the attachment side 210 are formed during the singulation process.
- the method 2100 includes: providing a semiconductor wafer having a chip pad in a block 2102 ; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad in a block 2104 ; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer in a block 2106 ; removing the horizontal cover exposing the underfill and the protruding connector in a block 2108 ; and singulating an integrated circuit package from the semiconductor wafer in a block 2110 .
- the resulting method, process, apparatus, device, product, and/or system is straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing package in package systems/fully compatible with conventional manufacturing methods or processes and technologies.
- Another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer.
Description
- The present invention relates generally to an integrated circuit packaging system, and more particularly to a system with interconnects.
- Products must be capable of competing in world markets and attracting many consumers or buyers. It is very important for products to continue to improve in features, performance, and reliability while reducing product costs, product size, and to be available quickly for purchase by the consumers or buyers.
- Market growth for high density and high output/input integrated circuit packages has resulted in a trend for electronic products that are lightweight, smaller in size, multi-functional, and capable of ever increasing higher speeds. Electronic products such as cell phone base products, global positioning systems (GPS), satellites, communication equipment, consumer products, and a vast line of other similar products are in ever increasing global demand.
- Smaller packages need to be electrically connected with other parts and components. As the smaller packages with more circuits continue to get shrink in size, there is a greater need to produce the smaller packages with more and more package connectors to support continually increasing amounts of electrical connections to and from those smaller packages.
- Thus, an increasing need remains to increase the electrical connections of packages as the sizes of the packages continue to shrink in size while the circuits inside those packages continue to increase. It is also critical that the electrical connections are created and placed with precision so that each of the electrical connections can be spaced apart from one another. Smaller packages must be able to connect to circuit boards and deliver increasing functionality, speed, and performance. In view of the economic and technological challenges, it is increasingly critical that answers be found to these problems.
- In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve reliability and product yields to meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
- Solutions to these problems have been long sought after but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
- The present invention provides a method of manufacture of an integrated circuit packaging system including: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer.
- The present invention provides an integrated circuit packaging system, including: an integrated circuit chip having a chip pad; a conductive post on the chip pad; and an underfill around the conductive post, the conductive post exposed from the underfill, and a non-horizontal underfill side of the underfill planar with a non-horizontal side of the integrated circuit chip.
- Certain embodiments of the invention have other steps or elements in addition to or in place of those mentioned above. The steps or elements will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
-
FIG. 1 is a bottom view of an integrated circuit packaging system in a first embodiment of the present invention. -
FIG. 2 is a cross-sectional view ofFIG. 1 taken along a line 2-2 ofFIG. 1 . -
FIG. 3 is a top view of an integrated circuit packaging system in a second embodiment of the present invention. -
FIG. 4 is a cross-sectional view ofFIG. 3 taken along a line 4-4 ofFIG. 3 . -
FIG. 5 is a top view of a semiconductor wafer used in manufacturing of the integrated circuit packaging system ofFIG. 2 . -
FIG. 6 is a cross-sectional view ofFIG. 5 taken along a line 6-6 ofFIG. 5 . -
FIG. 7 is a bottom view of a wafer frame used in manufacturing of the integrated circuit packaging system ofFIG. 2 . -
FIG. 8 is a cross-sectional view ofFIG. 7 taken along a line 8-8 ofFIG. 7 . -
FIG. 9 is a top view of the structure ofFIG. 7 on the structure ofFIG. 5 in a mounting phase. -
FIG. 10 is a cross-sectional view ofFIG. 9 taken along a line 10-10 ofFIG. 9 in an attaching phase. -
FIG. 11 is the structure ofFIG. 10 in an underfill applying phase. -
FIG. 12 is the structure ofFIG. 11 in a planarizing phase. -
FIG. 13 is the structure ofFIG. 12 in a singulation phase. -
FIG. 14 is a bottom view of a wafer frame used in manufacturing of the integrated circuit packaging system ofFIG. 2 in a third embodiment of the present invention. -
FIG. 15 is a cross-sectional view ofFIG. 14 taken along a line 15-15 ofFIG. 14 . -
FIG. 16 is a top view of the structure ofFIG. 14 on the structure ofFIG. 5 in a mounting phase. -
FIG. 17 is a cross-sectional view ofFIG. 16 taken along a line 17-17 ofFIG. 16 in an attaching phase. -
FIG. 18 is the structure ofFIG. 17 in an underfill applying phase. -
FIG. 19 is the structure ofFIG. 18 in an etching phase. -
FIG. 20 is the structure ofFIG. 19 in a singulation phase. -
FIG. 21 is a flow chart of a method of manufacture of the integrated circuit packaging system in a further embodiment of the present invention. - The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.
- In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail.
- The drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. Similarly, although the views in the drawings shown for ease of description and generally show similar orientations, this depiction in the FIGs. is arbitrary for the most part. Generally, the invention can be operated in any orientation.
- Where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with similar reference numerals. The embodiments have been numbered first embodiment, second embodiment, etc. as a matter of descriptive convenience and are not intended to have any other significance or provide limitations for the present invention.
- For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the present invention, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane, as shown in the figures.
- The term “on” means that there is direct contact between elements. The term “directly on” means that there is direct contact between one element and another element without an intervening element.
- The term “active side” refers to a side of a die, a module, a package, or an electronic structure having active circuitry fabricated thereon or having elements for connection to the active circuitry within the die, the module, the package, or the electronic structure. The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
- With a growing demand for flip chip packages, a critical need exists for producing high volume, reliable, and low cost flip chip packages. Embodiments of the present invention provides methods/solutions to meet the critical for the demand by providing methods to form interconnects and underfill on wafers during wafer level processing. The embodiments forthcoming describe methods that result in improved interconnect joint strengths, improved coplanar interconnects, underfill uniformity, and fine pitch interconnects for the flip chip packages.
- Referring now to
FIG. 1 , therein is shown a bottom view of an integratedcircuit packaging system 100 in a first embodiment of the present invention. The bottom view depicts first post ends 102, second post ends 104, third post ends 106, and fourth post ends 108 exposed from anunderfill 112 of the integratedcircuit packaging system 100. The integratedcircuit packaging system 100 can be a flip chip, as an example. - The integrated
circuit packaging system 100 can be formed having one of or any combination of the first post ends 102, the second post ends 104, the third post ends 106, or the fourth post ends 108 exposed in any position from theunderfill 112. The integratedcircuit packaging system 100 is shown having every row occupied with the first post ends 102 except the bottom row, as an example. The first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108 exposed from theunderfill 112 can provide electrical connectivity to circuitry within the integratedcircuit packaging system 100. - The
underfill 112 provides a hermetic seal protection around the first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108 and to the contents of the integratedcircuit packaging system 100. Theunderfill 112 also provides mechanical support and electrical isolation for the first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108. Theunderfill 112 can be formed from an etchant resistant electrically insulative material capable of providing structural rigidity and characteristics similar that of an epoxy, an encapsulant, or an anisotropic conductive film (ACF). - The
underfill 112 can be used to improve the thermal dissipation characteristics of the present invention. As an example, theunderfill 112 can be formed from a thermally conductive material to provide both improve thermal dissipation and the hermetic seal protection. Non-horizontal underfill sides 114 of theunderfill 112 enclose an area containing the first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108 forming an outline of a planar shape of the integratedcircuit packaging system 100. - For illustrative purposes, the first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108 are shown having a footprint shape of a circle. It is understood that the first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108 can have a different footprint shapes. For example, the first post ends 102 can have combination of footprint shapes that can include a rectangle, oval, or a multifaceted geometric shape.
- Referring now to
FIG. 2 , therein is shown a cross-sectional view ofFIG. 1 taken along a line 2-2 ofFIG. 1 . The cross-sectional view depicts firstconductive posts 202 having the first post ends 102, secondconductive posts 204 having the second post ends 104, thirdconductive posts 206 having the third post ends 106, and the fourthconductive posts 208 having the fourth post ends 108. - The first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108 are exposed from an
attachment side 210 of theunderfill 112. The first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108 can be formed from a metal that can include a copper metal, a conductive metal, a conductive metal alloy, or any combination thereof. - The first post ends 102 can be formed coplanar to the
attachment side 210 using a planarization process, an etching process, or a combination thereof. The planarization process results in the first post ends 102 having planarization marks and the etching process results in etch marks. - The planarization marks are defined as a physical appearance on a surface of an element that is a result of manufacturing processes that can include grinding, sanding, polishing, or any combination thereof. The planarization marks are accompanied by differences between a grain structure on the surface of the element and a grain structure below the surface of the element.
- The etch marks are defined as an etched physical appearance on a surface of an element that is the result of a chemical etchant. The chemical etchant is an acidic, alkali, or basic chemical used to dissolve unwanted materials such as metals, semiconductor materials, or glass from a reduction-oxidation (redox) reaction.
- The etched physical appearance are from changes in microstructure and macrostructure of the surface of the element as a result of the redox reactions introduced by the chemical etchant are observable using metallography techniques to observe characteristics that can include a surface crystal structure, surface reflective, surface refractive, and surface profile characteristics.
- The second
conductive posts 204 includes a raisedplatform 212 located centrally on the second post ends 104. The second post ends 104 can optionally include aprotect layer 214. - The
protect layer 214 can be formed from a conductive metal different from the metal of the first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108. Theprotect layer 214 can cover a portion of the secondconductive posts 204 over theattachment side 210 to prevent the portion of the secondconductive posts 204 from exposure to the chemical etchant. - The
protect layer 214 on the second post ends 104 includes etch marks as a result of the etching process. The second post ends 104 can be formed without theprotect layer 214 provided the second post ends 104 are formed from an etchant resistant conductive metal material. The second post ends 104 formed without theprotect layer 214 results in the second post ends 104 having the etch marks. - The third post ends 106 can project above the
attachment side 210 and include acavity 216 centrally located in the third post ends 106. Thecavity 216 is formed by surrounding sides and aninner post base 217 of the third post ends 106 that are coplanar with theattachment side 210. - The third post ends 106 can optionally include the
protect layer 214. Theprotect layer 214 can cover a portion of the thirdconductive posts 206 and thecavity 216 over theattachment side 210 to prevent the portion of the thirdconductive posts 206 from exposure to the chemical etchant. - The
protect layer 214 on the third post ends 106 includes etch marks as a result of the etching process. The third post ends 106 can be formed without theprotect layer 214 provided the third post ends 106 are formed from an etchant resistant conductive metal material. The third post ends 106 formed without theprotect layer 214 results in the third post ends 106 having the etch marks. - The fourth post ends 108 of the fourth
conductive posts 208 can be below theattachment side 210 and forms a bottom of arecess 218 of theunderfill 112. The fourth post ends 108 can optionally include theprotect layer 214 covering the fourthconductive posts 208. Theprotect layer 214 can cover a portion of the fourthconductive posts 208 to prevent the portion of the fourthconductive posts 208 from exposure to the chemical etchant. - The
protect layer 214 on the fourth post ends 108 includes etch marks as a result of the etching process. The fourth post ends 108 can be formed without theprotect layer 214 provided the fourth post ends 108 are formed from an etchant resistant conductive metal material. The fourth post ends 108 formed without theprotect layer 214 results in the fourth post ends 108 having the etch marks. - The
underfill 112 is attached to anintegrated circuit chip 222. Theintegrated circuit chip 222 is defined as an active device including a non-active side and anactive side 224 having circuitry fabricated thereon. A side of theunderfill 112 opposite theattachment side 210 is in direct contact with theactive side 224 of theintegrated circuit chip 222. - The
attachment side 210 can be parallel with theactive side 224.Chip pads 228 formed of conductive metal or metal alloys on theactive side 224. Thechip pads 228 are bond pads for theintegrated circuit chip 222. Thechip pads 228 are attached to ends of the firstconductive posts 202 opposite the first post ends 102, the secondconductive posts 204 opposite the second post ends 104, the thirdconductive posts 206 opposite the third post ends 106, and the fourthconductive posts 208 opposite the fourth post ends 108 using solder. Thechip pads 228 provide connectivity between circuitry of theintegrated circuit chip 222 and the firstconductive posts 202, the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208. - The first
conductive posts 202, the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208 are formed from a material that can include a copper metal, a conductive metal, a conductive metal alloy, or any combination thereof. The firstconductive posts 202, the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208 can be structured having multiple joined layers of different material having different physical characteristic properties. - The
underfill 112 surrounds, provides structural support, and hermetically seals theactive side 224, sides of thechip pads 228, and sides of the firstconductive posts 202, the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208.Non-horizontal sides 230 of theintegrated circuit chip 222 can be coplanar with the non-horizontal underfill sides 114. - The
attachment side 210 can also be formed using a planarization process, an etching process, or a combination thereof. Theattachment side 210 can exhibit characteristics of similar to the planarization marks and the etch marks of the first post ends 102. - It has been discovered that the present invention provides the integrated
circuit packaging system 100 with superior reliability over solder bumped packaging systems. Theunderfill 112 provides improved joint strength from lateral and tangential forces applied to the firstconductive posts 202, the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208 when integrating with a next level of integration (not shown) such as a printed circuit board or an integrated circuit packaging assembly. The improved joint strength is a result of theactive side 224, sides of thechip pads 228, and the firstconductive posts 202, the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208 held together by theunderfill 112. Unlike solder bumps, the first post ends 102 are formed to be coplanar with one another resulting in improved connectivity with the next level of integration. The combination of the improved joint strength and the improved connectivity results in the superior reliability of the integratedcircuit packaging system 100 over the solder bumped packaging systems. - It has also been discovered that the present invention provides the integrated
circuit packaging system 100 with increased interconnection density capabilities. Theunderfill 112 provides additional support enabling the firstconductive posts 202, the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208 to be thinner and closer together than solder bumps resulting in the increased interconnection density capabilities. - Referring now to
FIG. 3 , therein is shown a top view of an integratedcircuit packaging system 300 in a second embodiment of the present invention. The top view depicts anencapsulation 302 having a rectangular shape andpackage sides 304 formed around a periphery of the integratedcircuit packaging system 300. Theencapsulation 302 can optionally be omitted from the integratedcircuit packaging system 300. - The
encapsulation 302 can be formed form materials that can include an epoxy, a ceramic, a plastic, a molding compound, or any combination thereof. Theencapsulation 302 can be used to protect the integratedcircuit packaging system 300 by providing structural support, and hermetically sealing the contents of the integratedcircuit packaging system 300. - Referring now to
FIG. 4 , therein is shown a cross-sectional view ofFIG. 3 taken along a line 4-4 ofFIG. 3 . The integratedcircuit packaging system 300 can include the integratedcircuit packaging system 100, abase substrate 402, chip interconnects 404,discrete components 406, theencapsulation 302, andsystem connectors 408. - For purposes of illustration, the cross-sectional view taken along the line 4-4 is shown intersecting the first
conductive posts 202 having the first post ends 102. The secondconductive posts 204 ofFIG. 2 , the thirdconductive posts 206 ofFIG. 2 , and the fourthconductive posts 208 ofFIG. 3 are not shown or included here. - The
base substrate 402 can include a substrate, an interposer, a circuit board, or a laminate havingbase conductors 410 on aninner base side 412, on anouter base side 414 opposite theinner base side 412, and within thebase substrate 402. Thebase conductors 410 can be formed from a conductive material and provide connectivity between, on, and within theinner base side 412 and theouter base side 414. - The integrated
circuit packaging system 100 can be mounted over and connected to theinner base side 412 using the chip interconnects 404. The chip interconnects 404 attach the first post ends 102 with thebase conductors 410 and provide electrical connectivity between the first post ends 102 and thebase conductors 410 of thebase substrate 402. - The chip interconnects 404 can be formed of solder and include solder on pads, solder films, solder pastes, or any combination thereof. The chip interconnects 404 are oriented between the
attachment side 210 and theinner base side 412. - The
discrete components 406 can be mounted and connected to theinner base side 412 adjacent the integratedcircuit packaging system 100. Any one of thediscrete components 406 is defined to be either a transistor, a resistor, a capacitor, a diode, or an inductor. - The
encapsulation 302 can cover the integratedcircuit packaging system 100, thediscrete components 406, and theinner base side 412 to provide additional protection. The package sides 304 can be parallel to thenon-horizontal sides 230 and the non-horizontal underfill sides 114 of theunderfill 112. Theencapsulation 302 can be omitted and the integratedcircuit packaging system 300 can be protected by an enclosure (not shown) such as a cabinet, a room, a chamber, or embedded in a package subsystem. - The
system connectors 408 can be optionally attached to thebase conductors 410 on theouter base side 414. Thesystem connectors 408 can include bond wires, conductive balls, conductive bumps, conductive leads, or a combination thereof. - The
system connectors 408 can provide connectivity between the integratedcircuit packaging system 300 and the next level of integration. Thesystem connectors 408 can be omitted to enable other means of connectivity between the next level of integration and the integratedcircuit packaging system 300. - It has been discovered that the present invention provides the integrated
circuit packaging system 300 with a package profile height lower than a package profile height of solder bumped packaging systems. The first post ends 102 of the integratedcircuit packaging system 100 can be attached to theinner base side 412 of thebase substrate 402 using a thin solder film. A combination of the first post ends 102 coplanar with theattachment side 210 and the thin solder film results in the package profile height of the present invention to be lower than the package profile height of the solder bumped packaging systems. - Referring now to
FIG. 5 , therein is shown a top view of asemiconductor wafer 502 used in manufacturing of the integratedcircuit packaging system 100 ofFIG. 2 . The top view of thesemiconductor wafer 502 is shown having a shape of an ellipse. Thesemiconductor wafer 502 is defined as a thin slice of semiconductor material used as a substrate from which miniaturized electronic circuitry is built in and over a semiconductoractive side 504 of thesemiconductor wafer 502. -
Chip sites 506 are shown located on thesemiconductor wafer 502. Thechip sites 506 are areas of thesemiconductor wafer 502 having active circuitry along the semiconductoractive side 504. Each of thechip sites 506 can be used to form and build the miniaturized semiconductor circuitry of theintegrated circuit chip 222 ofFIG. 2 . For illustrative purposes, thesemiconductor wafer 502 is depicted with sixteen of thechip sites 506. Thesemiconductor wafer 502 can have any number of thechip sites 506. Thesemiconductor wafer 502 can have fifty-two of thechip sites 506, as an example. - Referring now to
FIG. 6 , therein is shown a cross-sectional view ofFIG. 5 taken along a line 6-6 ofFIG. 5 . The cross-sectional view shows a wafernon-active side 602 of thesemiconductor wafer 502 opposite the semiconductoractive side 504. - Each of the
chip sites 506 include thechip pads 228 exposed from the semiconductoractive side 504. Thechip pads 228 can provide connectivity to the miniaturized semiconductor circuitry within each of thechip sites 506. - The
chip pads 228 can include achip pad pitch 606 and a maximumwafer pad width 618. Thechip pad pitch 606 is defined as the distance between centers at adjacent locations of thechip pads 228 within each of thechip sites 506. Thechip pad pitch 606 of thechip pads 228 within each of thechip sites 506 can be identical. - The maximum
wafer pad width 618 is defined a largest of all possible distances measurable from any first peripheral edge of one of thechip pads 228 to a second peripheral edge of the one of thechip pads 228 opposite the first peripheral edge. - Referring now to
FIG. 7 , therein is shown a bottom view of awafer frame 702 used in manufacturing of the integratedcircuit packaging system 100 ofFIG. 2 . Thewafer frame 702 includes ahorizontal cover 704 with aconnection side 706. - A perimeter area formed by the
horizontal cover 704 can be less than a perimeter area formed by thesemiconductor wafer 502 ofFIG. 5 . Thehorizontal cover 704 is formed from a material that can be removed using processes that can include grinding, sanding, polishing, cutting, sawing, or any combination thereof. - The material used to form the
horizontal cover 704 can be a metal that includes copper, copper alloys, or any combination thereof. The bottom view of thewafer frame 702 is shown havingconnect sites 708. Theconnect sites 708 are areas on theconnection side 706. - Referring now to
FIG. 8 , therein is shown a cross-sectional view ofFIG. 7 taken along a line 8-8 ofFIG. 7 . The cross-sectional view depicts thewafer frame 702 having thehorizontal cover 704 with theconnection side 706 and anon-connection side 802 opposite theconnection side 706. - For illustrative purposes, the protruding
connectors 804 are shown perpendicular to theconnection side 706. The protrudingconnectors 804 can be oriented having any angle relative to theconnection side 706. The protrudingconnectors 804 can be oriented having an angle of ninety degrees with respect to theconnection side 706, as an example. - The protruding
connectors 804 can be formed from a material identical to the conductive metal of the firstconductive posts 202 ofFIG. 2 and integral to theconnection side 706. The protrudingconnectors 804 within each of theconnect sites 708 can have aconnector pitch 806 less than three hundred microns inclusive. - The
connector pitch 806 is defined as the distance between centers at adjacent locations of the protrudingconnectors 804 within each of theconnect sites 708. Theconnector pitch 806 of the protrudingconnectors 804 within each of theconnect sites 708 can be identical. - Attachment surfaces 808 can be formed on an end of each of the protruding
connectors 804 and can be facing away from theconnection side 706. The attachment surfaces 808 can be formed from a material similar to the material of the protrudingconnectors 804 and parallel with theconnection side 706. - The attachment surfaces 808 can have a
maximum body width 810 less than one hundred fifty microns inclusive. Themaximum body width 810 is defined a largest of all possible distances measurable from any peripheral edge of one of the attachment surfaces 808 to an edge of the one of the attachment surfaces 808 opposite the peripheral edge. - Referring now to
FIG. 9 , therein is shown a top view of the structure ofFIG. 7 on the structure ofFIG. 5 in a mounting phase. The top view depicts thewafer frame 702 ofFIG. 7 mounted over thesemiconductor wafer 502 having the semiconductoractive side 504 exposed around a circumference of thewafer frame 702 during a mounting process. The mounting process can include mechanized fixtures (not show) that can include automated computer monitoring, alignment, and positional equipment in a clean room environment. - Referring now to
FIG. 10 , therein is shown a cross-sectional view ofFIG. 9 taken along a line 10-10 ofFIG. 9 in an attaching phase. Each of theconnect sites 708 ofFIG. 7 on theconnection side 706 of thehorizontal cover 704 are aligned over thechip sites 506 ofFIG. 5 on the semiconductoractive side 504 of thesemiconductor wafer 502. - The
chip pads 228 of thesemiconductor wafer 502 are attached to the attachment surfaces 808 of the protrudingconnectors 804 using a conductive bonding material during an attaching process. The conductive bonding material can include a eutectic reaction layer with thermo-compression, ultra-sonic, thermo-sonic, thermo conductive applied energy. - Referring now to
FIG. 11 , therein is shown the structure ofFIG. 10 in an underfill applying phase. Theunderfill 112 is applied between thehorizontal cover 704 and thesemiconductor wafer 502 using a filling process that can include a combination of dispensing equipment (not shown) with contact heating, convective heating, or infrared heating. - The
underfill 112 surrounds the protrudingconnectors 804, surrounds thechip pads 228, and covers theconnection side 706 and the semiconductoractive side 504. A ring shapedarea 1102 around theunderfill 112 can expose the semiconductoractive side 504 between theunderfill 112 and a perimeter outline of thesemiconductor wafer 502. - It has been discovered that the present invention provides the integrated
circuit packaging system 100 with improved reliability. Theunderfill 112 is applied during wafer processing phases of manufacturing which involves a highly specialized facility than includes cleanrooms, filtered laminated air flow, controlled temperature and humidity, and specialized equipment operating with extreme precision from the front end of the line (FEOL) through the back end of the line (BEOL). Theunderfill 112 having a uniform distribution covers theconnection side 706, the semiconductoractive side 504, thechip pads 228, the protrudingconnectors 804, and attachment areas between the attachment surfaces 808 and the protrudingconnectors 804. The uniform distribution is defined a material having the same densities, composition, and characteristics throughout the material. The uniform distribution of theunderfill 112 provides results in improved reliability of the structure and circuitry of the integratedcircuit packaging system 100. - Referring now to
FIG. 12 , therein is shown the structure ofFIG. 11 in a planarizing phase. Thehorizontal cover 704 ofFIG. 11 is removed from above thechip sites 506 to expose the end of each of the protrudingconnectors 804 ofFIG. 11 opposite the end with the attachment surfaces 808 using a planarization process. - The planarization process can include grinding, sanding, polishing, cutting, sawing, or any combination thereof of the
horizontal cover 704 to expose the protrudingconnectors 804 and theunderfill 112. The planarization of the protrudingconnectors 804 results in formation of the firstconductive posts 202 with the first post ends 102. The first post ends 102 are exposed from theunderfill 112 and parallel to thesemiconductor wafer 502. The first post ends 102 are formed having the planarization marks. - Referring now to
FIG. 13 , therein is shown the structure ofFIG. 12 in a singulation phase. Non-horizontal planar cuts through thesemiconductor wafer 502 and theunderfill 112 are used to separate thechip sites 506 ofFIG. 12 from one another and the ring shapedarea 1102 during a singulation process. The singulation process includes cutting, sawing, grinding, or any combination thereof. - Each of the
chip sites 506 isolated from the structure ofFIG. 12 results in the formation of the integratedcircuit packaging system 1302. The integratedcircuit packaging system 1302 is similar to the integratedcircuit packaging system 100 ofFIG. 2 except the integratedcircuit packaging system 1302 has only the firstconductive posts 202 with the first post ends 102 and includes the integratedcircuit chip 222, theunderfill 112, and thechip pads 228. The non-horizontal underfill sides 114, thenon-horizontal sides 230, and theattachment side 210 are formed during the singulation process. - Referring now to
FIG. 14 , therein is shown a bottom view of a wafer frame used in manufacturing of the integratedcircuit packaging system 100 ofFIG. 2 in a third embodiment of the present invention. Thewafer frame 1402 includes ahorizontal cover 1404 with aconnection side 1406. - A perimeter area formed by the
horizontal cover 1404 can be less than a perimeter area formed by thesemiconductor wafer 502 ofFIG. 5 . Theprotect layer 214 ofFIG. 2 can optionally be used to separate and isolate thehorizontal cover 1404 from the secondconductive posts 204 ofFIG. 2 , from the thirdconductive posts 206 ofFIG. 2 , and from the fourthconductive posts 208 ofFIG. 2 . - The
horizontal cover 1404 formed from a material having a greater chemical etchant solubility than chemical etchant solubilities of the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208 can omit the application of theprotect layer 214. The chemical etchant solubility is defined as the ability of an element to dissolve in the chemical etchant to form a homogeneous solution. - The bottom view of the
wafer frame 1402 is shown havingconnect sites 1408. Theconnect sites 1408 are areas on theconnection side 1406 used to identify specific portions of thehorizontal cover 1404 within, above, and below the areas on theconnection side 1406. - Referring now to
FIG. 15 , therein is shown a cross-sectional view ofFIG. 14 taken along a line 15-15 ofFIG. 14 . For purposes of illustration, the cross-sectional view taken along the line 15-15 is shown intersecting the firstconductive posts 202 having the first post ends 102. The secondconductive posts 204 ofFIG. 2 , the thirdconductive posts 206 ofFIG. 2 , and the fourthconductive posts 208 ofFIG. 3 are not shown. The cross-sectional view depicts thewafer frame 1402 having thehorizontal cover 1404 with theconnection side 1406 and aside 1502 opposite theconnection side 1406. - Each of the
connect sites 1408 can include protrudingconnectors 1504 projecting perpendicularly from theconnection side 1406. The protrudingconnectors 1504 can formed from a material identical to the material of the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208 and integral to theconnection side 1406 of thehorizontal cover 1404. - The protruding
connectors 1504 within each of theconnect sites 1408 can have aconnector pitch 1506 less than three hundred microns inclusive. Theconnector pitch 1506 is defined as the distance between centers at adjacent locations of the protrudingconnectors 1504 within each of theconnect sites 1408. Theconnector pitch 1506 of the protrudingconnectors 1504 within each of theconnect sites 1408 can be identical. -
Attachment surfaces 1508 can be formed on an end of each of the protrudingconnectors 1504 opposite an end of the protrudingconnectors 1504 integral to theconnection side 1406. The attachment surfaces 1508 of the second post ends 104, the third post ends 106, and the fourth post ends 108 can be formed from a material similar to the material of the protrudingconnectors 1504 and parallel with theconnection side 1406. - The
protect layer 214 ofFIG. 2 can cover the ends of the protrudingconnectors 1504 integral to theconnection side 1406 and is between the protrudingconnectors 1504 and theconnection side 1406 of thehorizontal cover 1404. In this embodiment, the protect layer 214 (not shown) is within the horizontal cover. Theprotect layer 214 can be formed on or in thehorizontal cover 1404. - For example, the
protect layer 214 could optionally be omitted if the material of the protrudingconnectors 1504 is a chemical insoluble material. The chemical insoluble material is defined as a material capable being exposed to the chemical etchant without any loss or change to the material. - The
protect layer 214 can be formed on or in theconnection side 1406 of thehorizontal cover 1404. Theconnection side 1406 can be formed having indentations molded to shapes of the second post ends 104 and the third post ends 106. The indentations in theconnection side 1406 can be covered with theprotect layer 214 and used to form the secondconductive posts 204 and the thirdconductive posts 206, respectively. Theconnection side 1406 can also protruded portions molded to a shape of therecess 218 ofFIG. 2 and covered with theprotect layer 214 to form the fourthconductive posts 208. - In a further example, the
protect layer 214 can be formed on the protrudingconnectors 1504. The protrudingconnectors 1504 can be formed having an end shaped identically to the second post ends 104, the third post ends 106, and the fourth post ends 108. The end shaped identically to the second post ends 104, the third post ends 106, and the fourth post ends 108 can be covered with theprotect layer 214, joined to theconnection side 1406 of the horizontal cover 1040 with the attachment surfaces 1508 coplanar and facing away from theconnection side 1406. The protrudingconnectors 1504 can be used to form the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208, respectively. - In yet a further example, the
protect layer 214 can be formed as a part of the protrudingconnectors 1504. The protrudingconnectors 1504 can be formed having multiple layers of different material that can include a material identical to the material of theprotect layer 214. The material layered on the protrudingconnectors 1504 can be formed to be identical to the second post ends 104, the third post ends 106, and the fourth post ends 108 and used to form the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208 from the protrudingconnectors 1504, respectively. - The dimensions of each of the protruding
connectors 1504 used to form the secondconductive posts 204 ofFIG. 2 , the thirdconductive posts 206 ofFIG. 2 , and the fourthconductive posts 208 ofFIG. 2 are identical to the secondconductive posts 204, the thirdconductive posts 206, and the fourthconductive posts 208 respectively. - The dimensions of each of the protruding
connectors 1504 having theprotect layer 214 ofFIG. 2 can be identical to dimensions of the secondconductive posts 204 ofFIG. 2 , the thirdconductive posts 206 ofFIG. 2 , or the fourthconductive posts 208 ofFIG. 2 with theprotect layer 214. Portions of theconnection side 1406 integral to the second post ends 104 ofFIG. 2 , the third post ends 106 ofFIG. 2 , and the fourth post ends 108 ofFIG. 2 can extend away from or retract in theconnection side 1406, thus enabling ends of all of the protrudingconnectors 1504 to be coplanar. - The attachment surfaces 1508 can have a
maximum body width 1510 one hundred fifty microns inclusive. Themaximum body width 1510 is defined a largest of all possible distances measurable from any peripheral edge of one of the attachment surfaces 1508 to an edge of the one of the attachment surfaces 1508 opposite the peripheral edge. - Referring now to
FIG. 16 , therein is shown a top view of the structure ofFIG. 14 on the structure ofFIG. 5 in a mounting phase. The top view depicts thewafer frame 1402 ofFIG. 14 mounted over thesemiconductor wafer 502 having the semiconductoractive side 504 exposed around a circumference of thewafer frame 1402 during a mounting process. The mounting process can include mechanized fixtures (not show) that can include automated computer monitoring, alignment, and positional equipment in a clean room environment. - Referring now to
FIG. 17 , therein is shown a cross-sectional view ofFIG. 16 taken along a line 17-17 ofFIG. 16 in an attaching phase. Each of theconnect sites 1408 ofFIG. 14 on theconnection side 1406 of thehorizontal cover 1404 are aligned over thechip sites 506 ofFIG. 5 on the semiconductoractive side 504 of thesemiconductor wafer 502. - The
chip pads 228 of thesemiconductor wafer 502 are attached to the attachment surfaces 1508 of the protrudingconnectors 1504 using a conductive bonding material during an attaching process. The conductive bonding material can include a eutectic reaction layer with thermo-compression, ultra-sonic, thermo-sonic, thermo conductive applied energy. - Referring now to
FIG. 18 , therein is shown the structure ofFIG. 17 in an underfill applying phase. Theunderfill 112 is applied between thehorizontal cover 1404 and thesemiconductor wafer 502 using a filling process that can include a combination of dispensing equipment (not shown) with contact heating, convective heating, or infrared heating. - The
underfill 112 surrounds the protrudingconnectors 1504, surrounds thechip pads 228, and covers theconnection side 1406 and an area of the semiconductoractive side 504 facing theconnection side 1406. A ring shapedarea 1802 around theunderfill 112 can expose the semiconductoractive side 504 between theunderfill 112 and a perimeter outline of thesemiconductor wafer 502. - Referring now to
FIG. 19 , therein is shown the structure ofFIG. 18 in an etching phase. Thehorizontal cover 1404 ofFIG. 18 is removed from above thechip sites 506 to expose the end of each of the protrudingconnectors 1504 ofFIG. 18 opposite the end with the attachment surfaces 1508 using an etching process. - The etching process can form the first post ends 102, the second post ends 104 of
FIG. 2 , the third post ends 106 ofFIG. 2 , and the fourth post ends 108 ofFIG. 2 from the protrudingconnectors 804. Only the first post ends 102 are depicted in the figure. The first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108 are exposed from theunderfill 112. - The first post ends 102 are parallel to the
semiconductor wafer 502. The first post ends 102, the second post ends 104, the third post ends 106, and the fourth post ends 108 are formed having the etch marks. - Referring now to
FIG. 20 , therein is shown the structure ofFIG. 19 in a singulation phase. Non-horizontal planar cuts through thesemiconductor wafer 502 and theunderfill 112 are used to separate thechip sites 506 ofFIG. 19 from one another and the ring shapedarea 1802 during a singulation process. The singulation process includes cutting, sawing, grinding, or any combination thereof. - Each of the
chip sites 506 isolated from the structure ofFIG. 19 results in the formation of anintegrated circuit package 2002. Theintegrated circuit package 2002 can be identical to the integratedcircuit packaging system 100 ofFIG. 2 and include theintegrated circuit chip 222, the firstconductive posts 202, the secondconductive posts 204 ofFIG. 2 , the thirdconductive posts 206 ofFIG. 2 , and the fourthconductive posts 208. Theunderfill 112, and thechip pads 228. The non-horizontal underfill sides 114, thenon-horizontal sides 230, and theattachment side 210 are formed during the singulation process. - Referring now to
FIG. 21 , therein is shown is a flow chart of amethod 2100 of manufacture of the integratedcircuit packaging system 100 in a further embodiment of the present invention. Themethod 2100 includes: providing a semiconductor wafer having a chip pad in ablock 2102; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad in ablock 2104; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer in ablock 2106; removing the horizontal cover exposing the underfill and the protruding connector in ablock 2108; and singulating an integrated circuit package from the semiconductor wafer in ablock 2110. - The resulting method, process, apparatus, device, product, and/or system is straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing package in package systems/fully compatible with conventional manufacturing methods or processes and technologies.
- Another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
- These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.
- While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Claims (20)
1. A method of manufacture of an integrated circuit packaging system comprising:
providing a semiconductor wafer having a chip pad;
attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad;
forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer;
removing the horizontal cover exposing the underfill and the protruding connector; and
singulating an integrated circuit package from the semiconductor wafer.
2. The method as claimed in claim 1 wherein removing the horizontal cover includes planarizing the horizontal cover to expose the protruding connector having planarization marks.
3. The method as claimed in claim 1 wherein removing the horizontal cover includes etching the horizontal cover to expose the protruding connector having etch marks.
4. The method as claimed in claim 1 wherein attaching the wafer frame having the horizontal cover integral to the protruding connector includes attaching the wafer frame having a protect layer between the horizontal cover and the protruding connector.
5. The method as claimed in claim 1 wherein:
attaching the wafer frame having the horizontal cover integral to the protruding connector includes attaching the wafer frame having a protect layer between the horizontal cover and the protruding connector; and
removing the horizontal cover includes exposing the protect layer.
6. A method of manufacture of an integrated circuit packaging system comprising:
providing a semiconductor wafer having a chip pad;
attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad;
applying an underfill around the protruding connector, around the chip pad, and between the horizontal cover and the semiconductor wafer;
removing the horizontal cover exposing the underfill and the protruding connector; and
singulating an integrated circuit package from the semiconductor wafer.
7. The method as claimed in claim 6 wherein:
attaching the wafer frame having the horizontal cover integral to the protruding connector includes attaching the wafer frame having a protect layer between the horizontal cover and the protruding connector, the protect layer partially within the horizontal cover; and
removing the horizontal cover exposing the protruding connector.
8. The method as claimed in claim 6 wherein removing the horizontal cover includes planarizing the horizontal cover to expose the underfill having planarization marks.
9. The method as claimed in claim 6 wherein removing the horizontal cover exposing the underfill includes planarizing the horizontal cover to expose the underfill and the protruding connector having planarization marks.
10. The method as claimed in claim 6 wherein removing the horizontal cover includes removing the horizontal cover exposing the underfill coplanar with the protruding connector.
11. An integrated circuit packaging system comprising:
an integrated circuit chip having a chip pad;
a conductive post on the chip pad; and
an underfill around the conductive post, the conductive post exposed from the underfill, and a non-horizontal underfill side of the underfill planar with a non-horizontal side of the integrated circuit chip.
12. The system as claimed in claim 11 wherein the conductive post includes the conductive post having a post end with planarization marks exposed from the underfill.
13. The system as claimed in claim 11 wherein the conductive post includes the conductive post having a post end with etch marks exposed from the underfill.
14. The system as claimed in claim 11 wherein:
the conductive post includes a post end; and
the underfill includes an attachment side planar with the post end, the post end and the attachment side exposed having planarization marks.
15. The system as claimed in claim 11 wherein the underfill around the conductive post includes the conductive post having a protect layer exposed from the underfill.
16. The system as claimed in claim 11 wherein the underfill includes the underfill around the chip pad.
17. The system as claimed in claim 16 wherein:
the underfill includes an attachment side; and
further comprising:
a protect layer on the conductive post exposed above the attachment side.
18. The system as claimed in claim 16 wherein:
the underfill includes an attachment side; and
the conductive post includes a post end exposed below the attachment side.
19. The system as claimed in claim 16 wherein:
the underfill includes an attachment side;
the conductive post includes a post end of the conductive post exposed from the attachment side; and
further comprising:
a substrate attached to the post end.
20. The system as claimed in claim 16 wherein the underfill includes an attachment side of the underfill having etch marks.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/791,865 US20110291264A1 (en) | 2010-06-01 | 2010-06-01 | Integrated circuit packaging system with posts and method of manufacture thereof |
US13/966,259 US9082887B1 (en) | 2010-06-01 | 2013-08-13 | Integrated circuit packaging system with posts and method of manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/791,865 US20110291264A1 (en) | 2010-06-01 | 2010-06-01 | Integrated circuit packaging system with posts and method of manufacture thereof |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/966,259 Continuation US9082887B1 (en) | 2010-06-01 | 2013-08-13 | Integrated circuit packaging system with posts and method of manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20110291264A1 true US20110291264A1 (en) | 2011-12-01 |
Family
ID=45021408
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/791,865 Abandoned US20110291264A1 (en) | 2010-06-01 | 2010-06-01 | Integrated circuit packaging system with posts and method of manufacture thereof |
US13/966,259 Active US9082887B1 (en) | 2010-06-01 | 2013-08-13 | Integrated circuit packaging system with posts and method of manufacture thereof |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/966,259 Active US9082887B1 (en) | 2010-06-01 | 2013-08-13 | Integrated circuit packaging system with posts and method of manufacture thereof |
Country Status (1)
Country | Link |
---|---|
US (2) | US20110291264A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9443799B2 (en) * | 2014-12-16 | 2016-09-13 | International Business Machines Corporation | Interposer with lattice construction and embedded conductive metal structures |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5380679A (en) * | 1992-10-02 | 1995-01-10 | Nec Corporation | Process for forming a multilayer wiring conductor structure in semiconductor device |
US5473197A (en) * | 1993-05-28 | 1995-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having bump electrodes with a trapezoidal cross-section along one axis |
US6107164A (en) * | 1998-08-18 | 2000-08-22 | Oki Electric Industry Co., Ltd. | Using grooves as alignment marks when dicing an encapsulated semiconductor wafer |
US6208032B1 (en) * | 1998-06-23 | 2001-03-27 | Kabushiki Kaisha Toshiba | Semiconductor device and fabrication method thereof |
US20010038151A1 (en) * | 2000-03-09 | 2001-11-08 | Yoshikazu Takahashi | Semiconductor device and the method for manufacturing the same |
US20010040289A1 (en) * | 2000-04-19 | 2001-11-15 | Kaname Kobayashi | Semiconductor device and the method for manufacturing the same |
US20030062623A1 (en) * | 1997-01-20 | 2003-04-03 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method and testing method of the same |
US20030080422A1 (en) * | 2001-10-25 | 2003-05-01 | Seiko Epson Corporation | Semiconductor wafer, method of manufacturing semiconductor wafer having bumps, semiconductor chip having bumps and method of manufacturing the same, semiconductor device, circuit board, and electronic equipment |
US20080023805A1 (en) * | 2006-07-26 | 2008-01-31 | Texas Instruments Incorporated | Array-Processed Stacked Semiconductor Packages |
US20080217792A1 (en) * | 2007-03-07 | 2008-09-11 | Spansion Llc | Semiconductor device and method of manufacturing the same |
US20110037145A1 (en) * | 2009-08-17 | 2011-02-17 | Seung Seoup Lee | Wafer level package having cylindrical capacitor and method of fabricating the same |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3798620B2 (en) | 2000-12-04 | 2006-07-19 | 富士通株式会社 | Manufacturing method of semiconductor device |
TWI277160B (en) | 2002-02-25 | 2007-03-21 | Advanced Semiconductor Eng | Bumping process |
US7345361B2 (en) | 2003-12-04 | 2008-03-18 | Intel Corporation | Stackable integrated circuit packaging |
TWI234211B (en) | 2003-12-26 | 2005-06-11 | Advanced Semiconductor Eng | Method for forming an underfilling layer on a bumped wafer |
US6890795B1 (en) | 2003-12-30 | 2005-05-10 | Agency For Science, Technology And Research | Wafer level super stretch solder |
TW200711154A (en) | 2005-09-08 | 2007-03-16 | Advanced Semiconductor Eng | Flip-chip packaging process |
TWI335070B (en) | 2007-03-23 | 2010-12-21 | Advanced Semiconductor Eng | Semiconductor package and the method of making the same |
US7888184B2 (en) | 2008-06-20 | 2011-02-15 | Stats Chippac Ltd. | Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof |
US20100244212A1 (en) | 2009-03-27 | 2010-09-30 | Jong-Woo Ha | Integrated circuit packaging system with post type interconnector and method of manufacture thereof |
US8169058B2 (en) * | 2009-08-21 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
US8390108B2 (en) | 2009-12-16 | 2013-03-05 | Stats Chippac Ltd. | Integrated circuit packaging system with stacking interconnect and method of manufacture thereof |
-
2010
- 2010-06-01 US US12/791,865 patent/US20110291264A1/en not_active Abandoned
-
2013
- 2013-08-13 US US13/966,259 patent/US9082887B1/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5380679A (en) * | 1992-10-02 | 1995-01-10 | Nec Corporation | Process for forming a multilayer wiring conductor structure in semiconductor device |
US5473197A (en) * | 1993-05-28 | 1995-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having bump electrodes with a trapezoidal cross-section along one axis |
US20030062623A1 (en) * | 1997-01-20 | 2003-04-03 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method and testing method of the same |
US6208032B1 (en) * | 1998-06-23 | 2001-03-27 | Kabushiki Kaisha Toshiba | Semiconductor device and fabrication method thereof |
US6107164A (en) * | 1998-08-18 | 2000-08-22 | Oki Electric Industry Co., Ltd. | Using grooves as alignment marks when dicing an encapsulated semiconductor wafer |
US20010038151A1 (en) * | 2000-03-09 | 2001-11-08 | Yoshikazu Takahashi | Semiconductor device and the method for manufacturing the same |
US20010040289A1 (en) * | 2000-04-19 | 2001-11-15 | Kaname Kobayashi | Semiconductor device and the method for manufacturing the same |
US20030080422A1 (en) * | 2001-10-25 | 2003-05-01 | Seiko Epson Corporation | Semiconductor wafer, method of manufacturing semiconductor wafer having bumps, semiconductor chip having bumps and method of manufacturing the same, semiconductor device, circuit board, and electronic equipment |
US20080023805A1 (en) * | 2006-07-26 | 2008-01-31 | Texas Instruments Incorporated | Array-Processed Stacked Semiconductor Packages |
US20080217792A1 (en) * | 2007-03-07 | 2008-09-11 | Spansion Llc | Semiconductor device and method of manufacturing the same |
US20110037145A1 (en) * | 2009-08-17 | 2011-02-17 | Seung Seoup Lee | Wafer level package having cylindrical capacitor and method of fabricating the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9443799B2 (en) * | 2014-12-16 | 2016-09-13 | International Business Machines Corporation | Interposer with lattice construction and embedded conductive metal structures |
US9673064B2 (en) | 2014-12-16 | 2017-06-06 | International Business Machines Corporation | Interposer with lattice construction and embedded conductive metal structures |
US10460956B2 (en) | 2014-12-16 | 2019-10-29 | International Business Machines Corporation | Interposer with lattice construction and embedded conductive metal structures |
Also Published As
Publication number | Publication date |
---|---|
US9082887B1 (en) | 2015-07-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7968373B2 (en) | Integrated circuit package on package system | |
US8314486B2 (en) | Integrated circuit packaging system with shield and method of manufacture thereof | |
US8466567B2 (en) | Integrated circuit packaging system with stack interconnect and method of manufacture thereof | |
US8723309B2 (en) | Integrated circuit packaging system with through silicon via and method of manufacture thereof | |
US8106499B2 (en) | Integrated circuit packaging system with a dual substrate package and method of manufacture thereof | |
US7927917B2 (en) | Integrated circuit packaging system with inward and outward interconnects and method of manufacture thereof | |
KR20100108296A (en) | Integrated circuit packaging system with package stacking and method of manufacture thereof | |
KR20080112968A (en) | Integrated circuit package system employing device stacking | |
US20120326324A1 (en) | Integrated circuit packaging system with package stacking and method of manufacture thereof | |
US20110062602A1 (en) | Integrated circuit packaging system with fan-in package and method of manufacture thereof | |
US9530753B2 (en) | Integrated circuit packaging system with chip stacking and method of manufacture thereof | |
US8518752B2 (en) | Integrated circuit packaging system with stackable package and method of manufacture thereof | |
US20120205811A1 (en) | Integrated circuit packaging system with terminal locks and method of manufacture thereof | |
US9312194B2 (en) | Integrated circuit packaging system with terminals and method of manufacture thereof | |
TWI445102B (en) | Integrated circuit package system with package integration | |
US8629567B2 (en) | Integrated circuit packaging system with contacts and method of manufacture thereof | |
US8012867B2 (en) | Wafer level chip scale package system | |
US8368199B2 (en) | Integrated circuit package system for stackable devices and method for manufacturing thereof | |
US8460968B2 (en) | Integrated circuit packaging system with post and method of manufacture thereof | |
US8658470B2 (en) | Integrated circuit packaging system with formed interconnects and method of manufacture thereof | |
US8426955B2 (en) | Integrated circuit packaging system with a stack package and method of manufacture thereof | |
US7911040B2 (en) | Integrated circuit package with improved connections | |
US20130328220A1 (en) | Integrated circuit packaging system with film assist and method of manufacture thereof | |
US9082887B1 (en) | Integrated circuit packaging system with posts and method of manufacture thereof | |
US20110233748A1 (en) | Integrated circuit packaging system with interconnect and method of manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: STATS CHIPPAC LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOI, DAESIK;LEE, TAEWOO;LEE, KYUWON;AND OTHERS;REEL/FRAME:024540/0812 Effective date: 20100601 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |