US20110297957A1 - Compound seminconductor structure - Google Patents

Compound seminconductor structure Download PDF

Info

Publication number
US20110297957A1
US20110297957A1 US13/209,882 US201113209882A US2011297957A1 US 20110297957 A1 US20110297957 A1 US 20110297957A1 US 201113209882 A US201113209882 A US 201113209882A US 2011297957 A1 US2011297957 A1 US 2011297957A1
Authority
US
United States
Prior art keywords
layer
ωcm
type
whose
resistivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/209,882
Inventor
Toshihide Kikkawa
Kenji Imanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to US13/209,882 priority Critical patent/US20110297957A1/en
Publication of US20110297957A1 publication Critical patent/US20110297957A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02425Conductive materials, e.g. metallic silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds

Definitions

  • the present invention relates to a compound semiconductor structure and its manufacture method, and more particularly to a GaN series compound semiconductor structure using a conductive SiC substrate and its manufacture method.
  • GaN series compound semiconductor is represented by Al x In y Ga 1-x-y N (0 ⁇ x ⁇ 1.0, 0 ⁇ y ⁇ 1.0).
  • GaN has a wide band gap of 3.4 eV and can operate at high voltages.
  • Various semiconductor devices can be manufactured by forming a hetero junction using GaN series compound semiconductor.
  • Metal organic chemical vapor deposition (MOCVD) is mainly used as a crystal growth method.
  • GaN has a high breakdown voltage, and is expected to be applied to usage requiring high voltage and high speed operation such as a high electron mobility transistor (HEMT) used at a base station of mobile phones.
  • HEMT high electron mobility transistor
  • a variety of GaN-HEMTs have been reported which use as an electron transport layer a GaN layer of GaN/AlGaN crystals grown on a substrate such as sapphire, SiC, GaN and Si.
  • JP-A-2002-352956 proposes a GaN series HEMT having a high on-breakdown voltage and improved I-V characteristics, which is manufactured for example by laminating on a c-plane sapphire substrate an i-type GaN electron transport layer, an i-type AlGaN spacer layer, an Si-doped n-type AlGaN electron supply layer and an Si-doped n-type GaN protective layer by MOCVD, depositing an SiN layer by CVD, forming openings through the SiN layer, and forming source/drain ohmic electrodes and a gate Schottky electrode.
  • JP-A-2004-221325 proposes a HEMT which is manufactured by laminating on an SiC substrate an i-type GaN electron transport layer, an i-type AlGaN spacer layer, an Si-doped n-type AlGaN electron supply layer and an Si-doped n-type GaN cap layer, forming source/drain ohmic electrodes, thereafter depositing a first SiN protective film by CVD, forming an opening through the first SiN protective film, and forming a gate Schottky electrode, and further forming a second SiN protective film.
  • This structure can suppress current collapse, i.e., a change in an on-resistance during operation.
  • a breakdown voltage in current-off state in excess of 300 V is presently reported. Best output characteristics are obtained by a GaN-HEMT using an SiC substrate. A high thermal conductivity of SiC contributes to this performance. When a high speed operation GaN device is to be manufactured, a semi-insulating SiC substrate is used in order to restrict parasitic capacitance.
  • a compound semiconductor structure comprising:
  • a method for manufacturing a compound semiconductor structure comprising:
  • FIG. 1A is a cross sectional view showing the structure of a GaN-HEMT using a conductive SiC substrate according to an embodiment
  • FIG. 1B is a table showing the characteristics of a conductive SiC substrate
  • FIGS. 2A and 2B are schematic cross sectional views of a hydride VPE system and an MOCVD system, respectively;
  • FIG. 3 is a graph showing a power density at each run when conductive SiC substrates selected without a selection criterion are used and when conductive SiC substrates selected in accordance with a selection criterion are used;
  • FIGS. 4A , 4 B and 4 C show a table showing resistivities of green conductive SiC substrates, a graph showing absorption coefficients dependent upon resistivities, and a graph showing a relation between a resistivity and a surface temperature during crystal growth, respectively;
  • FIGS. 5A and 5B are graphs showing a trap concentration and a sheet resistivity of a grown layer dependent upon a resistivity of a conductive SiC substrate;
  • FIGS. 6A , 6 B and 6 C are graphs showing I-V characteristics of GaN-HEMTs formed on conductive SiC substrates and on a semi-insulating SiC substrate;
  • FIG. 7 is a graph showing regions of resistivity as the selection criterion for conductive SiC substrates derived from power density of HEMTs.
  • a semi-insulating SiC substrate is very expensive, presenting a possibility that this high cost may hinder prevail of GaN-HEMTs.
  • a conductive SiC substrate is available less expensively than a semi-insulating SiC substrate. If GaN series compound semiconductor devices having good characteristics can be manufactured using conductive SiC substrates, this contributes to prevail of GaN-HEMTs.
  • a conductive SiC substrate If a conductive SiC substrate is used, a GaN series compound semiconductor device having a high thermal conductivity of SiC can be manufactured less expensively. However, using a conductive substrate increases parasitic capacitance of a semiconductor device and hinders high speed operation. Parasitic capacitance can be reduced by intervening a thick semi-insulating or high resistivity compound semiconductor layer between a conductive substrate and constituent elements of a semiconductor device.
  • FIG. 1A is a schematic cross sectional view showing the structure of a GaN-HEMT device.
  • a semi-insulating or high resistivity AlN buffer layer 103 is grown thick on a (0001) single crystal conductive SiC substrate 101 .
  • MOCVD metal organic chemical vapor deposition
  • VPE hydride vapor phase epitaxy
  • FIGS. 2A and 2B schematically show the structures of a hydride VPE system and an MOCVD system.
  • FIG. 2A is a schematic cross sectional view showing the structure of a hydride VPE system.
  • a high frequency coil 31 for induction heating is wound around a quartz reaction tube 30 , and a carbon susceptor 32 for placing thereon a substrate 1 is disposed in the quartz reaction tube.
  • Two gas introducing pipes 34 and 35 are connected to the upstream end of the reaction tube 30 shown left in FIG. 2A , and a gas exhaust pipe 36 is connected to the downstream end of the reaction tube 30 .
  • a boat 38 is disposed in the reaction tube 30 at an upstream position of the susceptor 32 , and a source 39 of a group III element for a compound to be grown is accommodated in the boat.
  • the source is Al if AlN is to be grown, and Ga if GaN is to be grown.
  • Ammonia NH 3 as N source gas is introduced via the gas introducing pipe 34
  • HCl is introduced via the gas introducing pipe 35 .
  • HCl reacts with the group III element source 39 in the boat 38 to form group III element chloride AlCl.
  • Source gases AlCl and NH 3 are transported to the substrate and allow reaction on the substrate surface to grow AlN.
  • Surplus gas is exhausted via the gas exhaust pipe 36 to a detoxification tower.
  • FIG. 2B is a schematic cross sectional view showing the structure of an MOCVD system.
  • a high frequency coil 41 is disposed outside a quartz reaction tube 40 , and a carbon susceptor 42 for placing thereon a substrate 1 is disposed in the reaction tube 40 .
  • Two gas introducing pipes 44 and 45 are connected to the reaction tube 40 on the upstream side to supply source gases for compound.
  • source gases for compound For example, NH 3 as N source gas is introduced via the gas introducing pipe 44 , and organic group III element compound source material such as trimethylaluminum or trimethylgallium as group III element source gas is introduced via the gas introducing pipe 45 . Crystal growth progresses on the substrate 1 , and surplus gas is exhausted via the gas exhaust pipe 46 to a detoxification tower.
  • the gas exhaust pipe 46 is connected to a vacuum pump, and an exhaust port of the vacuum pump is coupled to a detoxification tower.
  • MOCVD is a method having been used widely as a compound semiconductor crystal growth method, and can obtain good crystallinity.
  • Various techniques for impurity doping and thickness control have been established.
  • a growth speed is 1 ⁇ m/hour (H) at the most.
  • Hydride VPE uses chloride as a group III element source.
  • a growth speed is extremely high to the extent that a growth speed of several tens ⁇ m/hour is possible.
  • a grown crystal layer has a high possibility of containing chlorine (Cl) dependent upon the source gas.
  • a growth speed of MOCVD is too slow, and hydride VPE capable of estblishing a high growth speed is suitable.
  • a semi-insulating or high resistivity AlN layer 103 with a thickness of 10 ⁇ m or more, e.g., a thickness of 20 ⁇ m to 50 ⁇ m, on a conductive SiC substrate by hydride VPE.
  • a thick AlN layer is grown by hydride VPE, dislocation is reduced and crystallinity can be improved.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • an AlN layer 103 is grown to a thickness of about 25 ⁇ m on a (0001) plane single crystal conductive SiC substrate 101 by hydride VPE.
  • a hydride VPE system has a structure as shown in FIG. 2A , and a group III element source material in the boat 38 is Al.
  • the conditions of hydride VPE are:
  • a resistivity of an AlN layer can be set extremely high, e.g., higher than 1E5 (1 ⁇ 10 5 ) ⁇ cm.
  • a HEMT structure lamination is grown on the AlN buffer layer 103 by MOCVD.
  • MOCVD system having the structure shown in FIG. 2B is used, and the conditions of MOCVD are, for example, as follows: Source materials and flow rates:
  • This GaN layer 104 is a non-doped layer, and forms a region of an active layer in which two-dimensional electron gas transports.
  • a non-doped AlGaN layer 105 having a thickness of, e.g., 5 nm, and in succession, silane (SiH 4 ) as source gas of n-type impurity is introduced to grow an n-type AlGaN layer 106 of 20 nm thick.
  • a doping amount of Si impurity in the n-type AlGaN layer 106 is, for example, about 4 ⁇ 10 18 cm ⁇ 3 .
  • the non-doped AlGaN layer 105 serves as a spacer layer and isolates the n-type AlGaN layer 106 from the active layer 104 .
  • the n-type AlGaN layer 106 serves as an electron supply layer to supply electron carriers to the active layer 104 . In this manner, the basic structure of HEMT is formed.
  • an n-type GaN layer 107 as a protective layer is grown on the n-type AlGaN layer 106 .
  • a doping amount of Si is, for example, about 5 ⁇ 10 18 cm ⁇ 3 .
  • the n-type AlGaN layer 106 is therefore covered with the n-type GaN layer 107 having a lower resistivity.
  • the substrate is taken out from the MOCVD system, an isolation region is formed by recess etching using BCl 3 , and thereafter an SiN film 108 is deposited by plasma CVD. Openings for source/drain contact regions are formed through the SiN film, and the n-type GaN layer is etched and removed by dry etching using Cl 2 .
  • a Ta layer of 10 nm thick is formed, an Al layer of 300 nm thick is formed on the Ta layer, and they are patterned to form a source electrode S and a drain electrode D.
  • These electrodes can be patterned, for example, by lift-off method. Annealing is performed at 600° C. to form ohmic contacts.
  • the SiN film 108 in a gate contact region is etched, and for example, an Ni layer of 20 nm thick and an Au layer of 400 nm thick are formed and patterned to form a gate electrode. This electrode can be formed, for example, also by lift-off method.
  • the gate electrode forms a Schottky contact.
  • the semi-insulating AlN layer 103 By growing the semi-insulating AlN layer 103 thick, at least to a thickness of 10 ⁇ m, it can be expected that parasitic capacitance of HEMT can be suppressed.
  • the AlN layer also has the effects of reducing dislocation and improving crystallinity with the growth of the AlN layer. In the context of this point, it is particularly preferable to grow the AlN layer not thinner than 20 ⁇ m. Although an upper limit of thickness is determined by a warp and crack of a wafer, an upper limit of, e.g., 50 ⁇ m, may be selected. A current collapse phenomenon of a change in an on-resistance during operation can be avoided by forming the GaN protective layer and SiN layer on and above the n-type AlGaN electron supply layer.
  • SiC has a high thermal conductivity and is expected to realize high breakdown voltage and high speed operation.
  • GaN-HEMT devices formed actually by growing a GaN series compound semiconductor crystal layers on a conductive SiC substrate had no reproductivity.
  • FIG. 3 shows measurement results of a power density per unit gate width at each experimental run.
  • a curve c 0 shows experiment results. There was a large variation and the devices cannot be brought into practical use. The present inventors have studied the reason why expected performance was not able to be realized.
  • a semi-insulating SiC substrate is transparent, whereas a conductive SiC substrate presents various coloring. This coloring is caused by various impurities contained in the substrate.
  • a black substrate attributable to B shows p-type conductivity
  • a green substrate attributable to N shows n-type conductivity
  • a blue substrate attributable to Al shows p-type conductivity.
  • Color of a conductive SiC substrate is governed by concentrations of impurities and energy levels, and the color becomes stronger as the resistivity is lower.
  • FIGS. 4A and 4B show some examples of a green substrate.
  • FIG. 4A is a table showing examples of resistivity. Samples S 1 have a resistivity around 0.12 ohm-cm, samples S 2 has a resistivity around 0.08 ohm-cm, samples S 3 have a resistivity around 0.04-0.06 ohm-cm, and samples S 4 have a resistivity aound 0.01-0.02 ohm-cm.
  • FIG. 4B is a graph showing optical absorption spectra of examples S 1 -S 4 of the green substrate. The abscissa represents a wavelength in the unit of ⁇ m, and the ordinate represents an absorption coefficient in the unit of cm ⁇ 1 .
  • Spectra identified with symbols S 1 - 54 correspond to samples S 1 -S 4 shown in FIG. 4A .
  • An absorption band having a peak near a wavelength of 0.6 ⁇ m is observed. It can be understood that the lower a resistivity, the higher a peak absorption coefficient is.
  • the peak absorption coefficient is more than twice the absorption coefficient at 0.5 ⁇ m.
  • the peak absorption coefficient is at most around 30 cm ⁇ 1 , and is less than twice the absorption coefficient at 0.5 ⁇ m.
  • a GaN series compound semiconductor layer is usually grown at a temperature of 1000° C. or higher, e.g., in an incandescent state at 1100° C.
  • Heat source is radiation heat from the carbon susceptor 32 , or 42 shown in FIG. 2A , or 2 B. It can be considered that if a conductive SiC substrate shows absorption near at a wavelength of, e.g., 0.6 ⁇ m, at least a portion of radiation heat from the carbon susceptor will be absorbed in the SiC substrate. In this case, it can therefore be considered that a temperature of the uppermost surface of the substrate during crystal growth may be lowered.
  • FIG. 4C is a graph showing measurement results of an actual temperature of a crystal growth surface at each resistivity of the green SiC substrate, under the setting of crystal growth at a surface temperature of 1100° C.
  • An abscissa represents a resistivity of the SiC substrate, and the ordinate represents a temperature at the uppermost growth surface. It clearly shows that as the resistivity of a substrate is lowed, the surface temperature is lowed. If the amount of the lowered temperature is within 10° C., countermeasure could be taken by finely adjusting the growth temperature. However, if the temperature lowering is more than 10° C., crystal uniformity and good device characteristics could not be obtained even when the temperature is forced to be raised. This may be ascribed to that the conditions of crystal growth in a growth system change greatly. Namely, a presently usable range is a range indicated by hatching in the graph, i.e., a resistivity range of 0.08 ⁇ cm or higher.
  • An epitaxial layer was grown on each green SiC substrate having a different resistivity, and a trap concentration was measured.
  • a HEMT structure was formed and a sheet resistivity was measured.
  • FIGS. 5A and 5B are graphs showing relation between a trap concentration and sheet resistivity of respective SiC substrates having different resistivities.
  • FIG. 5A indicates that as a resistivity of an SiC substrate lowers, a trap concentration increases. It is considered that a trap concentration increases if carbon is captured in crystal or point defects increase. It also indicates that trap formation cannot be suppressed even if temperature setting is adjusted.
  • FIG. 5B indicates that as resistivity of the SiC substrate lowers, sheet resistivity increases. It is considered that as traps increase, two-dimensional electron gas reduces and a sheet resistivity increases.
  • FIGS. 6A , 6 B and 6 C show I-V characteristics of GaN-HEMTs formed on green SiC substrates having resistivities of 0.06 ⁇ cm, 0.08 ⁇ cm and semi-insulating (resistivity larger than 1E5 ⁇ cm).
  • growth setting temperature was 1100° C.
  • growth setting temperature was further raised from 1100° C. to 1120° C. to adjust a surface temperatures.
  • the SiC substrate having the resistivity of 0.08 ⁇ cm showed I-V characteristics approximately similar to those of the semi-insulating substrate. It is clear that a drain current reduces for the substrate having resistivity of 0.06 ⁇ cm.
  • FIG. 7 shows results of on-wafer power measurement on each device having a gate width of 1 mm. Power density equivalent to a range of the semi-insulating SiC substrate could be obtained for green substrates having resistivity of 0.08 ⁇ cm or higher, for blue substrates having resistivity of 10 ⁇ cm or higher, and for black substrates having resistivity of 1E3 ⁇ cm or higher.
  • Resistivity of 1E5 ⁇ cm or higher is in a semi-insulating region, and no cost merit is enjoyed. It can therefore be said that an upper resistivity limit of a conductive SiC substrate in each color is 1E5 ⁇ cm.
  • FIG. 1B is a table collectively showing color, resistivity range, and peak wavelength of optical absorption band, of usable conductive substrate. There is a difference between optical absorption peak wavelengths corresponding to respective colors. Resistivity ranges establishing selection criterion are also different for the respective colors. For green conductive SiC substrate, conductive substrates having resistivity of 0.08 ⁇ cm to 1E5 ⁇ cm may be selected. For blue conductive SiC substrates, conductive substrates having resistivity of 10 ⁇ cm to 1E5 ⁇ cm may be selected. For black conductive SiC substrates, conductive substrates having resistivity of 1E3 ⁇ cm to 1E5 ⁇ cm may be selected.
  • a curve c 1 shown in FIG. 3 indicates a power concentration at each run when conductive SiC substrates are selected in accordance with the above-described selection criteria and thereafter a GaN-HEMT structure shown in FIG. 1A is formed on each substrate. It can be seen that variation reduces considerably and uniform characteristics are obtained. In this manner, it is possible to manufacture GaN-HEMT at low cost which is capable of high voltage and high speed operation, when a conductive SiC substrate is selected in accordance with the selection criteria shown in FIG. 1B , the selected substrate is used as the conductive SiC substrate 101 shown in FIG. 1A , and a GaN-HEMT structure is formed thereon.
  • GaN series compound semiconductor of Al x In y Ga i-x-y N (0 ⁇ x ⁇ 1.0, 0 ⁇ y ⁇ 1.0) including AlN, GaN and AlGaN will be possible to be grown on a conductive single crystal SiC substrate.
  • Products of GaN series compound semiconductor wafers may also be provided such as a wafer with a grown AlN buffer layer, and a wafer with a lamination of a GaN layer/a non-doped AlGaN layer/n-type AlGaN layer/n-type GaN layer or part of these layers grown on an AlN buffer layer.
  • These semiconductor device and semiconductor wafer are collectively called herein a semiconductor structure.
  • GaN-HEMT manufacture of GaN-HEMT has been described by way of example, electronic devices to be manufactured are not limited to HEMT, but other electronic devices and optical devices may also be manufactured.

Abstract

A method for manufacturing a compound semiconductor structure, includes (a) selecting a conductive SiC substrate in accordance with color and resistivity and (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate. The step (a) preferably selects a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 52 cm to 1×105 Ωcm, or whose main color is black, whose conductivity type is p-type and whose resistivity is 1×103 Ωcm to 1×105Ωcm, or whose main color is blue, whose conductivity type is p-type and whose resistivity is 10 Ωcm to 1×105 Ωcm. The step (b) preferably includes (b-1) growing an AlInGaN layer having a thickness not thinner than 10 μm on the conductive SiC substrate by hydride VPE.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application is a divisional of application Ser. No. 12/248,357, filed Oct. 9, 2008, which claims the benefit of priority of PCT/JP2006/307566, filed on Apr. 10, 2006, the entire contents of which are incorporated herein by reference.
  • BACKGROUND
  • 1. Field
  • The present invention relates to a compound semiconductor structure and its manufacture method, and more particularly to a GaN series compound semiconductor structure using a conductive SiC substrate and its manufacture method. Here,
  • GaN series compound semiconductor is represented by AlxIny Ga1-x-yN (0≦x≦1.0, 0≦y≦1.0).
  • 2. Description of the Related Art
  • Compound semiconductor devices using GaN or GaN series compound semiconductor are under vigorous development. GaN has a wide band gap of 3.4 eV and can operate at high voltages. Various semiconductor devices can be manufactured by forming a hetero junction using GaN series compound semiconductor. Metal organic chemical vapor deposition (MOCVD) is mainly used as a crystal growth method.
  • GaN has a high breakdown voltage, and is expected to be applied to usage requiring high voltage and high speed operation such as a high electron mobility transistor (HEMT) used at a base station of mobile phones. A variety of GaN-HEMTs have been reported which use as an electron transport layer a GaN layer of GaN/AlGaN crystals grown on a substrate such as sapphire, SiC, GaN and Si.
  • JP-A-2002-352956 proposes a GaN series HEMT having a high on-breakdown voltage and improved I-V characteristics, which is manufactured for example by laminating on a c-plane sapphire substrate an i-type GaN electron transport layer, an i-type AlGaN spacer layer, an Si-doped n-type AlGaN electron supply layer and an Si-doped n-type GaN protective layer by MOCVD, depositing an SiN layer by CVD, forming openings through the SiN layer, and forming source/drain ohmic electrodes and a gate Schottky electrode.
  • JP-A-2004-221325 proposes a HEMT which is manufactured by laminating on an SiC substrate an i-type GaN electron transport layer, an i-type AlGaN spacer layer, an Si-doped n-type AlGaN electron supply layer and an Si-doped n-type GaN cap layer, forming source/drain ohmic electrodes, thereafter depositing a first SiN protective film by CVD, forming an opening through the first SiN protective film, and forming a gate Schottky electrode, and further forming a second SiN protective film. This structure can suppress current collapse, i.e., a change in an on-resistance during operation.
  • A breakdown voltage in current-off state in excess of 300 V is presently reported. Best output characteristics are obtained by a GaN-HEMT using an SiC substrate. A high thermal conductivity of SiC contributes to this performance. When a high speed operation GaN device is to be manufactured, a semi-insulating SiC substrate is used in order to restrict parasitic capacitance.
  • SUMMARY
  • According to one aspect of the present invention, there is provided a compound semiconductor structure comprising:
      • a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 Ωcm to 1×105 Ωcm, or whose main color is black, whose conductivity type is p-type and whose resistivity is 1×103 Ωcm to 1×105 Ωcm, or whose main color is blue, whose conductivity type is p-type and whose resistivity is 10 Ωcm to 1×105 Ωcm; and
      • an AlInGaN layer having a thickness not thinner than 10 μm and formed on the conductive SiC substrate.
  • According to another aspect of the present invention, there is provided a method for manufacturing a compound semiconductor structure, comprising:
      • (a) selecting a conductive SiC substrate in accordance with color and resistivity; and
      • (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate.
    BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a cross sectional view showing the structure of a GaN-HEMT using a conductive SiC substrate according to an embodiment, and FIG. 1B is a table showing the characteristics of a conductive SiC substrate;
  • FIGS. 2A and 2B are schematic cross sectional views of a hydride VPE system and an MOCVD system, respectively;
  • FIG. 3 is a graph showing a power density at each run when conductive SiC substrates selected without a selection criterion are used and when conductive SiC substrates selected in accordance with a selection criterion are used;
  • FIGS. 4A, 4B and 4C show a table showing resistivities of green conductive SiC substrates, a graph showing absorption coefficients dependent upon resistivities, and a graph showing a relation between a resistivity and a surface temperature during crystal growth, respectively;
  • FIGS. 5A and 5B are graphs showing a trap concentration and a sheet resistivity of a grown layer dependent upon a resistivity of a conductive SiC substrate;
  • FIGS. 6A, 6B and 6C are graphs showing I-V characteristics of GaN-HEMTs formed on conductive SiC substrates and on a semi-insulating SiC substrate;
  • FIG. 7 is a graph showing regions of resistivity as the selection criterion for conductive SiC substrates derived from power density of HEMTs.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A semi-insulating SiC substrate is very expensive, presenting a possibility that this high cost may hinder prevail of GaN-HEMTs. A conductive SiC substrate is available less expensively than a semi-insulating SiC substrate. If GaN series compound semiconductor devices having good characteristics can be manufactured using conductive SiC substrates, this contributes to prevail of GaN-HEMTs.
  • If a conductive SiC substrate is used, a GaN series compound semiconductor device having a high thermal conductivity of SiC can be manufactured less expensively. However, using a conductive substrate increases parasitic capacitance of a semiconductor device and hinders high speed operation. Parasitic capacitance can be reduced by intervening a thick semi-insulating or high resistivity compound semiconductor layer between a conductive substrate and constituent elements of a semiconductor device.
  • FIG. 1A is a schematic cross sectional view showing the structure of a GaN-HEMT device. A semi-insulating or high resistivity AlN buffer layer 103 is grown thick on a (0001) single crystal conductive SiC substrate 101. It is known that metal organic chemical vapor deposition (MOCVD) and hydride vapor phase epitaxy (VPE) are typically used as a crystal growth method of growing GaN series compound semiconductor.
  • FIGS. 2A and 2B schematically show the structures of a hydride VPE system and an MOCVD system.
  • FIG. 2A is a schematic cross sectional view showing the structure of a hydride VPE system. A high frequency coil 31 for induction heating is wound around a quartz reaction tube 30, and a carbon susceptor 32 for placing thereon a substrate 1 is disposed in the quartz reaction tube. Two gas introducing pipes 34 and 35 are connected to the upstream end of the reaction tube 30 shown left in FIG. 2A, and a gas exhaust pipe 36 is connected to the downstream end of the reaction tube 30. A boat 38 is disposed in the reaction tube 30 at an upstream position of the susceptor 32, and a source 39 of a group III element for a compound to be grown is accommodated in the boat. For example, the source is Al if AlN is to be grown, and Ga if GaN is to be grown. Ammonia NH3 as N source gas is introduced via the gas introducing pipe 34, and HCl is introduced via the gas introducing pipe 35. HCl reacts with the group III element source 39 in the boat 38 to form group III element chloride AlCl. Source gases AlCl and NH3 are transported to the substrate and allow reaction on the substrate surface to grow AlN. Surplus gas is exhausted via the gas exhaust pipe 36 to a detoxification tower.
  • FIG. 2B is a schematic cross sectional view showing the structure of an MOCVD system. A high frequency coil 41 is disposed outside a quartz reaction tube 40, and a carbon susceptor 42 for placing thereon a substrate 1 is disposed in the reaction tube 40. Two gas introducing pipes 44 and 45 are connected to the reaction tube 40 on the upstream side to supply source gases for compound. For example, NH3 as N source gas is introduced via the gas introducing pipe 44, and organic group III element compound source material such as trimethylaluminum or trimethylgallium as group III element source gas is introduced via the gas introducing pipe 45. Crystal growth progresses on the substrate 1, and surplus gas is exhausted via the gas exhaust pipe 46 to a detoxification tower. If MOCVD is to be performed in a low pressure atmosphere, the gas exhaust pipe 46 is connected to a vacuum pump, and an exhaust port of the vacuum pump is coupled to a detoxification tower.
  • MOCVD is a method having been used widely as a compound semiconductor crystal growth method, and can obtain good crystallinity. Various techniques for impurity doping and thickness control have been established. However, a growth speed is 1 μm/hour (H) at the most.
  • Hydride VPE uses chloride as a group III element source. A growth speed is extremely high to the extent that a growth speed of several tens μm/hour is possible. A grown crystal layer has a high possibility of containing chlorine (Cl) dependent upon the source gas. For growing a compound semiconductor layer with a thickness of the order of 10 μm or more, a growth speed of MOCVD is too slow, and hydride VPE capable of estblishing a high growth speed is suitable.
  • For forming a GaN-HEMT on a conductive SiC substrate, it is desirable to first grow a semi-insulating or high resistivity AlN layer 103 with a thickness of 10 μm or more, e.g., a thickness of 20 μm to 50 μm, on a conductive SiC substrate by hydride VPE. As a thick AlN layer is grown by hydride VPE, dislocation is reduced and crystallinity can be improved. Thereafter, a HEMT constituting lamination is grown by MOCVD.
  • As shown in FIG. 1A, an AlN layer 103 is grown to a thickness of about 25 μm on a (0001) plane single crystal conductive SiC substrate 101 by hydride VPE. A hydride VPE system has a structure as shown in FIG. 2A, and a group III element source material in the boat 38 is Al. The conditions of hydride VPE are:
      • Pressure: normal pressure,
      • Gas flow rate: HCl 100 ccm (cubic centimeter per minute),
      • NH 3 10 LM (litter per minute),
      • Temperature: 1100° C.
  • A resistivity of an AlN layer can be set extremely high, e.g., higher than 1E5 (1×105) Ωcm.
  • A HEMT structure lamination is grown on the AlN buffer layer 103 by MOCVD.
  • An MOCVD system having the structure shown in FIG. 2B is used, and the conditions of MOCVD are, for example, as follows: Source materials and flow rates:
      • Trimethylgallium (TMG) 50 sccm (standard ccm),
      • Trimethylaluminum (TMA) (if necessary) 5 sccm,
      • Ammonia (NH3) 20 SLM (standard LM),
      • N-type impurity: silane (SiH4),
      • P-type impurity: biscyclopenta-dienyl-magnesium (Cp2Mg),
      • Pressure: 100 torr,
      • Temperature: 1100° C.
  • By supplying TMG and NH3 (and not supplying TMA), a GaN layer 104 having a thickness of, e.g., 3 μm, is grown on the AlN buffer layer 103. This GaN layer 104 is a non-doped layer, and forms a region of an active layer in which two-dimensional electron gas transports.
  • After the GaN layer 104 is grown, supply of TMA as Al source gas starts to grow a non-doped AlGaN layer 105 having a thickness of, e.g., 5 nm, and in succession, silane (SiH4) as source gas of n-type impurity is introduced to grow an n-type AlGaN layer 106 of 20 nm thick. A doping amount of Si impurity in the n-type AlGaN layer 106 is, for example, about 4×1018 cm−3. The non-doped AlGaN layer 105 serves as a spacer layer and isolates the n-type AlGaN layer 106 from the active layer 104. The n-type AlGaN layer 106 serves as an electron supply layer to supply electron carriers to the active layer 104. In this manner, the basic structure of HEMT is formed.
  • Further, stopping supply of TMA, an n-type GaN layer 107 as a protective layer is grown on the n-type AlGaN layer 106. A doping amount of Si is, for example, about 5×1018 cm−3. The n-type AlGaN layer 106 is therefore covered with the n-type GaN layer 107 having a lower resistivity.
  • The substrate is taken out from the MOCVD system, an isolation region is formed by recess etching using BCl3, and thereafter an SiN film 108 is deposited by plasma CVD. Openings for source/drain contact regions are formed through the SiN film, and the n-type GaN layer is etched and removed by dry etching using Cl2.
  • For example, a Ta layer of 10 nm thick is formed, an Al layer of 300 nm thick is formed on the Ta layer, and they are patterned to form a source electrode S and a drain electrode D. These electrodes can be patterned, for example, by lift-off method. Annealing is performed at 600° C. to form ohmic contacts. The SiN film 108 in a gate contact region is etched, and for example, an Ni layer of 20 nm thick and an Au layer of 400 nm thick are formed and patterned to form a gate electrode. This electrode can be formed, for example, also by lift-off method. The gate electrode forms a Schottky contact.
  • By growing the semi-insulating AlN layer 103 thick, at least to a thickness of 10 μm, it can be expected that parasitic capacitance of HEMT can be suppressed. The AlN layer also has the effects of reducing dislocation and improving crystallinity with the growth of the AlN layer. In the context of this point, it is particularly preferable to grow the AlN layer not thinner than 20 μm. Although an upper limit of thickness is determined by a warp and crack of a wafer, an upper limit of, e.g., 50 μm, may be selected. A current collapse phenomenon of a change in an on-resistance during operation can be avoided by forming the GaN protective layer and SiN layer on and above the n-type AlGaN electron supply layer.
  • SiC has a high thermal conductivity and is expected to realize high breakdown voltage and high speed operation. However, GaN-HEMT devices formed actually by growing a GaN series compound semiconductor crystal layers on a conductive SiC substrate had no reproductivity.
  • FIG. 3 shows measurement results of a power density per unit gate width at each experimental run. A curve c0 shows experiment results. There was a large variation and the devices cannot be brought into practical use. The present inventors have studied the reason why expected performance was not able to be realized.
  • A semi-insulating SiC substrate is transparent, whereas a conductive SiC substrate presents various coloring. This coloring is caused by various impurities contained in the substrate. A black substrate attributable to B shows p-type conductivity, a green substrate attributable to N shows n-type conductivity, and a blue substrate attributable to Al shows p-type conductivity. Color of a conductive SiC substrate is governed by concentrations of impurities and energy levels, and the color becomes stronger as the resistivity is lower.
  • FIGS. 4A and 4B show some examples of a green substrate. FIG. 4A is a table showing examples of resistivity. Samples S1 have a resistivity around 0.12 ohm-cm, samples S2 has a resistivity around 0.08 ohm-cm, samples S3 have a resistivity around 0.04-0.06 ohm-cm, and samples S4 have a resistivity aound 0.01-0.02 ohm-cm. FIG. 4B is a graph showing optical absorption spectra of examples S1-S4 of the green substrate. The abscissa represents a wavelength in the unit of μm, and the ordinate represents an absorption coefficient in the unit of cm−1. Spectra identified with symbols S1-54 correspond to samples S1-S4 shown in FIG. 4A. An absorption band having a peak near a wavelength of 0.6 μm is observed. It can be understood that the lower a resistivity, the higher a peak absorption coefficient is. In spectra S4 and S3, the peak absorption coefficient is more than twice the absorption coefficient at 0.5 μm. In spectra S2 and S1, the peak absorption coefficient is at most around 30 cm−1, and is less than twice the absorption coefficient at 0.5 μm.
  • A GaN series compound semiconductor layer is usually grown at a temperature of 1000° C. or higher, e.g., in an incandescent state at 1100° C. Heat source is radiation heat from the carbon susceptor 32, or 42 shown in FIG. 2A, or 2B. It can be considered that if a conductive SiC substrate shows absorption near at a wavelength of, e.g., 0.6 μm, at least a portion of radiation heat from the carbon susceptor will be absorbed in the SiC substrate. In this case, it can therefore be considered that a temperature of the uppermost surface of the substrate during crystal growth may be lowered.
  • FIG. 4C is a graph showing measurement results of an actual temperature of a crystal growth surface at each resistivity of the green SiC substrate, under the setting of crystal growth at a surface temperature of 1100° C. An abscissa represents a resistivity of the SiC substrate, and the ordinate represents a temperature at the uppermost growth surface. It clearly shows that as the resistivity of a substrate is lowed, the surface temperature is lowed. If the amount of the lowered temperature is within 10° C., countermeasure could be taken by finely adjusting the growth temperature. However, if the temperature lowering is more than 10° C., crystal uniformity and good device characteristics could not be obtained even when the temperature is forced to be raised. This may be ascribed to that the conditions of crystal growth in a growth system change greatly. Namely, a presently usable range is a range indicated by hatching in the graph, i.e., a resistivity range of 0.08 Ωcm or higher.
  • An epitaxial layer was grown on each green SiC substrate having a different resistivity, and a trap concentration was measured. A HEMT structure was formed and a sheet resistivity was measured.
  • FIGS. 5A and 5B are graphs showing relation between a trap concentration and sheet resistivity of respective SiC substrates having different resistivities. FIG. 5A indicates that as a resistivity of an SiC substrate lowers, a trap concentration increases. It is considered that a trap concentration increases if carbon is captured in crystal or point defects increase. It also indicates that trap formation cannot be suppressed even if temperature setting is adjusted.
  • FIG. 5B indicates that as resistivity of the SiC substrate lowers, sheet resistivity increases. It is considered that as traps increase, two-dimensional electron gas reduces and a sheet resistivity increases.
  • These results also indicate that good device characteristics can be obtained if a resistivity of a green SiC substrate is not lower than 0.08 Ωcm.
  • FIGS. 6A, 6B and 6C show I-V characteristics of GaN-HEMTs formed on green SiC substrates having resistivities of 0.06 Ωcm, 0.08 Ωcm and semi-insulating (resistivity larger than 1E5 Ωcm). For a substrate having resistivity of 0.08 Ωcm, growth setting temperature was 1100° C. For a substrate having a resistivity of 0.06 Ωcm, growth setting temperature was further raised from 1100° C. to 1120° C. to adjust a surface temperatures. The SiC substrate having the resistivity of 0.08 Ωcm showed I-V characteristics approximately similar to those of the semi-insulating substrate. It is clear that a drain current reduces for the substrate having resistivity of 0.06 Ωcm.
  • FIG. 7 shows results of on-wafer power measurement on each device having a gate width of 1 mm. Power density equivalent to a range of the semi-insulating SiC substrate could be obtained for green substrates having resistivity of 0.08 Ωcm or higher, for blue substrates having resistivity of 10 Ωcm or higher, and for black substrates having resistivity of 1E3 Ωcm or higher.
  • Resistivity of 1E5 Ωcm or higher is in a semi-insulating region, and no cost merit is enjoyed. It can therefore be said that an upper resistivity limit of a conductive SiC substrate in each color is 1E5 Ωcm.
  • FIG. 1B is a table collectively showing color, resistivity range, and peak wavelength of optical absorption band, of usable conductive substrate. There is a difference between optical absorption peak wavelengths corresponding to respective colors. Resistivity ranges establishing selection criterion are also different for the respective colors. For green conductive SiC substrate, conductive substrates having resistivity of 0.08 Ωcm to 1E5 Ωcm may be selected. For blue conductive SiC substrates, conductive substrates having resistivity of 10 Ωcm to 1E5 Ωcm may be selected. For black conductive SiC substrates, conductive substrates having resistivity of 1E3 Ωcm to 1E5 Ωcm may be selected.
  • A curve c1 shown in FIG. 3 indicates a power concentration at each run when conductive SiC substrates are selected in accordance with the above-described selection criteria and thereafter a GaN-HEMT structure shown in FIG. 1A is formed on each substrate. It can be seen that variation reduces considerably and uniform characteristics are obtained. In this manner, it is possible to manufacture GaN-HEMT at low cost which is capable of high voltage and high speed operation, when a conductive SiC substrate is selected in accordance with the selection criteria shown in FIG. 1B, the selected substrate is used as the conductive SiC substrate 101 shown in FIG. 1A, and a GaN-HEMT structure is formed thereon.
  • Although manufacture of GaN-HEMT has been described by way of example, GaN series compound semiconductor of AlxIny Gai-x-yN (0≦x≦1.0, 0≦y≦1.0) including AlN, GaN and AlGaN will be possible to be grown on a conductive single crystal SiC substrate. Products of GaN series compound semiconductor wafers may also be provided such as a wafer with a grown AlN buffer layer, and a wafer with a lamination of a GaN layer/a non-doped AlGaN layer/n-type AlGaN layer/n-type GaN layer or part of these layers grown on an AlN buffer layer. These semiconductor device and semiconductor wafer are collectively called herein a semiconductor structure.
  • Although manufacture of GaN-HEMT has been described by way of example, electronic devices to be manufactured are not limited to HEMT, but other electronic devices and optical devices may also be manufactured.
  • It will be apparent for those skilled in the art that various modifications, improvements, substitutions, combinations and the like are possible.
  • It is possible to provide GaN series compound semiconductor devices and wafers therefor.

Claims (9)

1. A compound semiconductor structure comprising:
a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 Ωcm to 1×105 Ωcm, or whose main color is black, whose conductivity type is p-type and whose resistivity is 1×103 Ωcm to 1×105 Ωcm, or whose main color is blue, whose conductivity type is p-type and whose resistivity is 10 Ωcm to 1×105 Ωcm; and
an AlInGaN layer having a thickness not thinner than 10 μm and formed on said conductive SiC substrate.
2. The compound semiconductor structure according to claim 1, wherein said SiC substrate is green, and an absorption coefficient at a peak wavelength of an optical absorption band around 0.6 μm is not larger than two times of an absorption coefficient at a wavelength of 0.5 μm.
3. The compound semiconductor structure according to claim 1, wherein said AlInGaN layer is an AlN layer.
4. The compound semiconductor structure according to claim 1, wherein said AlInGaN layer contains Cl.
5. The compound semiconductor structure according to claim 1, further comprising:
an i-type GaN layer, an i-type AlGaN layer and an n-type AlGaN layer laminated on and above said AlInGaN layer.
6. A compound semiconductor structure comprising:
a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 Ωcm to 1×105 Ωcm, or whose main color is black, whose conductivity type is p-type and whose resistivity is 1×103 Ωcm to 1×105 Ωcm, or whose main color is blue, whose conductivity type is p-type and whose resistivity is 10 Ωcm to 1×105 Ωcm;
an AlInGaN layer having a thickness not thinner than 10 μm and formed on said conductive SiC substrate;
an i-type GaN layer, an i-type AlGaN layer and an n-type AlGaN layer laminated on and above said AlInGaN layer;
a pair of source/drain electrodes in ohmic contact with said n-type AlGaN layer;
an n-type GaN layer formed on said n-type AlGaN layer between said pair of source/drain electrodes;
an SiN film deposited on said n-type GaN layer;
an opening formed through said SiN film between said pair of source/drain electrodes; and
a gate electrode in Schottky contact with said n-type GaN layer via said opening.
7. The compound semiconductor structure according to claim 6, wherein said SiC substrate is green, and an absorption coefficient at a peak wavelength of an optical absorption band around 0.6 μm is not larger than two times of an absorption coefficient at a wavelength of 0.5 μm.
8. The compound semiconductor structure according to claim 6, wherein said AlInGaN layer is an AlN layer.
9. The compound semiconductor structure according to claim 6, wherein said AlInGaN layer contains Cl.
US13/209,882 2006-04-10 2011-08-15 Compound seminconductor structure Abandoned US20110297957A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/209,882 US20110297957A1 (en) 2006-04-10 2011-08-15 Compound seminconductor structure

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
PCT/JP2006/307566 WO2007116517A1 (en) 2006-04-10 2006-04-10 Compound semiconductor structure and process for producing the same
US12/248,357 US8030164B2 (en) 2006-04-10 2008-10-09 Compound semiconductor structure
US13/209,882 US20110297957A1 (en) 2006-04-10 2011-08-15 Compound seminconductor structure

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/248,357 Division US8030164B2 (en) 2006-04-10 2008-10-09 Compound semiconductor structure

Publications (1)

Publication Number Publication Date
US20110297957A1 true US20110297957A1 (en) 2011-12-08

Family

ID=38580826

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/248,357 Active US8030164B2 (en) 2006-04-10 2008-10-09 Compound semiconductor structure
US13/209,882 Abandoned US20110297957A1 (en) 2006-04-10 2011-08-15 Compound seminconductor structure

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/248,357 Active US8030164B2 (en) 2006-04-10 2008-10-09 Compound semiconductor structure

Country Status (3)

Country Link
US (2) US8030164B2 (en)
JP (1) JP5274245B2 (en)
WO (1) WO2007116517A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120211763A1 (en) * 2011-02-22 2012-08-23 Covalent Materials Corporation Nitride semiconductor substrate and method of manufacturing the same
US20130161709A1 (en) * 2011-12-21 2013-06-27 Fujitsu Limited Semiconductor device and method of manufacturing the same
US20150171173A1 (en) * 2012-09-13 2015-06-18 Panasonic Intellectual Property Management Co., Ltd. Nitride semiconductor structure
US20200266292A1 (en) * 2019-02-19 2020-08-20 AZ Power, Inc Composite substrates of conductive and insulating or semi-insulating silicon carbide for gallium nitride devices
WO2022149788A1 (en) * 2021-01-08 2022-07-14 한국산업기술대학교산학협력단 High-efficiency nitride-based photodetector

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4712683B2 (en) * 2006-12-21 2011-06-29 パナソニック株式会社 Transistor and manufacturing method thereof
JP2011040676A (en) * 2009-08-18 2011-02-24 Sanken Electric Co Ltd Semiconductor device, and method of manufacturing the same
JP2011187623A (en) * 2010-03-08 2011-09-22 Furukawa Electric Co Ltd:The Semiconductor element and manufacturing method thereof
KR20120032258A (en) * 2010-09-28 2012-04-05 삼성엘이디 주식회사 Gallium nitride based semiconductor device and method of manufacturing the same
US8710511B2 (en) 2011-07-29 2014-04-29 Northrop Grumman Systems Corporation AIN buffer N-polar GaN HEMT profile
JP2013048191A (en) * 2011-08-29 2013-03-07 Mitsubishi Electric Corp Wide band-gap semiconductor device
JP5306438B2 (en) * 2011-11-14 2013-10-02 シャープ株式会社 Field effect transistor and manufacturing method thereof
JP5696083B2 (en) * 2012-03-26 2015-04-08 株式会社東芝 Nitride semiconductor device and manufacturing method thereof
US9608085B2 (en) * 2012-10-01 2017-03-28 Cree, Inc. Predisposed high electron mobility transistor
JP6174874B2 (en) * 2013-03-15 2017-08-02 ルネサスエレクトロニクス株式会社 Semiconductor device
EP3368497A1 (en) 2015-10-30 2018-09-05 Corning Incorporated Inorganic membrane filtration articles and methods thereof
CN112802815B (en) * 2020-12-29 2022-10-11 河北博威集成电路有限公司 GaN microwave power device special for 5G communication and packaging process thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866005A (en) * 1987-10-26 1989-09-12 North Carolina State University Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide
US20030103539A1 (en) * 1997-09-03 2003-06-05 Susumu Omi Nitride-type compound semiconductor laser device and laser apparatus incorporating the same
US20050082563A1 (en) * 2003-10-20 2005-04-21 United Epitaxy Company, Ltd. Group iii nitride semiconductor device and its method of manufacture
US20050183658A1 (en) * 2001-10-09 2005-08-25 Sumitomo Electric Industries, Ltd. AlxInyGa1-x-yN mixture crystal substrate, method of growing AlxInyGa1-x-yN mixture crystal substrate and method of producing AlxInyGa1-x-yN mixture crystal substrate
US20060138455A1 (en) * 2004-01-22 2006-06-29 Saxler Adam W Silicon carbide on diamond substrates and related devices and methods
US20060197107A1 (en) * 2005-03-03 2006-09-07 Fujitsu Limited Semiconductor device and production method thereof
US20070164321A1 (en) * 2006-01-17 2007-07-19 Cree, Inc. Methods of fabricating transistors including supported gate electrodes and related devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4166885B2 (en) * 1998-05-18 2008-10-15 富士通株式会社 Optical semiconductor device and manufacturing method thereof
US6459100B1 (en) * 1998-09-16 2002-10-01 Cree, Inc. Vertical geometry ingan LED
JP4663156B2 (en) * 2001-05-31 2011-03-30 富士通株式会社 Compound semiconductor device
JP4179539B2 (en) * 2003-01-15 2008-11-12 富士通株式会社 Compound semiconductor device and manufacturing method thereof
JP2006032911A (en) * 2004-06-15 2006-02-02 Ngk Insulators Ltd Semiconductor laminated structure, semiconductor device, and hemt element

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866005A (en) * 1987-10-26 1989-09-12 North Carolina State University Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide
US20030103539A1 (en) * 1997-09-03 2003-06-05 Susumu Omi Nitride-type compound semiconductor laser device and laser apparatus incorporating the same
US20050183658A1 (en) * 2001-10-09 2005-08-25 Sumitomo Electric Industries, Ltd. AlxInyGa1-x-yN mixture crystal substrate, method of growing AlxInyGa1-x-yN mixture crystal substrate and method of producing AlxInyGa1-x-yN mixture crystal substrate
US20050082563A1 (en) * 2003-10-20 2005-04-21 United Epitaxy Company, Ltd. Group iii nitride semiconductor device and its method of manufacture
US20060138455A1 (en) * 2004-01-22 2006-06-29 Saxler Adam W Silicon carbide on diamond substrates and related devices and methods
US20060197107A1 (en) * 2005-03-03 2006-09-07 Fujitsu Limited Semiconductor device and production method thereof
US20070164321A1 (en) * 2006-01-17 2007-07-19 Cree, Inc. Methods of fabricating transistors including supported gate electrodes and related devices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
G. Gradinaru, T. S. Sudarshan, S. A. Gradinaru, W. Mitchell, and H. M. Hobgood, Electrical properties of high resistivity 6H-SiC under high temperature/high field stress, (1997), Appl. Phys. Lett. 70, 735 *
M. Kanamw T. Kikkawa and K. Joshin, A 100-W High-Gain AIGaN/GaN HEMT Power Amplifier on a Conductive N-Sic Substrate for Wireless Base Station Applications, 2004, EEE, pages 799-802 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120211763A1 (en) * 2011-02-22 2012-08-23 Covalent Materials Corporation Nitride semiconductor substrate and method of manufacturing the same
US8785942B2 (en) * 2011-02-22 2014-07-22 Covalent Materials Corporation Nitride semiconductor substrate and method of manufacturing the same
US20130161709A1 (en) * 2011-12-21 2013-06-27 Fujitsu Limited Semiconductor device and method of manufacturing the same
US20150171173A1 (en) * 2012-09-13 2015-06-18 Panasonic Intellectual Property Management Co., Ltd. Nitride semiconductor structure
US9401403B2 (en) * 2012-09-13 2016-07-26 Panasonic Intellectual Property Management Co., Ltd. Nitride semiconductor structure
US20200266292A1 (en) * 2019-02-19 2020-08-20 AZ Power, Inc Composite substrates of conductive and insulating or semi-insulating silicon carbide for gallium nitride devices
WO2022149788A1 (en) * 2021-01-08 2022-07-14 한국산업기술대학교산학협력단 High-efficiency nitride-based photodetector
KR20220100749A (en) * 2021-01-08 2022-07-18 한국공학대학교산학협력단 High efficiency nitride-based photo detector
KR102485133B1 (en) 2021-01-08 2023-01-09 한국공학대학교 산학협력단 High efficiency nitride-based photo detector

Also Published As

Publication number Publication date
US8030164B2 (en) 2011-10-04
US20090065787A1 (en) 2009-03-12
JP5274245B2 (en) 2013-08-28
WO2007116517A1 (en) 2007-10-18
JPWO2007116517A1 (en) 2009-08-20

Similar Documents

Publication Publication Date Title
US8030164B2 (en) Compound semiconductor structure
US8193539B2 (en) Compound semiconductor device using SiC substrate and its manufacture
US8603871B2 (en) Compound semiconductor device and its manufacture method
US8450782B2 (en) Field effect transistor, method of manufacturing field effect transistor, and method of forming groove
US8044492B2 (en) Compound semiconductor device including AIN layer of controlled skewness
EP2346071B1 (en) Compound semiconductor device and method for manufacturing the same
US8030638B2 (en) Quasi single crystal nitride semiconductor layer grown over polycrystalline SiC substrate
US20100123139A1 (en) Semiconductor wafer, semiconductor device, semiconductor wafer manufacturing method and semiconductor device manufacturing method
JP5436819B2 (en) High-frequency semiconductor element, epitaxial substrate for forming high-frequency semiconductor element, and method for producing epitaxial substrate for forming high-frequency semiconductor element
JP2019534583A (en) High breakdown voltage gallium nitride high electron mobility transistor and method for forming the same
JP2006114652A (en) Semiconductor epitaxial wafer and field effect transistor
JP5746927B2 (en) Semiconductor substrate, semiconductor device, and method of manufacturing semiconductor substrate
US20230104038A1 (en) Epitaxial structure for high-electron-mobility transistor and method for manufacturing the same
JP2007042936A (en) Group iii-v compound semiconductor epitaxial wafer
JP5534049B2 (en) Compound semiconductor wafer having polycrystalline SiC substrate, compound semiconductor device, and manufacturing method thereof
CN219393401U (en) High-integration enhanced GaN-HEMT
JP2024015771A (en) semiconductor equipment
JP2024015770A (en) semiconductor equipment
JP2006114653A (en) Semiconductor epitaxial wafer and field-effect transistor
JPH11312692A (en) Semiconductor epitaxial substrate

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION