US20120104517A1 - Package structure with micro-electromechanical element and manufacturing method thereof - Google Patents

Package structure with micro-electromechanical element and manufacturing method thereof Download PDF

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Publication number
US20120104517A1
US20120104517A1 US12/959,595 US95959510A US2012104517A1 US 20120104517 A1 US20120104517 A1 US 20120104517A1 US 95959510 A US95959510 A US 95959510A US 2012104517 A1 US2012104517 A1 US 2012104517A1
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layer
micro
package
solder resist
bonding wires
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US8610272B2 (en
Inventor
Chun-An Huang
Hsin-Yi Liao
Shih-Kuang Chiu
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Assigned to SILICONWARE PRECISION INDUSTRIES CO., LTD. reassignment SILICONWARE PRECISION INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIU, SHIH-KUANG, HUANG, CHUN-AN, LIAO, HSIN-YI
Publication of US20120104517A1 publication Critical patent/US20120104517A1/en
Priority to US14/078,845 priority Critical patent/US8741693B2/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/096—Feed-through, via through the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to package structures and manufacturing methods thereof, and more particularly, to a package structure having a micro-electromechanical element and a manufacturing method thereof.
  • a micro-electromechanical element system is a micro-device that incorporates both electrical and mechanical functions.
  • the MEMS is manufactured by a variety of microfabrication techniques.
  • a micro-electromechanical element is first provided on the surface of a substrate, and a protective mask or an encapsulant is then encapsulated to protect the micro-electromechanical element from external damage, thereby obtaining a package structure with a micro-electromechanical element.
  • FIG. 1 a cross-sectional diagram of a conventional package structure with a micro-electromechanical element is shown.
  • a micro-electromechanical element 11 that functions as a pressure sensing element is disposed on a substrate 10 of land grid array (LGA) type, and an electrical connecting end 111 of the micro-electromechanical element 11 is connected to an electrical connecting end 101 of the LGA substrate 10 through wire bonding, thereby electrically connecting the micro-electromechanical element 11 and the substrate 10 .
  • LGA land grid array
  • a metal cap 12 is formed on the surface of the package substrate 10 to encase the micro-electromechanical element 11 therein. The metal cap 12 protects the micro-electromechanical element 11 from external contamination or damage.
  • One shortcoming of the package structure for the micro-electromechanical element is that the size is too large, which fails to meet the need for smaller, lighter and more compact end products.
  • FINEMEMS Inc. has filed a patent application (US patent application publication number 2006/0185429) relating to a wafer-level pressure sensing package substrate.
  • a micro-electromechanical element 11 that functions as a pressure sensing element is directly manufactured on a silicon substrate 13 , and then a glass cap 14 is bonded on the top of the micro-electromechanical element 11 .
  • TSV Through Silicon Via
  • FIGS. 3A to 3C are cross-section diagrams depicting the conventional package structure with the micro-electromechanical element and its manufacturing method.
  • the steps of manufacturing this third conventional structure first requires using a plurality of bonding wires 22 to electrically connect a silicon cap 21 and an electrical connecting pad 201 on the silicon substrate 20 ; enclosing the silicon cap 21 and the bonding wires 22 with a package layer 23 to protect the bonding wires 22 from external damage; and then removing part of the package layer 23 and the bonding wires 22 by lapping to expose the ends of the bonding wires 22 .
  • the locations where the ends of the bonding wires 221 are exposed may not be consistent, because the locations where ends of the bonding wires 221 are exposed depend on the curvature and height of bonding. These two parameters have to be precisely controlled to obtain consistency in the locations where the ends of the bonding wires 221 are exposed.
  • the present invention provides a package structure with a micro-electromechanical element.
  • the package structure includes: a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to the electrical contact of the micro-electromechanical, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires.
  • the present invention further discloses a method for manufacturing a package structure with a micro-electromechanical element.
  • the method includes: preparing a carrier board with a first surface and a second surface opposing to the first surface; providing a plurality of micro-electromechanical elements on the first surface of the carrier board, each of the micro-electromechanical elements having a plurality of electrical contacts; connecting the electrical contacts and the first surface of the carrier board by a plurality of bonding wires; forming a package layer on the first surface of the carrier board to enclose the micro-electromechanical element, the electrical contacts, and the bonding wires; removing the carrier board to expose one end of each of the bonding wires; and forming a build-up layer structure on the surface of the package layer that exposes the bonding wires, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires.
  • the package structure with the micro-electromechanical element of the present invention first uses the bonding wires to electrically connect to the micro-electromechanical element, and the package layer to enclose the bonding wires and the micro-electromechanical element, and then removes the carrier board to expose one ends of the bonding wires for external electrically connection. Since it is easier to control the locations of the exposed ends of the bonding wires, and the manufacturing method of the present invention is highly compatible with the current build-up layer processes, the overall cost can be favorably reduced.
  • FIG. 1 is a cross-sectional diagram of a conventional package structure with a micro-electromechanical element
  • FIG. 2 is a cross-sectional diagram of another conventional package structure with a micro-electromechanical element
  • FIGS. 3A to 3C are cross-sectional diagrams depicting yet another conventional package structure with a micro-electromechanical element and its manufacturing;
  • FIGS. 4A to 4G are cross-sectional diagrams depicting a package structure with a micro-electromechanical element and its manufacturing method according to a first embodiment of the present invention, wherein FIGS. 4 B′ and 4 C′ are top views of FIGS. 4B and 4C , respectively, and FIG. 4 G′ is another implementing aspect of FIG. 4G ; and
  • FIGS. 5A to 5D are cross-sectional diagrams depicting a package structure with a micro-electromechanical element and its manufacturing method according to a second embodiment of the present invention.
  • FIGS. 4A to 4G cross-sectional diagrams depicting a package structure with a micro-electromechanical element and its manufacturing method according to a first embodiment of the present invention are shown.
  • FIGS. 4 B′ and 4 C′ are top views of FIGS. 4B and 4C
  • FIG. 4 G′ is another implementing aspect of FIG. 4G
  • a carrier board 30 is prepared that has a first surface 30 a and a second surface 30 b opposing to the first surface 30 a .
  • the carrier board 30 may include a substrate 301 and an adhesive layer 302 attached thereon.
  • the exposed surface of the adhesive layer 302 is the first surface 30 a
  • the exposed surface of the substrate 301 is the second surface 30 b .
  • the substrate 301 can be made of silicon.
  • a plurality of micro-electromechanical elements 31 are provided on the first surface 30 a of the carrier board 30 .
  • Each of the micro-electromechanical elements 31 has a plurality of electrical contacts 32 provided thereon.
  • the micro-electromechanical elements 31 can be gyroscopes, accelerometers, RF MEMS elements, and the like.
  • micro-electromechanical elements 31 may have a cap (not shown) disposed thereon for protection.
  • a plurality of bonding wires 33 are connected between the electrical contacts 32 and the first surface 30 a of the carrier board 30 , and one ends of the bonding wires 33 are fixed in place by the adhesive layer 302 on the substrate 301 .
  • a package layer 34 is formed on the first surface 30 a of the carrier board 30 to enclose the micro-electromechanical elements 31 , the electrical contacts 32 and the bonding wires 33 .
  • the carrier board 30 is removed to expose one ends of the bonding wires 33 , wherein the method for removing the carrier board (separating the adhesive layer 302 and the structure above it) includes irradiation, heating, etching, or lapping.
  • a build-up layer structure 35 is formed on the surface of the package layer 34 that exposes the bonding wires 33 .
  • the build-up layer structure 35 includes at least a dielectric layer 351 and a plurality of conductive blind vias 353 formed in the dielectric layer 351 and electrically connected to one ends of the bonding wires 33 .
  • a solder resist layer 36 is formed on the build-up layer structure 35 .
  • a plurality of solder resist openings 360 are formed in the solder resist layer 36 to expose a portion of the surface of the conductive blind vias 353 , and a solder ball 37 is formed on the exposed conductive blind via 353 in each of the solder resist openings 360 .
  • the solder balls for external electrical connections are disposed directly on the conductive blind vias 353 where bonding wires 33 are exposed.
  • the build-up layer structure 35 may further include a trace layer 352 on the at least one dielectric layer 351 (referring to FIG. 4 G′), and the conductive blind vias 353 electrically connect the trace layer 352 and one ends of the bonding wires 33 .
  • a portion of the surface of the trace layer 352 (such as the surface that is not the conductive blind vias 353 end) is exposed from the solder resist openings 360 .
  • one ends of the bonding wires 33 are fanned out by the trace layer 352 , and solder balls 37 are formed on the exposed trace layer 352 in the solder resist openings 360 (referring to FIG. 4 G′).
  • singulation is performed to obtain a plurality of package structures with a micro-electromechanical element.
  • the build-up layer structure 35 is formed on the surface of the package layer 34 that exposes the bonding wires 33 .
  • the build-up layer structure 35 further includes the trace layer 352 formed on the at least one dielectric layer 351 , and the conductive blind vias 353 electrically connect between the trace layer 352 and one ends of the bonding wires 33 , thereby completing Redistribution Line (RDL) process.
  • RDL Redistribution Line
  • FIGS. 5A to 5D cross-sectional diagrams depicting a package structure with a micro-electromechanical element and its manufacturing method according to a second embodiment of the present invention are shown.
  • the second embodiment is similar to the first embodiment, but the main difference is that the carrier board 30 of the second embodiment is made of a single material, and the material is metal, or preferably aluminum. As such, one ends of the bonding wires 33 can be fixed in place to the metal carrier board 30 .
  • the rest is similar to the first embodiment, and will not be described further.
  • the present invention further discloses a package structure having a micro-electromechanical element.
  • the package structure includes: a micro-electromechanical element 31 having a plurality of electrical contacts 32 ; a package layer 34 enclosing the micro-electromechanical element 31 and the electrical contacts 32 , with a bottom surface 310 of the micro-electromechanical element 31 exposed from a lower surface 340 of the package layer 34 ; a plurality of bonding wires 33 embedded in the package layer 34 , each of the bonding wires 33 having one end connected to the electrical contact 32 of the micro-electromechanical 31 , and the other end exposed from the lower surface 340 of the package layer 34 ; and a build-up layer structure 35 provided on the lower surface 340 of the package layer 34 , the build-up layer 35 including at least one dielectric layer 351 and a plurality of conductive blind vias 353 formed in the dielectric layer 351 and electrically connected to one end of the bonding wire 33 .
  • solder resist layer 36 may be further included on the build-up layer structure 35 .
  • the solder resist layer 36 has a plurality of solder resist openings 360 to expose a portion of the surface of the conductive blind vias 353 from these solder resist openings 360 .
  • the build-up layer structure 35 may further include a trace layer formed on the at least one dielectric layer 351 , and the conductive blind vias 353 are electrically connected between the trace layer and one ends of the bonding wires 33 .
  • the package structure may further include a solder resist layer 36 provided on the build-up layer structure 35 .
  • the solder resist layer 36 has a plurality of solder resist openings 360 to expose a portion of the surface of the trace layer from these solder resist openings 360 .
  • solder balls 37 may be further included on the exposed trace layer in each solder resist opening 360 .
  • the micro-electromechanical element 31 can be a gyroscope, an accelerometer, a RF MEMS element, and the like.
  • the package structure with the micro-electromechanical element of the present invention first uses the bonding wires to electrically connect to the micro-electromechanical element, and the package layer to enclose the bonding wires and the micro-electromechanical element, and then removes the carrier board to expose one ends of the bonding wires for external electrically connection.
  • the manufacturing method of the present invention is highly compatible with the current build-up layer processes, facilitating the reduction of the overall cost.

Abstract

A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high.

Description

    FIELD OF THE INVENTION
  • The present invention relates to package structures and manufacturing methods thereof, and more particularly, to a package structure having a micro-electromechanical element and a manufacturing method thereof.
    • BACKGROUND OF THE INVENTION
  • A micro-electromechanical element system (MEMS) is a micro-device that incorporates both electrical and mechanical functions. The MEMS is manufactured by a variety of microfabrication techniques. A micro-electromechanical element is first provided on the surface of a substrate, and a protective mask or an encapsulant is then encapsulated to protect the micro-electromechanical element from external damage, thereby obtaining a package structure with a micro-electromechanical element.
  • Referring to FIG. 1, a cross-sectional diagram of a conventional package structure with a micro-electromechanical element is shown. A micro-electromechanical element 11 that functions as a pressure sensing element is disposed on a substrate 10 of land grid array (LGA) type, and an electrical connecting end 111 of the micro-electromechanical element 11 is connected to an electrical connecting end 101 of the LGA substrate 10 through wire bonding, thereby electrically connecting the micro-electromechanical element 11 and the substrate 10. Finally, a metal cap 12 is formed on the surface of the package substrate 10 to encase the micro-electromechanical element 11 therein. The metal cap 12 protects the micro-electromechanical element 11 from external contamination or damage. One shortcoming of the package structure for the micro-electromechanical element is that the size is too large, which fails to meet the need for smaller, lighter and more compact end products.
  • Refer to FIG. 2. In order to reduce the overall size of the package structure with the micro-electromechanical element, FINEMEMS Inc. has filed a patent application (US patent application publication number 2006/0185429) relating to a wafer-level pressure sensing package substrate. In the package substrate, a micro-electromechanical element 11 that functions as a pressure sensing element is directly manufactured on a silicon substrate 13, and then a glass cap 14 is bonded on the top of the micro-electromechanical element 11.
  • However, in the silicon substrate 13 a sensing cavity 131 and vias passing through the entire silicon substrate 13 are formed, so a Through Silicon Via (TSV) technique is required. This technique uses KOH as an etchant to form the vias or grooves.
  • Compared with the first prior-art structure, the structure disclosed by U.S. patent application publication number 2006/0185429 dramatically reduces the overall volume of the package structure with the micro-electromechanical element, but TSV technique for forming vias and grooves is costly.
  • As a result, as shown in FIG. 3C, modern MEMS industry has developed a package structure that provides an electrical connection path from a micro-electromechanical sensing element 202 on a silicon substrate 20 to the surface of the package structure by bonding wires 221, such that the size of the package structure with the micro-electromechanical element can be greatly reduced, without the need for TSV technique, and manufacturing cost can also be reduced.
  • Refer to FIGS. 3A to 3C, which are cross-section diagrams depicting the conventional package structure with the micro-electromechanical element and its manufacturing method. The steps of manufacturing this third conventional structure first requires using a plurality of bonding wires 22 to electrically connect a silicon cap 21 and an electrical connecting pad 201 on the silicon substrate 20; enclosing the silicon cap 21 and the bonding wires 22 with a package layer 23 to protect the bonding wires 22 from external damage; and then removing part of the package layer 23 and the bonding wires 22 by lapping to expose the ends of the bonding wires 22. The locations where the ends of the bonding wires 221 are exposed may not be consistent, because the locations where ends of the bonding wires 221 are exposed depend on the curvature and height of bonding. These two parameters have to be precisely controlled to obtain consistency in the locations where the ends of the bonding wires 221 are exposed.
  • Therefore, there is a need for a technical solution that makes the locations where the ends of the bonding wires are exposed in the package structure with the micro-electromechanical element more consistent while reducing manufacturing cost.
    • SUMMARY OF THE INVENTION
  • In light of the forgoing drawbacks, the present invention provides a package structure with a micro-electromechanical element. The package structure includes: a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to the electrical contact of the micro-electromechanical, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires.
  • The present invention further discloses a method for manufacturing a package structure with a micro-electromechanical element. The method includes: preparing a carrier board with a first surface and a second surface opposing to the first surface; providing a plurality of micro-electromechanical elements on the first surface of the carrier board, each of the micro-electromechanical elements having a plurality of electrical contacts; connecting the electrical contacts and the first surface of the carrier board by a plurality of bonding wires; forming a package layer on the first surface of the carrier board to enclose the micro-electromechanical element, the electrical contacts, and the bonding wires; removing the carrier board to expose one end of each of the bonding wires; and forming a build-up layer structure on the surface of the package layer that exposes the bonding wires, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires.
  • It can be seen from the above, the package structure with the micro-electromechanical element of the present invention first uses the bonding wires to electrically connect to the micro-electromechanical element, and the package layer to enclose the bonding wires and the micro-electromechanical element, and then removes the carrier board to expose one ends of the bonding wires for external electrically connection. Since it is easier to control the locations of the exposed ends of the bonding wires, and the manufacturing method of the present invention is highly compatible with the current build-up layer processes, the overall cost can be favorably reduced.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
  • FIG. 1 is a cross-sectional diagram of a conventional package structure with a micro-electromechanical element;
  • FIG. 2 is a cross-sectional diagram of another conventional package structure with a micro-electromechanical element;
  • FIGS. 3A to 3C are cross-sectional diagrams depicting yet another conventional package structure with a micro-electromechanical element and its manufacturing;
  • FIGS. 4A to 4G are cross-sectional diagrams depicting a package structure with a micro-electromechanical element and its manufacturing method according to a first embodiment of the present invention, wherein FIGS. 4B′ and 4C′ are top views of FIGS. 4B and 4C, respectively, and FIG. 4G′ is another implementing aspect of FIG. 4G; and
  • FIGS. 5A to 5D are cross-sectional diagrams depicting a package structure with a micro-electromechanical element and its manufacturing method according to a second embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE EMBODIMENTS
  • The present invention is described by the following specific embodiments. Those with ordinary skill in the art can readily understand the other advantages and functions of the present invention after reading the disclosure of this specification. The present invention can also be implemented with different embodiments. Various details described in this specification can be modified based on different viewpoints and applications without departing from the scope of the present invention.
  • It should be noted that the structures, proportions and sizes depicted in the attached drawing are intended to illustrate and accompany the disclosure of this specification and to facilitate understanding for those with ordinary skill in the art, they are in no way limit the present invention, and have no substantial meanings. Any structure modification, changes in proportions or adjustment in sizes, without influencing technical effects generated and objectives achieved by the present invention, shall fall within the scope of the technical contents disclosed in the present invention. Meanwhile, terms such as “top”, “down”, “one” and “a” used herein are convenient usage for descriptions, and in no way limit the implementing scope of the present invention, therefore, changes or modifications of relative relationships, without substantial changes to the technical contents, are construed to be the scope that can be implemented by the present invention.
    • First Embodiment
  • Referring to FIGS. 4A to 4G, cross-sectional diagrams depicting a package structure with a micro-electromechanical element and its manufacturing method according to a first embodiment of the present invention are shown. FIGS. 4B′ and 4C′ are top views of FIGS. 4B and 4C, and FIG. 4G′ is another implementing aspect of FIG. 4G As shown in FIG. 4A, a carrier board 30 is prepared that has a first surface 30 a and a second surface 30 b opposing to the first surface 30 a. The carrier board 30 may include a substrate 301 and an adhesive layer 302 attached thereon. The exposed surface of the adhesive layer 302 is the first surface 30 a, and the exposed surface of the substrate 301 is the second surface 30 b. The substrate 301 can be made of silicon.
  • As shown in FIGS. 4B and 4B′, a plurality of micro-electromechanical elements 31 are provided on the first surface 30 a of the carrier board 30. Each of the micro-electromechanical elements 31 has a plurality of electrical contacts 32 provided thereon. The micro-electromechanical elements 31 can be gyroscopes, accelerometers, RF MEMS elements, and the like.
  • It should be noted that the micro-electromechanical elements 31 may have a cap (not shown) disposed thereon for protection.
  • As shown in FIGS. 4C and 4C′, a plurality of bonding wires 33 are connected between the electrical contacts 32 and the first surface 30 a of the carrier board 30, and one ends of the bonding wires 33 are fixed in place by the adhesive layer 302 on the substrate 301.
  • As shown in FIG. 4D, a package layer 34 is formed on the first surface 30 a of the carrier board 30 to enclose the micro-electromechanical elements 31, the electrical contacts 32 and the bonding wires 33.
  • As shown in FIG. 4E, the carrier board 30 is removed to expose one ends of the bonding wires 33, wherein the method for removing the carrier board (separating the adhesive layer 302 and the structure above it) includes irradiation, heating, etching, or lapping.
  • As shown in FIG. 4F, a build-up layer structure 35 is formed on the surface of the package layer 34 that exposes the bonding wires 33. The build-up layer structure 35 includes at least a dielectric layer 351 and a plurality of conductive blind vias 353 formed in the dielectric layer 351 and electrically connected to one ends of the bonding wires 33. A solder resist layer 36 is formed on the build-up layer structure 35. A plurality of solder resist openings 360 are formed in the solder resist layer 36 to expose a portion of the surface of the conductive blind vias 353, and a solder ball 37 is formed on the exposed conductive blind via 353 in each of the solder resist openings 360.
  • It should be noted that, in the implementing aspect shown in FIG. 4F the solder balls for external electrical connections are disposed directly on the conductive blind vias 353 where bonding wires 33 are exposed. However, in other implementing aspects the build-up layer structure 35 may further include a trace layer 352 on the at least one dielectric layer 351 (referring to FIG. 4G′), and the conductive blind vias 353 electrically connect the trace layer 352 and one ends of the bonding wires 33. A portion of the surface of the trace layer 352 (such as the surface that is not the conductive blind vias 353 end) is exposed from the solder resist openings 360. In other words, one ends of the bonding wires 33 are fanned out by the trace layer 352, and solder balls 37 are formed on the exposed trace layer 352 in the solder resist openings 360 (referring to FIG. 4G′). The above aspects can be easily understood by those with ordinary skill in the art, and will not be further described.
  • As shown in FIG. 4G, singulation is performed to obtain a plurality of package structures with a micro-electromechanical element.
  • As shown in FIG. 4G′, another implementing aspect in which the build-up layer structure 35 is formed on the surface of the package layer 34 that exposes the bonding wires 33 is provided. In this aspect, the build-up layer structure 35 further includes the trace layer 352 formed on the at least one dielectric layer 351, and the conductive blind vias 353 electrically connect between the trace layer 352 and one ends of the bonding wires 33, thereby completing Redistribution Line (RDL) process.
    • Second Embodiment
  • Referring to FIGS. 5A to 5D, cross-sectional diagrams depicting a package structure with a micro-electromechanical element and its manufacturing method according to a second embodiment of the present invention are shown.
  • The second embodiment is similar to the first embodiment, but the main difference is that the carrier board 30 of the second embodiment is made of a single material, and the material is metal, or preferably aluminum. As such, one ends of the bonding wires 33 can be fixed in place to the metal carrier board 30. The rest is similar to the first embodiment, and will not be described further.
  • The present invention further discloses a package structure having a micro-electromechanical element. The package structure includes: a micro-electromechanical element 31 having a plurality of electrical contacts 32; a package layer 34 enclosing the micro-electromechanical element 31 and the electrical contacts 32, with a bottom surface 310 of the micro-electromechanical element 31 exposed from a lower surface 340 of the package layer 34; a plurality of bonding wires 33 embedded in the package layer 34, each of the bonding wires 33 having one end connected to the electrical contact 32 of the micro-electromechanical 31, and the other end exposed from the lower surface 340 of the package layer 34; and a build-up layer structure 35 provided on the lower surface 340 of the package layer 34, the build-up layer 35 including at least one dielectric layer 351 and a plurality of conductive blind vias 353 formed in the dielectric layer 351 and electrically connected to one end of the bonding wire 33.
  • In the above package structure having the micro-electromechanical element, a solder resist layer 36 may be further included on the build-up layer structure 35. The solder resist layer 36 has a plurality of solder resist openings 360 to expose a portion of the surface of the conductive blind vias 353 from these solder resist openings 360.
  • Moreover, in the above package structure having the micro-electromechanical element, the build-up layer structure 35 may further include a trace layer formed on the at least one dielectric layer 351, and the conductive blind vias 353 are electrically connected between the trace layer and one ends of the bonding wires 33. The package structure may further include a solder resist layer 36 provided on the build-up layer structure 35. The solder resist layer 36 has a plurality of solder resist openings 360 to expose a portion of the surface of the trace layer from these solder resist openings 360.
  • In the above package structure having the micro-electromechanical element, solder balls 37 may be further included on the exposed trace layer in each solder resist opening 360.
  • In the above package structure having the micro-electromechanical element, the micro-electromechanical element 31 can be a gyroscope, an accelerometer, a RF MEMS element, and the like.
  • In conclusion, the package structure with the micro-electromechanical element of the present invention first uses the bonding wires to electrically connect to the micro-electromechanical element, and the package layer to enclose the bonding wires and the micro-electromechanical element, and then removes the carrier board to expose one ends of the bonding wires for external electrically connection. Compared to the prior art, it is easier to control the locations of the exposed ends of the bonding wires, so the overall accuracy and yield can be controlled more easily. Moreover, the manufacturing method of the present invention is highly compatible with the current build-up layer processes, facilitating the reduction of the overall cost.
  • The above embodiments are only used to illustrate the principles of the present invention, and they should not be construed as to limit the present invention in any way. The above embodiments can be modified by those with ordinary skill in the art without departing from the scope of the present invention as defined in the following appended claims.

Claims (20)

1. A package structure, comprising:
a micro-electromechanical element having a plurality of electrical contacts;
a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer;
a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts of the micro-electromechanical element, and the other end exposed from the lower surface of the package layer; and
a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to the other ends of the bonding wires.
2. The package structure of claim 1, further comprising a solder resist layer having a plurality of solder resist openings provided on the build-up layer structure to expose a portion of the surface of the conductive blind vias from the solder resist openings.
3. The package structure of claim 2, further comprising a solder ball provided on the exposed conductive blind via in each of the solder resist openings.
4. The package structure of claim 1, wherein the build-up layer structure further includes a trace layer on the at least one dielectric layer, and the conductive blind vias electrically connect the trace layer and the bonding wires.
5. The package structure of claim 4, further comprising a solder resist layer having a plurality of solder resist openings provided on the build-up layer structure to expose a portion of the surface of the trace layer from the solder resist openings.
6. The package structure of claim 5, further comprising a solder ball provided on the exposed trace layer in each of the solder resist openings.
7. The package structure of claim 1, wherein the micro-electromechanical element is a gyroscope, an accelerometer, or an RF MEMS element.
8. A method for manufacturing a package structure having a micro-electromechanical element, comprising:
preparing a carrier board having a first surface and a second surface opposing the first surface;
providing a plurality of micro-electromechanical elements on the first surface of the carrier board, each of the micro-electromechanical elements having a plurality of electrical contacts;
connecting the electrical contacts and the first surface of the carrier board by a plurality of bonding wires;
forming a package layer on the first surface of the carrier board to enclose the micro-electromechanical element, the electrical contacts, and the bonding wires;
removing the carrier board to expose one end of each of the bonding wires; and
forming a build-up layer structure on the surface of the package layer that exposes the bonding wires, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires.
9. The method of claim 8, wherein the carrier board further includes a substrate and an adhesive layer attached thereon, the exposed surface of the adhesive layer is the first surface, and the exposed surface of the substrate is the second surface.
10. The method of claim 9, wherein the substrate is a material containing silicon.
11. The method of claim 8, further comprising forming a solder resist layer having a plurality of solder resist openings on the build-up layer structure to expose a portion of the surface of the conductive blind vias from the solder resist openings.
12. The method of claim 11, further comprising forming a solder ball on the exposed conductive blind via in each of the solder resist openings.
13. The method of claim 12, further comprising performing singulation to obtain a plurality of package structures each with the micro-electromechanical element.
14. The method of claim 8, wherein the build-up layer structure further includes a trace layer on the at least one dielectric layer, and the conductive blind vias electrically connect the trace layer and one ends of the bonding wires.
15. The method of claim 14, further comprising forming a solder resist layer having a plurality of solder resist openings on the build-up layer structure to expose a portion of the surface of the trace layer from the solder resist openings.
16. The method of claim 15, further comprising forming a solder ball provided on the exposed trace layer in each of the solder resist openings.
17. The method of claim 16, further comprising performing singulation to obtain a plurality of package structures each with the micro-electromechanical element.
18. The method of claim 8, wherein the material of the carrier board is aluminum.
19. The method of claim 8, wherein removing the carrier board includes irradiation, heating, etching, or lapping
20. The method of claim 8, wherein the micro-electromechanical element is a gyroscope, an accelerometer, or an RF MEMS element.
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US20140080242A1 (en) 2014-03-20

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