US20120327769A1 - System and Method for Increasing Input/Output Speeds in a Network Switch - Google Patents
System and Method for Increasing Input/Output Speeds in a Network Switch Download PDFInfo
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- US20120327769A1 US20120327769A1 US13/165,400 US201113165400A US2012327769A1 US 20120327769 A1 US20120327769 A1 US 20120327769A1 US 201113165400 A US201113165400 A US 201113165400A US 2012327769 A1 US2012327769 A1 US 2012327769A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/60—Software-defined switches
Definitions
- the present invention relates generally to network switches and, more particularly, to a system and method for increasing input/output speeds in a network switch.
- a system and/or method for increasing input/output speeds in a network switch substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
- FIG. 1 illustrates an embodiment of a physical layer device according to the present invention.
- FIG. 2 illustrates an example embodiment of data flow marking through modification of a synchronization header.
- FIG. 3 illustrates an example embodiment of data flow marking using multi-lane distribution PCS lane identifiers.
- FIG. 4 illustrates a first embodiment of an application of a 100 GbE PHY according to the present invention.
- FIG. 5 illustrates a second embodiment of an application of a 100 GbE PHY according to the present invention.
- a network switch can support over 100 ports, each of which can be operating at 10.3125 gbps.
- Increasing switch bandwidth can be effected through an increase in the I/O speeds.
- the switch bandwidth can be increased by increasing the I/O speed to 25.7 gbps. With this I/O speed increase, only four lanes would be required to transport 100 GbE traffic. This is in contrast to a conventional use of ten lanes to transport 100 GbE traffic.
- physical layer device of the present invention can be embodied as a 100 GbE physical layer device that supports a transport of various combinations of 10 GbE and 40 GbE data flows through I/O speeds of 25.7 gbps. As will be described, the transport of various combinations of 10 GbE and 40 GbE data flows is performed efficiently without a conventional waste of I/O bandwidth.
- the example embodiment of 100 GbE physical layer device 100 includes two data flow paths for each direction of traffic, wherein each data flow path supports a transport of half of the data flows in a single direction. As would be appreciated, in another embodiment, all of the data flows in a single direction can be handled by a single data flow path.
- Each data flow path is designed to receive as input five 10.3125 gbps data flows.
- the lower data flow path receives the five 10G data flows denoted as RX_IN[0:4], while the upper data flow path receives the five 10G data flows denoted as RX_IN[5:9].
- RX_IN[0:4] receives the five 10G data flows
- RX_IN[5:9] receives the five 10G data flows.
- physical layer device 100 facilitate an increase of I/O speed from 10.3125 gbps to 25.7 gbps, thereby narrowing the I/O interface.
- 5 to 2 gearbox 105 does not use simple bit multiplexing to adapt a set of input lanes to a set of output lanes at a 5:2 ratio. Rather, 5 to 2 Gearbox 105 is designed to operate on data flows that have been marked with a data flow identifier by 10 G PCS/Lane Marker module 104 . In general, the addition of data flow identifiers by 10 G PCS/Lane Marker module 104 enables an inverse 2 to 5 gearbox to decode, align, and identify each data flow. Inverse 2 to 5 gearbox can then present each data flow to a specific location based on the data flow identifier.
- the 10 G traffic on RX_IN[5:9] are stripped at the 66-bit boundary for transport onto 25 G data flows TX_Out[2:3], while the 10 G traffic on RX_IN[0:4] are stripped at the 66-bit boundary for transport onto 25 G data flows TX_Out[0:1].
- the 66-bit boundaries are defined by the 66-bit frames resulting from the 64B/66B PCS coding process. These 66-bit frames include 64 bits of data along with a 2-bit synchronization (sync) header.
- the 66-bit blocks are either data frames or control frames.
- the sync header is ‘01’ for data frames and ‘10’ for control frames.
- the remaining 64 bits of the 66-bit frame contain the scrambled payload.
- the sync header on data flows 0 and 5 are modified every 1000 66-bit blocks from ‘10’ to ‘11’, a previously unused sync header bit combination.
- the next immediate control frame sync header is then changed to from ‘10’ to ‘00’, which is also a previously unused sync header bit combination.
- This example marking of the sync headers in data flows 0 and 5 with previously unused sync header bit combinations is illustrated in FIG. 2 . It should be noted that in one embodiment, no modification is made to the sync header of a data frame in order not to potentially increase undetected error probability.
- control frame sync headers can be implementation dependent.
- particular data flow or data flows that are chosen for marking can also be implementation dependent.
- marking of one or more data flows enables an inverse gearbox to decode, align, and identify each data flow.
- the payload within a control frame can be modified for data flow marking.
- a fiber channel control frame payload can be unscrambled and its contents replaced with an unused signal order set that identifies the data flow.
- the particular unused signal order set used that identifies the data flow would be implementation dependent.
- the unused signal ordered set would be replaced with the data that previously existed in the payload of the control frame.
- data flow marking is facilitated by occasionally replacing standard Ethernet Idle frames with Multi-Lane Distribution (MLD) PCS lane identifiers used as physical data flow identifiers.
- MLD PCS lane identifiers are defined in IEEE 802.3 Clause 82. Table 1 below identifies the data flow identifier components that are arranged in the format illustrated in FIG. 3 .
- Bit Interleaved Parity (BIP) field BIP 7 is a bit-wise inversion of BIP 3 .
- gearbox has 10 input data flows
- only the first ten MLD PCS lane identifiers need be used as physical data flow identifiers.
- additional MLD PCS lane identifiers can be used to accommodate gearboxes that have greater than ten input data flows.
- the 10 G traffic on RX_IN[5:9] are stripped at the 66-bit boundary for transport onto 25 G data flows TX_Out[2:3], while the 10 G traffic on RX_IN[0:4] are stripped at the 66-bit boundary for transport onto 25 G data flows TX_Out[0:1].
- the 66-bit stripped Ethernet idle frame is replaced with the physical data flow identifiers defined above in Table 1 to identify the physical data flows.
- the frequency at which the Ethernet IPG idle data is replaced with physical data flow identifiers would be implementation dependent.
- the 66-bit data would be decoded by the inverse gearbox to identify each data flow per the included physical data flow identifiers.
- the inverse gearbox would then replace the physical data flow identifier with the Ethernet idle frame before presentation of the data at a specific output port.
- 10 G PCS/Lane Marker module 104 in physical layer device 100 to mark the data flows that are received at the input (e.g., RX_IN[5:9]).
- the marked data flows are then passed to 5 to 2 Gearbox 105 .
- 5 to 2 Gearbox 105 receives the 66-bit data flow frames from the five 10G input data flows marked by 10 G PCS/Lane Marker module 104 and generates two higher-rate 25 G data flows in accordance with a frame distribution scheme defined by the 5:2 ratio.
- a 5 to 2 gearbox can also be defined that can generate four 25 G data flows from ten 10 G data flows.
- Gearbox 105 passes the two higher rate 25G data flows to Selector module 106 .
- Selector module 106 also receives loopback and pattern generation inputs.
- Selector module 106 passes one of the selected inputs to Multiplexer (Mux)/Feed Forward Equalizer (FFE) module 107 .
- Mux/FFE module 107 then outputs the two higher rate 25G data flows as TX_OUT[2:3].
- the two higher rate 25G output data flows represent a higher rate I/O interface that facilitates a narrower interface module.
- the counterpart to the transmit direction in the lower half of physical layer device 100 is the receive direction in the upper half of physical layer device 100 .
- the upper data flow path in the right-to-left direction of physical layer device 100 receives two higher rate 25G data flows as inputs RX_IN[2:3] by Equalization (EQ)/Clock and Data Recovery (CDR) module 111 .
- the signals received by EQ/CDR module 111 then pass through De-Mux module 112 , FIFO module 113 , and De-Skew module 114 before being presented to the inverse 2 to 5 Gearbox 115 .
- a single inverse 4 to 10 gearbox can be used to facilitate a single data flow path.
- 2 to 5 Gearbox 115 is also operative to remove the data flow markers that were inserted by 10 G PCS/Lane Marker module 104 .
- removal of the data flow markers can include the process of reestablishing the 66-bit control frames in their original form. As such, contents of the sync header or the payload can be reestablished in their original form as would be apparent.
- Gearbox 115 passes the five lower rate 10 G data flows to Selector module 116 .
- Selector module 116 also receives loopback and pattern generation inputs.
- Selector module 116 passes one of the selected inputs to Mux module 117 .
- Mux module 107 then outputs the five lower rate 10 G data flows as TX_OUT[5:9].
- FIG. 4 illustrates one embodiment of an example application in providing an interface to a device such as a switch, packet processor, ASIC, etc.
- 100 GbE PHYs 420 , 430 provide a transport mechanism between IF modules 410 and 100 GbE switch 440 .
- PHYs 420 , 430 support a narrower interface 425 between each other using four 25 G data flows that are supported by a 5 to 2 gearbox and an inverse 2 to 5 gearbox.
- One application of such an arrangement is transport to a remote expansion box to support a large number of ports that could not otherwise be supported within a single box.
- a transport application could be applied to the support of an expansion server blade.
- 100 GbE PHY 430 supports a single 100 Gigabit Attachment Unit Interface (CAUI) 435 with switch 440 .
- IF modules 410 can include various combinations of 10 G and 40 G interfaces.
- IF modules 410 can include support for 10 GbE such as 10 GBASE-SR, 10 GBASE-LR, SFP+ Direct Attach Copper, etc., and 40 GbE such as 40 GBASE-SR4, 40 GBASE-LR4, etc.
- IF modules 410 can support ten 10 GbE data flows for delivery over interface 415 . In another arrangement, IF modules 410 can support one 40 GbE data flow and six 10 GbE data flows. In yet another arrangement, IF modules 410 can support two 40 GbE data flows and two 10 GbE data flows. Regardless of the combination of 10/40 GbE data flows that are provided by IF modules 410 for delivery over interface 415 , 100 GbE PHYs 420 , 430 can deliver the 10/40 GbE combination of data flows to switch 440 over CAUI interface 435 . This application illustrates the ability of 100 GbE PHYs 420 , 430 to accommodate legacy traffic in an I/O interface of a switch in an efficient manner.
- interface 435 is based on a 40 Gigabit Attachment Unit Interface (XLAUI).
- XLAUI 40 Gigabit Attachment Unit Interface
- This arrangement illustrates a usage scenario where PHYs 420 , 430 support transport of traffic in a fractional pipe. Assume for example that IF modules 410 support two 40 G data flows. These two 40 G data flows can be carried over interface 425 using four 20 G data flows that are generated by a 5 to 2 gearbox. Each of these 20 G data flows represent a fraction of the true 25 G data flow capacity. After transport between PHYs 420 , 430 , the four 20 G data flows are provided to switch 440 using two XLAUI interfaces 435 .
- XLAUI 40 Gigabit Attachment Unit Interface
- IF modules 410 can support a single 40 G data flow, wherein the 40 G data flow can be carried over interface 425 using four 10 G data flows that are generated by a 5 to 2 gearbox. After transport between PHYs 420 , 430 , the four 10 G data flows are provided to switch 440 using a single XLAUI interfaces at interface 435 .
- FIG. 5 illustrates a second embodiment of an example application in providing an interface to a device such as a switch, packet processor, ASIC, etc.
- 100 GbE switch 530 incorporates the physical layer device components of FIG. 1 in supporting a 25 G I/O interface.
- 100 GbE PHY 520 supports an I/O interface 525 that can support various combinations of legacy 10 G/40 G traffic such as that outlined above in an efficient manner.
Abstract
Description
- 1. Field of the Invention
- The present invention relates generally to network switches and, more particularly, to a system and method for increasing input/output speeds in a network switch.
- 2. Introduction
- Increasing demands are being placed upon the data communications infrastructure. These increasing demands are driven by various factors, including the increasing bandwidth requirements of multimedia traffic. To accommodate the increasing bandwidth requirements, communication link speeds have also continued to evolve. Today, 10 Gigabit Ethernet (GbE) ports are commonly used. Many of today's network switches, for example, support 10 gigabit I/O port speeds.
- Even with 10 GbE ports, increased switch bandwidth is needed. Increasing switch I/O port speeds is a consideration, but such an increase can lead to inefficiencies due to the existence of legacy links. What is needed therefore is a mechanism that increases I/O speeds in a network switch, yet enables support for legacy speeds in an efficient manner.
- A system and/or method for increasing input/output speeds in a network switch, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
- In order to describe the manner in which the above-recited and other advantages and features of the invention can be obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
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FIG. 1 illustrates an embodiment of a physical layer device according to the present invention. -
FIG. 2 illustrates an example embodiment of data flow marking through modification of a synchronization header. -
FIG. 3 illustrates an example embodiment of data flow marking using multi-lane distribution PCS lane identifiers. -
FIG. 4 illustrates a first embodiment of an application of a 100 GbE PHY according to the present invention. -
FIG. 5 illustrates a second embodiment of an application of a 100 GbE PHY according to the present invention. - Various embodiments of the invention are discussed in detail below. While specific implementations are discussed, it should be understood that this is done for illustration purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without parting from the spirit and scope of the invention.
- Due to bandwidth demand, a network switch can support over 100 ports, each of which can be operating at 10.3125 gbps. Increasing switch bandwidth can be effected through an increase in the I/O speeds. For example, in one embodiment the switch bandwidth can be increased by increasing the I/O speed to 25.7 gbps. With this I/O speed increase, only four lanes would be required to transport 100 GbE traffic. This is in contrast to a conventional use of ten lanes to transport 100 GbE traffic.
- Significantly, increasing the I/O speed on the switch narrows the switch interface (i.e., from ten lanes to four lanes), which makes the interface module narrower. While the narrowing of the switch interface has obvious benefits in increasing switch bandwidth, support of legacy speeds such as 10 GbE or 40 GbE would not be possible, at least efficiently. Typically, support of legacy speeds is to operate the port at a lower speed. This method of operation is inefficient as it wastes significant amounts of bandwidth. For example, transporting 10 GbE over an I/O port that has 2.5 times the currently-used capacity is an inefficient use of available I/O port bandwidth.
- In the present invention, it is recognized that a mechanism is needed to use full I/O port bandwidth when transporting all traffic types. One embodiment of such a mechanism is that illustrated by the example physical layer device of
FIG. 1 . As illustrated, physical layer device of the present invention can be embodied as a 100 GbE physical layer device that supports a transport of various combinations of 10 GbE and 40 GbE data flows through I/O speeds of 25.7 gbps. As will be described, the transport of various combinations of 10 GbE and 40 GbE data flows is performed efficiently without a conventional waste of I/O bandwidth. - As illustrated, the example embodiment of 100 GbE
physical layer device 100 includes two data flow paths for each direction of traffic, wherein each data flow path supports a transport of half of the data flows in a single direction. As would be appreciated, in another embodiment, all of the data flows in a single direction can be handled by a single data flow path. - Consider first the two data flow paths going from left to right in the bottom half of
physical layer device 100. Each data flow path is designed to receive as input five 10.3125 gbps data flows. The lower data flow path receives the five 10G data flows denoted as RX_IN[0:4], while the upper data flow path receives the five 10G data flows denoted as RX_IN[5:9]. In general, it is desired thatphysical layer device 100 facilitate an increase of I/O speed from 10.3125 gbps to 25.7 gbps, thereby narrowing the I/O interface. - To illustrate such an operation, a description of the upper data flow path in the left-to-right direction of
physical layer device 100 is now provided. In general, the increase in I/O speed is facilitated by 5 to 2 Gearbox 105, which works on data flows that are marked by 10 G PCS/LaneMarker module 104. As illustrated, 10 G PCS/LaneMarker module 104 operates on five 10G data flows RX_IN[5:9] that have passed through delay locked loop (DLL)module 101, de-multiplexer (De-Mux)module 102 and first-in-first-out (FIFO)module 103. Here, it should be noted that in one embodiment, a single 10 to 4 gearbox can be used to facilitate a single data flow path. - In the present invention, 5 to 2
gearbox 105 does not use simple bit multiplexing to adapt a set of input lanes to a set of output lanes at a 5:2 ratio. Rather, 5 to 2 Gearbox 105 is designed to operate on data flows that have been marked with a data flow identifier by 10 G PCS/LaneMarker module 104. In general, the addition of data flow identifiers by 10 G PCS/Lane Marker module 104 enables an inverse 2 to 5 gearbox to decode, align, and identify each data flow. Inverse 2 to 5 gearbox can then present each data flow to a specific location based on the data flow identifier. - In
physical layer device 100, the 10 G traffic on RX_IN[5:9] are stripped at the 66-bit boundary for transport onto 25 G data flows TX_Out[2:3], while the 10 G traffic on RX_IN[0:4] are stripped at the 66-bit boundary for transport onto 25 G data flows TX_Out[0:1]. The 66-bit boundaries are defined by the 66-bit frames resulting from the 64B/66B PCS coding process. These 66-bit frames include 64 bits of data along with a 2-bit synchronization (sync) header. The 66-bit blocks are either data frames or control frames. The sync header is ‘01’ for data frames and ‘10’ for control frames. The remaining 64 bits of the 66-bit frame contain the scrambled payload. - In one embodiment, the sync header on data flows 0 and 5 are modified every 1000 66-bit blocks from ‘10’ to ‘11’, a previously unused sync header bit combination. The next immediate control frame sync header is then changed to from ‘10’ to ‘00’, which is also a previously unused sync header bit combination. This example marking of the sync headers in data flows 0 and 5 with previously unused sync header bit combinations is illustrated in
FIG. 2 . It should be noted that in one embodiment, no modification is made to the sync header of a data frame in order not to potentially increase undetected error probability. - As would be appreciated, the time between modification of control frame sync headers can be implementation dependent. Moreover, the particular data flow or data flows that are chosen for marking can also be implementation dependent. Here, it is significant that the marking of one or more data flows enables an inverse gearbox to decode, align, and identify each data flow.
- In an alternative embodiment, the payload within a control frame can be modified for data flow marking. For example, a fiber channel control frame payload can be unscrambled and its contents replaced with an unused signal order set that identifies the data flow. As would be appreciated, the particular unused signal order set used that identifies the data flow would be implementation dependent. At the receiving end, the unused signal ordered set would be replaced with the data that previously existed in the payload of the control frame.
- In yet another embodiment, data flow marking is facilitated by occasionally replacing standard Ethernet Idle frames with Multi-Lane Distribution (MLD) PCS lane identifiers used as physical data flow identifiers. MLD PCS lane identifiers are defined in IEEE 802.3 Clause 82. Table 1 below identifies the data flow identifier components that are arranged in the format illustrated in
FIG. 3 . Here, Bit Interleaved Parity (BIP) field BIP7 is a bit-wise inversion of BIP3. -
TABLE 1 Data Flow Encoding Number (M0, M1, M2, BIP3, M4, M5, M6, BIP7) 0 0xC1, 0x68, 0x21, BIP3, 0x3E, 0x97, 0xDE, BIP 71 0x9D, 0x71, 0x8E, BIP3, 0x62, 0x8E, 0x71, BIP 72 0x59, 0x4B, 0xE8, BIP3, 0xA6, 0xB4, 0x17, BIP 73 0x4D, 0x95, 0x7B, BIP3, 0xB2, 0x6A, 0x84, BIP 74 0xF5, 0x07, 0x09, BIP3, 0x0A, 0xF8, 0xF6, BIP 75 0xDD, 0x14, 0xC2, BIP3, 0x22, 0xEB, 0x3D, BIP7 6 0x9A, 0x4A, 0x26, BIP3, 0x65, 0xB5, 0xD9, BIP7 7 0x7B, 0x45, 0x66, BIP3, 0x84, 0xBA, 0x99, BIP 78 0xA0, 0x24, 0x76, BIP3, 0x5F, 0xDB, 0x89, BIP 79 0x68, 0xC9, 0xFB, BIP3, 0x97, 0x36, 0x04, BIP7 - Where the gearbox has 10 input data flows, only the first ten MLD PCS lane identifiers need be used as physical data flow identifiers. In one embodiment, additional MLD PCS lane identifiers can be used to accommodate gearboxes that have greater than ten input data flows.
- Using the MLD PCS lane identifiers as physical data flow identifiers, the 10 G traffic on RX_IN[5:9] are stripped at the 66-bit boundary for transport onto 25 G data flows TX_Out[2:3], while the 10 G traffic on RX_IN[0:4] are stripped at the 66-bit boundary for transport onto 25 G data flows TX_Out[0:1]. Occasionally, the 66-bit stripped Ethernet idle frame is replaced with the physical data flow identifiers defined above in Table 1 to identify the physical data flows. As would be appreciated, the frequency at which the Ethernet IPG idle data is replaced with physical data flow identifiers would be implementation dependent.
- At the receiving end, the 66-bit data would be decoded by the inverse gearbox to identify each data flow per the included physical data flow identifiers. The inverse gearbox would then replace the physical data flow identifier with the Ethernet idle frame before presentation of the data at a specific output port.
- Here, it should be noted that the addition of physical data flow identifiers enables the physical layer device to source traffic on a fractional pipe where a portion of the capacity of the higher-rate output data flows is left unused. For example, 40 GbE traffic can be input on RX_IN[5:9] and output as 2×20 G traffic on TX_OUT[2:3].
- As has been described, various mechanisms can be used by 10 G PCS/
Lane Marker module 104 inphysical layer device 100 to mark the data flows that are received at the input (e.g., RX_IN[5:9]). Returning toFIG. 1 , the marked data flows are then passed to 5 to 2Gearbox 105. 5 to 2Gearbox 105 receives the 66-bit data flow frames from the five 10G input data flows marked by 10 G PCS/Lane Marker module 104 and generates two higher-rate 25 G data flows in accordance with a frame distribution scheme defined by the 5:2 ratio. As would be appreciated, a 5 to 2 gearbox can also be defined that can generate four 25 G data flows from ten 10 G data flows. - More generally, it should be noted that the principles of the present invention are not confined to the example 5:2 ratio. Other ratios can be used to accommodate specific combinations of input data flows.
- 5 to 2
Gearbox 105 passes the twohigher rate 25G data flows toSelector module 106. Although not shown,Selector module 106 also receives loopback and pattern generation inputs.Selector module 106 passes one of the selected inputs to Multiplexer (Mux)/Feed Forward Equalizer (FFE)module 107. Mux/FFE module 107 then outputs the twohigher rate 25G data flows as TX_OUT[2:3]. - The two
higher rate 25G output data flows represent a higher rate I/O interface that facilitates a narrower interface module. The counterpart to the transmit direction in the lower half ofphysical layer device 100 is the receive direction in the upper half ofphysical layer device 100. - As illustrated, the upper data flow path in the right-to-left direction of
physical layer device 100 receives twohigher rate 25G data flows as inputs RX_IN[2:3] by Equalization (EQ)/Clock and Data Recovery (CDR)module 111. The signals received by EQ/CDR module 111 then pass throughDe-Mux module 112,FIFO module 113, andDe-Skew module 114 before being presented to theinverse 2 to 5Gearbox 115. In one embodiment, asingle inverse 4 to 10 gearbox can be used to facilitate a single data flow path. - In addition to generating five 10 G data flows based on the two 25 G data flows in accordance with the defined 2:5 ratio, 2 to 5
Gearbox 115 is also operative to remove the data flow markers that were inserted by 10 G PCS/Lane Marker module 104. Here, removal of the data flow markers can include the process of reestablishing the 66-bit control frames in their original form. As such, contents of the sync header or the payload can be reestablished in their original form as would be apparent. - 2 to 5
Gearbox 115 passes the fivelower rate 10 G data flows toSelector module 116. Although not shown,Selector module 116 also receives loopback and pattern generation inputs.Selector module 116 passes one of the selected inputs toMux module 117.Mux module 107 then outputs the fivelower rate 10 G data flows as TX_OUT[5:9]. - Having described a physical layer device that incorporates a 5 to 2 gearbox and an
inverse 2 to 5 gearbox, example applications are provided in the efficient transport of various combinations of 10 GbE and 40 GbE data flows. -
FIG. 4 illustrates one embodiment of an example application in providing an interface to a device such as a switch, packet processor, ASIC, etc. In this illustrated embodiment, 100GbE PHYs IF modules GbE switch 440. As described above,PHYs narrower interface 425 between each other using four 25 G data flows that are supported by a 5 to 2 gearbox and aninverse 2 to 5 gearbox. - One application of such an arrangement is transport to a remote expansion box to support a large number of ports that could not otherwise be supported within a single box. For example, such a transport application could be applied to the support of an expansion server blade.
- In one example application, 100
GbE PHY 430 supports a single 100 Gigabit Attachment Unit Interface (CAUI) 435 withswitch 440. In this arrangement, IFmodules 410 can include various combinations of 10 G and 40 G interfaces. For example, IFmodules 410 can include support for 10 GbE such as 10 GBASE-SR, 10 GBASE-LR, SFP+ Direct Attach Copper, etc., and 40 GbE such as 40 GBASE-SR4, 40 GBASE-LR4, etc. - In one arrangement, IF
modules 410 can support ten 10 GbE data flows for delivery overinterface 415. In another arrangement, IFmodules 410 can support one 40 GbE data flow and six 10 GbE data flows. In yet another arrangement, IFmodules 410 can support two 40 GbE data flows and two 10 GbE data flows. Regardless of the combination of 10/40 GbE data flows that are provided byIF modules 410 for delivery overinterface GbE PHYs CAUI interface 435. This application illustrates the ability of 100GbE PHYs - In another arrangement,
interface 435 is based on a 40 Gigabit Attachment Unit Interface (XLAUI). This arrangement illustrates a usage scenario wherePHYs modules 410 support two 40 G data flows. These two 40 G data flows can be carried overinterface 425 using four 20 G data flows that are generated by a 5 to 2 gearbox. Each of these 20 G data flows represent a fraction of the true 25 G data flow capacity. After transport betweenPHYs - In another fractional-pipe scenario, IF
modules 410 can support a single 40 G data flow, wherein the 40 G data flow can be carried overinterface 425 using four 10 G data flows that are generated by a 5 to 2 gearbox. After transport betweenPHYs interface 435. -
FIG. 5 illustrates a second embodiment of an example application in providing an interface to a device such as a switch, packet processor, ASIC, etc. In this illustrated embodiment, 100GbE switch 530 incorporates the physical layer device components ofFIG. 1 in supporting a 25 G I/O interface. Here, 100GbE PHY 520 supports an I/O interface 525 that can support various combinations oflegacy 10 G/40 G traffic such as that outlined above in an efficient manner. - These and other aspects of the present invention will become apparent to those skilled in the art by a review of the preceding detailed description. Although a number of salient features of the present invention have been described above, the invention is capable of other embodiments and of being practiced and carried out in various ways that would be apparent to one of ordinary skill in the art after reading the disclosed invention, therefore the above description should not be considered to be exclusive of these other embodiments. Also, it is to be understood that the phraseology and terminology employed herein are for the purposes of description and should not be regarded as limiting.
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US20130083810A1 (en) * | 2011-09-30 | 2013-04-04 | Broadcom Corporation | System and Method for Bit-Multiplexed Data Streams Over Multirate Gigabit Ethernet |
CN104065551A (en) * | 2013-03-21 | 2014-09-24 | 美国博通公司 | System And Method For 10/40 Gigabit Ethernet Multi-lane Gearbox |
WO2015089705A1 (en) * | 2013-12-16 | 2015-06-25 | 华为技术有限公司 | Data transmission method, device and system |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8098661B2 (en) * | 2008-04-04 | 2012-01-17 | Doron Handelman | Methods and apparatus for enabling communication between network elements that operate at different bit rates |
US9008105B2 (en) | 2013-03-21 | 2015-04-14 | Broadcom Corporation | System and method for 10/40 gigabit ethernet multi-lane gearbox |
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US9602401B2 (en) * | 2014-09-22 | 2017-03-21 | Intel Corporation | Technologies for high-speed PCS supporting FEC block synchronization with alignment markers |
Citations (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5502499A (en) * | 1993-12-03 | 1996-03-26 | Scientific-Atlanta, Inc. | Synchronizing waveform generator |
US5550815A (en) * | 1994-12-30 | 1996-08-27 | Lucent Technologies Inc. | Apparatus and method for reducing data losses in a growable packet switch |
US5838684A (en) * | 1996-02-22 | 1998-11-17 | Fujitsu, Ltd. | Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method |
US6249525B1 (en) * | 1998-03-27 | 2001-06-19 | Nexabit Networks, Inc. | Method of and apparatus for inserting and/or deleting escape characters into and from data packets and datagrams therefor on high speed data stream networking lines |
US20030043798A1 (en) * | 2001-08-30 | 2003-03-06 | Pugel Michael Anthony | Method, apparatus and data structure enabling multiple channel data stream transmission |
US20040030805A1 (en) * | 2002-08-07 | 2004-02-12 | Ichiro Fujimori | System and method for implementing a single chip having a multiple sub-layer phy |
US20040052530A1 (en) * | 2002-09-17 | 2004-03-18 | Cechan Tian | Optical network with distributed sub-band rejections |
US20040078621A1 (en) * | 2002-08-29 | 2004-04-22 | Cosine Communications, Inc. | System and method for virtual router failover in a network routing system |
US20040090995A1 (en) * | 2002-11-07 | 2004-05-13 | Kang Sung Soo | Ethernet switching apparatus and method using frame multiplexing and demultiplexing |
US20040151195A1 (en) * | 2003-02-01 | 2004-08-05 | 3Com Corporation | High-speed switch architecture |
US6888848B2 (en) * | 2000-12-14 | 2005-05-03 | Nortel Networks Limited | Compact segmentation of variable-size packet streams |
US6907002B2 (en) * | 2000-12-29 | 2005-06-14 | Nortel Networks Limited | Burst switching in a high capacity network |
US20050232204A1 (en) * | 1999-08-27 | 2005-10-20 | International Business Machines Corporation | Network switch and components and method of operation |
US6990097B2 (en) * | 2001-06-01 | 2006-01-24 | 4198638 Canada Inc. | Cell-based switch fabric with inter-cell control for regulating packet flow |
US20060133411A1 (en) * | 2001-05-18 | 2006-06-22 | Denton I C | Multi-protocol networking processor with data traffic support spanning local, regional and wide area networks |
US20060143355A1 (en) * | 2002-05-16 | 2006-06-29 | Taborek Richard Sr | Protocol independent data transmission using a 10 Gigabit Attachment Unit Interface |
US20070109968A1 (en) * | 2002-06-04 | 2007-05-17 | Fortinet, Inc. | Hierarchical metering in a virtual router-based network switch |
US7245633B1 (en) * | 1999-11-29 | 2007-07-17 | Siemens Aktiengesellschaft | Multiplexing method for gigabit ethernet signals in the synchronous digital hierarchy |
US7369491B1 (en) * | 2003-05-14 | 2008-05-06 | Nortel Networks Limited | Regulating data-burst transfer |
US7460563B1 (en) * | 2002-08-31 | 2008-12-02 | Cisco Technology, Inc. | Determination of interleaving channels in a serial interleaver |
US7519055B1 (en) * | 2001-12-21 | 2009-04-14 | Alcatel Lucent | Optical edge router |
US20090168812A1 (en) * | 2008-01-02 | 2009-07-02 | Cisco Technology, Inc. | Secure Combined Interoperable Multiplexing |
US20090232133A1 (en) * | 2005-05-31 | 2009-09-17 | Yang Yu | Ethernet access device and method thereof |
US20100092174A1 (en) * | 2008-10-13 | 2010-04-15 | Matthew Brown | Differential Inverse Multiplexing Virtual Channels in 40G Ethernet Applications |
US7715377B2 (en) * | 2002-01-03 | 2010-05-11 | Integrated Device Technology, Inc. | Apparatus and method for matrix memory switching element |
US7843830B1 (en) * | 2005-05-05 | 2010-11-30 | Force 10 Networks, Inc | Resilient retransmission of epoch data |
US7961649B2 (en) * | 2003-02-20 | 2011-06-14 | Nortel Networks Limited | Circulating switch |
US8205141B2 (en) * | 2009-04-29 | 2012-06-19 | Applied Micro Circuits Corporation | Virtual lane forward error correction in multilane distribution |
US20120155486A1 (en) * | 2010-12-15 | 2012-06-21 | Electronics And Telecommunications Research Institute | Ethernet apparatus and method for selectively operating multiple lanes |
US20120219005A1 (en) * | 2011-02-24 | 2012-08-30 | Broadcom Corporation | Aggregating communication channels |
US20120236869A1 (en) * | 2011-03-15 | 2012-09-20 | Telefonaktiebolaget L M Ericsson (Publ) | Data network elements, crossbars, and methods providing coupling between remote phy and mac devices |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6690682B1 (en) * | 1999-03-12 | 2004-02-10 | Lucent Technologies Inc. | Bit multiplexing of packet-based channels |
US6788682B1 (en) * | 2000-08-02 | 2004-09-07 | 3Com Corporation | Mapping of packets between links of trunk groups using Mux/Demux devices |
US7965712B2 (en) * | 2008-04-04 | 2011-06-21 | Doron Handelman | Methods and apparatus for enabling communication between network elements that operate at different bit rates |
JP5375221B2 (en) * | 2009-03-12 | 2013-12-25 | 富士通株式会社 | Frame transfer apparatus and frame transfer method |
-
2011
- 2011-06-21 US US13/165,400 patent/US8582437B2/en active Active
-
2013
- 2013-11-08 US US14/075,113 patent/US9130851B2/en not_active Expired - Fee Related
Patent Citations (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5502499A (en) * | 1993-12-03 | 1996-03-26 | Scientific-Atlanta, Inc. | Synchronizing waveform generator |
US5550815A (en) * | 1994-12-30 | 1996-08-27 | Lucent Technologies Inc. | Apparatus and method for reducing data losses in a growable packet switch |
US5838684A (en) * | 1996-02-22 | 1998-11-17 | Fujitsu, Ltd. | Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method |
US6249525B1 (en) * | 1998-03-27 | 2001-06-19 | Nexabit Networks, Inc. | Method of and apparatus for inserting and/or deleting escape characters into and from data packets and datagrams therefor on high speed data stream networking lines |
US20050232204A1 (en) * | 1999-08-27 | 2005-10-20 | International Business Machines Corporation | Network switch and components and method of operation |
US7620048B2 (en) * | 1999-08-27 | 2009-11-17 | International Business Machines Corporation | Network switch and components and method of operation |
US7257616B2 (en) * | 1999-08-27 | 2007-08-14 | International Business Machines Corporation | Network switch and components and method of operation |
US7245633B1 (en) * | 1999-11-29 | 2007-07-17 | Siemens Aktiengesellschaft | Multiplexing method for gigabit ethernet signals in the synchronous digital hierarchy |
US6888848B2 (en) * | 2000-12-14 | 2005-05-03 | Nortel Networks Limited | Compact segmentation of variable-size packet streams |
US6907002B2 (en) * | 2000-12-29 | 2005-06-14 | Nortel Networks Limited | Burst switching in a high capacity network |
US20060133411A1 (en) * | 2001-05-18 | 2006-06-22 | Denton I C | Multi-protocol networking processor with data traffic support spanning local, regional and wide area networks |
US6990097B2 (en) * | 2001-06-01 | 2006-01-24 | 4198638 Canada Inc. | Cell-based switch fabric with inter-cell control for regulating packet flow |
US20030043798A1 (en) * | 2001-08-30 | 2003-03-06 | Pugel Michael Anthony | Method, apparatus and data structure enabling multiple channel data stream transmission |
US7519055B1 (en) * | 2001-12-21 | 2009-04-14 | Alcatel Lucent | Optical edge router |
US7715377B2 (en) * | 2002-01-03 | 2010-05-11 | Integrated Device Technology, Inc. | Apparatus and method for matrix memory switching element |
US20060143355A1 (en) * | 2002-05-16 | 2006-06-29 | Taborek Richard Sr | Protocol independent data transmission using a 10 Gigabit Attachment Unit Interface |
US20070109968A1 (en) * | 2002-06-04 | 2007-05-17 | Fortinet, Inc. | Hierarchical metering in a virtual router-based network switch |
US20040030805A1 (en) * | 2002-08-07 | 2004-02-12 | Ichiro Fujimori | System and method for implementing a single chip having a multiple sub-layer phy |
US20040078621A1 (en) * | 2002-08-29 | 2004-04-22 | Cosine Communications, Inc. | System and method for virtual router failover in a network routing system |
US7460563B1 (en) * | 2002-08-31 | 2008-12-02 | Cisco Technology, Inc. | Determination of interleaving channels in a serial interleaver |
US20040052530A1 (en) * | 2002-09-17 | 2004-03-18 | Cechan Tian | Optical network with distributed sub-band rejections |
US20040090995A1 (en) * | 2002-11-07 | 2004-05-13 | Kang Sung Soo | Ethernet switching apparatus and method using frame multiplexing and demultiplexing |
US20040151195A1 (en) * | 2003-02-01 | 2004-08-05 | 3Com Corporation | High-speed switch architecture |
US7961649B2 (en) * | 2003-02-20 | 2011-06-14 | Nortel Networks Limited | Circulating switch |
US7369491B1 (en) * | 2003-05-14 | 2008-05-06 | Nortel Networks Limited | Regulating data-burst transfer |
US7843830B1 (en) * | 2005-05-05 | 2010-11-30 | Force 10 Networks, Inc | Resilient retransmission of epoch data |
US20090232133A1 (en) * | 2005-05-31 | 2009-09-17 | Yang Yu | Ethernet access device and method thereof |
US20090168812A1 (en) * | 2008-01-02 | 2009-07-02 | Cisco Technology, Inc. | Secure Combined Interoperable Multiplexing |
US20100092174A1 (en) * | 2008-10-13 | 2010-04-15 | Matthew Brown | Differential Inverse Multiplexing Virtual Channels in 40G Ethernet Applications |
US7839839B2 (en) * | 2008-10-13 | 2010-11-23 | Applied Micro Circuits Corporation | Differential inverse multiplexing virtual channels in 40G ethernet applications |
US8205141B2 (en) * | 2009-04-29 | 2012-06-19 | Applied Micro Circuits Corporation | Virtual lane forward error correction in multilane distribution |
US20120155486A1 (en) * | 2010-12-15 | 2012-06-21 | Electronics And Telecommunications Research Institute | Ethernet apparatus and method for selectively operating multiple lanes |
US20120219005A1 (en) * | 2011-02-24 | 2012-08-30 | Broadcom Corporation | Aggregating communication channels |
US20120236869A1 (en) * | 2011-03-15 | 2012-09-20 | Telefonaktiebolaget L M Ericsson (Publ) | Data network elements, crossbars, and methods providing coupling between remote phy and mac devices |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8601481B2 (en) * | 2011-03-02 | 2013-12-03 | International Business Machines Corporation | Workflow validation and execution |
US20120227047A1 (en) * | 2011-03-02 | 2012-09-06 | International Business Machines Corporation | Workflow validation and execution |
US20130083810A1 (en) * | 2011-09-30 | 2013-04-04 | Broadcom Corporation | System and Method for Bit-Multiplexed Data Streams Over Multirate Gigabit Ethernet |
US8873591B2 (en) * | 2011-09-30 | 2014-10-28 | Broadcom Corporation | System and method for bit-multiplexed data streams over multirate gigabit Ethernet |
US9170952B1 (en) * | 2011-12-28 | 2015-10-27 | Altera Corporation | Configurable multi-standard device interface |
DE102014203561B4 (en) | 2013-02-28 | 2019-08-22 | Avago Technologies International Sales Pte. Ltd. | SYSTEM AND METHOD FOR A DATA FLUID IDENTIFICATION AND ORIENTATION IN A 40/100 GIGABIT ETHERNET GEARBOX |
CN104065551A (en) * | 2013-03-21 | 2014-09-24 | 美国博通公司 | System And Method For 10/40 Gigabit Ethernet Multi-lane Gearbox |
US20160294990A1 (en) * | 2013-12-16 | 2016-10-06 | Huawei Technologies Co., Ltd. | Data transmission method, device, and system |
JP2017505570A (en) * | 2013-12-16 | 2017-02-16 | 華為技術有限公司Huawei Technologies Co.,Ltd. | Data transmission method, apparatus, and system |
WO2015089705A1 (en) * | 2013-12-16 | 2015-06-25 | 华为技术有限公司 | Data transmission method, device and system |
US10447827B2 (en) * | 2013-12-16 | 2019-10-15 | Huawei Technologies Co., Ltd. | Methods and devices for implementing flexible ethernet within a physical coding sublayer |
US9426096B2 (en) * | 2014-05-21 | 2016-08-23 | Intel Corporation | Single-lane, twenty-five gigabit ethernet |
US9992125B2 (en) * | 2014-05-21 | 2018-06-05 | Intel Corporation | Single-lane, twenty-five gigabit ethernet |
US20190068284A1 (en) * | 2017-08-30 | 2019-02-28 | Ciena Corporation | Systems and methods for relative phase measurement and alignment of 66b encoded signals |
US10256909B2 (en) * | 2017-08-30 | 2019-04-09 | Ciena Corporation | Systems and methods for relative phase measurement and alignment of 66B encoded signals |
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US8582437B2 (en) | 2013-11-12 |
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