US20140225262A1 - Electrical contact - Google Patents
Electrical contact Download PDFInfo
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- US20140225262A1 US20140225262A1 US14/261,409 US201414261409A US2014225262A1 US 20140225262 A1 US20140225262 A1 US 20140225262A1 US 201414261409 A US201414261409 A US 201414261409A US 2014225262 A1 US2014225262 A1 US 2014225262A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
An electrical contact includes a substrate, at least an insulation layer, a metal layer, a conductive layer, and a metal silicide layer. The substrate includes at least a silicon region. The insulation layer is disposed on the substrate and includes at least a contact hole exposing the silicon region. The metal layer is formed on the sidewalls and the bottom of the contact hole. The metal layer adjacent to the bottom surface is thinner than the metal layer on the sidewalls. The conductive layer covers the metal layer and fills up the contact hole. The metal silicide layer is adjacent to the bottom of the contact hole.
Description
- This application is a division of U.S. application Ser. No. 13/364,289, filed Feb. 1, 2012, the disclosure of which is hereby incorporated by reference herein in its entirety.
- 1. Field of the Invention
- The present invention relates generally to an electrical contact, and more particularly, to an electrical contact connecting a semiconductor device.
- 2. Description of the Prior Art
- As semiconductor processes advance to very deep sub-micron geometries, such as 20-nm node and beyond, and with the progress of device miniaturization, junction resistance between semiconductors and external contact metals has become a critical issue; therefore, there is a strong need to invent electrical contact structures with relatively low junction resistance, which can be used to connecting semiconductors and conductive lines.
- In a convention method of fabricating an electrical contact, in order to reduce junction resistance, a self-aligned silicide (salicide) process is utilized to form a metal silicide layer on the junction of metal and semiconductor layer. For example, a semiconductor device covered with a metal layer is provided first. Next, an annealing process is carried out to diffuse atoms inside the metal layer into certain regions, like silicon regions contacted with the metal layer, so that metal silicide layers is formed on the surface of the certain regions. Then, remaining metal layers are removed and another annealing process is performed. During this process, the resistivity of the metal silicide layers can be reduced. An insulation layer, which has a plurality of contact holes, is than formed on the semiconductor device so that the metal silicide layers can be exposed from the contact holes. Finally, a barrier layer and a conductive layer are deposited inside the contact holes to thereby complete a contact structure. The above-saying procedures, however, need at least two annealing processes and a removing process of the metal layer. Such complicated steps are no doubt increase cost of the manufacture and the thermal budget of the semiconductor device is over consumed.
- Regarding the drawbacks described above, there is always a continuing need to develop an electrical contact and a fabricating method thereof, which can simply a fabricating process and save thermal budget of semiconductor devices from over consuming.
- One object of the invention is to provide a structure of an electrical contact which can not only simplify fabricating processes but also avoid over consuming thermal budget.
- According to one embodiment of the invention, an electrical contact is provided and includes a substrate, at least an insulation layer, a metal layer, a conductive layer, and a metal silicide layer. The substrate includes at least a silicon region. The insulation layer is disposed on the substrate and includes at least a contact hole exposing the silicon region. The metal layer is formed on the sidewalls and the bottom of the contact hole. The metal layer adjacent to the bottom surface is thinner than the metal layer on the sidewalls. The conductive layer covers the metal layer and fills up the contact hole. The metal silicide layer is adjacent to the bottom of the contact hole.
- According to another embodiment of the invention, another electrical contact is also provided and includes a substrate, at least an insulation layer, a metal layer, a conductive layer, a barrier layer, and a metal silicide layer. The substrate includes at least a silicon region. The insulation layer is disposed on the substrate and includes at least a contact hole exposing the silicon region. The metal layer is formed only on the sidewalls of the contact hole. The conductive layer covers the metal layer and fills up the contact hole. The barrier layer is located between the metal layer and the conductive layer. The metal silicide layer is adjacent to the bottom of the contact hole. In addition, the metal silicide layer and the metal layer have same metal components.
- In sum, the invention provides an electrical contact structure which can omit a process for removing the metal layer. In addition, a phase transition process and a process for depositing barrier layer are also combined to other processes. Therefore, processes for fabricating the electrical contact structure may be simplified and thermal budget of an entire semiconductor device may also be saved.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
- The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
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FIGS. 1-10 are schematic diagrams showing a method for fabricating an electrical contact according to one embodiment of the invention, wherein -
FIG. 1 is a schematic diagram showing a CMOS with metal gates according to one embodiment of the invention; -
FIG. 2 is a schematic diagram showing a CMOS with polysilicon gates according to another embodiment of the invention; -
FIG. 3 is a flow chart illustrating a fabrication process of an electrical contact according to a first exemplary embodiment of the invention; -
FIG. 4 is a flow chart illustrating a fabrication process of an electrical contact according to a second exemplary embodiment of the invention; and -
FIGS. 5-10 are schematic diagrams showing a method for fabricating an electrical contact according to one embodiment of the invention. - In the following description, numerous specific details are given to provide a thorough understanding of the invention. It will, however, be apparent to one skilled in the art that the invention may be practiced without these specific details. Furthermore, some well-known system configurations and process steps are not disclosed in detail, as these should be well-known to those skilled in the art.
- Please refer to
FIGS. 1-10 .FIGS. 1-10 are schematic diagrams showing a method for fabricating an electrical contact according to one embodiment of the invention. Referring toFIG. 1 , a semiconductor device is provided first, for example, a complementary metal oxide semiconductor transistor (CMOS), which is fabricated through a gate—last process accompanied with a high-k first process. A structure of which is described as follows. Asubstrate 100, for example, a silicon substrate, a silicon-on-insulator (SOI) or the like is provided. A first region and a second region are defined on thesubstrate 100, such as anNMOS region 102 and aPMOS region 104. A plurality of shallow trench isolations (STI) 106 is formed in thesubstrate 100 for separating the two transistor regions. Afirst gate structure 120 and asecond gate structure 122 are formed on theNMOS region 102 and thePMOS region 104, respectively. Each sidewall of thegate structures first spacer 124 and asecond spacer 126. A lightlydoped region 128 is disposed in thesubstrate 100 below thefirst spacer 124 and thesecond spacer 126. At least a lightly doped region and at least a source/drain region 130 are disposed between theshallow trench isolations 106, and the source/drain region 130 is not covered by thefirst spacer 124 and thesecond spacer 126. It is worth noting that anepitaxial layer 132 may be additionally formed in the source/drain region 130 within eachNMOS region 102 andPMOS region 104 to thereby adjust carrier mobility in the CMOS device. In this embodiment, theepitaxial layer 132 is only fabricated in thesubstrate 100 on each side of thesecond spacer 126 within thePMOS region 104, wherein theepitaxial layer 132 preferably includes germanium silicon and may have a single layer or a multiple layers structure. In addition, because the position of the metal silicides are defined by the contact holes 140, no metal silicide exists in the source/drain region 130 at this time. Acover layer 136 is formed on thesubstrate 100, which may cover thefirst gate structure 120 and thesecond gate structure 122. The cover layer may be a contact etch stop layer (CESL) which has a suitable stress. Additionally, an inter-layer dielectric (ILD) is on thesubstrate 100 and coversNMOS region 102 andPMOS region 104. - In this embodiment, the
first gate structure 120 is a kind of metal gate structure which includes a high-k dielectric layer 110, awork function layer 150 and ametal layer 152. Thesecond gate structure 122 is also a metal gate which structure is similar to thefirst gate structure 120. The only difference between the twogates cover layer 112 and adielectric layer 108 may be formed on and below the high-k dielectric layer 110, respectively and the composition of which may be of dielectric material, such as metal oxide or metal nitride. A barrier layer (not shown) may be located between the work function layers 144 and 150, and themetal layer 150 respectively, to prevent atoms from diffusing from themetal layer 152. In addition, the high-K dielectric layer 110 described above includes HfO2, HfSiO4, HfSiON, Al2O3, La2O3, Ta2O5, Y2O3, ZrO2, SrTiO3, ZrSiO4, HfZrO4, strontium bismuth tantalate (SBT), lead zirconate titanate (PZT), or barium strontium titanate (BST), but is not limited thereto. - According to the preceding paragraph, a CMOS, fabricated through gate-last processes is provided, which is not the only kind of semiconductor devices suitable for the invention. The semiconductor device may also be a CMOS with polysilicon gate or a CMOS fabricated through gate-first processes. Referring to
FIG. 2 ,FIG. 2 is a schematic diagram showing a CMOS with polysilicon gates according to another embodiment of the invention. A structure of which is similar toFIG. 1 , but thecover layer 136 directly covers and contacts thegate structures dielectric layer 108, e.g. silicon dioxide, and apolysilicon layer 116 are in the gate structures. In addition, thedielectric layer 108 maybe replaced with the high-k dielectric layer 100 as described above. -
FIG. 3 is a flow chart illustrating a fabrication process of an electrical contact according to a first exemplary embodiment of the invention.FIG. 4 is a flow chart illustrating a fabrication process of an electrical contact according to a second exemplary embodiment of the invention. Please refer toFIG. 3 . In this embodiment, astep 200 is performed first to obtain semiconductor devices as shown inFIG. 1 orFIG. 2 . Then, astep 210 is performed, so that a plurality of contact holes 140 is formed inside theILD 138 via a photolithography and an etching process. The positions of the contact holes 140 correspond to the areas of subsequent metal silicide. A self-aligned silicide (salicide) process is then carried out to form a metal silicide in thesubstrate 100. As illustrated insteps metal layer 160 is first filled into the contact holes 140 where it covers certain regions of the device. A annealing process, such as rapid thermal annealing (RTA), is carried out to diffuse atoms inside themetal layer 160 into the certain regions, so that a metal silicide layer is formed near eachcontact hole 140. Then, the remainingmetal layers 160 are removed and another annealing process, such as rapid thermal annealing (RTA), is performed. During this process, the resistivity of the metal silicide can be reduced. Finally, abarrier layer 162 and aconductive layer 180 are deposited inside thecontact hole 140; acontact structure 170 is therefore completed. According to the second exemplary embodiment, this embodiment provides astep 220 which is substantially the same as a combination of thesteps FIG. 4 . And astep 240 is provided, which is the same as a combination of thesteps step 270 showed inFIG. 3 is also omitted in this embodiment. That is to say, the second exemplary embodiment omits a process for removingmetal layer 160 and cancels additional processes for phase transition and depositing thebarrier layer 162. Therefore, a fabrication process for an electrical contact can be further simplified and the thermal budget will not be over consumed. -
FIGS. 5-10 are schematic diagrams showing a method for fabricating an electrical contact according to the second exemplary embodiment of the invention. The specific technique features according to the invention will be described clearly in the following sequences. As shown inFIG. 5 , at least acontact hole 140 is formed inside theILD 138 to expose a related silicon region. In this case, the silicon region refers to source/drain region 130. According to another embodiment, the silicon region may refer to any semiconductor region exposed by thecontact hole 140. For example, the semiconductor region may be doped or un-doped monocrystalline silicon or polycrystalline silicon, wherein dopants include phosphor, arsenic, boron, germanium or a combination of which, but are not limited to. Then, ametal layer 160 deposition process, like a radio frequency physical vapor deposition (RFPVD) process, is carried out to form ametal layer 160 on thesidewalls 140 a and abottom surface 140 b of thecontact hole 140. In addition, themetal layer 160 is preferably approximately 150 Angstroms thick. An annealing process may be further performed in the subsequent process to correspondingly increase conductivity of the silicon region. Abarrier layer 162, like Ti/TiN, Ta/TaN, or other metal nitride with similar properties, may further cover themetal layer 160 to prevent electromigration generated by the conductive layer 180 (not shown). In addition, thebarrier layer 162 maybe replaced with an adhesive layer (not shown) or a protective layer (not shown) to improve the adhesivity between theconductive layer 180 and the metal layer, or to prevent themetal layer 160 from oxidizing. In this case, since themetal layer 160 is already covered by thebarrier layer 162, noextra barrier layer 162 is needed to be formed on themetal layer 160. Additionally, themetal layer 160 may include tungsten, aluminum, copper, titanium, tantalum, niobium, erbium, molybdenum, cobalt, nickel, platinum or alloys of which and thebarrier layer 162 includes TiN, TaN, Ti/TiN or Ta/TaN, but are not limited thereto. - Please refer to
FIG. 6 . In the following processes, metal silicides will be formed in the silicon regions and the fabricating processes of which are described therein. First, an annealing process, such as a rapid thermal annealing (RTA), with a temperature inferior to 350° C. is carried out, so that metal atoms inside themetal layer 160 may enter or diffuse into the silicon region, e.g. the source/drain region 130, or the silicon atoms inside the source/drain region 130 may enter or diffuse into themetal layer 160. As a result, a firstmetal silicide layer 164 is formed nearby the bottom 140 b of thecontact hole 140. It should be noted that the annealing temperature described above may be higher than 350° C., according to another embodiment. In some cases, because the conductivity of the firstmetal silicide layer 164 is not low enough, another annealing process can be performed in a subsequent process. - In addition, a film thickness of the
metal layer 160 and processing parameters, such as time and temperature, may further be modified in order to meet the needs of a variety of products. That is to say, the thickness of themetal layer 160 near the bottom 140 b of thecontact hole 140 may be thicker, thinner, or even reduced to zero in different embodiments. Please refer to FIG, 7 andFIG. 8 . Both of these pictures are schematic enlarged diagrams showing an encircled region depicted in theFIG. 6 . As shown inFIG. 7 , in this embodiment, the thickness of themetal layer 160 near the bottom 140 b is reduced after performing the above-described annealing process. Therefore, the thickness W of themetal layer 160 is smaller than the thickness W′ of themetal layer 160 on thesidewalls 140 a. According toFIG. 8 , however, theentire metal layer 160 near the bottom 140 b of thecontact hole 140 may disappear under appropriate processing parameter; therefore, the firstmetal silicide layer 164 near the bottom 140 b may substantially contact thebarrier layer 162, if thebarrier layer 162 covering themetal layer 160 is formed before the annealing process. Additionally, the regions where the firstmetal silicide layer 164 exists are approximately corresponding to the regions exposed by the contact holes 140, that is to say, the firstmetal silicide layer 164 is on a surface of the silicon region and adjacent to the bottom 140 b of thecontact hole 140. It should be noted that, according to each exemplary embodiment, residues of themetal layer 160 are not removed after the annealing process; therefore, themetal layer 160, which is formed during a self-aligned silicide (salicide) process, must remain on thesidewalls 140 a of thecontact hole 140. - As shown in
FIG. 9 , a deposition and a planarizing processes a performed, aconductive layer 180 is formed to fill up eachcontact hole 140. The fabricating processes of these are described as follows. First, a deposition process of a conductive material is performed, such as tungsten deposition, to deposit aconductive layer 180 covering theILD 138. According to the second exemplary embodiment, since the temperature of the annealing process (a part of the deposition process) is approximately 400° C., the firstmeal silicide layer 164 can be a transition to a secondmetal silicide layer 168, which has relatively high conductivity, during the annealing process (may be deemed as a phase transition process); for example, from a solid phase of Ni2Si to a solid phase of NiSi. This second exemplary embodiment integrates the phase transition process with theconductive layer 180 deposition so that no additional annealing process needs to be carried out before performing theconductive layer 180 deposition contrary to the first exemplary embodiment. Finally, a planarizing process is performed, such as a chemical mechanical polishing (CMP) process, to planarize theconductive layer 180 and remove themetal layer 160 and thebarrier layer 162 on theILD 138. In addition, theconductive layer 180 is not limited to tungsten; it may further comprise aluminum, titanium, tantalum, niobium, molybdenum, copper, alloys of above, or other suitable conductive material. - Please refer to
FIG. 10 , which is a schematic top-view showing a layout of thecontact structure 170 encircled in theFIG. 9 . According to the invention, the layout of thecontact structure 170 may be of a plug shape or a slot shape. In this embodiment, each of thecontact structures 170 within theNMOS region 102 has a hole with a slot shape, and each of thecontact structures 170 within thePMOS region 104 has a hole with a plug shape. That is to say, eachcontact structure 170 within theNMOS region 102 belongs to a slot contact (slot contact hole), while eachcontact structure 170 within thePMOS region 104 belongs to a plug contact. The layout described above, should however not be construed in a limited sense. Depending on different requirements, eachNMOS region 102 andPMOS region 104 may have slot contacts or plug contacts. For example, thecontact structures 170 locating on left side and right side of theNMOS region 102 may be slot contacts and plug contacts respectively. - According to each exemplary embodiment, the CMOS device, which is fabricated through a gate-last process accompanied with a high-k first process is provided; the CMOS may however be replaced with another type of semiconductor device, which is fabricated through a gate-last process and accompanied with a high-k last process. In addition, semiconductor devices suitable for applying in the invention should not be restricted to the CMOS devices with metal gates, which may be further replaced by other substantially equivalent semiconductor devices in IC. For example, the electrical contact may be also connected to devices like NMOS, PMOS, semiconductor resistor, diode device, photosensitive device, bipolar junction transistor (BJT) or the like. That is to say, the silicon regions located in each device can be connected to the respective electrical contact. Hence, signals can be transmitted between the devices and an external circuit.
- To summarize, the present invention provides an
electrical contact structure 170 which can omit a process of removing themetal layer 160. In addition, a phase transition process and a process for depositingbarrier layer 162 are also combined to other processes. Therefore, processes for fabricating theelectrical contact structure 170 may be simplified and the thermal budget of an entire semiconductor device may also be saved. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (15)
1. An electrical contact, comprising:
a substrate having at least a silicon region;
at least an insulation layer on the substrate, wherein the insulation layer comprises at least a contact hole exposing the silicon region and having sidewalls and a bottom surface;
a metal layer formed on the sidewalls of the contact hole;
a conductive layer covering the metal layer, wherein the conductive layer fills up the contact hole; and
a metal silicide layer adjacent to the bottom of the contact hole, wherein the metal layer is further on the bottom and the metal layer adjacent to the bottom surface is thinner than the metal layer on the sidewalls.
2. The electrical contact according to claim 1 , furthering comprising a barrier layer disposed between the metal layer and the conductive layer.
3. The electrical contact according to claim 2 , wherein the barrier layer comprises TiN, TaN, Ti/TiN or Ta/TaN.
4. The electrical contact according to claim 1 , wherein the metal silicide layer substantially contacts the barrier layer.
5. The electrical contact according to claim 1 , wherein the metal silicide layer is adjacent to the metal layer.
6. The electrical contact according to claim 1 , wherein the metal layer is thinner than 150 Angstroms.
7. The electrical contact according to claim 1 , wherein the metal layer comprises tungsten, aluminum, copper, titanium, tantalum, niobium, erbium, molybdenum, cobalt, nickel, platinum or alloys thereof.
8. The electrical contact according to claim 1 , wherein the contact hole is a slot contact hole.
9. The electrical contact according to claim 1 , wherein the metal silicide layer and the metal layer have same metal components.
10. An electrical contact, comprising:
a substrate having at least a silicon region;
at least an insulation layer on the substrate, wherein the insulation layer comprises at least a contact hole exposing the silicon region and having sidewalls and a bottom surface;
a metal layer formed only on the sidewalls of the contact hole;
a conductive layer covering the metal layer, wherein the conductive layer fills up the contact hole;
a barrier layer located between the metal layer and the conductive layer; and
a metal silicide layer adjacent to the bottom of the contact hole, wherein the metal silicide layer and the metal layer have same metal components.
11. The electrical contact according to claim 10 , wherein the barrier layer comprises TiN, TaN, Ti/TiN or Ta/TaN.
12. The electrical contact according to claim 10 , wherein the metal silicide layer substantially contacts the barrier layer.
13. The electrical contact according to claim 10 , wherein the metal silicide layer is adjacent to the metal layer.
14. The electrical contact according to claim 10 , wherein the metal layer is thinner than 150 Angstroms.
15. The electrical contact according to claim 10 , wherein the metal layer comprises tungsten, aluminum, copper, titanium, tantalum, niobium, erbium, molybdenum, cobalt, nickel, platinum or alloys thereof.
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US14/261,409 US20140225262A1 (en) | 2012-02-01 | 2014-04-24 | Electrical contact |
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US13/364,289 US8772159B2 (en) | 2012-02-01 | 2012-02-01 | Method of fabricating electrical contact |
US14/261,409 US20140225262A1 (en) | 2012-02-01 | 2014-04-24 | Electrical contact |
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US9153483B2 (en) * | 2013-10-30 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor integrated circuit fabrication |
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US20150372100A1 (en) * | 2014-06-19 | 2015-12-24 | GlobalFoundries, Inc. | Integrated circuits having improved contacts and methods for fabricating same |
CN107275278A (en) * | 2016-04-07 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
US10269714B2 (en) | 2016-09-06 | 2019-04-23 | International Business Machines Corporation | Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements |
US10804270B2 (en) | 2017-10-18 | 2020-10-13 | International Business Machines Corporation | Contact formation through low-tempearature epitaxial deposition in semiconductor devices |
US10796995B2 (en) * | 2017-11-29 | 2020-10-06 | Tohoku University | Semiconductor devices including a first cobalt alloy in a first barrier layer and a second cobalt alloy in a second barrier layer |
US11094795B2 (en) | 2018-11-20 | 2021-08-17 | Nanya Technology Corporation | Semiconductor device and method for manufacturing the same |
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US8772159B2 (en) | 2014-07-08 |
US20130193577A1 (en) | 2013-08-01 |
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